A64S06162AG-70F [AMICC]
16M(1M x 16bit) Normal mode & Page mode with Deep Power Down Static Random Access Memory; 16M （ 1M X 16位），正常模式和页模式与深度掉电静态随机存取存储器
| 型号： | A64S06162AG-70F |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 16M(1M x 16bit) Normal mode & Page mode with Deep Power Down Static Random Access Memory |
| 文件： | 总14页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A64S06162A
Preliminary
Document Title
16M(1M x 16bit) Normal mode & Page mode with Deep Power Down Static
Random Access Memory
Revision history
Rev. No.
History
Issue Date
Remark
0.0
Initial issue
May 24, 2005
Preliminary
AMIC Technology, Corp.
(May, 2005, Version 0.0)
1
A64S06162A
Preliminary
MEMORY
16M(1M x 16bit) Normal mode & Page mode with Deep Power Down
Static Random Access Memory
DESCRIPTION
The A64S06162A is a 16Mb high speed, low power Static Random Access Memory(SRAM)
organized as 1,048,576 words by 16 bits and supports Deep Power Down and Page Mode.
The A64S06162A is a Pseudo SRAM based on successfully proven DRAM CELL SRAM which
was specifically developed for cost sensitive, low power computing and communication
applications such as mobile cellular phone handsets, personal digital assistants and other
battery-operated consumer products.
FEATURES
• Standard Asynchronous SRAM Interface with Deep Power Down and Page Mode
• Organization
• Power Supply Voltage
• Page Size
• Page Mode Access (tPAA)
• Data Retention Voltage
• Deep Power Down
: 1M x 16Bit
: 2.7 ~ 3.3 V
: 4 words
: 35ns
: 2.4V
: 5uA
• Tri-state Output and TTL Compatible
PRODUCT FAMILY
ISB1
IccDR
(Max)
ICC1
Operating
Temperature
Product Family
A64S06162A
Voltage
2.7 ~ 3.3 V
Speed
70
Mode
Page
(Max)
(Max)
-40 ~ 85 ℃
100uA
100uA
2.0mA
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Ref. Cont.
DC Generator Circuit
A
B
C
D
E
F
/LB
IO8
IO9
/OE
/UB
A0
A3
A5
A1
A4
A6
A7
A2
/CS
IO1
IO3
IO4
IO5
/WE
A11
/PD
IO0
IO2
VCC
VSS
IO6
IO7
NC
IO0
IO7
Row
Address
IO10
Memory Array
8192 rows
128 x 16 columns
VSS IO11 A17
IO8
Column
Address
VCC IO12 VSS A16
IO15
IO14 IO13 A14
A15
A13
A10
Column Decoder
G
H
IO15 A19
A12
A9
Control Logic
A18
A8
/CS
/PD /OE /WE
/UB /LB
Note : E3 pin ( VSS) can be remain as a NC
Name
Function
Name
VCC
Function
/CS
/OE
Chip Select Input
Output Enable Input
Write Enable Input
Address Input
Power
VSS
/UB
/LB
Ground
/WE
Upper Byte (IO8∼15)
Lower Byte (IO0∼7)
Deep Power Down
A0∼A19
IO0∼IO15
Data Input / Output
/PD
AMIC Technology, Corp.
(May, 2005, Version 0.0)
2
A64S06162A
Preliminary
PRODUCT LIST
Part Name
Function
A64S06162A-70U
16M, 48-FBGA , 70 ns, 3.0V, -40℃∼85℃
ABSOLUTE MAXIMUM RATING
Item
Symbol
VIN, VOUT
VCC
Ratings
-0.2 to VCC+0.3 V
-0.2 to 3.6
Unit
V
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
V
Power Dissipation
PD
TSTG
TA
1.0
W
℃
℃
Storage temperature
-55 to 150
-40 ~ 85
Operating Temperature (Extended)
Note :
Stresses greater than those listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS
/PD
/OE
/WE
/LB
/UB
I/O 0~7
I/O 8~15
MODE
Power
X
L
X
X
X
X
High-Z
High-Z
Deselected
Deep Power
Down
H
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
H
H
L
X
X
H
H
H
H
H
L
X
H
L
X
H
X
L
High-Z
High-Z
High-Z
High-Z
Deselected
Deselected
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
High-Z
High-Z
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X
L
High-Z
High-Z
H
L
Data Out
High-Z
High-Z
L
H
L
Data Out
Data Out
High-Z
L
L
Data Out
Data In
High-Z
X
X
X
L
H
L
Lower Byte Write
Upper Byte Write
Word Write
L
H
L
Data In
Data In
L
L
Data In
AMIC Technology, Corp.
(May, 2005, Version 0.0)
3
A64S06162A
Preliminary
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
Supply Voltage (5)
Ground
Symbol
Vcc
Min
2.7
0
Typ
3.0
0
Max
3.3
0
Unit
V
Vss
V
Vcc+0.2 2)
0.4
Input High Voltage
Input Low Voltage
0.8*Vcc
-0.2 3)
-
-
V
V
VIH
VIL
Note :
1.TA = -40℃ to 85℃, otherwise specified.
2. Overshoot : Vcc + 1.0V in case of pulse width ≤ 20 ns.
3. Undershoot : -1.0V in case of pulse width ≤ 20 ns.
4. Overshoot and undershoot are sampled, not 100% tested.
5. Stable power supply required 100 us before device operation.
CAPACITANCE (TA = 25 ℃, f = 1.0MHz)
Symbol
CIN
Parameter
Condition
VIN =0V
Max.
8
Unit
pF
Input Capacitance
Output Capacitance
VIO =0V
10
pF
COUT
Note : This parameter is sampled and not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
ILI
Test Condition
VIN = Vss to Vcc
Min
Typ
Max
Unit
Input Leakage Current
-1
1
uA
Output Leakage Current
ILO
/CS = VIH, /UB=/LB= VIH or /OE=VIH or
/WE=VIL, VIO=Vss to Vcc
-1
1
uA
Icc1
Cycle Time = 1 us, 100%duty, IIO=0mA,
/CS ≤ 0.2V, VIN ≤ 0.2V or
VIN ≥ Vcc-0.2V
2.0
20
mA
mA
mA
Icc2
Iccp
Cycle time=Min, IIO=0mA, 100% duty
/CS = VIL,VIN=VIL or VIH
/CS1 = VIL, CS2=VIH,Tpwc = min Page
address cycling
10
Output Low Voltage
Output High Voltage
Standby Current(TTL)
VOL
VOH
ISB
IOL = 2 mA
IOH = -1 mA
0.4
V
V
2.2
/CS=VIH, /UB=/LB= VIH, Other inputs = VIH or
VIL
0.3
mA
Standby Current(CMOS)
Deep Power Down Current
ISB1
ISB2
/CS ≥ Vcc-0.2V, /UB=/LB ≥ Vcc-0.2V
(/UB,/LB Controlled) Other inputs = 0 or Vcc
100
5
uA
uA
/PD ≤ Vss+0.2V
AMIC Technology, Corp.
(May, 2005, Version 0.0)
4
A64S06162A
Preliminary
Data Retention Electric Characteristic
TA = -40℃ to 85℃ (Normal), unless otherwise specified
Item
Symbol
Test Condition
Min
Max
Unit
Typ.
(1)
VDR
/CS=/PD=VIH＞Vcc-0.2V or
/UB,/LB≥Vcc-0.2V,
VIN≥VCC-0.2V or
2.4
3.3
V
Voltage for Data
Retention
VIN≤VSS + 0.2V
Vcc=2.4V,
100
uA
Data Retention
Current
IccDR
/CS=/PD=VIH＞Vcc-0.2V or
/UB,/LB≥Vcc-0.2V,
VIN≥VCC-0.2V or
VIN≤VSS + 0.2V
Chip Deselect to Data
Retention Time
Refer to data retention wave
form
0
-
-
-
-
ns
tCDR
tR
tRC
ns
Operating Recovery
Time
(1) Vcc = 2.4V, TA = 25℃
Data Retention Wave Form
Data Retention Mode
VCC
2.7V
tCDR
tR
VIH
VDR
/CS ≥ Vcc-0.2V
/CS
VSS
AMIC Technology, Corp.
(May, 2005, Version 0.0)
5
A64S06162A
Preliminary
AC TEST CONDITIONS
TA = -40℃ to 85℃ (Normal), unless otherwise specified
PARAMETER
Value
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load
0.4V to 2.2V
5ns
1.5V
CL = 30pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : (1) Including jig and scope capacitance
POWER UP TIME
At starting, maintain stable power for a minimum 100us with /CS = /PD = high.
AMIC Technology, Corp.
(May, 2005, Version 0.0)
6
A64S06162A
Preliminary
AC CHARACTERISTICS (Vcc = 2.7 ~ 3.3V, TA = -40 to 85℃)
70ns
Parameter List
Symbol
Unit
Min
70
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tRC
tAS
Address Set-up Time
Address Access Time
tAA
70
70
35
70
Chip Select to Output
tCO
tOE
R
E
A
D
Output Enable to Valid Output
/UB,/LB Access Time
tBA
Chip select to Low-Z Output
/UB, /LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
/UB, /LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Page Read Precharge Time
Page Read Cycle Time
tLZ
10
10
5
tBLZ
tOLZ
tHZ
0
25
25
25
tBHZ
tOHZ
tOH
tP
0
0
10
10
35
tPRC
tPAA
tWC
tCW
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
Page Read Address Access Time
Write Cycle Time
35
70
60
60
60
50
0
Chip Select to End of Write
Address Valid to End of Write
/UB, /LB Valid to End of Write
Write Pulse Width
W
R
I
Write Recovery Time
Write to Output High-Z
0
20
T
E
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
Page Write Precharge Time
Page Write Cycle Time
40
0
tOW
tP
5
10
35
20
0
tPWC
tPDW
tPDH
Page Write Data to Write Time overlap
Page Write Data Hold from Write Time
AMIC Technology, Corp.
(May, 2005, Version 0.0)
7
A64S06162A
Preliminary
TIMING DIAGRAMS
READ CYCLE (/PD = /WE = VIH)
tRC
Address(A2 – A19)
Page Address(A0 – A1)
tAA
tP
tCO
/CS
tAS
tLZ(2)
tBA
/UB,/LB
/OE
tOE
tHZ(1,2)
tOHZ(1)
DATA OUT
Note (READ CYCLE) :
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels
2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given
device and from device to device.
3. /WE is high for the read cycle.
4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us.
AMIC Technology, Corp.
(May, 2005, Version 0.0)
8
A64S06162A
Preliminary
PAGE READ CYCLE (/PD = /WE = VIH)
tRC
Address (A2-A19)
tPRC
Page Corresponding (A0-A1)
Addresses
tP(5)
tAA
tPAA
tCO
/CS
tAS
tLZ(2)
tBA
/UB,/LB
/OE
tOE
tHZ(1,2)
tOHZ(1)
DATA OUT
Note (PAGE MODE READ CYCLE) :
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels
2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given
device and from device to device.
3. /WE is high for the read cycle.
4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us.
5. tP (precharge time) should be guaranteed for new Address.
6. After initial page access is accomplished, the page mode operation provides fast read access speed of
random locations within that page
AMIC Technology, Corp.
(May, 2005, Version 0.0)
9
A64S06162A
Preliminary
WRITE CYCLE 1 (/CS Controlled, /PD = VIH)
tWC
ADDR
tWR
tAS
tCW
/CS
tAW
tBW
tP
/UB,/LB
/WE
tWP
tDW
tDH
High-Z
High-Z
Data In
Data Valid
High-Z
tWC
Data
Out
WRITE CYCLE 2 (/UB /LB Controlled, /PD = VIH
ADDR
tWR(4)
tCW(2)
/CS
tP
tAW
tBW
/UB,/LB
tAS(3)
tWP
/WE
tDW
tDH
Data In
Data Valid
High-Z
Data
Out
Notes (WRITE CYCLE) :
1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest
transition among /CS going low and /WE going low: A write end at the earliest
transition among /CS going high and /WE going high. tWP is measured from the
beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends
as /CS.
5. Do not access device with cycle timing shorter than tRC for continuous periods > 16us.
AMIC Technology, Corp.
(May, 2005, Version 0.0)
10
A64S06162A
Preliminary
PAGE MODE WRITE CYCLE (/PD = VIH)
tWC
Address(A2 – A19)
tPWC
Page Address(A0 – A1)
tP
tCW(3)
tBW
/CS
tAS(1)
/UB,/LB
tWP(1)
/WE
tPDH
tPDW
tDW tDH
tPDW tPDH
DATA IN
DATA OUT
High-Z
Notes (PAGE MODE WRITE CYCLE) :
1. A write occurs during the overlap of a low /CS and low /WE.
A write begins at the latest transition among /CS going low in initial page mode .
A write end at the earliest transition among /CS going high and Page Address transition.
tWP is measured from the beginning of write to the end of write in initial page access.
2. tPWC is measured from Page Address trasition (After initial page access)
to Page Address transition or /CS going high.
2. tCW is measured from the later of /CS going low to the end of write in initial page access.
3. tAS is measured from the address valid to the beginning of write.
4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us.
5. tP (precharge time) should be guaranteed for new Page Address.
6. After initial page access is accomplished, the page mode operation provides fast read access speed of
random locations within that page
AMIC Technology, Corp.
(May, 2005, Version 0.0)
11
A64S06162A
Preliminary
Deep Power Down Mode
100us
1us
/PD
Wake Up
Normal Operation
Normal Operation
Deep Power Down Mode
Mode
/CS
AMIC Technology, Corp.
(May, 2005, Version 0.0)
12
A64S06162A
Preliminary
Ordering Information
Part No.
Package
Access Time
(ns)
Operating Current
Max. (mA)
Power Down Mode
Standby Current
Max. (µA)
A64S06162AG-70
A64S06162AG-70F
A64S06162AG-70U
A64S06162AG-70UF
70
70
70
70
20
20
20
20
5
5
5
5
48B Mini BGA
48B Pb-Free Mini BGA
48B Mini BGA
48B Pb-Free Mini BGA
•Note : -U is for -40c ~ 85c temperature grade
AMIC Technology, Corp.
(May, 2005, Version 0.0)
13
A64S06162A
Preliminary
PACKAGE DIMENSION FOR BGA TYPE
Unit: millimeters
48 BALL FINE PITCH 6mm x 8mm BGA(0.75mm ball pitch)
Bottom View
Top View
B
A1 INDEX MARK
B
B1
6
5
4
3
2
1
#A1
B/2
Side View
D
A
Y
C
Min
Typical
0.75
6.00
3.75
8.00
5.25
0.35
-
Max
-
A
B
-
5.90
6.10
-
B1
C
-
7.90
8.10
-
C1
D
-
0.30
0.40
1.20
0.90
0.30
0.10
E
-
E1
E2
Y
-
0.20
-
-
0.25
-
AMIC Technology, Corp.
(May, 2005, Version 0.0)
14
相关型号：
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16M(1M x 16bit) Normal mode & Page mode with Deep Power Down Static Random Access Memory
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