A2505PN-F [AMICC]
16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface; 16兆位，低电压，串行闪存的85MHz SPI总线接口
| 型号： | A2505PN-F |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface |
| 文件： | 总38页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A25L16P Series
16 Mbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
Preliminary
Document Title
16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
0.2
Initial issue
March 10, 2006
March 23, 2006
March 27, 2006
Preliminary
Change part no. from A25L160P to A25L16P
Change the frequency to 70 MHz
Add the Fast Read Dual Input-Output Mode
Add QFN 8L (5 x 6mm) package type
Top or bottom boot block configuration available
Change the frequency to 85 MHz
0.3
0.4
0.5
April 20, 2006
December 5, 2006
February 6, 2007
Remove the REMS mode
Correct the A25LPT memory organization of Table 2-1
Reduce the options of protected area size to all sectors
protected and all sectors unprotected
Modify the ICC1 and ICC3 of Table 10
Modify the tW and tBE of Table 11
0.6
Add transient voltage (<20ns) on any pin to ground potential spec.
April 24, 2007
PRELIMINARY (April, 2007, Version 0.6)
AMIC Technology Corp.
A25L16P Series
16 Mbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
Preliminary
FEATURES
GENERAL DESCRIPTION
16 Mbit of Flash Memory
The A25L16P is a 16 Mbit (2M x 8) Serial Flash Memory,
with advanced write protection mechanisms, accessed by a
high speed SPI-compatible bus.
Flexible Sector Architecture (4/4/8/16/32)KB/64x31 KB
Bulk Erase (16 Mbit) in 20s (typical)
Sector Erase (512 Kbit) in 1s (typical)
Page Program (up to 256 Bytes) in 1.5ms (typical)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
85MHz Clock Rate (maximum)
Fast Read Dual Operation Instruction (3Bh/BBh)
Deep Power-down Mode 1µA (typical)
Top or Bottom Boot Block Configuration Available
Electronic Signature
The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The memory is organized as 32 sectors, each containing 256
pages. Each page is 256 bytes wide. Thus, the whole
memory can be viewed as consisting of 8192 pages, or
2,097,152 bytes.
The whole memory can be erased using the Bulk Erase
instruction, or a sector at a time, using the Sector Erase
instruction.
- JEDEC Standard Two-Byte Signature (2015h, Bottom;
or 2025, Top)
- RES Instruction, One-Byte, Signature (14h)
Package Options
- 8-pin SOP (209mil), 16-pin SOP, or 8-pin QFN
- All Pb-free (Lead-free) products are ROHS complaint
Pin Configurations
SO8 Connections
SO16 Connections
QFN8 Connections
A25L16P
HOLD
VCC
DU
DU
DU
DU
S
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A25L16P
A25L16P
DIO
DU
DU
DU
DU
VSS
VCC
1
8
S
DIO
VCC
S
DO
1
2
3
4
8
7
6
5
2
3
4
7
6
5
HOLD
C
DO
HOLD
C
DIO
W
VSS
W
VSS
DO
W
Note:
DU = Do not Use
PRELIMINARY (April, 2007, Version 0.6)
1
AMIC Technology Corp.
A25L16P Series
Block Diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
DIO
DO
I/O Shift Register
Address register
and Counter
256 Byte
Data Buffer
Status
Register
1FFFFFh
Size of the
read-only
memory area
00000h
000FFh
256 Byte (Page Size)
X Decoder
Pin Descriptions
Pin No.
Logic Symbol
Description
VCC
C
Serial Clock
Serial Data Input 1
DIO
DO
Serial Data Output 2
DIO
C
DO
Chip Select
S
S
A25L16P
Write Protect
Hold
W
W
HOLD
HOLD
VCC
Supply Voltage
Ground
VSS
VSS
Notes:
1. The DIO is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
2. The DO is also used as an input pin when the Fast Read
Dual Input-Output instruction is executed.
PRELIMINARY (April, 2007, Version 0.6)
2
AMIC Technology Corp.
A25L16P Series
SIGNAL DESCRIPTION
Serial Data Output (DO). This output signal is used to
transfer data serially out of the device. Data is shifted out on
the falling edge of Serial Clock (C).
The DO pin is also used as an input pin when the Fast Read
Dual Input-Output Function is executed.
Serial Data Input / Output (DIO). This input signal is used to
transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are
latched on the rising edge of Serial Clock (C).
The DIO pin is also used as an output pin when the Fast
Read Dual Output function and Fast Read Dual Input-Output
function are executed.
Serial Clock (C). This input signal provides the timing of the
serial interface. Instructions, addresses, or data present at
Serial Data Input (DIO) are latched on the rising edge of
Serial Clock (C). Data on Serial Data Output (DO) changes
after the falling edge of Serial Clock (C).
Status Register cycle is in progress, the device will be in the
Standby mode (this is not the Deep Power-down mode).
Driving Chip Select ( ) Low enables the device, placing it in
S
the active power mode.
After Power-up, a falling edge on Chip Select ( ) is required
S
prior to the start of any instruction.
Hold (
). The Hold (
) signal is used to pause
HOLD
HOLD
any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DIO) and Serial
Clock (C) are Don’t Care. To start the Hold condition, the
device must be selected, with Chip Select ( ) driven Low.
S
Write Protect ( ). The main purpose of this input signal is
W
to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the
values in the BP2, BP1 and BP0 bits of the Status Register).
Chip Select ( ). When this input signal is High, the device
S
is deselected and Serial Data Output (DO) is at high
impedance. Unless an internal Program, Erase or Write
SPI MODES
the falling edge of Serial Clock (C).
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
PRELIMINARY (April, 2007, Version 0.6)
3
AMIC Technology Corp.
A25L16P Series
Figure 1. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA)
SDI
SCK
= (0, 0) or (1, 1)
C Q D
C Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Other)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
W HOLD
S
W HOLD
S
W HOLD
Note: The Write Protect ( ) and Hold (
W
) signals should be driven, High or Low as appropriate.
HOLD
Figure 2. SPI Modes Supported
CPOL CPHA
0
1
0
1
C
C
DIO
DO
MSB
MSB
PRELIMINARY (April, 2007, Version 0.6)
4
AMIC Technology Corp.
A25L16P Series
OPERATING FEATURES
Page Programming
Status Register
To program one data byte, two instructions are required:
Write Enable (WREN), which is one byte, and a Page
Program (PP) sequence, which consists of four bytes plus
data. This is followed by the internal Program cycle (of
duration tPP).
To spread this overhead, the Page Program (PP) instruction
allows up to 256 bytes to be programmed at a time (changing
bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific
instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether
the memory is busy with a Write Status Register, Program or
Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the
status of the internal Write Enable Latch, BP2, BP1, and BP0
bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile.
They define the size of the area to be software protected
against Program and Erase instructions.
Sector Erase and Bulk Erase
SRWD bit. The Status Register Write Disable (SRWD) bit is
The Page Program (PP) instruction allows bits to be reset
from 1 to 0. Before this can be applied, the bytes of memory
need to have been erased to all 1s (FFh). This can be
achieved, a sector at a time, using the Sector Erase (SE)
instruction, or throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal Erase cycle (of
duration tSE or tBE).
operated in conjunction with the Write Protect ( ) signal.
W
The Status Register Write Disable (SRWD) bit and Write
Protect (
) signal allow the device to be put in the
W
Hardware Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits.
The Erase instruction must be preceded by a Write Enable
(WREN) instruction.
Protection Modes
The environments where non-volatile memory devices are
used can be very noisy. No SPI device can operate correctly
in the presence of excessive noise. To help combat this, the
A25L16P boasts the following data protection mechanisms:
Power-On Reset and an internal timer (tPUW) can provide
protection against inadvertant changes while the power
supply is outside the operating specification.
Program, Erase and Write Status Register instructions
are checked that they consist of a number of clock pulses
that is a multiple of eight, before they are accepted for
execution.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register
(WRSR), Program (PP) or Erase (SE or BE) can be achieved
by not waiting for the worst case delay (tW, tPP, tSE, or tBE).
The Write In Progress (WIP) bit is provided in the Status
Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle,
Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep
Power-Down Modes
All instructions that modify data must be preceded by a
Write Enable (WREN) instruction to set the Write Enable
Latch (WEL) bit. This bit is returned to its reset state by
the following events:
When Chip Select ( ) is Low, the device is enabled, and in
S
the Active Power mode.
When Chip Select ( ) is High, the device is disabled, but
S
- Power-up
could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Stand-by Power
mode. The device consumption drops to ICC1.
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
The Deep Power-down mode is entered when the specific
instruction (the Enter Deep Power-down Mode (DP)
instruction) is executed. The device consumption drops
further to ICC2. The device remains in this mode until another
specific instruction (the Release from Deep Power-down
Mode and Read Electronic Signature (RES) instruction) is
executed.
All other instructions are ignored while the device is in the
Deep Power-down mode. This can be used as an extra
software protection mechanism, when the device is not in
active use, to protect the device from inadvertent Write,
Program or Erase instructions.
- Bulk Erase (BE) instruction completion
The Write Protect ( ) signal allows the Block Protect
W
(BP2, BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be protected. This is the Hardware
Protected Mode (HPM).
In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protection
from inadvertant Write, Program and Erase instructions,
as all instructions are ignored except one particular
instruction (the Release from Deep Power-down
instruction).
PRELIMINARY (April, 2007, Version 0.6)
5
AMIC Technology Corp.
A25L16P Series
Table 1. Protected Area Sizes
A25L16PT Top Boot Block
Status Register Content
Memory Content
BP2 Bit
BP1 Bit
BP0 Bit
Protected Area
Unprotected Area
0
1
0
1
0
1
none
All sectors (32 sectors: 0 to 31)
All sectors1 (32 sectors: 0 to 31)
none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
2. The sector 31 include sector 31-0, sector 31-1, sector 31-2, sector 31-3 and sector 31-4.
A25L16PU Bottom Boot Block
Status Register Content
Memory Content
BP2 Bit
BP1 Bit
BP0 Bit
Protected Area
Unprotected Area
0
1
0
1
0
1
none
All sectors (32 sectors: 0 to 31)
All sectors1 (32 sectors: 0 to 31)
none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
2. The sector 0 include sector 0-0, sector 0-1, sector 0-2, sector 0-3 and sector 0-4.
Hold Condition
with Serial Clock (C) being Low, the Hold condition ends
after Serial Clock (C) next goes Low. This is shown in Figure
3.
During the Hold condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DIO) and Serial
Clock (C) are Don’t Care.
The Hold (
) signal is used to pause any serial
HOLD
communications with the device without resetting the
clocking sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle
that is currently in progress.
To enter the Hold condition, the device must be selected,
Normally, the device is kept selected, with Chip Select (
)
S
with Chip Select ( ) Low.
S
The Hold condition starts on the falling edge of the Hold
driven Low, for the whole duration of the Hold condition. This
is to ensure that the state of the internal logic remains
unchanged from the moment of entering the Hold condition.
(
) signal, provided that this coincides with Serial Clock
HOLD
(C) being Low (as shown in Figure 3.).
The Hold condition ends on the rising edge of the Hold
If Chip Select ( ) goes High while the device is in the Hold
S
condition, this has the effect of resetting the internal logic of
the device. To restart communication with the device, it is
(
) signal, provided that this coincides with Serial Clock
HOLD
(C) being Low.
necessary to drive Hold (
) High, and then to drive
HOLD
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
Chip Select ( ) Low. This prevents the device from going
S
back to the Hold condition.
Figure 3. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
PRELIMINARY (April, 2007, Version 0.6)
6
AMIC Technology Corp.
A25L16P Series
MEMORY ORGANIZATION
The memory is organized as:
Each page can be individually programmed (bits are
programmed from 1 to 0). The device is Sector or Bulk
Erasable (bits are erased from 0 to 1) but not Page Erasable.
2,097,152 bytes (8 bits each)
32 sectors (one (4/4/8/16/32) Kbytes & 64x31 Kbytes
each)
8192 pages (256 bytes each).
Table 2-1. A25L16PT Memory Organization
Sector
31-4
31-4
31-2
31-1
31-0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Sector Size (Kbytes)
Address Range
4
1FF000h
1FE000h
1FC000h
1F8000h
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
F0000h
E0000h
D0000h
C0000h
B0000h
A0000h
90000h
1FFFFFh
1FEFFFh
1FDFFFh
1FBFFFh
1F7FFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
FFFFFh
EFFFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
4
8
16
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
8
80000h
8FFFFh
7
70000h
7FFFFh
6
60000h
6FFFFh
5
50000h
5FFFFh
4
40000h
4FFFFh
3
30000h
3FFFFh
2
20000h
2FFFFh
1
10000h
1FFFFh
0
00000h
0FFFFh
PRELIMINARY (April, 2007, Version 0.6)
7
AMIC Technology Corp.
A25L16P Series
Table 2-2. A25L16PU Memory Organization
Sector
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Sector Size (Kbytes)
Address Range
1FFFFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
FFFFFh
EFFFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
8FFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
07FFFh
03FFFh
01FFFh
00FFFh
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
16
8
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
F0000h
E0000h
D0000h
C0000h
B0000h
A0000h
90000h
80000h
70000h
60000h
50000h
40000h
30000h
20000h
10000h
08000h
04000h
02000h
01000h
00000h
8
7
6
5
4
3
2
1
0-4
0-3
0-2
0-1
0-0
4
4
PRELIMINARY (April, 2007, Version 0.6)
8
AMIC Technology Corp.
A25L16P Series
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input (DIO) is sampled on the first rising edge of
after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk
Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), Write Disable (WRDI) or Deep Power-down (DP)
Serial Clock (C) after Chip Select ( ) is driven Low. Then,
S
instruction, Chip Select ( ) must be driven High exactly at a
S
byte boundary, otherwise the instruction is rejected, and is
the one-byte instruction code must be shifted in to the device,
most significant bit first, on Serial Data Input (DIO), each bit
being latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes
at Higher Speed (Fast_Read), Read Status Register (RDSR)
or Release from Deep Power-down, Read Device
Identification and Read Electronic Signature (RES)
instruction, the shifted-in instruction sequence is followed by
not executed. That is, Chip Select ( ) must driven High
S
when the number of clock pulses after Chip Select ( ) being
S
driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write
Status Register cycle, Program cycle or Erase cycle are
ignored, and the internal Write Status Register cycle,
Program cycle or Erase cycle continues unaffected.
a data-out sequence. Chip Select ( ) can be driven High
S
Table 3. Instruction Set
One-byte
Instruction Code
Address
Bytes
Dummy
Bytes
Data
Bytes
Instruction
WREN
Description
Write Enable
Write Disable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
06h
04h
05h
01h
03h
0Bh
0
0
0
0
3
3
0
0
0
0
0
1
0
WRDI
0
RDSR
Read Status Register
Write Status Register
1 to ∞
1
WRSR
READ
Read Data Bytes
1 to ∞
1 to ∞
FAST_READ
Read Data Bytes at Higher Speed
FAST_READ_DUAL
_OUTPUT
Read Data Bytes at Higher Speed by
Dual Output (1)
00111011
10111011
3Bh
BBh
3
1
1 to ∞
1 to ∞
FAST_READ_DUAL
_INPUT-OUTPUT
Read Data Bytes at Higher Speed by
Dual Input and Dual Output (1)
3(2)
1(2)
PP
SE
Page Program
Sector Erase
0000 0010
1101 1000
02h
D8h
C7h
or
3
3
0
0
1 to 256
0
1100 0111
BE
Bulk Erase
0
0
0
or
01100000
60h
B9h
9Fh
DP
Deep Power-down
1011 1001
1001 1111
0
0
0
0
0
RDID
Read Device Identification
1 to 4
Release from Deep Power-down, and
Read Electronic Signature
0
0
3
0
1 to ∞
RES
1010 1011
ABh
Release from Deep Power-down
0
Note: (1) DIO = (D6, D4, D2, D0)
DO = (D7, D5, D3, D1)
(2) Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0)
DO = (A23, A21, A19, …….., A7, A5, A3, A1)
PRELIMINARY (April, 2007, Version 0.6)
9
AMIC Technology Corp.
A25L16P Series
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4.) sets the
Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every
Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving
Chip Select ( ) Low, sending the instruction code, and then
S
driving Chip Select ( ) High.
S
Figure 4. Write Enable (WREN) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DIO
High Impedance
DO
Write Disable (WRDI)
﹣ Power-up
The Write Disable (WRDI) instruction (Figure 5.) resets the
﹣ Write Disable (WRDI) instruction completion
﹣ Write Status Register (WRSR) instruction completion
﹣ Page Program (PP) instruction completion
﹣ Sector Erase (SE) instruction completion
﹣ Bulk Erase (BE) instruction completion
Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving
S
Chip Select ( ) Low, sending the instruction code, and then
driving Chip The Write Enable Latch (WEL) bit is reset under
the following conditions:
Figure 5. Write Disable (WRDI) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DIO
High Impedance
DO
PRELIMINARY (April, 2007, Version 0.6)
10
AMIC Technology Corp.
A25L16P Series
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the
Status Register to be read. The Status Register may be read
at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as
shown in Figure 6.
status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal
Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits
are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions.
These bits are written with the Write Status Register (WRSR)
instruction. When one or both of the Block Protect (BP2, BP1,
BP0) bits is set to 1, the relevant memory area (as defined in
Table 1.) becomes protected against Page Program (PP)
and Sector Erase (SE) instructions. The Block Protect (BP2,
BP1, BP0) bits can be written provided that the Hardware
Protected mode has not been set. The Bulk Erase (BE)
instruction is executed if, and only if, both Block Protect (BP2,
BP1, BP0) bits are 0.
Table 4. Status Register Format
b7
b0
SRWD
0
0
BP2 BP1 BP0 WEL WIP
Status Register
Write Protect
SRWD bit. The Status Register Write Disable (SRWD) bit is
Block Protect Bits
operated in conjunction with the Write Protect ( ) signal.
W
Write Enable Latch Bit
Write In Progress Bit
The Status Register Write Disable (SRWD) bit and Write
Protect (
) signal allow the device to be put in the
W
Hardware Protected mode (when the Status Register Write
The status and control bits of the Status Register are as
follows:
WIP bit. The Write In Progress (WIP) bit indicates whether
the memory is busy with a Write Status Register, Program or
Erase cycle. When set to 1, such a cycle is in progress, when
reset to 0 no such cycle is in progress.
Disable (SRWD) bit is set to 1, and Write Protect ( ) is
W
driven Low). In this mode, the non-volatile bits of the Status
Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer
accepted for execution.
WEL bit. The Write Enable Latch (WEL) bit indicates the
Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12
14 15
13
C
Instruction
DIO
Status Register Out
Status Register Out
High Impedance
DO
5
7
6
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
PRELIMINARY (April, 2007, Version 0.6)
11
AMIC Technology Corp.
A25L16P Series
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new
values to be written to the Status Register. Before it can be
Write Status Register cycle is in progress, the Status
Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0
when it is completed. When the cycle is completed, the Write
Enable Latch (WEL) is reset.
accepted,
a
Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded and executed, the
device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by
The Write Status Register (WRSR) instruction allows the
user to change the values of the Block Protect (BP2, BP1,
BP0) bits, to define the size of the area that is to be treated
as read-only, as defined in Table 1. The Write Status
Register (WRSR) instruction also allows the user to set or
reset the Status Register Write Disable (SRWD) bit in
S
driving Chip Select ( ) Low, followed by the instruction code
and the data byte on Serial Data Input (DIO).
The instruction sequence is shown in Figure 7. The Write
Status Register (WRSR) instruction has no effect on b6, b5,
b1 and b0 of the Status Register. b6 and b5 are always read
as 0.
accordance with the Write Protect ( ) signal. The Status
W
Register Write Disable (SRWD) bit and Write Protect (
)
W
S
Chip Select ( ) must be driven High after the eighth bit of
signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction
is not executed once the Hardware Protected Mode (HPM) is
entered.
the data byte has been latched in. If not, the Write Status
Register (WRSR) instruction is not executed. As soon as
S
Chip Select ( ) is driven High, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the
Figure 7. Write Status Register (WRSR) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12
14 15
13
C
Status
Instruction
Register In
7
6
5
4
3
2
1
0
DIO
DO
High Impedance
MSB
PRELIMINARY (April, 2007, Version 0.6)
12
AMIC Technology Corp.
A25L16P Series
Table 5. Protection Modes
Memory Content
SRWD
Bit
Write Protection of the
Status Register
W
Signal
Mode
Protected Area1
Unprotected Area1
1
0
1
0
0
1
Status Register is Writable (if the
Software WREN instruction has set the
Protected WEL bit) The values in the
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
(SPM)
SRWD, BP2, BP1 and BP0 bits
can be changed
Status Register is Hardware write
protected The values in the
SRWD, BP2, BP1 and BP0 bits
cannot be changed
Hardware
Protected
(HPM)
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
0
1
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
Status Register are rejected, and are not accepted for
execution). As a consequence, all the data bytes in the
memory area that are software protected (SPM) by the
Block Protect (BP2, BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware
Protected Mode (HPM) can be entered:
The protection features of the device are summarized in Table
5.
When the Status Register Write Disable (SRWD) bit of the
Status Register is 0 (its initial delivery state), it is possible to
write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction, regardless of the whether Write Protect
by setting the Status Register Write Disable (SRWD) bit
after driving Write Protect ( ) Low
(
) is driven High or Low.
W
W
When the Status Register Write Disable (SRWD) bit of the
Status Register is set to 1, two cases need to be considered,
or by driving Write Protect (
) Low after setting the
W
Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM)
once entered is to pull Write Protect ( ) High.
depending on the state of Write Protect ( ):
W
If Write Protect ( ) is driven High, it is possible to write
W
W
to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect ( ) is permanently tied High, the Hardware
W
Protected Mode (HPM) can never be activated, and only the
Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
If Write Protect (W) is driven Low, it is not possible to
write to the Status Register even if the Write Enable
Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction. (Attempts to write to the
PRELIMINARY (April, 2007, Version 0.6)
13
AMIC Technology Corp.
A25L16P Series
Read Data Bytes (READ)
therefore, be read with a single Read Data Bytes (READ)
instruction. When the highest address is reached, the
address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
S
The device is first selected by driving Chip Select ( ) Low.
The instruction code for the Read Data Bytes (READ)
instruction is followed by a 3-byte address (A23-A0), each bit
being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on
Serial Data Output (DO), each bit being shifted out, at a
maximum frequency fR, during the falling edge of Serial Clock
(C).
The Read Data Bytes (READ) instruction is terminated by
S
S
driving Chip Select ( ) High. Chip Select ( ) can be driven
High at any time during data output. Any Read Data Bytes
(READ) instruction, while an Erase, Program or Write cycle is
in progress, is rejected without having any effects on the
cycle that is in progress.
The instruction sequence is shown in Figure 8. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
DIO
DO
Instruction
24-Bit Address
23
21
2
1
0
22
3
MSB
Data Out 2
Data Out 1
High Impedance
5
4
1
0
6
3
2
7
7
MSB
PRELIMINARY (April, 2007, Version 0.6)
14
AMIC Technology Corp.
A25L16P Series
Read Data Bytes at Higher Speed (FAST_READ)
Speed (FAST_READ) instruction. When the highest address
is reached, the address counter rolls over to 000000h,
allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ)
S
The device is first selected by driving Chip Select ( ) Low.
The instruction code for the Read Data Bytes at Higher
Speed (FAST_READ) instruction is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then the
memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum
frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher
S
instruction is terminated by driving Chip Select ( ) High.
S
Chip Select ( ) can be driven High at any time during data
output. Any Read Data Bytes at Higher Speed (FAST_READ)
instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle
that is in progress.
Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
DIO
DO
Instruction
24-Bit Address
21
23
2
1
0
22
3
MSB
High Impedance
S
C
32 33 34 35 36 37 38 39 40
Dummy Byte
41 42 43 44 45 46 47
7
6
5
4
3
2
0
1
DIO
DO
Data Out 2
Data Out 1
0
5
4
1
5
4
1
6
3
2
0
6
3
2
7
7
7
MSB
MSB
MSB
Note: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6)
15
AMIC Technology Corp.
A25L16P Series
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the
Fast_Read (0Bh) instruction except the data is output on two
pins, DO and DIO, instead of just DO. This allows data to be
transferred from the A25L16P at twice the rate of standard
SPI devices.
Similar to the Fast Read instruction, the Fast Read Dual
Output instruction can operate at the highest possible
frequency of fC (See AC Characteristics). This is
accomplished by adding eight “dummy” clocks after the
24-bit address as shown in figure 10. The dummy clocks
allow the device’s internal circuits additional time for setting
up the initial address. The input data during the dummy
clocks is “don’t care”. However, the DIO pin should be
high-impedance prior to the falling edge of the first data out
clock.
Figure 10. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
DIO
DO
Instruction
24-Bit Address
21
23
2
1
0
22
3
MSB
High Impedance
S
C
32 33 34 35 36 37 38 39 40
Dummy Byte
41 42 43 44 45 46 47
DIO switches from input to output
7
6
5
4
3
2
0
6
4
2
0
6
4
2
0
6
4
2
3
0
1
6
7
4
5
2
3
0
1
1
DIO
DO
3
1
3
5
7
5
1
5
7
7
7
MSB
MSB
MSB
Data Out 1
Data Out 2
Data Out 3
Data Out 4
Note: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6)
16
AMIC Technology Corp.
A25L16P Series
Fast Read Dual Input-Output (BBh)
The Fast Read Dual Input-Output (BBh) instruction is similar
to the Fast_Read (0Bh) instruction except the data is input
and output on two pins, DO and DIO, instead of just DO. This
allows data to be transferred from the A25L16P at twice the
rate of standard SPI devices.
Similar to the Fast Read instruction, the Fast Read Dual
Output instruction can operate at the highest possible
frequency of fC (See AC Characteristics). This is
accomplished by adding four “dummy” clocks after the 24-bit
address as shown in figure 11. The dummy clocks allow the
device’s internal circuits additional time for setting up the
initial address. The input data during the dummy clocks is
“don’t care”. However, the DIO and DO pins should be
high-impedance prior to the falling edge of the first data out
clock.
Figure 11. FAST_READ_DUAL_INPUT-OUTPUT Instruction Sequence and Data-Out Sequence
Note: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6)
17
AMIC Technology Corp.
A25L16P Series
Page Program (PP)
The Page Program (PP) instruction allows bytes to be
programmed in the memory (changing bits from 1 to 0).
Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
programmed correctly within the same page. If less than 256
Data bytes are sent to device, they are correctly programmed
at the requested addresses without having any effects on the
other bytes of the same page.
S
Chip Select ( ) must be driven High after the eighth bit of
the last data byte has been latched in, otherwise the Page
Program (PP) instruction is not executed.
The Page Program (PP) instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code, three
S
As soon as Chip Select ( ) is driven High, the self-timed
address bytes and at least one data byte on Serial Data Input
(DIO). If the 8 least significant address bits (A7-A0) are not
all zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the
same page (from the address whose 8 least significant bits
Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Page Program cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the
Write Enable Latch (WEL) bit is reset.
S
(A7-A0) are all zero). Chip Select ( ) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 12. If more than
256 bytes are sent to the device, previously latched data are
discarded and the last 256 data bytes are guaranteed to be
A Page Program (PP) instruction applied to a page which is
protected by the Block Protect (BP2, BP1, BP0) bits (see
Table 2 and Table 1) is not executed.
Figure 12. Page Program (PP) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
Data Byte 1
23
21
2
1
0
22
3
5
4
1
0
6
3
2
DIO
7
MSB
MSB
S
C
40 41 42 43 44 45 46
Data Byte 2
48 49 50 51 52 53 54 55
Data Byte 3
47
Data Byte 256
DIO
5
4
1
5
4
1
0
6
3
2
0
6
7
3
2
5
4
1
6
3
2
0
7
7
MSB
MSB
MSB
Note: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6)
18
AMIC Technology Corp.
A25L16P Series
Sector Erase (SE)
The Sector Erase (SE) instruction sets all bits to 1 (FFh).
Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
S
instruction is not executed. As soon as Chip Select ( ) is
driven High, the self-timed Sector Erase cycle (whose
duration is tBE) is initiated. While the Sector Erase cycle is in
progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Sector Erase (SE) instruction is executed only if all
Block Protect (BP2, BP1, BP0) bits are 0. The Sector
Erase (SE) instruction is ignored if one, or more, sectors
are protected.
The Sector Erase (SE) instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code on Serial
S
Data Input (DIO). Chip Select ( ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 13. Chip Select
S
(
) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Sector Erase
Figure 13. Sector Erase (SE) Instruction Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
Instruction
24-Bit Address
22
3
23
21
2
1
0
DIO
MSB
Notes: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6)
19
AMIC Technology Corp.
A25L16P Series
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh).
Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
S
instruction is not executed. As soon as Chip Select ( ) is
driven High, the self-timed Bulk Erase cycle (whose duration
is tBE) is initiated. While the Bulk Erase cycle is in progress,
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Bulk Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all
Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase
(BE) instruction is ignored if one, or more, sectors are
protected.
The Bulk Erase (BE) instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code on Serial
S
Data Input (DIO). Chip Select ( ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 14. Chip Select
S
(
) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Bulk Erase
Figure 14. Bulk Erase (BE) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DIO
or
Notes: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6)
20
AMIC Technology Corp.
A25L16P Series
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only
way to put the device in the lowest consumption mode (the
Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
The Deep Power-down mode automatically stops at
Power-down, and the device always Powers-up in the
Standby mode.
The Deep Power-down (DP) instruction is entered by driving
S
Chip Select ( ) Low, followed by the instruction code on
S
Serial Data Input (DIO). Chip Select ( ) must be driven Low
S
Driving Chip Select ( ) High deselects the device, and puts
for the entire duration of the sequence. The instruction
sequence is shown in Figure 15.
the device in the Standby mode (if there is no internal cycle
currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only
be entered by executing the Deep Power-down (DP)
S
Chip Select ( ) must be driven High after the eighth bit of
the instruction code has been latched in, otherwise the Deep
Power-down (DP) instruction is not executed. As soon as
instruction, to reduce the standby current (from ICC1 to ICC2
as specified in DC Characteristics Table.).
,
S
Chip Select ( ) is driven High, it requires a delay of tDP
before the supply current is reduced to ICC2 and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase,
Program or Write cycle is in progress, is rejected without
having any effects on the cycle that is in progress.
Once the device has entered the Deep Power-down mode,
all instructions are ignored except the Release from Deep
Power-down and Read Electronic Signature (RES)
instruction. This releases the device from this mode. The
Release from Deep Power-down and Read Electronic
Signature (RES) instruction also allows the Electronic Signa-
ture of the device to be output on Serial Data Output (DO).
Figure 15. Deep Power-down (DP) Instruction Sequence
S
tDP
1
3
0
2
4
5
6
7
C
Instruction
DO
Stand-by Mode
Deep Power-down Mode
PRELIMINARY (April, 2007, Version 0.6)
21
AMIC Technology Corp.
A25L16P Series
Read Device Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit
manufacturer identification code to be read, followed by two
bytes of device identification. The manufacturer identification
is assigned by JEDEC, and has the value 37h, plus the
continuation identification for AMIC Technology. The device
identification is assigned by the device manufacturer, and
indicates the memory in the first bytes (20h), and the
memory capacity of the device in the second byte (15h,
bottom) or (25h, top).
Then, the 8-bit instruction code for the instruction is shifted in.
This is followed by the 32-bit device identification, stored in
the memory, being shifted out on Serial Data Output (DO),
each bit being shifted out during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 16. The Read
Identification (RDID) instruction is terminated by driving Chip
S
Select ( ) High at any time during data output.
Any Read Identification (RDID) instruction while an Erase, or
Program cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
S
When Chip Select ( ) is driven High, the device is put in the
Stand-by Power mode. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive,
decode and execute instructions.
S
The device is first selected by driving Chip Select ( ) Low.
Table. Read Identification (READ_ID) Data-Out Sequence
Manufacture Identification
Device Identification
Memory Capacity
Continuation ID
Manufacture ID
Memory Type
20h
15h (Bottom)
25h (Top)
7Fh
37h
Figure 16. Read Identification (RDID) Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10
13 14 15 16 17 18
21 22 23 24 25 26
29 30 31 32 33 34
37 38 39
C
Instruction
DIO
DO
31
29
26
24 23
21
22
18
16 15 14 13
10
9
8
7
6
5
2
1
0
30
25
17
High Impedance
Continuation ID
Manufacture ID
Memory Type
Device ID
PRELIMINARY (April, 2007, Version 0.6)
22
AMIC Technology Corp.
A25L16P Series
edge of Serial Clock (C). Then, the 8-bit Electronic Signature,
stored in the memory, is shifted out on Serial Data Output
(DO), each bit being shifted out during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 17.
The Release from Deep Power-down and Read Electronic
Signature (RES) instruction is terminated by driving Chip
Release from Deep Power-down and Read
Electronic Signature (RES)
Once the device has entered the Deep Power-down mode,
all instructions are ignored except the Release from Deep
Power-down and Read Electronic Signature (RES)
instruction. Executing this instruction takes the device out of
the Deep Power-down mode.
S
Select ( ) High after the Electronic Signature has been read
The instruction can also be used to read, on Serial Data
Output (DO), the 8-bit Electronic Signature, whose value for
the A25L16P is 14h.
at least once. Sending additional clock cycles on Serial Clock
S
(C), while Chip Select ( ) is driven Low, cause the
Electronic Signature to be output repeatedly.
Except while an Erase, Program or Write Status Register
cycle is in progress, the Release from Deep Power-down and
Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and
can be applied even if the Deep Power-down mode has not
been entered.
S
When Chip Select ( ) is driven High, the device is put in the
Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by
Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the Stand-
Any Release from Deep Power-down and Read Electronic
Signature (RES) instruction while an Erase, Program or Write
Status Register cycle is in progress, is not decoded, and has
no effect on the cycle that is in progress.
S
by Power mode is delayed by tRES2, and Chip Select (
)
must remain High for at least tRES2 (max), as specified in AC
Characteristics Table . Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive,
decode and execute instructions.
S
The device is first selected by driving Chip Select ( ) Low.
The instruction code is followed by 3 dummy bytes, each bit
being latched-in on Serial Data Input (DIO) during the rising
Figure 17. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and
Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
C
tRES2
Instruction
3 Dummy Bytes
21
23
2
1
0
22
3
DIO
MSB
High Impedance
DO
5
4
1
0
6
3
2
7
MSB
Deep Power-down Mode
Stand-by Mode
Note: The value of the 8-bit Electronic Signature, for the A25L16P, is 14h.
PRELIMINARY (April, 2007, Version 0.6)
23
AMIC Technology Corp.
A25L16P Series
Figure 18. Release from Deep Power-down (RES) Instruction Sequence
S
tRES1
1
3
0
2
4
5
6
7
C
Instruction
DIO
High Impedance
DO
Deep Power-down Mode Stand-by Mode
previously in the Deep Power-down mode, though, the
transition to the Stand-by Power mode is delayed by tRES1
S
Driving Chip Select ( ) High after the 8-bit instruction byte
has been received by the device, but before the whole of the
8-bit Electronic Signature has been transmitted for the first
time (as shown in Figure 18.), still insures that the device is
put into Stand-by Power mode. If the device was not pre-
viously in the Deep Power-down mode, the transition to the
Stand-by Power mode is immediate. If the device was
,
S
and Chip Select ( ) must remain High for at least tRES1 (max),
as specified in AC Characteristics Table. Once in the
Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
PRELIMINARY (April, 2007, Version 0.6)
24
AMIC Technology Corp.
A25L16P Series
POWER-UP AND POWER-DOWN
These values are specified in Table 6.
At Power-up and Power-down, the device must not be
If the delay, tVSL, has elapsed, after VCC has risen above
VCC(min), the device can be selected for READ instructions
even if the tPUW delay is not yet fully elapsed.
S
selected (that is Chip Select ( ) must follow the voltage
applied on VCC) until VCC reaches the correct value:
V
CC (min) at Power-up, and then for a further delay of tVSL
At Power-up, the device is in the following state:
VSS at Power-down
The device is in the Standby mode (not the Deep
Power-down mode).
S
Usually a simple pull-up resistor on Chip Select ( ) can be
used to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is included.
The logic inside the device is held reset while VCC is less
than the POR threshold value, VWI – all operations are
disabled, and the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page
Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write
Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises above the
VWI threshold. However, the correct operation of the device
is not guaranteed if, by this time, VCC is still below VCC(min).
No Write Status Register, Program or Erase instructions
should be sent until the later of:
The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling,
to stabilize the VCC feed. Each device in a system should
have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when VCC drops from the operating voltage,
to below the POR threshold value, VWI, all operations are
disabled and the device does not respond to any instruction.
(The designer needs to be aware that if a Power-down
occurs while a Write, Program or Erase cycle is in progress,
some data corruption can result.)
-
tPUW after VCC passed the VWI threshold
tVSL afterVCC passed the VCC(min) level
Figure 19. Power-up Timing
VCC
VCC(max)
VCC(min)
tPU
Full Device Access
time
PRELIMINARY (April, 2007, Version 0.6)
25
AMIC Technology Corp.
A25L16P Series
Table 6. Power-Up Timing
Symbol
Parameter
Min.
2.7
10
Max.
Unit
V
VCC(min)
tPU
VCC (minimum)
VCC (min) to device operation
ms
Note: These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register
contains 00h (all Status Register bits are 0).
PRELIMINARY (April, 2007, Version 0.6)
26
AMIC Technology Corp.
A25L16P Series
Absolute Maximum Ratings*
*Comments
Stressing the device above the rating listed in the Absolute
Maximum Ratings" table may cause permanent damage to the
device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated
in the Operating sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to
the AMIC SURE Program and other relevant quality docu-
ments.
Storage Temperature (TSTG) . . . . . . . . . . . . -65°C to + 150°C
Lead Temperature during Soldering (Note 1)
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC+0.6V
Transient Voltage (<20ns) on Any Pin to Ground Potential . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VCC+2.0V
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . -0.6V to +4.0V
Electrostatic Discharge Voltage (Human Body model) (VESD)
(Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . -2000V to 2000V
Notes:
1. Compliant with JEDEC Std J-STD-020B (for small body,
Sn-Pb or Pb assembly).
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω ,
R2=500Ω)
DC AND AC PARAMETERS
This section summarizes the operating and measurement
conditions, and the DC and AC characteristics of the device.
The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the
Measurement Conditions summarized in the relevant tables.
Designers should check that the operating conditions in their
circuit match the measurement conditions when relying on
the quoted parameters.
Table 7. Operating Conditions
Symbol
VCC
Parameter
Min.
2.7
Max.
3.6
Unit
V
Supply Voltage
Ambient Operating Temperature
TA
–40
85
°C
Table 8. Data Retention and Endurance
Parameter
Condition
Min.
Max.
Unit
Erase/Program Cycles
At 85°C
At 85°C
100,000
Cycles per sector
Years
Data Retention
20
Note: 1. This is preliminary data
Table 9. Capacitance
Symbol
COUT
Parameter
Test Condition
VOUT = 0V
VIN = 0V
Min.
Max.
Unit
pF
Output Capacitance (DO)
8
6
CIN
Input Capacitance (other pins)
pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz.
PRELIMINARY (April, 2007, Version 0.6)
27
AMIC Technology Corp.
A25L16P Series
Table 10. DC Characteristics
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min.
Max.
± 2
Unit
µA
ILI
ILO
± 2
µA
ICC1
ICC2
Standby Current
10
10
µA
µA
S
S
= VCC, VIN = VSS or VCC
= VCC, VIN = VSS or VCC
Deep Power-down Current
C= 0.1VCC / 0.9.VCC at 50MHz, DO = open
C= 0.1VCC / 0.9.VCC at 33MHz, DO = open
16
12
mA
mA
ICC3
Operating Current (READ)
ICC4
ICC5
ICC6
ICC7
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
15
15
15
15
mA
mA
mA
mA
S
S
S
S
= VCC
= VCC
= VCC
= VCC
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.5
0.3VCC
VCC+0.4
0.4
V
V
V
V
0.7VCC
VOL
VOH
IOL = 1.6mA
IOH = –100µA
VCC–0.2
Note: 1. This is preliminary data at 85°C
Table 11. Instruction Times
Symbol
Alt.
Parameter
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Min.
Typ.
100
3
Max.
300
5
Unit
ms
ms
s
tW
tPP
tSE
1
3
tBE
Bulk Erase Cycle Time
20
40
s
Note: 1. At 85°C
2. This is preliminary data
Table 12. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
CL
Load Capacitance
30
pF
ns
V
Input Rise and Fall Times
Input Pulse Voltages
5
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
VCC / 2
Input Timing Reference Voltages
Output Timing Reference Voltages
V
V
Note: Output Hi-Z is defined as the point where data out is no longer driven.
PRELIMINARY (April, 2007, Version 0.6)
28
AMIC Technology Corp.
A25L16P Series
Figure 20. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC
PRELIMINARY (April, 2007, Version 0.6)
29
AMIC Technology Corp.
A25L16P Series
Table 13. AC Characteristics
Alt.
Parameter
Min. 5
Typ.
Max.5
Unit
Symbol
fC
fC
Clock Frequency for the following instructions: FAST_READ,
PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR
D.C.
85
MHz
fR
tCH
tCL
Clock Frequency for READ instructions
Clock High Time
D.C.
6
50
MHz
ns
1
1
tCLH
tCLL
Clock Low Time
5
ns
2
2
tCLCH
tCHCL
tSLCH
Clock Rise Time3 (peak to peak)
Clock Fall Time3 (peak to peak)
0.1
0.1
5
V/ns
V/ns
ns
tCSS
S
S
Active Setup Time (relative to C)
Not Active Hold Time (relative to C)
tCHSL
5
ns
tDVCH
tCHDX
tCHSH
tDSU
tDH
Data In Setup Time
Data In Hold Time
5
5
5
ns
ns
ns
S
S
S
Active Hold Time (relative to C)
Not Active Setup Time (relative to C)
Deselect Time
tSHCH
tSHSL
5
ns
ns
tCSH
100
2
tSHQZ
tCLQV
tCLQX
tHLCH
tDIS
tV
Output Disable Time
Clock Low to Output Valid
Output Hold Time
8
8
ns
ns
ns
ns
tHO
0
5
Setup Time (relative to C)
HOLD
HOLD
tCHHH
5
ns
Hold Time (relative to C)
tHHCH
tCHHL
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
5
5
ns
ns
ns
ns
2
tHHQX
tLZ
8
8
2
tHLQZ
tHZ
to Output High-Z
HOLD
4
4
tWHSL
tSHWL
Write Protect Setup Time
Write Protect Hold Time
20
ns
ns
µs
100
2
tDP
3
S
S
S
High to Deep Power-down Mode
2
2
tRES1
tRES2
30
30
µs
µs
High to Standby Mode without Electronic Signature Read
High to Standby Mode with Electronic Signature Read
tW
tpp
tSE
tBE
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Bulk Erase Cycle Time
100
1.5
1
300
5
ms
ms
s
3
20
40
s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
PRELIMINARY (April, 2007, Version 0.6)
30
AMIC Technology Corp.
A25L16P Series
Figure 21. Serial Input Timing
tSHSL
S
tSHCH
tCHSL
tSLCH
tCHSH
C
tCHCL
tDVCH
tCLCH
tCHDX
DIO
DO
MSB IN
LSB IN
High Impedance
Figure 22. Write Protect Setup and Hold Timing during WRSR when SRWD=1
W
tSHWL
tWHSL
S
C
DIO
High Impedance
DO
PRELIMINARY (April, 2007, Version 0.6)
31
AMIC Technology Corp.
A25L16P Series
Figure 23. Hold Timing
S
tHLCH
tCHHL
tHHCH
C
tCHHH
DIO
tHLQZ
tHHQX
DO
HOLD
Figure 24. Output Timing
S
tCH
C
ADDR.LSB IN
DIO
tCL
tSHQZ
tCLQV
tCLQV
tCLQX
tCLQX
DIO/DO
LSB OUT
tQLQH
tQHQL
* DIO is output pin for the Fast Read Dual Output instructions (3Bh)
PRELIMINARY (April, 2007, Version 0.6)
32
AMIC Technology Corp.
A25L16P Series
Part Numbering Scheme
X XX X X X X
A25
X
Package Material
Blank: normal
F: PB free
Temperature*
Package
M = SOP8
N = SOP16
Q = QFN8
Device Version*
Device Function
P = Page Program &
Sector Erase
Device Density
05 = 512 Kbit
40 = 4 Mbit
80 = 8 Mbit
16 = 16 Mbit
Device Voltage
L = 2.7-3.6V
Device Type
A25 = AMIC Serial Flash
* Optional
PRELIMINARY (April, 2007, Version 0.6)
33
AMIC Technology Corp.
A25L16P Series
Ordering Information
Part No.
Speed (MHz)
Active Read
Current
Program/Erase
Current
Standby
Current
Package
Typ. (mA)
Typ. (mA)
Typ. (μA)
A25L16PTM-F
A25L16PTM-UF
A25L16PTN-F
A25L16PTN-UF
A25L16PTQ-F
A25L16PTQ-UF
A25L16PUM-F
A25L16PUM-UF
A25L16PUN-F
A25L16PUN-UF
A25L16PUQ-F
A25L16PUQ-UF
8 Pb-Free Pin SOP (209mil)
8 Pb-Free Pin SOP (209mil)
16 Pin Pb-Free SOP
16 Pin Pb-Free SOP
8 Pin Pb-Free QFP
85
20
15
10
8 Pin Pb-Free QFP
8 Pb-Free Pin SOP (209mil)
8 Pb-Free Pin SOP (209mil)
16 Pin Pb-Free SOP
16 Pin Pb-Free SOP
8 Pin Pb-Free QFP
85
20
15
10
8 Pin Pb-Free QFP
-U is for industrial operating temperature range: -40°C ~ +85°C
PRELIMINARY (April, 2007, Version 0.6)
34
AMIC Technology Corp.
A25L16P Series
Package Information
SOP 8L (209mil) Outline Dimensions
unit: mm
8
5
1
4
C
D
GAGE PLANE
SEATING PLANE
θ
e
b
L
Dimensions in mm
Symbol
Min
1.75
0.05
1.70
0.35
0.19
5.13
7.70
5.18
Nom
1.95
0.15
1.80
0.42
0.20
5.23
7.90
5.28
1.27 BSC
0.65
-
Max
2.16
A
A1
A2
b
0.25
1.91
0.48
0.25
5.33
8.10
5.38
C
D
E
E1
e
L
0.50
0°
0.80
8°
θ
Notes:
Maximum allowable mold flash is 0.15mm at the package
ends and 0.25mm between leads
PRELIMINARY (April, 2007, Version 0.6)
35
AMIC Technology Corp.
A25L16P Series
Package Information
SOP 16L (300mil) Outline Dimensions
unit: inch
0.008 typ.
D
9
16
1
8
0.016 typ.
0.050 typ.
SEATING PLANE
θ
0.004max.
L
Dimensions in inch
Symbol
Min
0.093
0.004
0.398
0.291
0.394
0.016
0°
Max
A
A1
D
E
0.104
0.012
0.413
0.299
0.419
0.050
8°
H
L
θ
Notes:
1. Dimensions “D” does not include mold flash,
protrusions or gate burrs.
2. Dimensions “E” does not include interlead flash, or
protrusions.
PRELIMINARY (April, 2007, Version 0.6)
36
AMIC Technology Corp.
A25L16P Series
Package Information
QFN 8L (6 X 5 X 0.8mm) Outline Dimensions
unit: mm/mil
e
b
4
1
2
3
4
1
0.25 C
C0.30
Pin1 ID Area
8
7
6
5
5
8
E
E2
// 0.10 C
y C
Seating Plane
Dimensions in mm
Min Nom Max
Dimensions in mil
Symbol
Min
Nom
29.5
Max
A
A1
A3
b
0.700 0.750 0.800
0.000 0.020 0.050
0.203 REF
27.6
0.0
31.5
2.0
0.8
8.0 REF
15.8
0.350 0.400 0.480
13.8
18.9
D
5.900 6.000 6.100 232.3 236.2 240.2
3.200 3.400 3.600 126.0 133.9 141.7
4.900 5.000 5.100 192.9 196.9 200.8
3.800 4.000 4.200 149.6 157.5 165.4
D2
E
E2
L
0.500 0.600 0.750
1.270 BSC
19.7
23.6
50.0 BSC
-
29.5
e
y
0
-
0.080
0
3.2
Note:
1. Controlling dimension: millimeters
2. Leadframe thickness is 0.203mm (8mil)
PRELIMINARY (April, 2007, Version 0.6)
37
AMIC Technology Corp.
相关型号：
©2020 ICPDF网 联系我们和版权申明