M49000000S [AMD]
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit); 32兆位( 4米×8位/ 2的M× 16位) CMOS 3.0伏只,同时操作闪存和32兆位( 2M ×16位)型号: | M49000000S |
厂家: | AMD |
描述: | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) |
文件: | 总64页 (文件大小:1054K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am49DL32xBG
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 26645 Revision A Amendment +1 Issue Date July 19, 2002
PRELIMINARY
Am49DL32xBG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL32xG 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM with Page Mode
DISTINCTIVE CHARACTERISTICS
SOFTWARE FEATURES
MCP Features
■ Power supply voltage of 2.7 to 3.3 volt
■ Data Management Software (DMS)
—
AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
Eases sector erase limitations
■ High performance
—
Access time as fast as 70 ns
—
■ Package
■ Supports Common Flash Memory Interface (CFI)
■ Erase Suspend/Erase Resume
—
73-Ball FBGA
■ Operating Temperature
—
Suspends erase operations to allow programming in same
bank
—
–40°C to +85°C
■ Data# Polling and Toggle Bits
Flash Memory Features
—
Provides a software method of detecting the status of
program or erase cycles
ARCHITECTURAL ADVANTAGES
■ Unlock Bypass Program command
■ Simultaneous Read/Write operations
—
Reduces overall programming time when issuing multiple
program command sequences
—
Data can be continuously read from one bank while
executing erase/program functions in other bank
Zero latency between read and write operations
—
HARDWARE FEATURES
■ Secured Silicon (SecSi) Sector: Extra 256 Byte sector
■ Any combination of sectors can be erased
—
Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
Customer lockable: Sector is one-time programmable. Once
locked, data cannot be changed
■ Ready/Busy# output (RY/BY#)
—
Hardware method for detecting program or erase cycle
completion
—
■ Hardware reset pin (RESET#)
—
Hardware method of resetting the internal state machine to
reading array data
■ Zero Power Operation
Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
—
■ WP#/ACC input pin
—
Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
■ Top or bottom boot block
■ Manufactured on 0.17 µm process technology
■ Compatible with JEDEC standards
—
Acceleration (ACC) function accelerates program timing
■ Sector protection
—
Pinout and software compatible with single-power-supply
flash standard
—
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
PERFORMANCE CHARACTERISTICS
—
Temporary Sector Unprotect allows changing data in
protected sectors in-system
■ High performance
—
—
Access time as fast as 70 ns
Program time: 4 µs/word typical utilizing Accelerate function
pSRAM Features
■ Ultra low power consumption (typical values)
■ Power dissipation
—
—
—
2 mA active read current at 1 MHz
—
—
—
Operating: 40 mA maximum
Standby: 70 µA maximum
Deep power-down standby: 5 µA
10 mA active read current at 5 MHz
200 nA in standby or automatic sleep mode
■ CE1s# and CE2s Chip Select
■ Minimum 1 million write cycles guaranteed per sector
■ 20 Year data retention at 125°C
■ Power down features using CE1s# and CE2s
■ Data retention supply voltage: 2.7 to 3.3 volt
■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
■ 8-word page mode access
—
Reliable operation for the life of the system
Publication# 26645
Issue Date: July 19, 2002
Rev: A Amendment/+1
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
Am29DL32xG Features
DMS (Data Management Software) allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is an advantage compared to systems where
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and
software integration efforts.
The Am29DL322G/323G/324G consists of 32 megabit,
3.0 volt-only flash memory devices, organized as
2,097,152 words of 16 bits each or 4,194,304 bytes of
8 bits each. Word mode data appears on DQ15–DQ0;
byte mode data appears on DQ7–DQ0. The device is
designed to be programmed in-system with the stan-
dard 3.0 volt VCC supply, and can also be programmed
in standard EPROM programmers.
The devices are available with access times of 70 and
85 ns. The device is offered in a 73-ball FBGA pack-
age. Standard control pins—chip enable (CE#f), write
enable (WE#), and output enable (OE#)—control nor-
mal read and write operations, and avoid bus
contention issues.
The devices requires only a single 3.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The Am29DL32xG device family uses multiple bank
architectures to provide flexibility for different applica-
tions. Three devices are available with the following
bank sizes:
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device
DL322
DL323
DL324
Bank 1
Bank 2
28
4
8
24
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via
programming equipment.
16
16
The Secured Silicon (SecSi) Sector is an extra 256
byte sector capable of being permanently locked by
AMD or customers. The SecSi Sector Indicator Bit
(DQ7) is permanently set to a 1 if the part is factory
locked, and set to a 0 if customer lockable. This
way, customer lockable parts can never be used to re-
place a factory locked part.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number). Customer lockable
devices are one-time programmable and one-time
lockable.
2
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . .10
Flash Device Bus Operations . . . . . . . . . . . . . . . 12
Word/Byte Configuration ........................................................12
Requirements for Reading Array Data ...................................12
Writing Commands/Command Sequences ............................12
Accelerated Program Operation ..........................................12
Autoselect Functions ...........................................................12
Simultaneous Read/Write Operations with Zero Latency .......12
Standby Mode ........................................................................ 13
Automatic Sleep Mode ...........................................................13
RESET#: Hardware Reset Pin ...............................................13
Output Disable Mode .............................................................. 13
Table 3. Device Bank Division ........................................................13
Table 4. Top Boot Sector Addresses .............................................14
Table 6. Bottom Boot Sector Addresses .........................................16
Autoselect Mode ..................................................................... 18
Sector/Sector Block Protection and Unprotection ..................18
Table 8. Top Boot Sector/Sector Block Addresses
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling .................................................................32
Figure 5. Data# Polling Algorithm .................................................. 32
RY/BY#: Ready/Busy# ............................................................ 33
DQ6: Toggle Bit I ....................................................................33
Figure 6. Toggle Bit Algorithm........................................................ 33
DQ2: Toggle Bit II ................................................................... 34
Reading Toggle Bits DQ6/DQ2 ...............................................34
DQ5: Exceeded Timing Limits ................................................ 34
DQ3: Sector Erase Timer ....................................................... 34
Table 18. Write Operation Status ................................................... 35
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 36
Industrial (I) Devices ............................................................ 36
V f/V s Supply Voltage ...................................................36
CC CC
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37
CMOS Compatible ..................................................................37
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents)............................................................. 39
Figure 10. Typical ICC1 vs. Frequency............................................ 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test Setup.................................................................... 40
Figure 12. Input Waveforms and Measurement Levels ................. 40
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 41
CE#s Timing ...........................................................................41
Figure 13. Timing Diagram for Alternating
for Protection/Unprotection .............................................................18
Table 9. Bottom Boot Sector/Sector Block Addresses
Between Pseudo SRAM to Flash................................................... 41
Read-Only Operations ...........................................................42
Figure 14. Read Operation Timings ............................................... 42
Hardware Reset (RESET#) .................................................... 43
Figure 15. Reset Timings ............................................................... 43
Word/Byte Configuration (CIOf) ..............................................44
Figure 16. CIOf Timings for Read Operations................................ 44
Figure 17. CIOf Timings for Write Operations................................ 44
Erase and Program Operations ..............................................45
Figure 18. Program Operation Timings.......................................... 46
Figure 19. Accelerated Program Timing Diagram.......................... 46
Figure 20. Chip/Sector Erase Operation Timings .......................... 47
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 48
Figure 22. Data# Polling Timings (During Embedded Algorithms). 48
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 49
Figure 24. DQ2 vs. DQ6................................................................. 49
Temporary Sector Unprotect .................................................. 50
Figure 25. Temporary Sector Unprotect Timing Diagram .............. 50
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 51
Alternate CE#f Controlled Erase and Program Operations ....52
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 53
Read Cycle .............................................................................54
Figure 28. Psuedo SRAM Read Cycle........................................... 54
Figure 29. Page Read Timing ........................................................ 55
Write Cycle .............................................................................56
Figure 30. Pseudo SRAM Write Cycle—WE# Control................... 56
Figure 31. Pseudo SRAM Write Cycle—CE1#s Control................ 57
Figure 32. Pseudo SRAM Write Cycle—
for Protection/Unprotection .............................................................19
Write Protect (WP#) ................................................................19
Temporary Sector/Sector Block Unprotect ............................. 19
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms .............................................................................................. 21
SecSi (Secured Silicon) Sector Flash Memory Region .......... 22
Factory Locked: SecSi Sector Programmed and Protected At
the Factory .......................................................................... 22
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ...........................................................22
Hardware Data Protection ......................................................22
Low V Write Inhibit ...........................................................22
CC
Write Pulse “Glitch” Protection ............................................22
Logical Inhibit ......................................................................22
Power-Up Write Inhibit .........................................................23
Common Flash Memory Interface (CFI) . . . . . . .23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................26
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..26
Byte/Word Program Command Sequence ............................. 27
Unlock Bypass Command Sequence .................................. 27
Figure 3. Program Operation .......................................................... 28
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................28
Erase Suspend/Erase Resume Commands ........................... 29
Figure 4. Erase Operation............................................................... 29
Table 15. Autoselect Device IDs (Word Mode) ...............................30
Table 17. Autoselect Device IDs (Byte Mode) ................................31
UB#s and LB#s Control.................................................................. 58
Flash Erase And Programming Performance . . 59
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 59
July 19, 2002
Am49DL32xBG
3
P R E L I M I N A R Y
Figure 35. Read Address Skew ..................................................... 61
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 59
pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 60
pSRAM Power on and Deep Power Down . . . . . 60
Figure 33. Deep Power-down Timing.............................................. 60
Figure 34. Power-on Timing............................................................ 60
pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 61
Figure 36. Write Address Skew...................................................... 61
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm .............62
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63
4
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Part Number
Am49DL32xBG
Flash Memory
Pseudo SRAM
Speed
Options
Standard Voltage Range:
VCC = 2.7–3.3 V
70
70
85
85
70
70
30
70
25
85
85
35
85
30
Max Access Time, ns
Page Access Time (pSRAM), ns
CE#f Access, ns
N/A
70
N/A
85
OE# Access, ns
30
40
MCP BLOCK DIAGRAM
VCC
f
VSS
A20 to A0
RY/BY#
A20 to A0
A–1
WP#/ACC
RESET#
CE#f
32 MBit
Flash Memory
DQ15/A–1 to DQ0
CIOf
DQ15/A–1 to DQ0
VCCs/VCCQ VSS/VSSQ
A20 to A0
32 MBit
Pseudo
SRAM
LB#s
DQ15 to DQ0
UB#s
WE#
OE#
CE1#s
CE2s
July 19, 2002
Am49DL32xBG
5
P R E L I M I N A R Y
FLASH MEMORY BLOCK DIAGRAM
OE# CIOf
V
V
CC
SS
Upper Bank Address
A20–A0
Upper Bank
X-Decoder
RY/BY#
A20–A0
RESET#
STATE
CONTROL
&
COMMAND
REGISTER
WE#
CE#
Status
DQ15–DQ0
CIOf
Control
WP#/ACC
DQ15–DQ0
X-Decoder
Lower Bank
A20–A0
Lower Bank Address
OE# CIOf
6
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
CONNECTION DIAGRAM
73-Ball FBGA
Top View
Flash only
A1
A10
NC
NC
Pseudo
SRAM only
B1
B5
NC
C5
B6
B10
NC
NC
NC
Shared
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
NC
F9
NC
UB# RESET# CE2s
E5
E2
A2
E3
A5
E4
E6
A18 RY/BY# A20
F1
NC
G1
NC
F2
A1
F3
A4
F4
A17
G4
DQ1
F7
F10
A10
G7
DQ6
H7
A14
G8
NC
NC
G2
A0
G3
G9 G10
V
SS
A16
NC
H2
CE#f
J2
H3
OE#
J3
H4
DQ9
J4
H5
DQ3
J5
H6
DQ4
J6
H8
H9
DQ13 DQ15/A-1 CIOf
J7
DQ12
K7
J8
DQ7
K8
J9
V
CC
f
V s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
DQ11
L5
K6
NC
L6
NC
DQ8
DQ2
DQ5
DQ14
L1
NC
M1
NC
L10
NC
NC
M10
NC
package and/or data integrity may be compromised if
the package body is exposed to temperatures above
150°C for prolonged periods of time.
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (TSOP, SO, PDIP, PLCC). The
July 19, 2002
Am49DL32xBG
7
P R E L I M I N A R Y
PIN DESCRIPTION
LOGIC SYMBOL
A20–A0
= 21 Address Inputs (Common)
21
A-1
= 2 Address Inputs (Flash)
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
A20–A0
DQ15–DQ0
CE#f
A-1
SA
CE1#s
CE2s
= Chip Enable 1 (pSRAM)
= Chip Enable 2 (pSRAM)
= Output Enable (Common)
= Write Enable (Common)
= Ready/Busy Output
16 or 8
CE#f
DQ15–DQ0
OE#
CE1#s
CE2s
WE#
RY/BY#
RY/BY#
UB#s
OE#
= Upper Byte Control (pSRAM)
= Lower Byte Control (pSRAM)
WE#
LB#s
WP#/ACC
RESET#
UB#s
CIOf
= I/O Configuration (Flash)
CIOf = VIH = Word mode (x16),
CIOf = VIL = Byte mode (x8)
LB#s
RESET#
= Hardware Reset Pin, Active Low
CIOf
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
VCC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
VCC
VSS
NC
s
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
8
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am49DL32x 70
B
G
T
I
T
TAPE AND REEL
T
S
=
=
7 inches
13 inches
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
SPEED OPTION
See “Product Selector Guide” on page 5.
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top sector
Bottom sector
PROCESS TECHNOLOGY
0.17 µm
G
=
PSEUDO SRAM DEVICE DENSITY
32 Mbits
B
=
AMD DEVICE NUMBER/DESCRIPTION
Am49DL32xBG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL32xG 32Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation
Flash Memory and 32 Mbit (2 M x 16-Bit) Pseudo Static RAM with Page Mode
Valid Combinations
Valid Combinations
Order Number Package Marking
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
Am49DL322BGT70
Am49DL322BGT85
Am49DL322BGB70
Am49DL322BGB85
Am49DL323BGT70
Am49DL323BGT85
Am49DL323BGB70
Am49DL323BGB85
Am49DL324BGT70
Am49DL324BGT85
Am49DL324BGB70
Am49DL324BGB85
T,S
T,S
T,S
T,S
T,S
T,S
T,S
T,S
T,S
T,S
T,S
T,S
M49000000J
M49000000K
M49000000L
M49000000M
M49000000N
M49000000O
M49000000P
M49000000Q
M49000000R
M49000000S
M49000000T
M49000000U
July 19, 2002
Am49DL32xBG
9
P R E L I M I N A R Y
needed to execute the command. The contents of the
MCP DEVICE BUS OPERATIONS
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH
Operation
(Notes 1, 2)
WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
CE#f CE1#s CE2s OE# WE#
Address
LB#s UB#s RESET#
(Note 7)
(Note 8)
(Note 7)
(Note 8)
H
H
H
H
H
L
Read from
Flash
AIN
DOUT
DOUT
L
L
H
L
X
X
X
X
H
L/H
H
L
AIN
DIN
DIN
Write to Flash
Standby
L
H
H
(Note 4)
VCC
±
VCC ±
H
H
H
L
X
X
X
X
X
X
X
X
X
X
H
H
High-Z
High-Z
High-Z
High-Z
0.3 V
0.3 V
VCC
±
VCC
±
Deep Power-down
Standby
0.3 V
0.3 V
H
H
H
H
X
X
X
X
X
X
Output Disable
L
L
H
H
L/H
L/H
L/H
High-Z
High-Z
DIN
High-Z
High-Z
X
(Note 7)
H
H
H
H
H
H
L
Flash Hardware
Reset
X
L
X
H
X
L
X
X
X
X
X
L
(Note 8)
(Note 7)
(Note 8)
(Note 7)
H
L
Sector Protect
(Note 5)
SADD, A6 = L,
A1 = H, A0 = L
VID
Sector
Unprotect
(Note 5)
H
SADD, A6 = H,
A1 = H, A0 = L
VID
DIN
DIN
L
H
X
L
X
X
X
X
(Note 6)
(Note 6)
X
(Note 8)
(Note 7)
(Note 8)
H
H
H
L
H
L
Temporary
Sector
Unprotect
VID
X
X
X
High-Z
DOUT
High-Z
DOUT
DIN
DOUT
DOUT
High-Z
DIN
L
H
L
L
L
AIN
Read from pSRAM
Write to pSRAM
H
H
L
L
H
H
L
H
L
H
H
X
X
H
L
L
AIN
DIN
X
H
L
L
High-Z
DIN
H
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = pSRAM Address Input, Byte Mode,
SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are
inhibited.
5. The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Autoselect
Mode” section.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same
time.
6. If WP#/ACC = VIL, the two outermost boot sectors remain
protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or
unprotected using the method described in “Autoselect Mode”. If
WP#/ACC = VHH, all sectors will be unprotected.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC
= VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by
40%.
7. Data will be retained in pSRAM.
8. Data will be lost in pSRAM.
10
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
Table 2. Device Bus Operations—Flash Byte Mode, CIOf = VIL
Operation
(Notes 1, 2)
WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
CE#f CE1#s CE2s OE# WE#
Address
LB#s UB#s RESET#
(Note 7)
(Note 8)
(Note 7)
(Note 8)
H
H
H
H
H
L
Read from
Flash
AIN
DOUT
L
L
H
L
X
X
X
X
H
L/H
High-Z
High-Z
H
L
AIN
DIN
Write to Flash
Standby
L
H
H
(Note 4)
VCC
±
VCC ±
H
H
H
L
X
X
X
X
X
X
X
X
X
X
H
H
High-Z
High-Z
High-Z
High-Z
0.3 V
0.3 V
VCC
±
VCC
±
Deep Power-down
Standby
0.3 V
0.3 V
H
H
H
H
X
X
X
X
X
X
Output Disable
L
L
H
H
L/H
L/H
L/H
High-Z
High-Z
DIN
High-Z
High-Z
X
(Note 7)
H
H
H
H
H
H
L
Flash Hardware
Reset
X
L
X
H
X
L
X
X
X
X
X
L
(Note 8)
(Note 7)
(Note 8)
(Note 7)
H
L
Sector Protect
(Note 5)
SADD, A6 = L,
A1 = H, A0 = L
VID
Sector
Unprotect
(Note 5)
H
SADD, A6 = H,
A1 = H, A0 = L
VID
DIN
L
H
X
L
X
X
X
X
(Note 6)
(Note 6)
X
(Note 8)
(Note 7)
(Note 8)
H
H
H
L
H
L
Temporary
Sector
Unprotect
VID
DIN
X
X
X
High-Z
DOUT
DOUT
DOUT
L
H
L
L
L
AIN
Read from pSRAM
Write to pSRAM
H
H
L
L
H
H
L
H
L
H
H
X
X
High-Z
DOUT
DIN
H
L
High-Z
DIN
L
AIN
DIN
X
H
L
L
High-Z
DIN
H
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = pSRAM Address Input, Byte Mode,
SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are
inhibited.
5. The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Autoselect
Mode” section.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same
time.
6. If WP#/ACC = VIL, the two outermost boot sectors remain
protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or
unprotected using the method described in “Autoselect Mode”. If
WP#/ACC = VHH, all sectors will be unprotected.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC
= VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by
40%.
7. Data will be retained in pSRAM.
8. Data will be lost in pSRAM.
July 19, 2002
Am49DL32xBG
11
P R E L I M I N A R Y
An erase operation can erase one sector, multiple sec-
FLASH DEVICE BUS OPERATIONS
Word/Byte Configuration
tors, or the entire device. Table 3 indicates the address
space that each sector occupies. Similarly, a “sector
address” is the address bits required to uniquely select
a sector. The “Flash Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
The CIOf pin controls whether the device data I/O pins
operate in the byte or word configuration. If the CIOf
pin is set at logic ‘1’, the device is in word configura-
tion, DQ15–DQ0 are active and controlled by CE#f
and OE#.
The device address space is divided into four banks. A
“bank address” is the address bits required to uniquely
select a bank.
If the CIOf pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
active and controlled by CE#f and OE#. The data I/O
pins DQ14–DQ8 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The Flash
AC Characteristics section contains timing specifica-
tion tables and timing diagrams for write operations.
Requirements for Reading Array Data
Accelerated Program Operation
To read array data from the outputs, the system must
drive the CE#f and OE# pins to VIL. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The CIOf pin determines
whether the device outputs array data in words or
bytes.
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that VHH must not be asserted on
WP#/ACC for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result.
See “Write Protect (WP#)” on page 19 for related in-
formation.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the Flash Read-Only Operations table for tim-
ing specifications and to Figure 14 for the timing dia-
gram. ICC1 in the DC Characteristics table represents
the active current specification for reading array data.
Autoselect Functions
Writing Commands/Command Sequences
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE#f to VIL, and OE# to VIH.
For program operations, the CIOf pin determines
whether the device accepts program data in bytes or
words. Refer to “Flash Device Bus Operations” for
more information.
Simultaneous Read/Write Operations with
Zero Latency
The device features an Unlock Bypass mode to facil-
itate faster programming. Once a bank enters the Un-
lock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The
“Byte/Word Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 21 shows how read and write cycles
12
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
may be initiated for simultaneous operation with zero
RESET#: Hardware Reset Pin
latency. ICC6f and ICC7f in the table represent the cur-
rent specifications for read-while-program and
read-while-erase, respectively.
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE#f and RESET# are held at VIH, but not
within VCC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (tCE) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4f). If RESET# is
held at VIL but not within VSS±0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
ICC3f in the table represents the standby current spec-
ification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC5f in the table represents the automatic sleep mode
current specification.
Refer to the pSRAM AC Characteristics tables for RE-
SET# parameters and to Figure 15 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 3. Device Bank Division
Bank 1
Device
Bank 2
Sector Sizes
Part Number
Megabits
Sector Sizes
Megabits
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
Fifty-six
64 Kbyte/32 Kword
Am29DL322G
Am29DL323G
Am29DL324G
4 Mbit
28 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Forty-eight
64 Kbyte/32 Kword
8 Mbit
24 Mbit
16 Mbit
Eight 8 Kbyte/4 Kword,
thirty-one 64 Kbyte/32 Kword
Thirty-two
64 Kbyte/32 Kword
16 Mbit
July 19, 2002
Am49DL32xBG
13
P R E L I M I N A R Y
Table 4. Top Boot Sector Addresses
Sector Address
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
A20–A12
Address Range
SA0
SA1
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
000000h–07FFFh
008000h–0FFFFh
010000h–17FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
14
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
Table 4. Top Boot Sector Addresses (Continued)
Sector Address
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
A20–A12
Address Range
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3F1FFFh
3F2000h–3F3FFFh
3F4000h–3F5FFFh
3F6000h–3F7FFFh
3F8000h–3F9FFFh
3FA000h–3FBFFFh
3FC000h–3FDFFFh
3FE000h–3FFFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). The bank address bits are A20–A18 for
Am29DL322GT, A20 and A19 for Am29DL323GT, and A20 for Am29DL324GT.
Table 5. Top Boot SecSi Sector Addresses
Sector Address
Sector Size
(x8)
(x16)
Device
A20–A12
(Bytes/Words)
Address Range
Address Range
Am29DL322GT, Am29DL323GT,
Am29DL324GT
111111xxx
256/128
3FE000h–3FE0FFh 1F0000h–1FF07Fh
July 19, 2002
Am49DL32xBG
15
P R E L I M I N A R Y
Table 6. Bottom Boot Sector Addresses
Sector Address
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
A20–A12
Address Range
SA0
SA1
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
000000h–000FFFh
001000h–001FFFh
002000h–002FFFh
003000h–003FFFh
004000h–004FFFh
005000h–005FFFh
006000h–006FFFh
007000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
16
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
Table 6. Bottom Boot Sector Addresses (Continued)
Sector Address
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
A20–A12
Address Range
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
111000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). The bank address bits
are A20–A18 for Am29DL322GB, A20 and A19 for Am29DL323GB, and A20 for Am29DL324GB.
Table 7. Bottom Boot SecSi Sector Addresses
Sector Address
Sector Size
(x8)
(x16)
Device
A20–A12
(Bytes/Words)
Address Range
Address Range
Am29DL322GB, Am29DL323GB,
Am29DL324GB
000000xxx
256/128
000000h–0000FFh
00000h–00007Fh
July 19, 2002
Am49DL32xBG
17
P R E L I M I N A R Y
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be
programmed with its corresponding programming al-
gorithm. However, the autoselect codes can also be
accessed in-system through the command register.
Sector/
Sector
A20–A12
Sector Block Size
SA0
000000XXX
64 Kbytes
000001XXX,
000010XXX
000011XXX
SA1–SA3
192 (3x64) Kbytes
SA4–SA7
SA8–SA11
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXXXX
1000XXXXX
1001XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Tables 15 and 16. This
method does not require VID. Refer to the Autoselect
Command Sequence section for more information.
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
Sector/Sector Block Protection and
Unprotection
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
8).
111100XXX,
111101XXX,
111110XXX
SA60–SA62
192 (4x64) Kbytes
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
18
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
Table 9. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection
diagram. This method uses standard microprocessor
bus cycle timing. For sector unprotect, all unprotected
sectors must first be protected prior to the first sector
unprotect write cycle.
Sector/Sector Block
Size
Sector
A20–A12
SA70
111111XXX
64 Kbytes
The device is shipped with all sectors unprotected.
111110XXX,
111101XXX,
111100XXX
It is possible to determine whether a sector is pro-
tected or unprotected. See the Autoselect Mode
section for details.
SA69-SA67
192 (3x64) Kbytes
SA66-SA63
SA62-SA59
SA58-SA55
SA54-SA51
SA50-SA47
SA46-SA43
SA42-SA39
SA38-SA35
SA34-SA31
SA30-SA27
SA26-SA23
SA22–SA19
SA18-SA15
SA14-SA11
1110XXXXX
1101XXXXX
1100XXXXX
1011XXXXX
1010XXXXX
1001XXXXX
1000XXXXX
0111XXXXX
0110XXXXX
0101XXXXX
0100XXXXX
0011XXXXX
0010XXXXX
0001XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using VID. This function is one of two provided by the
WP#/ACC pin.
If the system asserts VIL on the WP#/ACC pin, the de-
vice disables program and erase functions in the two
“outermost” 8 Kbyte boot sectors independently of
whether those sectors were protected or unprotected
using the method described in “Autoselect Mode”. The
two outermost 8 Kbyte boot sectors are the two sec-
tors containing the lowest addresses in a
top-boot-configured device, or the two sectors contain-
ing the highest addresses in a top-boot-configured
device.
000011XXX,
000010XXX,
000001XXX
SA10-SA8
192 (3x64) Kbytes
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether the two outermost 8 Kbyte boot
sectors were last set to be protected or unprotected.
That is, sector protection or unprotection for these two
sectors depends on whether they were last protected
or unprotected using the method described in “Autose-
lect Mode”.
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
000000111
000000110
000000101
000000100
000000011
000000010
000000001
000000000
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
Temporary Sector/Sector Block Unprotect
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Note that the sector unprotect algorithm un-
protects all sectors in parallel. All previously protected
sectors must be individually re-protected. To change
data in protected sectors efficiently, the temporary
sector un protect function is available. See “Temporary
Sector/Sector Block Unprotect”.
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
8).
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID (11.5 V – 12.5 V). During this mode,
formerly protected sectors can be programmed or
erased by selecting the sector addresses. Once VID is
removed from the RESET# pin, all the previously pro-
tected sectors are protected again. Figure 1 shows the
algorithm, and Figure 25 shows the timing diagrams,
for this feature.
Sector protection and unprotection can be imple-
mented as follows.
Sector protection and unprotection requires VID on the
RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 26 shows the timing
July 19, 2002
Am49DL32xBG
19
P R E L I M I N A R Y
Figure 1. Temporary Sector Unprotect Operation
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once
again.
20
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 µs
Wait 1 µs
unprotect address
No
First Write
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Note: The term “sector” in the figure applies to both sectors and sector blocks.
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms
July 19, 2002
Am49DL32xBG
21
P R E L I M I N A R Y
(ACC) and unlock bypass functions are not available
SecSi (Secured Silicon) Sector Flash
Memory Region
when programming the SecSi Sector.
The SecSi Sector area can be protected using one of
the following procedures:
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector uses a SecSi Sector Indica-
tor Bit to indicate whether or not the SecSi Sector is
locked when shipped from the factory. This bit is per-
manently set at the factory and cannot be changed,
which prevents cloning of a factory locked part. This
ensures the security of the ESN once the product is
shipped to the field.
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the without raising
any device pin to a high voltage. Note that this
method is only applicable to the SecSi Sector.
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “Au-
toselect Mode”.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi Sector Indicator
Bit permanently set to a “1.” The customer-lockable
version is shipped with the unprotected, allowing cus-
tomers to utilize the that sector in any manner they
choose. The customer-lockable version has the SecSi
Sector Indicator Bit permanently set to a “0.” Thus, the
SecSi Sector Indicator Bit prevents customer-lockable
devices from being used to replace devices that are
factory locked.
Once the SecSi Sector is locked and verified, the sys-
tem must write the Exit SecSi Sector Region
command sequence to return to reading and writing
the remainder of the array.
The SecSi Sector protection must be used with cau-
tion since, once protected, there is no procedure
available for unprotecting the SecSi Sector area and
none of the bits in the SecSi Sector memory space
can be modified in any way.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the
addresses normally occupied by the boot sectors. This
mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until
power is removed from the device. On power-up, or
following a hardware reset, the device reverts to send-
ing commands to the boot sectors.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Tables 15 and 16
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subse-
In a factory locked device, the SecSi Sector is pro-
tected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is available preprogrammed with a random, se-
cure ESN only.
quent writes are ignored until VCC is greater than VLKO
.
In the Top Boot device the ESN will be at addresses
1FF000h–1FF007h in word mode (or addresses
3FE000h–3FE00Fh in byte mode).
The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC
is greater than VLKO
.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#f
or WE# do not initiate a write cycle.
If the security feature is not required, the SecSi Sector
can be treated as an additional Flash memory space,
expanding the size of the available Flash array. The
SecSi Sector can be read any number of times, but
can be programmed and locked only once, and cannot
be erased. Note that the accelerated programming
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle,
22
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
CE#f and WE# must be a logical zero while OE# is a
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The sys-
tem can read CFI information at the addresses given
in Tables 10–13. To terminate reading CFI data, the
system must write the reset command. The CFI Query
mode is not accessible when the device is executing
an Embedded Program or embedded erase algorithm.
logical one.
Power-Up Write Inhibit
If WE# = CE#f = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 10–13. The
system must write the reset command to return the de-
vice to the autoselect mode.
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
Table 10. CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
July 19, 2002
Am49DL32xBG
23
P R E L I M I N A R Y
Table 11. System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
VCC Min. (write/erase)
0027h
1Bh
1Ch
36h
38h
D7–D4: volt, D3–D0: 100 millivolt
V
CC Max. (write/erase)
0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
V
PP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 12. Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
27h
4Eh
0016h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0002h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
24
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
Table 13. Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
0004h
Silicon Revision Number (Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0001h
0004h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
00XXh
(See Note)
Simultaneous Operation
00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank)
Burst Mode Type
00 = Not Supported, 01 = Supported
0000h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
4Fh
9Ah
9Ch
9Eh
0085h
0095h
000Xh
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
Note:
The number of sectors in Bank 2 is device dependent. Am29DL322 = 38h, Am29DL323 = 30h, Am29DL324 = 20h.
July 19, 2002
Am49DL32xBG
25
P R E L I M I N A R Y
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. Tables 15 and 16 define the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading array data.
command returns that bank to the erase-sus-
pend-read mode. Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to reading array data. If a
bank entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns
that bank to the erase-suspend-read mode.
All addresses are latched on the falling edge of WE#
or CE#f, whichever happens later. All data is latched
on the rising edge of WE# or CE#f, whichever hap-
pens first. Refer to the pSRAM AC Characteristics
section for timing diagrams.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to read-
ing array data (or erase-suspend-read mode if that
bank was in Erase Suspend).
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Tables 15 and 16 show the address and data require-
ments. The autoselect command sequence may be
written to an address within a bank that is either in the
read or erase-suspend-read mode. The autoselect
command may not be written while the device is ac-
tively programming or erasing in the other bank.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. After completing a programming operation
in the Erase Suspend mode, the system may once
again read array data with the same exception. See
the Erase Suspend/Erase Resume Commands sec-
tion for more information.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au-
toselect command. The bank then enters the
autoselect mode. The system may read at any ad-
dress within the same bank any number of times
without initiating another autoselect command
sequence:
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
section for more information. The Flash Read-Only
Operations table provides the read parameters, and
Figure 14 shows the timing diagram.
■ A read cycle at address (BA)XX00h (where BA is
the bank address) returns the manufacturer code.
■ A read cycle at address (BA)XX01h in word mode
(or (BA)XX02h in byte mode) returns the device
code.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
■ A read cycle to an address containing a sector ad-
dress (SA) within the same bank, and the address
02h on A7–A0 in word mode (or the address 04h on
A6–A-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. (Refer to Ta-
bles 4–6 for valid sector addresses).
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to reading array data. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
which the system was writing to reading array data. If
the program command sequence is written to a bank
that is in the Erase Suspend mode, writing the reset
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The system can access the SecSi Sector region by is-
suing the three-cycle Enter SecSi Sector command
26
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
sequence. The device continues to access the SecSi data is still “0.” Only erase operations can convert a
Sector region until the system issues the four-cycle
Exit SecSi Sector command sequence. The Exit SecSi
Sector command sequence returns the device to nor-
mal operation. Tables 15 and 16 show the address
and data requirements for both command sequences.
See also “SecSi (Secured Silicon) Sector Flash Mem-
ory Region” for further information. Note that a
hardware reset (RESET#=VIL) will reset the device to
reading array data.
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to a bank faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
That bank then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Tables 15 and 16 show the re-
quirements for the command sequence.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the CIOf pin. Programming
is a four-bus-cycle operation. The program command
sequence is initiated by writing two unlock write cy-
cles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or
timings. The device automatically provides internally
generated program pulses and verifies the pro-
grammed cell margin. Tables 15 and 16 show the
address and data requirements for the byte program
command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the reading array data.
When the Embedded Program algorithm is complete,
that bank then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. Refer to the Write Oper-
ation Status section for information on these status
bits.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was success-
ful. However, a succeeding read will show that the
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 18 for timing diagrams.
July 19, 2002
Am49DL32xBG
27
P R E L I M I N A R Y
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
START
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations
tables in the AC Characteristics section for parame-
ters, and Figure 20 section for timing diagrams.
Write Program
Command Sequence
Data Poll
from System
Sector Erase Command Sequence
Embedded
Program
algorithm
in progress
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then
followed by the address of the sector to be erased,
and the sector erase command. Tables 15 and 16
show the address and data requirements for the sec-
tor erase command sequence.
Verify Data?
Yes
No
No
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Increment Address
Last Address?
Yes
Programming
Completed
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than
50 µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets that bank to reading array
data. The system must rewrite the command se-
quence and any additional addresses and commands.
Note: Seefor program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables 15 and
16 show the address and data requirements for the
chip erase command sequence.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete,
that bank returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. Refer to the Write Operation Status
section for information on these status bits.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can de-
termine the status of the erase operation by reading
28
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Refer to the Write Operation Status section for more
information.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. The bank
address of the erase-suspended bank is required
when writing this command. Further writes of the Re-
sume command are ignored. Another Erase Suspend
command can be written after the chip has resumed
erasing.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations
tables in the AC Characteristics section for parame-
ters, and Figure 20 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
START
Write Erase
Command Sequence
(Notes 1, 2)
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is writ-
ten during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Yes
Erasure Completed
Notes:
1. See Tables 15 and 16 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
Figure 4. Erase Operation
July 19, 2002
Am49DL32xBG
29
P R E L I M I N A R Y
Table 14. Command Definitions (Flash Word Mode)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
4
RA
XXX
555
555
RD
F0
AA
AA
2AA
2AA
55
55
(BA)555
(BA)555
90
90
(BA)X00
0001
Device ID
(BA)X01 see Table 15
SecSi Sector Factory
Protect (Note 9)
4
4
555
555
AA
AA
2AA
2AA
55
55
(BA)555
(BA)555
90
90
(BA)X03 0082/0002
Sector Protect Verify
(Note 10)
(SADD)
0000/0001
X02
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
88
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program
(Note 11)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 12)
Chip Erase
2
6
6
1
1
1
BA
555
555
BA
BA
55
90
AA
AA
B0
30
98
XXX
2AA
2AA
00
55
55
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
10
30
Sector Erase
SADD
Erase Suspend (Note 13)
Erase Resume (Note 14)
CFI Query (Note 15)
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SADD = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A20–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE#f pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
2. All values are in hexadecimal.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A20–A12 are don’t cares.
6. No unlock or command cycles required when bank is in read
mode.
14. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
15. Command is valid when device is ready to read array data or when
device is in autoselect mode.
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. See the Autoselect Command Sequence section for
more information.
Table 15. Autoselect Device IDs (Word Mode)
Device
Autoselect Device ID
2255h (T), 2256h (B)
2250h (T), 2253h (B)
225Ch (T), 225Fh (B)
Am29DL322G
Am29DL323G
Am29DL324G
9. The data is 82h for factory locked and 02h for not factory locked.
10. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
T = Top Boot Sector, B = Bottom Boot Sector
30
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
Table 16. Command Definitions (Flash Byte Mode)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
RD
F0
XXX
(BA)
AAA
Manufacturer ID
4
6
4
4
AAA
AAA
AAA
AAA
AA
AA
AA
AA
555
555
555
555
55
55
55
55
90
90
90
90
(BA) 00
(BA) 02
01
(BA)
AAA
see
Table 17
Device ID
SecSi Sector Factory Protect
(Note 9)
(BA)
AAA
(BA)
X06
82/02
00
01
Sector Protect Verify
(Note 10)
(BA)
AAA
(SADD)
X04
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
2
2
6
6
1
1
1
AAA
AAA
AAA
AAA
XXX
XXX
AAA
AAA
BA
AA
AA
AA
AA
A0
90
555
555
555
555
PA
55
55
55
55
PD
00
55
55
AAA
AAA
AAA
AAA
88
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
Chip Erase
XXX
555
555
AA
AA
B0
30
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
AAA
10
30
Sector Erase
55 SADD
Erase Suspend (Note 13)
Erase Resume (Note 14)
CFI Query (Note 15)
BA
55
98
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SADD = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A20–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE#f pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
2. All values are in hexadecimal.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A20–A12 are don’t cares.
6. No unlock or command cycles required when bank is in read
mode.
14. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
15. Command is valid when device is ready to read array data or when
device is in autoselect mode.
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
Table 17. Autoselect Device IDs (Byte Mode)
Device
Autoselect Device ID
55h (T), 56h (B)
Am29DL322G
Am29DL323G
Am29DL324G
50h (T), 53h (B)
9. The data is 82h for factory locked and 02h for not factory locked.
5Ch (T), 5Fh (B)
10. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
T = Top Boot Sector, B = Bottom Boot Sector
July 19, 2002
Am49DL32xBG
31
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 18 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6
each offer a method for determining whether a pro-
gram or erase operation is complete or in progress.
The device also provides a hardware-based output
signal, RY/BY#, to determine whether an Embedded
Program or Erase operation is in progress or has been
completed.
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ6–DQ0 may be still
invalid. Valid data on DQ7–DQ0 will appear on suc-
cessive read cycles.
Table 18 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 22
in the pSRAM AC Characteristics section shows the
Data# Polling timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a
bank is in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the command
sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to reading
array data.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the bank returns to reading array data. If not all se-
lected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected. However, if the
system reads DQ7 at an address within a protected
sector, the status may not be valid.
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
32
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
DQ6 also toggles during the erase-suspend-program
RY/BY#: Ready/Busy#
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
Table 18 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 23 in
the “Flash AC Characteristics” section shows the tog-
gle bit timing diagrams. Figure 24 shows the
differences between DQ2 and DQ6 in graphical form.
See also the subsection on DQ2: Toggle Bit II.
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is reading array data, the standby
mode, or one of the banks is in the erase-sus-
pend-read mode.
START
Table 18 shows the outputs for RY/BY#.
Read DQ7–DQ0
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE#f to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Yes
No
DQ5 = 1?
Yes
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
Read DQ7–DQ0
Twice
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data#
Polling).
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 6. Toggle Bit Algorithm
July 19, 2002
Am49DL32xBG
33
P R E L I M I N A R Y
cles, determining the status as described in the
DQ2: Toggle Bit II
previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it re-
turns to determine the status of the operation (top of
Figure 6).
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE#f to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 18 to compare out-
puts for DQ2 and DQ6.
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicating
that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 23 shows the toggle bit timing diagram. Figure
24 shows the differences between DQ2 and DQ6 in
graphical form.
Under both these conditions, the system must write
the reset command to return to reading array data (or
to the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
Reading Toggle Bits DQ6/DQ2
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
Table 18 shows the status of DQ3 relative to the other
status bits.
34
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
Table 18. Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1)
DQ2
(Note 2)
Status
DQ6
DQ3
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase-Suspend-
Read
Erase
Suspend
Mode
Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
July 19, 2002
Am49DL32xBG
35
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . –40°C to +85°C
V
CCf/VCCs Supply Voltage
Voltage with Respect to Ground
VCCf/VCCs for standard voltage range . . 2.7 V to 3.3 V
VCCf/VCCs (Note 1) . . . . . . . . . . . .–0.3 V to +4.0 V
RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
2. Minimum DC input voltage on pins OE#, RESET#, and
WP#/ACC is –0.5 V. During voltage transitions, OE#,
WP#/ACC, and RESET# may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 7. Maximum DC
input voltage on pin RESET# is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
VCC
+2.0 V
–0.5 V
–2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 7. Maximum Negative
Overshoot Waveform
Figure 8. Maximum Positive
Overshoot Waveform
36
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
FLASH DC CHARACTERISTICS
CMOS Compatible
Parameter
Parameter Description
Symbol
Test Conditions
Min
Typ
Max
Unit
VIN = VSS to VCC
VCC = VCC max
,
ILI
Input Load Current
±1.0
35
µA
µA
µA
ILIT
ILO
RESET# Input Load Current
Output Leakage Current
VCC = VCC max; RESET# = 12.5 V
VOUT = VSS to VCC
CC = VCC max
,
±1.0
V
VCC = VCC max, WP#/ACC
= VACC max
ILIA
ACC Input Leakage Current
35
µA
5 MHz
1 MHz
5 MHz
1 MHz
10
2
16
4
CE#f = VIL, OE# = VIH,
Byte Mode
Flash VCC Active Read Current
(Notes 1, 2)
ICC1
f
mA
10
2
16
4
CE#f = VIL, OE# = VIH,
Word Mode
I
CC2f
CC3f
Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL
15
30
mA
µA
VCCf = VCC max, CE#f, RESET#,
Flash VCC Standby Current (Note 2)
I
0.2
0.2
0.2
5
5
5
WP#/ACC = VCCf ± 0.3 V
VCCf = VCC max, RESET# = VSS ± 0.3 V,
Flash VCC Reset Current (Note 2)
ICC4
ICC5
f
f
µA
µA
WP#/ACC = VCCf ± 0.3 V
Flash VCC Current Automatic Sleep Mode VCCf = VCC max, VIH = VCC ± 0.3 V;
(Notes 2, 4)
VIL = VSS ± 0.3 V
Byte
Word
Byte
21
21
21
21
45
45
45
45
Flash VCC Active Read-While-Program
Current (Notes 1, 2)
ICC6
f
CE#f = VIL, OE# = VIH
mA
mA
Flash VCC Active Read-While-Erase
Current (Notes 1, 2)
ICC7f
CE#f = VIL, OE# = VIH
Word
Flash VCC Active
ICC8f
Program-While-Erase-Suspended Current CE#f = VIL, OE#f = VIH
(Notes 2, 5)
17
35
mA
ACC pin
VCC pin
5
10
30
mA
mA
V
ACC Accelerated Program Current,
CE#f = VIL, OE# = VIH
Word or Byte
IACC
15
VIL
VIH
Input Low Voltage
Input High Voltage
–0.2
0.8
V
CC + 0.2
2.4
V
Voltage for WP#/ACC Program
Acceleration and Sector
Protection/Unprotection
VHH
8.5
9.5
V
Voltage for Sector Protection, Autoselect
and Temporary Sector Unprotect
VID
VOL
11.5
12.5
0.45
V
V
Output Low Voltage
IOL = 4.0 mA, VCCf = VCCs = VCC min
IOH = –2.0 mA, VCCf = VCCs = VCC min
IOH = –100 µA, VCC = VCC min
0.85 x
VCC
VOH1
Output High Voltage
V
V
VOH2
VLKO
VCC–0.4
Flash Low VCC Lock-Out Voltage (Note 5)
2.3
2.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at
VIH
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. CC active while Embedded Erase or Embedded Program is in
progress.
4. Automatic sleep mode enables the low power mode when
addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 200 nA.
.
5. Not 100% tested.
I
July 19, 2002
Am49DL32xBG
37
P R E L I M I N A R Y
pSRAM DC & OPERATING CHARACTERISTICS
Parameter
Symbol
Parameter Description
Input Leakage Current
Output Leakage Current
Test Conditions
VIN = VSS to VCC
Min
–1.0
–1.0
Typ
Max
1.0
Unit
µA
ILI
CE1#s = VIH, CE2s = VIL or OE# = VIH or
WE# = VIL, VIO= VSS to VCC
ILO
1.0
µA
Cycle time = Min., IIO = 0 mA, 100% duty,
CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH,
tRC = Min.
I
CC1s
Operating Current
40
mA
mA
Cycle time = Min., IIO = 0 mA, 100% duty,
CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH,
tPC = Min.
Page Access Operating
Current
I
CC2s
VOL
25
Output Low Voltage
IOL = 1.0 mA
0.4
V
V
VOH
ISB
Output High Voltage
Standby Current (CMOS)
IOH = –0.5 mA
2
CE#1 = VCCS – 0.2 V, CE2 = VCCS – 0.2 V
70
5
µA
µA
IDSB
Deep Power-down Standby CE2 = 0.2 V
Input Low Voltage
–0.3
(Note 1)
VIL
VIH
0.4
V
V
VCC
0.3
+
Input High Voltage
2.4
(Note 2)
Notes:
1. VCC – 1.0 V for a 10 ns pulse width.
2. VCC + 1.0 V for a 10 ns pulse width.
38
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
FLASH DC CHARACTERISTICS
Zero-Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
10
8
3.3 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
July 19, 2002
Am49DL32xBG
39
P R E L I M I N A R Y
TEST CONDITIONS
Table 19. Test Specifications
3.3 V
Test Condition
70, 85
Unit
Output Load
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
40
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
CE#s Timing
Parameter
Test Setup
AllSpeeds
Unit
JEDEC
Std
Description
—
tCCR
CE#s Recover Time
—
Min
0
ns
E#f
tCCR
tCCR
E1#s
E2s
tCCR
tCCR
Figure 13. Timing Diagram for Alternating
Between Pseudo SRAM to Flash
July 19, 2002
Am49DL32xBG
41
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed
JEDEC
tAVAV
Std. Description
Test Setup
70
85
85
85
85
40
35
Unit
ns
tRC
Read Cycle Time (Note 1)
Min
Max
Max
Max
Max
Max
70
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tACC Address to Output Delay
CE#f, OE# = VIL
OE# = VIL
70
70
30
30
ns
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
ns
Output Enable to Output Delay
ns
Chip Enable to Output High Z (Notes 1, 3)
Output Enable to Output High Z (Notes 1, 3)
ns
30
0
ns
Output Hold Time From Addresses, CE#f or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
ns
ns
ns
Read
0
Output Enable Hold Time
(Note 1)
tOEH
Toggle and
Data# Polling
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 19 for test specifications
3. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the
data bus driven to VCC/2 is taken as tDF
.
tRC
Addresses Stable
tACC
Addresses
CE#f
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
42
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
Max
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#f, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#f, OE#
RESET#
tRP
Figure 15. Reset Timings
July 19, 2002
Am49DL32xBG
43
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Word/Byte Configuration (CIOf)
Parameter
Speed
JEDEC
Std
Description
70
85
Unit
ns
t
ELFL/tELFH
CE#f to CIOf Switching Low or High
CIOf Switching Low to Output HIGH Z
CIOf Switching High to Output Active
Max
Max
Min
5
tFLQZ
tFHQV
30
ns
70
85
ns
CE#f
OE#
CIOf
tELFL
Data Output
(DQ14–DQ0)
Data Output
(DQ7–DQ0)
CIOf
DQ0–DQ14
Switching
from word
to byte
Address
Input
DQ15
Output
mode
DQ15/A-1
tFLQZ
tELFH
CIOf
CIOf
Switching
from byte
to word
Data Output
(DQ7–DQ0)
Data Output
(DQ14–DQ0)
DQ0–DQ14
mode
Address
Input
DQ15
Output
DQ15/A-1
tFHQV
Figure 16. CIOf Timings for Read Operations
CE#f
WE#
The falling edge of the last WE# signal
CIOf
tSET
(tAS
)
tHOLD (tAH
)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 17. CIOf Timings for Write Operations
44
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed
JEDEC
tAVAV
Std
tWC
tAS
Description
70
85
Unit
ns
Write Cycle Time (Note 1)
Min
Min
Min
Min
70
85
tAVWL
Address Setup Time
0
ns
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
ns
tWLAX
40
40
45
45
ns
Address Hold Time From CE#f or OE# high
during toggle bit polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
ns
ns
ns
Data Hold Time
0
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tWLEL
tELWL
tWS
tCS
WE# Setup Time (CE#f to WE#)
CE#f Setup Time
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
tEHWH
tWHEH
tWLWH
tWHDL
tWH
WE# Hold Time (CE#f to WE#)
CE#f Hold Time
tCH
tWP
Write Pulse Width
30
35
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
Byte
30
0
5
tWHWH1
tWHWH1 Programming Operation (Note 2)
µs
µs
Word
7
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
tWHWH1
Typ
4
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Min
Max
0.4
50
0
sec
µs
tVCS
tRB
VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
ns
tBUSY
90
ns
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
July 19, 2002
Am49DL32xBG
45
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#f
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY/BY#
VCC
f
tVCS
otes:
. PA = program address, PD = program data, DOUT is the true data at the program address.
. Illustration shows device in word mode.
Figure 18. Program Operation Timings
VHH
VIL or VIH
WP#/ACC
VIL or VIH
tVHH
tVHH
Figure 19. Accelerated Program Timing Diagram
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Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
tWC
VA
Addresses
CE#f
2AAh
SADD
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
f
otes:
. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
.
These waveforms are for the word mode.
Figure 20. Chip/Sector Erase Operation Timings
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Am49DL32xBG
47
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
tWC
Valid PA
tWC
tRC
tWC
Valid PA
Valid RA
Valid PA
Addresses
tAH
tCPH
tACC
tCE
CE#f
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
Data
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE#f Controlled Write Cycles
Figure 21. Back-to-back Read/Write Cycle Timings
tRC
Addresses
CE#f
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 22. Data# Polling Timings (During Embedded Algorithms)
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Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
tAHT
tAS
Addresses
CE#f
tAHT
tASO
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 23. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 24. DQ2 vs. DQ6
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Am49DL32xBG
49
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
tVHH
Description
All Speed Options
Unit
ns
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
250
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
Min
Min
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
tRRB
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#f
WE#
tRRB
tRSP
RY/BY#
Figure 25. Temporary Sector Unprotect Timing Diagram
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Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
V
V
ID
IH
RESET#
SADD,
Valid*
Valid*
Valid*
Status
A6, A1, A0
Sector/Sector Block Protect or Unprotect
60h 60h
Verify
40h
Data
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
CE#f
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address.
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram
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51
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Parameter
Speed
70
JEDEC
tAVAV
Std
tWC
tAS
tAH
tDS
tDH
Description
85
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
70
85
tAVWL
tELAX
tDVEH
tEHDX
0
ns
40
40
45
45
ns
ns
0
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
CE#f Pulse Width
CE#f Pulse Width High
40
45
tCPH
30
5
Byte
Programming Operation
(Note 2)
tWHWH1
tWHWH1
µs
Word
7
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
Notes:
tWHWH1
tWHWH2
Typ
Typ
4
µs
Sector Erase Operation (Note 2)
0.4
sec
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
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Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SADD for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#f
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SADD = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings
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53
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Read Cycle
Speed
Parameter
Description
Symbol
Unit
70
70
70
70
85
85
85
85
tRC
tACC
tCO
tOE
Read Cycle Time
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Max
Max
Max
Max
Min
Min
Min
Max
Max
Max
Min
Min
Min
Max
Min
Chip Enable Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold from Address Change
Page Mode Time
25
25
10
0
tBA
tCOE
tOEE
tBE
0
tOD
tODO
tBD
20
20
20
10
70
30
30
10
tOH
tPM
tPC
Page Mode Cycle Time
tAA
Page Mode Address Access Time
Page Output Data Hold Time
tAOH
tRC
Addresses
A0 to A20
tACC
tOH
tCO
CE#1
Fixed High
CE2
OE#
tOD
tOE
tODO
WE#
tBA
LB#, UB#
tBE
tOEE
tBD
Indeterminate
High-Z
High-Z
D
OUT
Valid Data Out
I/O1 to 16
tCOE
Notes:
1. tOD, tODo, tBD, and tODW are defined as the time at which
the outputs achieve the open circuit condition and are
not referenced to output voltage levels.
3. If CE#, LB#, or UB# goes low at the same time or after WE#
goes low, the outputs will remain at high impedance.
2. If CE#, LB#, or UB# goes low at the same time or before
WE# goes high, the outputs will remain at high impedance.
Figure 28. Psuedo SRAM Read Cycle
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Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
tPM
Addresses
A0 to A2
tRC
tPC
tPC
tPC
Addresses
A3 to A20
CE#1
CE2
Fixed High
OE#
WE#
LB#, UB#
tOD
tOE
tBA
tBD
tOH
DOUT
tODO
tOEE
tAOH
tAOH
tAOH
tBE
D
OUT
DOUT
DOUT
DOUT
I/O1 to 16
tCOE
tCO
tAA
tAA
Maximum 8 words
tAA
tACC
Figure 29. Page Read Timing
Notes:
1. tOD, tODo, tBD, and tODW are defined as the time at which
the outputs achieve the open circuit condition and are
not referenced to output voltage levels.
3. If CE#, LB#, or UB# goes low at the same time or after WE#
goes low, the outputs will remain at high impedance.
2. If CE#, LB#, or UB# goes low at the same time or before
WE# goes high, the outputs will remain at high impedance.
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55
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Write Cycle
Speed
Parameter
Description
Symbol
Unit
70
70
50
60
60
85
85
60
70
70
tWC
tWP
tCW
tBW
tAS
Write Cycle Time
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Time
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
Min
Min
Min
Max
Min
Min
Min
Min
0
0
tWR
tODW
tOEW
tDS
Write Recovery Time
WE# Low to Write to Output High-Z
WE# High to Write to Output Active
Data Set-up Time
20
0
30
0
tDH
Data Hold from Write Time
CE2 Hold Time
ns
µs
tCH
300
tWC
Addresses
A0 to A20
tAS
tWR
tWP
WE#
tCW
CE#1
CE2
tCH
tBW
LB#, UB#
tODW
tOEW
(Note 3)
(Note 4)
High-Z
DOUT
I/O1 to 16
tDH
tDS
DIN
I/O1 to 16
(Note 1)
Valid Data In
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1s, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1s, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
Figure 30. Pseudo SRAM Write Cycle—WE# Control
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Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
tWC
Addresses
A0 to A20
tAS
tWP
tWR
WE#
tCW
CE#1
tCH
CE2
tBW
LB#, UB#
tBE
tODW
D
OUT
High-Z
High-Z
I/O1 to 16
tCOE
tDS
tDH
D
IN
(Note 1)
(Note 1)
Valid Data In
I/O1 to 16
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
Figure 31. Pseudo SRAM Write Cycle—CE1#s Control
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P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
tWC
Addresses
A0 to A20
tAS
tWP
tWR
WE#
tCW
CE#1
tCH
CE2
tBW
UB#, LB#
tCOE
tODW
tBE
High-Z
High-Z
DOUT
I/O1 to 16
tDS
Valid Data In
tDH
DIN
I/O1 to 16
(Note 1)
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
Figure 32. Pseudo SRAM Write Cycle—
UB#s and LB#s Control
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July 19, 2002
P R E L I M I N A R Y
FLASH ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
0.4
28
5
5
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
Byte Program Time
Accelerated Byte/Word Program Time
Word Program Time
150
120
210
63
4
µs
Excludes system level
overhead (Note 5)
7
µs
Byte Mode
Word Mode
21
14
Chip Program Time
(Note 3)
sec
42
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
12 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
+100 mA
V
CC Current
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
11
Max
14
Unit
pF
CIN
COUT
CIN2
Output Capacitance
VOUT = 0
VIN = 0
12
14
17
16
pF
Control Pin Capacitance
WP#/ACC Pin Capacitance
16
pF
CIN3
VIN = 0
20
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
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Am49DL32xBG
59
P R E L I M I N A R Y
pSRAM DATA RETENTION
Parameter
Parameter Description
Symbol
Min
Typ
Max
3.3
70
Unit
V
Test Setup
VDR
IDR
VCC for Data Retention
Data Retention Current
CS1#s ≥ VCC – 0.2 V (Note 1)
2.7
VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V
(Note 1)
1.0
(Note 2)
µA
tCS
tCH
CE2 Setup Time
0
300
10
0
ns
µs
ms
ns
µs
CE2 Hold Time
tDPD
tCHC
tCHP
CE2 Pulse Width
CE2 Hold from CE#1
CE2 Hold from Power On
30
Notes:
1. CE1#s ≥ VCC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled).
2. Typical values are not 100% tested.
pSRAM POWER ON AND DEEP POWER DOWN
CE#1
tDPD
CE#2
tcs
tCH
Figure 33. Deep Power-down Timing
Note: Data cannot be retained during deep power-down standby mode.
VDD min
VDD
tCHC
CE#1
tCHP
tCH
CE#2
Figure 34. Power-on Timing
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Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
pSRAM ADDRESS SKEW
over 10 µs
CE#1
WE#
Address
tRC min
Figure 35. Read Address Skew
Note: If multiple invalid address cycles shorter than tRC min occur for a period greater than 10 µs, at least one valid address
cycle over tRC min is required during that period.
over 10 µs
CE#1
tWP min
WE#
Address
tWC min
Figure 36. Write Address Skew
Note: If multiple invalid address cycles shorter than tWC min occur for a period greater than 10 µs, at least one valid address
cycle over tWC min, in addition to tWP min, is required during that period.
July 19, 2002
Am49DL32xBG
61
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm
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Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (March 8, 2002)
Initial release.
Revision A+1 (July 19, 2002)
Table 8. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection
Added Table.
Table 12. Command Definitions (Flash Word Mode)
Table 13. Command Definitions (Flash Byte Mode)
Modified Note 10. changed 80h to 82h and 00h to 02h.
Trademarks
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
July 19, 2002
Am49DL32xBG
63
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