M49000001Y [SPANSION]
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM; 64兆位(4M ×16位) CMOS 3.0伏只,同时操作闪存和16兆位( 1一M× 16位)伪静态RAM![M49000001Y](http://pdffile.icpdf.com/pdf1/p00102/img/icpdf/M49000001Y_547414_icpdf.jpg)
型号: | M49000001Y |
厂家: | ![]() |
描述: | 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM |
文件: | 总69页 (文件大小:956K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Am49PDL640AG
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 30049 Revision A Amendment +5 Issue Date November 20, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
PRELIMINARY
Am49PDL640AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and
16 Mbit (1 M x 16-Bit) Pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
■ 20 year data retention at 125°C
MCP Features
■ Power supply voltage of 2.7 to 3.1 volt
—
Reliable operation for the life of the system
SOFTWARE FEATURES
■ High performance
—
Access time as fast as 70 ns initial/ 25 ns subsequent
■ Software command-set compatible with JEDEC 42.4
■ Package
standard
—
73-Ball FBGA
—
Backward compatible with Am29F and Am29LV families
■ Operating Temperature
■ CFI (Common Flash Interface) complaint
—
–25°C to +85°C
—
Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■ Erase Suspend / Erase Resume
—
Suspends an erase operation to allow read or program
operations in other sectors of same bank
■ Simultaneous Read/Write operations
—
—
Data can be continuously read from one bank while
executing erase/program functions in another bank.
Zero latency between read and write operations
■ Unlock Bypass Program command
—
Reduces overall programming time when issuing multiple
program command sequences
■ Flex Bank™ architecture
HARDWARE FEATURES
—
4 separate banks, with up to two simultaneous operations
per device
Bank A: 8 Mbit (4 Kw x 8 and 32Kw x 15)
■ Any combination of sectors can be erased
—
—
—
—
■ Ready/Busy# output (RY/BY#)
Bank B: 24 Mbit (32 Kw x 48)
—
Hardware method for detecting program or erase cycle
completion
Bank C: 24 Mbit (32 Kw x 48)
■ Hardware reset pin (RESET#)
Bank D: 8 Mbit (4 Kw x 8 and 32 Kw x 15)
—
Hardware method of resetting the internal state machine to
the read mode
■ Manufactured on 0.17 µm process technology
■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector
■ WP#/ACC input pin
—
Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
—
Write protect (WP#) function protects sectors 0, 1, 140, and
141, regardless of sector protect status
—
Acceleration (ACC) function accelerates program timing
■ Persistent Sector Protection
—
A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
—
Customer lockable: Sector is one-time programmable. Once
sector is locked, data cannot be changed.
■ Zero Power Operation
Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■ Boot sectors
—
—
Sectors can be locked and unlocked in-system at VCC level
■ Password Sector Protection
—
A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
—
Top and bottom boot sectors in the same device
■ Compatible with JEDEC standards
—
Pinout and software compatible with single-power-supply
flash standard
Pseudo SRAM Features
■ Power dissipation
PERFORMANCE CHARACTERISTICS
■ High performance
—
—
Operating: 30 mA maximum
Standby: 100 µA maximum
—
—
Access time as fast as 70 ns
Program time: 4 µs/word typical utilizing Accelerate function
—
Deep Power-down current: 10 µA
■ Ultra low power consumption (typical values)
■ CE1s# and CE2s Chip Select
—
—
—
23 mA active read current
15 mA program/erase current
200 nA in standby or automatic sleep mode
■ Power down features using CE1s# and CE2s
■ Data retention supply voltage: 2.7 to 3.1 volt
■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
■ Multiple pSRAM vendors available
■ Minimum 1 million write cycles guaranteed per sector
Publication# 30049 Rev: A Amendment/+5
Issue Date: November 20, 2003
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. 11/20/03
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
Am29PDL640G Features
The Am29PDL640G is a 64 Mbit, 3.0 volt-only Page Mode
and Simultaneous Read/Write Flash memory device orga-
nized as 4 Mwords. The device is offered in 73-ball
Fine-pitch BGA packages. The word-wide data (x16) ap-
pears on DQ15-DQ0. This device can be programmed
in-system or in standard EPROM programmers. A 12.0 V
VPP is not required for write or erase operations.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard. Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
The device offers fast page access times of 25, 30, and 45
ns, with corresponding random access times of 65, 70, 85,
and 90 ns, respectively, allowing high speed microproces-
sors to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Device programming occurs by executing the program com-
mand sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to pro-
gram data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase op-
eration is complete by reading the DQ7 (Data# Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or ac-
cept another command.
Simultaneous Read/Write Operation with
Zero Latency
The Simultaneous Read/Write architecture provides simul-
taneous operation by dividing the memory space into 4
banks, which can be considered to be four separate memory
arrays as far as certain operations are concerned. The de-
vice can improve overall system performance by allowing a
host system to program or erase in one bank, then immedi-
ately and simultaneously read from another bank with zero
latency (with two simultaneous operations operating at any
one time). This releases the system from waiting for the
completion of a program or erase operation, greatly improv-
ing system performance.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or
via programming equipment.
The device can be organized in both top and bottom sector
configurations. The banks are organized as follows:
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
Bank
Sectors
A
B
C
D
8 Mbit (4 Kw x 8 and 32 Kw x 15)
24 Mbit (32 Kw x 48)
24 Mbit (32 Kw x 48)
8 Mbit (4 Kw x 8 and 32 Kw x 15)
Page Mode Features
The device is AC timing, input/output, and package compat-
ible with 4 Mbit x16 page mode mask ROM. The page size
is 8 words.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
After initial page access is accomplished, the page mode op-
eration provides fast read access speed of random locations
within that page.
AMD’s Flash technology combined years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V
to 3.1 V) for both read and write functions. Internally gener-
ated and regulated voltages are provided for the program
and erase operations.
2
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram . . . . . . . . . . . . . . . . 6
PSRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . .9
Random Read (Non-Page Read) ........................................ 11
Page Mode Read ................................................................ 11
Table 2. Page Select .......................................................................11
Simultaneous Operation ......................................................... 11
Table 3. Bank Select .......................................................................11
Writing Commands/Command Sequences ............................ 11
Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 12
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 13
Table 4. Am29PDL640G Sector Architecture .................................13
Table 5. Bank Address ....................................................................14
Table 6. SecSiTM SectorSecure Sector Addresses .........................14
Table 7. Am29PDL640G Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................15
Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . 16
Persistent Sector Protection ................................................... 16
Persistent Protection Bit (PPB) ............................................ 16
Persistent Protection Bit Lock (PPB Lock) .......................... 16
Dynamic Protection Bit (DYB) ............................................. 16
Table 8. Sector Protection Schemes ...............................................17
Persistent Sector Protection Mode Locking Bit ................... 17
Password Protection Mode ..................................................... 17
Password and Password Mode Locking Bit ........................ 18
64-bit Password ................................................................... 18
Write Protect (WP#) ................................................................ 18
Persistent Protection Bit Lock .............................................. 18
High Voltage Sector Protection .............................................. 19
Figure 1. In-System Sector Protection/
Sector Unprotection Algorithms ...................................................... 20
Temporary Sector Unprotect .................................................. 21
Figure 2. Temporary Sector Unprotect Operation........................... 21
SecSi™ (Secured Silicon) Sector
SectorFlash Memory Region ................................................. 21
SecSi Sector Protection Bit ................................................. 22
Figure 3. SecSi Sector Protect Verify.............................................. 22
Hardware Data Protection ...................................................... 23
Low VCC Write Inhibit ......................................................... 23
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Common Flash Memory Interface (CFI). . . . . . . 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 27
Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi™ Sector/Exit SecSi Sector
Word Program Command Sequence ...................................... 28
Unlock Bypass Command Sequence .................................. 28
Figure 4. Program Operation ......................................................... 29
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Erase Suspend/Erase Resume Commands ........................... 30
Figure 5. Erase Operation.............................................................. 30
Password Program Command ................................................ 30
Password Verify Command .................................................... 31
Password Protection Mode Locking Bit Program Command .. 31
Persistent Sector Protection Mode Locking Bit Program Com-
mand ....................................................................................... 31
SecSi Sector Protection Bit Program Command .................... 31
PPB Lock Bit Set Command ................................................... 31
DYB Write Command ............................................................. 31
Password Unlock Command .................................................. 32
PPB Program Command ........................................................ 32
All PPB Erase Command ........................................................ 32
DYB Write Command ............................................................. 32
PPB Lock Bit Set Command ................................................... 32
PPB Status Command ............................................................ 32
PPB Lock Bit Status Command .............................................. 32
Sector Protection Status Command ....................................... 32
Table 13. Memory Array Command Definitions ............................. 33
Table 14. Sector Protection Command Definitions ........................ 34
Write Operation Status . . . . . . . . . . . . . . . . . . . . 35
DQ7: Data# Polling ................................................................. 35
Figure 6. Data# Polling Algorithm .................................................. 35
DQ6: Toggle Bit I .................................................................... 36
Figure 7. Toggle Bit Algorithm........................................................ 36
DQ2: Toggle Bit II ................................................................... 37
Reading Toggle Bits DQ6/DQ2 ............................................... 37
DQ5: Exceeded Timing Limits ................................................ 37
DQ3: Sector Erase Timer ....................................................... 37
Table 15. Write Operation Status ................................................... 38
pSRAM Power Down . . . . . . . . . . . . . . . . . . . . . . 39
Figure 8. State Diagram................................................................. 39
Table 16. Standby Mode Characteristics ....................................... 39
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 40
Figure 9. Maximum Negative Overshoot Waveform ...................... 40
Figure 10. Maximum Positive Overshoot Waveform...................... 40
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 11. Test Setup.................................................................... 43
Figure 12. Input Waveforms and Measurement Levels ................. 43
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44
pSRAM CE#s Timing .............................................................. 44
Figure 13. Timing Diagram for Alternating
Between pSRAM to Flash.............................................................. 44
Read-Only Operations ........................................................... 45
Figure 14. Read Operation Timings............................................... 45
Figure 15. Page Read Operation Timings...................................... 46
Hardware Reset (RESET#) .................................................... 47
Figure 16. Reset Timings............................................................... 47
Erase and Program Operations .............................................. 48
Figure 17. Program Operation Timings.......................................... 49
Figure 18. Accelerated Program Timing Diagram.......................... 49
Figure 19. Chip/Sector Erase Operation Timings .......................... 50
Command Sequence .............................................................. 28
November 20, 2003
Am49PDL640AG
3
P R E L I M I N A R Y
Figure 20. Back-to-back Read/Write Cycle Timings ....................... 51
Write Cycle ............................................................................. 60
Figure 31. pSRAM Write Cycle–WE# Controlled........................... 61
Figure 32. pSRAM Write Cycle–CS1# Controlled.......................... 61
Figure 33. pSRAM Write Cycle–UB#, LB# Controlled ................... 62
Figure 34. Deep Power Down Mode.............................................. 62
Figure 35. Abnormal Timing........................................................... 63
Figure 36. Avoidable Timing 1 ....................................................... 63
Figure 37. Avoidable Timing 2 ....................................................... 63
Erase And Programming Performance . . . . . . . 64
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 64
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 64
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 64
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 65
FLK073—73-Ball Fine-Pitch Grid Array 13 x 9 mm ................ 65
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 21. Data# Polling Timings (During Embedded Algorithms).. 51
Figure 22. Toggle Bit Timings (During Embedded Algorithms)....... 52
Figure 23. DQ2 vs. DQ6.................................................................. 52
Temporary Sector Unprotect .................................................. 53
Figure 24. Temporary Sector Unprotect Timing Diagram ............... 53
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram .............................................................. 54
Alternate CE#f Controlled Erase and Program Operations .... 55
Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings........................................................................... 56
Power Up Time ....................................................................... 57
Figure 27. Power Up ....................................................................... 57
Figure 28. VCCS Slew Rate............................................................ 57
Read Cycle ............................................................................. 58
Read Cycle ............................................................................. 59
Figure 29. pSRAM Read Cycle–Address Controlled ...................... 59
Figure 30. pSRAM Read Cycle–CS1# Controlled........................... 59
4
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Part Number
Am49PDL640AG
Flash Memory
Pseudo SRAM
Speed
Options
Standard Voltage Range:
VCC = 2.7–3.1 V
70
70
25
70
25
85
85
30
85
30
70
70
85
85
Max Access Time (ns) tACC
Max Page Access (ns) tPACC
CE#f Access (ns) tCE
N/A
70
N/A
85
OE# Access (ns) tOE
35
40
MCP BLOCK DIAGRAM
VCC
f
VSS
A21 to A0
RY/BY#
A21 to A0
WP#/ACC
RESET#
CE#f
64 MBit
Flash Memory
DQ15 to DQ0
DQ15 to DQ0
VCCs/VCCQ VSS/VSSQ
A19 to A0
16 MBit
Pseudo SRAM
LB#s
DQ15 to DQ0
UB#s
WE#
OE#
CE1#s
CE2s
November 20, 2003
Am49PDL640AG
5
P R E L I M I N A R Y
FLASH MEMORY BLOCK DIAGRAM
V
V
CC
OE#
SS
Mux
Bank 1
Bank 1 Address
A21–A0
X-Decoder
Bank 2 Address
RY/BY#
Bank 2
X-Decoder
A21–A0
RESET#
STATE
CONTROL
&
COMMAND
REGISTER
Status
WE#
CE#
DQ15–DQ0
WP#/ACC
Control
Mux
DQ15–DQ0
X-Decoder
Bank 3
Bank 3 Address
Bank 4 Address
X-Decoder
Bank 4
A21–A0
Mux
PSRAM BLOCK DIAGRAM
Standby/Deep Power
Down Mode Control
Refresh Control
V
CC
V
SS
Refresh
Counter
Memory Cell Array
1 M x 16
Row
Address
Decoder
Address
Buffer
A19-A0
DQ7-DQ0
Sense AMP
Input
Data
Contol
Output
Data
Control
DQ15-DQ8
Column Decoder
Address Buffer
CE#1
CE2
OE#
WE#
Control
Logic
LB#
UB#
6
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
CONNECTION DIAGRAM
73-Ball FBGA
Top View
Flash only
A1
A10
NC
NC
Pseudo
SRAM only
B1
B5
B6
B10
NC
NC
NC
NC
Shared
C5
C1
C3
C4
C6
C7
C8
NC
A7
LB#s WP#/ACC WE#
A8
A11
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
A21
F9
NC
UB#s RESET#1 CE2s
E5
E2
A2
E3
A5
E4
A18
F4
E6
RY/BY
A20
F1
NC
G1
NC
F2
A1
F3
A4
F7
F10
A17
G4
DQ1
H4
A10
G7
DQ6
H7
A14
G8
NC
NC
G2
A0
G3
G9 G10
V
SS
A16
H9
NC
J9
NC
H2
CE#f
J2
H3
OE#
J3
H5
DQ3
J5
H6
DQ4
J6
H8
DQ9
J4
DQ13 DQ15
J7
DQ12
K7
J8
DQ7
K8
V
CC
f
V s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
DQ11
L5
K6
NC
L6
NC
DQ8
DQ2
DQ5
DQ14
L1
NC
M1
NC
L10
NC
NC
M10
NC
integrity may be compromised if the package body is
exposed to temperatures above 150°C for prolonged
periods of time.
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (BGA). The package and/or data
November 20, 2003
Am49PDL640AG
7
P R E L I M I N A R Y
PIN DESCRIPTION
LOGIC SYMBOL
A19–A0
A21–A20
DQ15–DQ0
CE#f
= 20 Address Inputs (Common)
19
= 2 Address Inputs (Flash)
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
A19–A0
A21–A20
CE#f
CE#1s
CE2s
= Chip Enable 1 (pSRAM)
= Chip Enable 2 (pSRAM)
= Output Enable (Common)
= Write Enable (Common)
= Ready/Busy Output
16 or 8
CE#1s
CE2s
DQ15–DQ0
RY/BY#
OE#
WE#
OE#
RY/BY#
UB#s
WE#
= Upper Byte Control (pSRAM)
= Lower Byte Control (pSRAM)
= Hardware Reset Pin, Active Low
WP#/ACC
RESET#
UB#s
LB#s
RESET#
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
LB#s
VCC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
VCC
VSS
NC
s
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
8
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am49PDL640 70
A
G
a
N
T
TAPE AND REEL
T
S
=
=
7 inches
13 inches
TEMPERATURE RANGE
Light Industrial (–25°C to +85°C)
N
=
SPEED OPTION
See Product Selector Guide and Valid Combinations
pSRAM VENDOR
Blank = Etron
a
=
Si-7
PROCESS TECHNOLOGY
0.17 µm
G
=
Pseudo SRAM DEVICE DENSITY
16 Mbits
A
=
AMD DEVICE NUMBER/DESCRIPTION
Am49PDL640AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29PDL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
Valid Combinations
Valid Combinations
Order Number
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
Package Marking
M49000001Y
M49000001Z
M49000004F
M49000004G
Am49PDL640AG70N
Am49PDL640AG85N
Am49PDL640AGa70N
Am29PDL640AGa85N
T, S
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
November 20, 2003
Am49PDL640AG
9
P R E L I M I N A R Y
Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH
WP#/
ACC
(Note 4)
Operation
(Notes 1, 2)
LB#s
(Note 3) (Note 3)
UB#s
DQ7– DQ15–
CE#f
CE1#s
CE2s OE# WE#
Addr.
RESET#
DQ0
DQ8
(Note 7)
(Note 8)
(Note 7)
(Note 8)
H
H
H
H
H
Read from Active
Flash
AIN
AIN
DOUT
DOUT
L
L
L
H
L
X
X
X
X
H
H
L/H
L
H
L
Write to Active
Flash
DIN
DIN
H
(Note 5)
VCC
0.3 V
VCC
0.3 V
Standby
H
H
H
L
X
X
X
X
X
X
X
X
X
X
H
H
High-Z High-Z
High-Z High-Z
VCC
VCC
Deep Power-down Standby
(Note 10)
0.3 V
0.3 V
H
H
H
H
X
X
X
X
X
X
Output Disable (Note 9)
L
L
H
H
L
L/H
L/H
High-Z High-Z
High-Z High-Z
(Note 7)
(Note 8)
(Note 7)
H
H
H
H
L
Flash Hardware
Reset
X
X
X
X
X
X
H
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Notes 5, 9)
VID
DIN
L
H
L
X
X
L/H
X
(Note 8)
(Note 7)
(Note 8)
H
H
H
L
H
L
SADD,
A6 = H,
A1 = H,
A0 = L
Sector Unprotect
(Notes 5, 9)
VID
DIN
L
X
H
H
X
L
L
X
H
X
X
X
X
(Note 6)
(Note 6)
X
X
(Note 7)
(Note 8)
H
H
H
L
Temporary
Sector Unprotect
VID
DIN
X
High-Z
DOUT
DOUT
DOUT
L
H
L
L
L
AIN
Read from pSRAM
Write to pSRAM
L
L
H
H
H
H
High-Z
DOUT
DIN
H
L
High-Z
DIN
L
AIN
DIN
H
X
L
H
L
L
X
High-Z
DIN
H
High-Z
=
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN
Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are
6. If WP#/ACC = VIL, the two outermost boot sectors remain
protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or
inhibited.
2. Do not apply CE#f1 = VIL, CE1#s = VIL and CE2s = VIH at the
same time.
unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = VHH, all sectors will
be unprotected.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC
= VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by
40%.
7. Data will be retained in pSRAM.
8. Data will be lost in pSRAM.
9. CE# inputs on both flash devices may be held low for this
operation
5. The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
10. Deep Power-down Standby is not available.
10
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
Table 2. Page Select
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
Word
A2
0
A1
A0
0
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
0
0
1
1
0
0
1
1
0
1
0
0
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
0
1
1
0
1
1
1
0
1
1
Simultaneous Operation
Refer to the AC Read-Only Operations table for timing
specifications and to Figure 14 for the timing diagram.
ICC1 in the DC Characteristics table represents the ac-
tive current specification for reading array data.
The device is capable of reading data from one bank
of memory while a program or erase operation is in
progress in another bank of memory (simultaneous
operation), in addition to the conventional features
(read, program, erase-suspend read, and erase-sus-
pend program). The bank selected can be selected by
bank addresses (A21–A19) with zero latency.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
inputs (assuming the addresses have been stable for
at least tACC–tOE time).
The simultaneous operation can execute multi-func-
tion mode in the same bank.
Table 3. Bank Select
Bank
A21–A19
000
Bank A
Bank B
Bank C
Bank D
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 8 words, with the appropriate page being
selected by the higher address bits A21–A3 and the
LSB bits A2–A0 determining the specific word within
that page. This is an asynchronous operation with the
microprocessor supplying the specific word location.
001, 010, 011
100, 101, 110
111
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Here again, CE# selects
the device and OE# is the output control and should
be used to gate data to the output inputs if the device
is selected. Fast page mode accesses are obtained by
keeping A21–A3 constant and changing A2 to A0 to
select the specific word within that page.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once a bank enters the Un-
lock Bypass mode, only two write cycles are required
to program a word, instead of four. The “Word Pro-
gram Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 4 indicates the address
space that each sector occupies. A “bank address” is
the address bits required to uniquely select a bank.
Similarly, a “sector address” refers to the address bits
November 20, 2003
Am49PDL640AG
11
P R E L I M I N A R Y
required to uniquely select a sector. The “Command
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Definitions” section has details on erasing a sector or
the entire chip, or suspending/resuming the erase op-
eration.
ICC3 in the table represents the CMOS standby cur-
rent specification.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The Flash
AC Characteristics section contains timing specifica-
tion tables and timing diagrams for write operations.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
Accelerated Program Operation
this mode when addresses remain stable for tACC
+
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput at the
factory.
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Note that during automatic sleep mode, OE# must be
at VIH before the device reduces current to the stated
sleep mode specification. ICC5 in the table repre-
sents the automatic sleep mode current specification.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that VHH must not be asserted on
WP#/ACC for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the WP#/ACC pin should be raised to VCC when not in
use. That is, the WP#/ACC pin should not be left float-
ing or unconnected; inconsistent behavior of the de-
vice may result.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS 0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is
held at VIL but not within VSS 0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The sys-
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VIO 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VIO 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
12
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
Table 4. Am29PDL640G Sector Architecture
Output Disable Mode
Sector
Address
A21–A12
Sector
Size
(Kwords)
When the OE# input is at VIH, output from the device is
disabled. The output pins (except for RY/BY#) are
placed in the high impedance state.
Bank Sector
Address Range
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
80000h–87FFFh
88000h–8FFFFh
Table 4. Am29PDL640G Sector Architecture
90000h–97FFFh
Sector
Address
A21–A12
Sector
Size
(Kwords)
98000h–9FFFFh
Bank Sector
Address Range
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
SA0
SA1
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
4
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
4
SA2
4
SA3
4
SA4
4
SA5
4
SA6
4
SA7
4
SA8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA9
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
November 20, 2003
Am49PDL640AG
13
P R E L I M I N A R Y
Table 4. Am29PDL640G Sector Architecture Table 4. Am29PDL640G Sector Architecture
Sector
Address
A21–A12
Sector
Size
(Kwords)
Sector
Address
A21–A12
Sector
Size
(Kwords)
Bank Sector
Address Range
Bank Sector
Address Range
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
1100110xxx
1100111xxx
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
SA134 1111111000
SA135 1111111001
SA136 1111111010
SA137 1111111011
SA138 1111111100
SA139 1111111101
SA140 1111111110
SA141 1111111111
4
4
4
4
4
4
4
Table 5. Bank Address
Bank
A21–A19
000
A
B
C
D
001, 010, 011
100, 101, 110
111
Table 6. SecSiTM SectorSecure Sector Addresses
Device
Sector Size
Address Range
Am29PDL640G
128 words
00000h–0007Fh
14
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
Autoselect Mode
Sector/
Sector Block Size
Sector
A21–A12
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
must be as shown in Table 7. In addition, when verify-
ing sector protection, the sector address must appear
on the appropriate highest order address bits (see
Table 4). Table 7 shows the remaining address bits
that are don’t care. When all necessary bits have been
set as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
However, the autoselect codes can also be accessed
in-system through the command register, for instances
when the device is erased or programmed in a system
without access to high voltage on the A9 pin. The com-
mand sequence is illustrated in Table 14. Note that if a
Bank Address (BA) on address bits A21, A20, and A19
is asserted during the third write cycle of the autose-
lect command, the host system can read autoselect
data that bank and then immediately read array data
from the other bank, without exiting the autoselect
mode.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 14. This method
does not require VID. Refer to the Autoselect Com-
mand Sequence section for more information.
Table 7. Am29PDL640G Boot Sector/Sector Block
Addresses for Protection/Unprotection
1111100XXX,
1111101XXX,
1111110XXX
SA131–SA133
96 (3x32) Kwords
Sector/
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A21–A12
Sector Block Size
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111101
1111111111
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
0000001XXX,
0000010XXX,
0000011XXX
SA8–SA10
96 (3x32) Kwords
November 20, 2003
Am49PDL640AG
15
P R E L I M I N A R Y
SECTOR PROTECTION
The Am29PDL640G features several levels of sector
protection, which can disable both the program and
erase operations in certain sectors or sector groups:
■ Persistently Locked—The sector is protected and
cannot be changed.
■ Dynamically Locked—The sector is protected and
can be changed by a simple command.
Persistent Sector Protection
■ Unlocked—The sector is unprotected and can be
A command sector protection method that replaces
the old 12 V controlled protection method.
changed by a simple command.
To achieve these states, three types of “bits” are used:
Password Sector Protection
A highly sophisticated protection method that requires
a password before changes to certain sectors or sec-
tor groups are permitted
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is as-
signed to a maximum four sectors (see the sector ad-
dress tables for specific sector protection groupings).
All 4 Kword boot-block sectors have individual sector
Persistent Protection Bits (PPBs) for greater flexibility.
Each PPB is individually modifiable through the PPB
Write Command.
WP# Hardware Protection
A write protect pin that can prevent program or erase
operations in sectors 0, 1, 140, and 141.
All parts default to operate in the Persistent Sector
Protection mode. The customer must then choose if
the Persistent or Password Protection method is most
desirable. There are two one-time programmable
non-volatile bits that define which sector protection
method will be used. If the Persistent Sector Protec-
tion method is desired, programming the Persistent
Sector Protection Mode Locking Bit permanently
sets the device to the Persistent Sector Protection
mode. If the Password Sector Protection method is de-
sired, programming the Password Mode Locking Bit
permanently sets the device to the Password Sector
Protection mode. It is not possible to switch between
the two protection modes once a locking bit has been
set. One of the two modes must be selected when
the device is first programmed. This prevents a pro-
gram or virus from later setting the Password Mode
Locking Bit, which would cause an unexpected shift
from the default Persistent Sector Protection Mode
into the Password Protection Mode.
The device erases all PPBs in parallel. If any PPB re-
quires erasure, the device must be instructed to pre-
program all of the sector PPBs prior to PPB erasure.
Otherwise, a previously erased sector PPBs can po-
tentially be over-erased. The flash device does not
have a built-in means of preventing sector PPBs
over-erasure.
Persistent Protection Bit Lock (PPB Lock)
The Persistent Protection Bit Lock (PPB Lock) is a glo-
bal volatile bit. When set to “1”, the PPBs cannot be
changed. When cleared (“0”), the PPBs are change-
able. There is only one PPB Lock bit per device. The
PPB Lock is cleared after power-up or hardware reset.
There is no command sequence to unlock the PPB
Lock.
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector.
After power-up or hardware reset, the contents of all
DYBs is “0”. Each DYB is individually modifiable
through the DYB Write Command.
The WP# Hardware Protection feature is always avail-
able, independent of the software managed protection
method chosen.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at the factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
When the parts are first shipped, the PPBs are
cleared, the DYBs are cleared, and PPB Lock is de-
faulted to power up in the cleared state – meaning the
PPBs are changeable.
When the device is first powered on the DYBs power
up cleared (sectors not protected). The Protection
State for each sector is determined by the logical OR
of the PPB and the DYB related to that sector. For the
sectors that have the PPBs cleared, the DYBs control
whether or not the sector is protected or unprotected.
By issuing the DYB Write command sequences, the
DYBs will be set or cleared, thus placing each sector in
the protected or unprotected state. These are the
so-called Dynamic Locked or Unlocked states. They
are called dynamic states because it is very easy to
It is possible to determine whether a sector is pro-
tected or unprotected. See Autoselect Mode for de-
tails.
Persistent Sector Protection
The Persistent Sector Protection method replaces the
12 V controlled protection method in previous AMD
flash devices. This new method provides three differ-
ent sector protection states:
16
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
switch back and forth between the protected and un-
Table 8. Sector Protection Schemes
protected conditions. This allows software to easily
protect sectors against inadvertent changes yet does
not prevent the easy removal of protection when
changes are needed. The DYBs maybe set or cleared
as often as needed.
PPB
Lock
DYB
PPB
Sector State
Unprotected—PPB and DYB are
changeable
0
0
0
The PPBs allow for a more static, and difficult to
change, level of protection. The PPBs retain their state
across power cycles because they are non-volatile. In-
dividual PPBs are set with a command but must all be
cleared as a group through a complex sequence of
program and erasing commands. The PPBs are also
limited to 100 erase cycles.
Unprotected—PPB not
changeable, DYB is changeable
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
0
0
0
1
1
1
Protected—PPB and DYB are
changeable
The PPB Lock bit adds an additional level of protec-
tion. Once all PPBs are programmed to the desired
settings, the PPB Lock may be set to “1”. Setting the
PPB Lock disables all program and erase commands
to the non-volatile PPBs. In effect, the PPB Lock Bit
locks the PPBs into their current state. The only way to
clear the PPB Lock is to go through a power cycle.
System boot code can determine if any changes to the
PPB are needed; for example, to allow new system
code to be downloaded. If no changes are needed
then the boot code can set the PPB Lock to disable
any further changes to the PPBs during system opera-
tion.
Protected—PPB not
changeable, DYB is changeable
Table 9 contains all possible combinations of the DYB,
PPB, and PPB lock relating to the status of the sector.
In summary, if the PPB is set, and the PPB lock is set,
the sector is protected and the protection can not be
removed until the next power cycle clears the PPB
lock. If the PPB is cleared, the sector can be dynami-
cally locked or unlocked. The DYB then controls
whether or not the sector is protected or unprotected.
The WP#/ACC write protect pin adds a final level of
hardware protection to sectors 0, 1, 140, and 141.
When this pin is low it is not possible to change the
contents of these sectors. These sectors generally
hold system boot code. The WP#/ACC pin can prevent
any changes to the boot code that could override the
choices made while setting up sector protection during
system initialization.
If the user attempts to program or erase a protected
sector, the device ignores the command and returns to
read mode. A program command to a protected sector
enables status polling for approximately 1 µs before
the device returns to read mode without having modi-
fied the contents of the protected sector. An erase
command to a protected sector enables status polling
for approximately 50 µs after which the device returns
to read mode without having erased the protected sec-
tor.
It is possible to have sectors that have been persis-
tently locked, and sectors that are left in the dynamic
state. The sectors in the dynamic state are all unpro-
tected. If there is a need to protect some of them, a
simple DYB Write command sequence is all that is
necessary. The DYB write command for the dynamic
sectors switch the DYBs to signify protected and un-
protected, respectively. If there is a need to change the
status of the persistently locked sectors, a few more
steps are required. First, the PPB Lock bit must be dis-
abled by either putting the device through a power-cy-
cle, or hardware reset. The PPBs can then be
changed to reflect the desired settings. Setting the
PPB lock bit once again will lock the PPBs, and the de-
vice operates normally again.
The programming of the DYB, PPB, and PPB lock for a
given sector can be verified by writing a
DYB/PPB/PPB lock verify command to the device.
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sec-
tor Protection mode locking bit exists to guarantee that
the device remain in software sector protection. Once
set, the Persistent Sector Protection locking bit pre-
vents programming of the password protection mode
locking bit. This guarantees that a hacker could not
place the device in password protection mode.
The best protection is achieved by executing the PPB
lock bit set command early in the boot code, and pro-
tect the boot code by holding WP#/ACC = VIL.
Password Protection Mode
The Password Sector Protection Mode method allows
an even higher level of security than the Persistent
Sector Protection Mode. There are two main differ-
ences between the Persistent Sector Protection and
the Password Sector Protection Mode:
November 20, 2003
Am49PDL640AG
17
P R E L I M I N A R Y
■ When the device is first powered on, or comes out
The Password Mode Locking Bit, once set, prevents
reading the 64-bit password on the DQ bus and further
password programming. The Password Mode Locking
Bit is not erasable. Once Password Mode Locking Bit
is programmed, the Persistent Sector Protection Lock-
ing Bit is disabled from programming, guaranteeing
that no changes to the protection scheme are allowed.
of a reset cycle, the PPB Lock bit set to the locked
state, rather than cleared to the unlocked state.
■ The only means to clear the PPB Lock bit is by writ-
ing a unique 64-bit Password to the device.
The Password Sector Protection method is otherwise
identical to the Persistent Sector Protection method.
64-bit Password
A 64-bit password is the only additional tool utilized in
this method.
The 64-bit Password is located in its own memory
space and is accessible through the use of the Pass-
word Program and Verify commands (see “Password
Verify Command”). The password function works in
conjunction with the Password Mode Locking Bit,
which when set, prevents the Password Verify com-
mand from reading the contents of the password on
the pins of the device.
The password is stored in a one-time programmable
(OTP) region of the flash memory. Once the Password
Mode Locking Bit is set, the password is permanently
set with no means to read, program, or erase it. The
password is used to clear the PPB Lock bit. The Pass-
word Unlock command must be written to the flash,
along with a password. The flash device internally
compares the given password with the pre-pro-
grammed password. If they match, the PPB Lock bit is
cleared, and the PPBs can be altered. If they do not
match, the flash device does nothing. There is a
built-in 2 µs delay for each “password check.” This
delay is intended to thwart any efforts to run a program
that tries all possible combinations in order to crack
the password.
Write Protect (WP#)
The Write Protect feature provides a hardware method
of protecting sectors 0, 1, 140, and 141 without using
VID. This function is provided by the WP# pin and over-
rides the previously discussed High Voltage Sector
Protection method.
If the system asserts VIL on the WP#/ACC pin, the de-
vice disables program and erase functions in the two
outermost 4 Kword sectors on both ends of the flash
array independent of whether it was previously pro-
tected or unprotected.
Password and Password Mode Locking Bit
In order to select the Password sector protection
scheme, the customer must first program the pass-
word. The password may be correlated to the unique
Electronic Serial Number (ESN) of the particular flash
device. Each ESN is different for every flash device;
therefore each password should be different for every
flash device. While programming in the password re-
gion, the customer may perform Password Verify oper-
ations.
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether sectors 0, 1, 140, and 141
were last set to be protected or unprotected. That is,
sector protection or unprotection for these sectors de-
pends on whether they were last protected or unpro-
tected using the method described in High Voltage
Sector Protection.
Once the desired password is programmed in, the
customer must then set the Password Mode Locking
Bit. This operation achieves two objectives:
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
1. Permanently sets the device to operate using the
Password Protection Mode. It is not possible to re-
verse this function.
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile
bit that reflects the state of the Password Mode Lock-
ing Bit after power-up reset. If the Password Mode
Lock Bit is also set after a hardware reset (RESET#
asserted) or a power-up reset, the ONLY means for
clearing the PPB Lock Bit in Password Protection
Mode is to issue the Password Unlock command. Suc-
cessful execution of the Password Unlock command
clears the PPB Lock Bit, allowing for sector PPBs
modifications. Asserting RESET#, taking the device
through a power-on reset, or issuing the PPB Lock Bit
Set command sets the PPB Lock Bit to a “1” when the
Password Mode Lock Bit is not set.
2. Disables all further commands to the password re-
gion. All program, and read operations are ignored.
Both of these objectives are important, and if not care-
fully considered, may lead to unrecoverable errors.
The user must be sure that the Password Protection
method is desired when setting the Password Mode
Locking Bit. More importantly, the user must be sure
that the password is correct when the Password Mode
Locking Bit is set. Due to the fact that read operations
are disabled, there is no means to verify what the
password is afterwards. If the password is lost after
setting the Password Mode Locking Bit, there will be
no way to clear the PPB Lock bit.
18
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
If the Password Mode Locking Bit is not set, including
High Voltage Sector Protection
Persistent Protection Mode, the PPB Lock Bit is
cleared after power-up or hardware reset. The PPB
Lock Bit is set by issuing the PPB Lock Bit Set com-
mand. Once set the only means for clearing the PPB
Lock Bit is by issuing a hardware or power-up reset.
The Password Unlock command is ignored in Persis-
tent Protection Mode.
Sector protection and unprotection may also be imple-
mented using programming equipment. The proce-
dure requires high voltage (VID) to be placed on the
RESET# pin. Refer to Figure Note: for details on this
procedure. Note that for sector unprotect, all unpro-
tected sectors must first be protected prior to the first
sector write cycle.
November 20, 2003
Am49PDL640AG
19
P R E L I M I N A R Y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 µs
Wait 1 µs
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Note:These algorithms are valid only in Persistent Sector Protection Mode. They are not valid in Password Protection Mode.
Figure 1. In-System Sector Protection/
Sector Unprotection Algorithms
20
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
AMD offers the device with the SecSi Sector either
Temporary Sector Unprotect
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to utilize the
sector in any manner they choose. The customer-lock-
able version has the SecSi (Secured Silicon) Sector
Indicator Bit permanently set to a “0.” Thus, the SecSi
Sector Indicator Bit prevents customer-lockable de-
vices from being used to replace devices that are fac-
tory locked.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 23 shows the timing diagrams, for this feature.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi™ Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the boot sectors. This
mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until
power is removed from the device. On power-up, or
following a hardware reset, the device reverts to send-
ing commands to the normal address space. Note that
the ACC function and unlock bypass modes are not
available when the SecSi Sector is enabled.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
Temporary Sector
Unprotect Completed
(Note 2)
In a factory locked device, the SecSi Sector is pro-
tected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is preprogrammed with both a random number
and a secure ESN. The SecSi Sector is located at ad-
dresses 000000h–00007Fh in Persistent Protection
mode, and at addresses 000005h–00007Fh in Pass-
word Protection mode. The device is available prepro-
grammed with one of the following:
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
sectors 0, 1, 140, 141 will remain protected).
2. All previously protected sectors are protected once
again.
■ A random, secure ESN only
Figure 2. Temporary Sector Unprotect Operation
■ Customer code through the ExpressFlash service
■ Both a random, secure ESN and customer code
through the ExpressFlash service.
SecSi™ (Secured Silicon) Sector
SectorFlash Memory Region
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. AMD
programs the customer’s code, with or without the ran-
dom ESN. The devices are then shipped from AMD’s
factory with the SecSi Sector permanently locked.
Contact an AMD representative for details on using
AMD’s ExpressFlash service.
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is up to 128 words in length,
and uses a SecSi Sector Indicator Bit (DQ7) to indi-
cate whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
If the security feature is not required, the SecSi Sec-
torSecure Sector can be treated as an additional Flash
memory space. The SecSi Sector can be read any
November 20, 2003
Am49PDL640AG
21
P R E L I M I N A R Y
number of times, but can be programmed and locked
SecSi Sector Protection Bit
only once. Note that the accelerated programming
(ACC) and unlock bypass functions are not available
when programming the SecSi Sector.
The SecSi Sector Protection Bit prevents program-
ming of the SecSi Sector memory area. Once set, the
SecSi Sector memory area contents are non-modifi-
able.
The SecSi Sector area can be protected using one of
the following procedures:
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure Note:,
except that RESET# may be at either VIH or VID.
This allows in-system protection of the SecSi Sector
Region without raising any device pin to a high volt-
age. Note that this method is only applicable to the
SecSi Sector.
START
If data = 00h,
RESET# =
SecSi Sector is
VIH or VID
unprotected.
If data = 01h,
SecSi Sector is
protected.
Wait 1 µs
Write 60h to
any address
■ To verify the protect/unprotect status of the SecSi
Remove VIH or VID
from RESET#
Sector, follow the algorithm shown in Figure 3.
Once the SecSi Sector is locked and verified, the sys-
tem must write the Exit SecSi Sector Region com-
mand sequence to return to reading and writing the
remainder of the array.
Write 40h to SecSi
Sector address
Write reset
with A6 = 0,
command
A1 = 1, A0 = 0
The SecSi Sector lock must be used with caution
since, once locked, there is no procedure available for
unlocking the SecSi Sector area and none of the bits
in the SecSi Sector memory space can be modified in
any way.
SecSi Sector
Read from SecSi
Protect Verify
Sector address
complete
with A6 = 0,
A1 = 1, A0 = 0
Figure 3. SecSi Sector Protect Verify
22
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
Hardware Data Protection
COMMON FLASH MEMORY INTERFACE
(CFI)
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 10–13. To terminate reading CFI data,
the system must write the reset command. The CFI
Query mode is not accessible when the device is exe-
cuting an Embedded Program or embedded Erase al-
gorithm.
greater than VLKO
.
Write Pulse “Glitch” Protection
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 10–13. The
system must write the reset command to return the
device to reading array data.
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an AMD representative for copies of
these documents.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
November 20, 2003
Am49PDL640AG
23
P R E L I M I N A R Y
Table 9. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 10. System Interface String
Description
Addresses
Data
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0031h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0004h
0000h
0009h
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
24
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
Table 11. Device Geometry Definition
Addresses
Data
Description
27h
0017h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
007Dh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
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Am49PDL640AG
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P R E L I M I N A R Y
Table 12. Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0004h
Silicon Revision Number (Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
0002h
0001h
0001h
0007h
0077h
0000h
0002h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors excluding Bank 1
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
0085h
0095h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
4Fh
0001h
00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both
Top and Bottom
Program Suspend
50h
57h
58h
59h
5Ah
5Bh
0001h
0004h
0017h
0030h
0030h
0017h
0 = Not supported, 1 = Supported
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
Bank 1 Region Information
X = Number of Sectors in Bank 1
Bank 2 Region Information
X = Number of Sectors in Bank 2
Bank 3 Region Information
X = Number of Sectors in Bank 3
Bank 4 Region Information
X = Number of Sectors in Bank 4
26
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P R E L I M I N A R Y
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 14 defines the valid register command
sequences. Writing incorrect address and data values
or writing them in the improper sequence may place
the device in an unknown state. A reset command is
then required to return the device to reading array
data.
erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
which the system was writing to the read mode. If the
program command sequence is written to a bank that
is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-sus-
pend-read mode. Once programming begins, however,
the device ignores reset commands until the operation
is complete.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If a bank
entered the autoselect mode while in the Erase Sus-
pend mode, writing the reset command returns that
bank to the erase-suspend-read mode.
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. The system can read array data using the
standard read timing, except that if it reads at an ad-
dress within erase-suspended sectors, the device out-
puts status data. After completing a programming
operation in the Erase Suspend mode, the system
may once again read array data with the same excep-
tion. See the Erase Suspend/Erase Resume Com-
mands section for more information.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to the
read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
The autoselect command sequence may be written to
an address within a bank that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively pro-
gramming or erasing in the other bank.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
Note that the ACC function and unlock bypass modes
are not available when the SecSi Sector is enabled.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au-
toselect command. The bank then enters the autose-
lect mode. The system may read any number of
autoselect codes without reinitiating the command se-
quence.
See also Requirements for Reading Array Data in the
section for more information. The Read-Only Opera-
tions table provides the read parameters, and Figure
14 shows the timing diagram.
Table 14 shows the address and data requirements.
To determine sector protection information, the system
must write to the appropriate bank address (BA) and
sector address (SA). Table 4 shows the address range
and bank number associated with each sector.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
The reset command may be written between the se-
quence cycles in an erase command sequence before
November 20, 2003
Am49PDL640AG
27
P R E L I M I N A R Y
from “0” back to a “1.” Attempting to do so may
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was success-
ful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
The SecSi Sector region provides a secured data area
containing a random, eight word electronic serial num-
ber (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the de-
vice to normal operation. The SecSi Sector is not ac-
cessible when the device is executing an Embedded
Program or embedded Erase algorithm. Table 14
shows the address and data requirements for both
command sequences. See also “SecSi™ (Secured Sili-
con) Sector SectorFlash Memory Region” for further
information. Note that the ACC function and unlock by-
pass modes are not available when the SecSi Sector
is enabled.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram data to a bank faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. That bank
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 14 shows the requirements for the
command sequence.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 14 shows the address
and data requirements for the program command se-
quence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the read mode.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Write Operation
Status section for information on these status bits.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to the read
mode, to ensure data integrity. Note that the SecSi
Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress.
Figure 4 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 16 for timing diagrams.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
28
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
START
Figure 5 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Write Program
Command Sequence
Data Poll
from System
Sector Erase Command Sequence
Embedded
Program
algorithm
in progress
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command.Table 14 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
Verify Data?
Yes
No
No
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Increment Address
Last Address?
Yes
Programming
Completed
After the command sequence is written, a sector erase
time-out of 80 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 80
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
that bank to the read mode. The system must rewrite
the command sequence and any additional addresses
and commands. Note that the SecSi Sector, autose-
lect, and CFI functions are unavailable when an erase
operation is in progress.
Note: See Table 14 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 14
shows the address and data requirements for the chip
erase command sequence.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to the Write Operation Status sec-
tion for information on these status bits. Note that the
SecSi Sector, autoselect, and CFI functions are un-
available when an erase operation is in progress.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
November 20, 2003
Am49PDL640AG
29
P R E L I M I N A R Y
data from the non-erasing bank. The system can de-
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. The device
allows reading autoselect codes even at addresses
within erasing sectors, since the codes are not stored
in the memory array. When the device exits the au-
toselect mode, the device reverts to the Erase Sus-
pend mode, and is ready for another valid operation.
Refer to the Autoselect Mode and Autoselect Com-
mand Sequence sections for details.
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer
to the Write Operation Status section for information
on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
To resume the sector erase operation, the system
must write the Erase Resume command (address bits
are don’t care). The bank address of the erase-sus-
pended bank is required when writing this command.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after
the chip has resumed erasing.
Figure 5 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
START
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 80 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation. Addresses are “don’t-cares” when
writing the Erase suspend command.
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Notes:
1. See Table 14 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 5. Erase Operation
Password Program Command
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard Word Program operation.
Refer to the Write Operation Status section for more
information.
The Password Program Command permits program-
ming the password that is used as part of the hard-
ware protection scheme. The actual password is
64-bits long. Four Password Program commands are
required to program the password. The system must
enter the unlock cycle, password program command
(38h) and the program address/data for each portion
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Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
of the password when programming. There are no pro-
Persistent Sector Protection Mode
Locking Bit Program Command
visions for entering the 2-cycle unlock cycle, the pass-
word program command, and all the password data.
There is no special addressing order required for pro-
gramming the password. Also, when the password is
undergoing programming, Simultaneous Operation is
disabled. Read operations to any memory location will
return the programming status. Once programming is
complete, the user must issue a Read/Reset com-
mand to return the device to normal operation. Once
the Password is written and verified, the Password
Mode Locking Bit must be set in order to prevent verifi-
cation. The Password Program Command is only ca-
pable of programming “0”s. Programming a “1” after a
cell is programmed as a “0” results in a time-out by the
Embedded Program Algorithm™ with the cell remain-
ing as a “0”. The password is all ones when shipped
from the factory. All 64-bit password combinations are
valid as a password.
The Persistent Sector Protection Mode Locking Bit
Program Command programs the Persistent Sector
Protection Mode Locking Bit, which prevents the Pass-
word Mode Locking Bit from ever being programmed.
If the Persistent Sector Protection Mode Locking Bit is
verified as programmed without margin, the Persistent
Sector Protection Mode Locking Bit Program Com-
mand should be reissued to improve program margin.
By disabling the program circuitry of the Password
Mode Locking Bit, the device is forced to remain in the
Persistent Sector Protection mode of operation, once
this bit is set. Exiting the Persistent Protection Mode
Locking Bit Program command is accomplished by
writing the Read/Reset command.
SecSi Sector Protection Bit Program
Command
Password Verify Command
The SecSi Sector Protection Bit Program Command
programs the SecSi Sector Protection Bit, which pre-
vents the SecSi sector memory from being cleared. If
the SecSi Sector Protection Bit is verified as pro-
grammed without margin, the SecSi Sector Protection
Bit Program Command should be reissued to improve
program margin. Exiting the VCC-level SecSi Sector
Protection Bit Program Command is accomplished by
writing the Read/Reset command.
The Password Verify Command is used to verify the
Password. The Password is verifiable only when the
Password Mode Locking Bit is not programmed. If the
Password Mode Locking Bit is programmed and the
user attempts to verify the Password, the device will al-
ways drive all F’s onto the DQ data bus.
The Password Verify command is permitted if the
SecSi sector is enabled. Also, the device will not oper-
ate in Simultaneous Operation when the Password
Verify command is executed. Only the password is re-
turned regardless of the bank address. The lower two
address bits (A1-A0) are valid during the Password
Verify. Writing the Read/Reset command returns the
device back to normal operation.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the
PPB Lock bit if it is cleared either at reset or if the
Password Unlock command was successfully exe-
cuted. There is no PPB Lock Bit Clear command.
Once the PPB Lock Bit is set, it cannot be cleared un-
less the device is taken through a power-on clear or
the Password Unlock command is executed. Upon set-
ting the PPB Lock Bit, the PPBs are latched into the
DYBs. If the Password Mode Locking Bit is set, the
PPB Lock Bit status is reflected as set, even after a
power-on reset cycle. Exiting the PPB Lock Bit Set
command is accomplished by writing the Read/Reset
command (only in the Persistent Protection Mode).
Password Protection Mode Locking Bit
Program Command
The Password Protection Mode Locking Bit Program
Command programs the Password Protection Mode
Locking Bit, which prevents further verifies or updates
to the Password. Once programmed, the Password
Protection Mode Locking Bit cannot be erased! If the
Password Protection Mode Locking Bit is verified as
program without margin, the Password Protection
Mode Locking Bit Program command can be executed
to improve the program margin. Once the Password
Protection Mode Locking Bit is programmed, the Per-
sistent Sector Protection Locking Bit program circuitry
is disabled, thereby forcing the device to remain in the
Password Protection mode. Exiting the Mode Locking
Bit Program command is accomplished by writing the
Read/Reset command.
DYB Write Command
The DYB Write command is used to set or clear a DYB
for a given sector. The high order address bits
(A21–A12) are issued at the same time as the code
01h or 00h on DQ7-DQ0. All other DQ data bus pins
are ignored during the data write cycle. The DYBs are
modifiable at any time, regardless of the state of the
PPB or PPB Lock Bit. The DYBs are cleared at
power-up or hardware reset.Exiting the DYB Write
command is accomplished by writing the Read/Reset
command.
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31
P R E L I M I N A R Y
erasing the PPBs, two additional cycles are needed to
Password Unlock Command
determine whether the PPB has been erased with
margin. If the PPBs has been erased without margin,
the erase command should be reissued to improve the
program margin.
The Password Unlock command is used to clear the
PPB Lock Bit so that the PPBs can be unlocked for
modification, thereby allowing the PPBs to become ac-
cessible for modification. The exact password must be
entered in order for the unlocking function to occur.
This command cannot be issued any faster than 2 µs
at a time to prevent a hacker from running through all
64-bit combinations in an attempt to correctly match a
password. If the command is issued before the 2 µs
execution window for each portion of the unlock, the
command will be ignored.
It is the responsibility of the user to preprogram all
PPBs prior to issuing the All PPB Erase command. If
the user attempts to erase a cleared PPB, over-era-
sure may occur making it difficult to program the PPB
at a later time. Also note that the total number of PPB
program/erase cycles is limited to 100 cycles. Cycling
the PPBs beyond 100 cycles is not guaranteed.
Once the Password Unlock command is entered, the
RY/BY# indicates that the device is busy. Approxi-
mately 2 µs is required for each portion of the unlock.
Once the first portion of the password unlock com-
pletes (RY/BY# is not low or DQ6 does not toggle
when read), the Password Unlock command and next
part of the password are written. The system must
thus monitor RY/BY# or the status bits to confirm
when to write the next portion of the password.
DYB Write Command
The DYB Write command is used for setting the DYB,
which is a volatile bit that is cleared at reset. There is
one DYB per sector. If the PPB is set, the sector is pro-
tected regardless of the value of the DYB. If the PPB is
cleared, setting the DYB to a 1 protects the sector from
programs or erases. Since this is a volatile bit, remov-
ing power or resetting the device will clear the DYBs.
The bank address is latched when the command is
written.
Note that immediately following successful unlock,
write the SecSi Sector exit command before attempt-
ing to verify, program, or erase the PPBs.
PPB Lock Bit Set Command
The PPB Lock Bit set command is used for setting the
DYB, which is a volatile bit that is cleared at reset.
There is one DYB per sector. If the PPB is set, the sec-
tor is protected regardless of the value of the DYB. If
the PPB is cleared, setting the DYB to a 1 protects the
sector from programs or erases. Since this is a volatile
bit, removing power or resetting the device will clear
the DYBs. The bank address is latched when the com-
mand is written.
PPB Program Command
The PPB Program command is used to program, or
set, a given PPB. Each PPB is individually pro-
grammed (but is bulk erased with the other PPBs).
The specific sector address (A21–A12) are written at
the same time as the program command 60h with A6
= 0. If the PPB Lock Bit is set and the corresponding
PPB is set for the sector, the PPB Program command
will not execute and the command will time-out without
programming the PPB.
PPB Status Command
After programming a PPB, two additional cycles are
needed to determine whether the PPB has been pro-
grammed with margin. If the PPB has been pro-
grammed without margin, the program command
should be reissued to improve the program margin.
Also note that the total number of PPB program/erase
cycles is limited to 100 cycles. Cycling the PPBs be-
yond 100 cycles is not guaranteed.
The programming of the PPB for a given sector can be
verified by writing a PPB status verify command to the
device.
PPB Lock Bit Status Command
The programming of the PPB Lock Bit for a given sec-
tor can be verified by writing a PPB Lock Bit status ver-
ify command to the device.
The PPB Program command does not follow the Em-
bedded Program algorithm.
Note that immediately following the PPB Lock Status
Command write the SecSi Sector Exit command be-
fore attempting to verify, program, or erase the PPBs.
All PPB Erase Command
The All PPB Erase command is used to erase all
PPBs in bulk. There is no means for individually eras-
ing a specific PPB. Unlike the PPB program, no spe-
cific sector address is required. However, when the
PPB erase command is written all Sector PPBs are
erased in parallel. If the PPB Lock Bit is set the ALL
PPB Erase command will not execute and the com-
mand will time-out without erasing the PPBs. After
Sector Protection Status Command
The programming of either the PPB or DYB for a given
sector or sector group can be verified by writing a Sec-
tor Protection Status command to the device.
Note that there is no single command to independently
verify the programming of a DYB for a given sector
group.
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Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
Command Definitions Tables
Table 13. Memory Array Command Definitions
Bus Cycles (Notes 1–4)
Command (Notes)
Addr Data Addr Data
RA RD
XXX F0
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (5)
Reset (6)
1
1
4
6
Manufacturer ID
555
555
AA 2AA
55 (BA) 555 90 (BA)X00
55 (BA) 555 90 (BA)X01
01
7E
Device ID (10)
AA 2AA
(BA)X0E 15 (BA)X0F
01
Autoselect
(Note 7)
SecSi Sector Factory
Protect (8)
(see
note 8)
4
4
555
555
AA 2AA
55 (BA) 555 90
X03
Sector Group Protect
Verify (9)
XX00/
XX01
AA 2AA
55 (BA) 555 90 (SA)X02
Program
4
6
6
1
1
1
2
3
2
2
1
2
555
555
555
BA
BA
55
AA 2AA
AA 2AA
AA 2AA
B0
55
55
55
555
555
555
A0
80
80
PA
555
555
PD
AA
AA
Chip Erase
Sector Erase
2AA
2AA
55
55
555
SA
10
30
Program/Erase Suspend (11)
Program/Erase Resume (12)
CFI Query (13)
30
98
Accelerated Program (14)
Unlock Bypass Entry (15)
Unlock Bypass Program (15)
Unlock Bypass Erase (15)
Unlock Bypass CFI (13, 15)
Unlock Bypass Reset (15)
XX
555
XX
XX
XX
XX
A0
PA
PD
55
AA 2AA
555
20
A0
80
98
90
PA
XX
PD
10
XX
00
Legend:
BA = Address of bank switching to autoselect mode, bypass mode, or
erase operation. Determined by A21:A19, see Tables 4 and 5 for more
detail.
PA = Program Address (A21:A0). Addresses latch on falling edge of
WE# or CE# pulse, whichever happens later.
RA = Read Address (A21:A0).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A21:A12) for verifying (in autoselect mode) or
erasing.
WD = Write Data. See “Configuration Register” definition for specific
write data. Data latched on rising edge of WE#.
X = Don’t care
PD = Program Data (DQ15:DQ0) written to location PA. Data latches
on rising edge of WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
8. The data is 80h for factory locked and 00h for not factory locked.
2. All values are in hexadecimal.
9. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
3. Shaded cells in table denote read cycles. All other cycles are
write operations.
10. Device ID must be read across cycles 4, 5, and 6.
4. During unlock and command cycles, when lower address bits are
555 or 2AAh as shown in table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don’t cares.
11. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Program/Erase Suspend mode.
Program/Erase Suspend command is valid only during a sector
erase operation, and requires bank address.
5. No unlock or command cycles required when bank is reading
array data.
12. Program/Erase Resume command is valid only during Erase
Suspend mode, and requires bank address.
6. The Reset command is required to return to reading array (or to
erase-suspend-read mode if previously in Erase Suspend) when
bank is in autoselect mode, or if DQ5 goes high (while bank is
providing status information).
13. Command is valid when device is ready to read array data or
when device is in autoselect mode.
14. WP#/ACC must be at VID during the entire operation of command.
15. Unlock Bypass Entry command is required prior to any Unlock
Bypass operation. Unlock Bypass Reset command is required to
return to the reading array.
7. Fourth cycle of autoselect command sequence is a read cycle.
System must provide bank address to obtain manufacturer ID or
device ID information. See Autoselect Command Sequence
section for more information.
November 20, 2003
Am49PDL640AG
33
P R E L I M I N A R Y
Table 14. Sector Protection Command Definitions
Bus Cycles (Notes 1-4)
Command (Notes)
Addr Data Addr Data Addr Data
Addr
Data
Addr
Data
Addr Data
Reset
1
3
4
6
4
4
4
4
6
6
3
4
4
4
4
6
4
6
4
XXX F0
SecSi Sector Entry
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
AA 2AA
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
88
90
60
60
38
SecSi Sector Exit
XX
OW
00
68
SecSi Protection Bit Program (5, 6)
SecSi Protection Bit Status
Password Program (5, 7, 8)
Password Verify (8, 9)
Password Unlock (7, 10, 11, 17)
PPB Program (5, 6, 12)
All PPB Erase (5, 13, 14)
PPB Lock Bit Set
OW
48
OW
RD(0)
OW
RD(0)
PD[0-3]
XX[0-3]
C8 PWA[0-3] PWD[0-3]
28 PWA[0-3] PWD[0-3]
60
60
78
58
48
48
58
60
60
60
60
(SA)WP
EP
68
60
(SA)WP
(SA)EP
48
40
(SA)WP RD(0)
(SA)WP RD(0)
PPB Lock Bit Status (15, 18)
DYB Write (7)
SA
SA
SA
SA
PL
PL
SL
SL
RD(1)
X1
DYB Erase (7)
X0
DYB Status
RD(0)
68
PPMLB Program (5, 6, 12)
PPMLB Status (5)
PL
SL
48
48
PL
SL
RD(0)
RD(0)
RD(0)
68
SPMLB Program (5, 6, 12)
SPMLB Status (5)
RD(0)
Legend:
DYB = Dynamic Protection Bit
OW = Address (A6:A0) is (0011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits
A21:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)
WP = PPB Address (A6:A0) is (0111010) (Note 16)
EP = PPB Erase Address (A6:A0) is (1111010) (Note 16)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
PL = Password Protection Mode Lock Address (A5:A0) is (001010)
RD(0) = Read Data DQ0 for protection indicator bit.
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
11. A 2 µs timeout is required between any two portions of password.
12. A 100 µs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
3. Shaded cells in table denote read cycles. All other cycles are
write operations.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command
must be issued and verified again. Before issuing erase
command, all PPBs should be programmed to prevent PPB
overerasure.
4. During unlock and command cycles, when lower address bits are
555 or 2AAh as shown in table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don’t cares.
5. The reset command returns device to reading array.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6
validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0
in cycle 6, program command must be issued and verified again.
16. For all other parts that use the Persistent Protection Bit (excluding
PDL128G), the WP and EP addresses are 00000010.
17. Immediately following successful unlock, write the SecSi Sector
Exit command before attempting to verify, program, or erase the
PPBs.
7. Data is latched on the rising edge of WE#.
8. Entire command sequence must be entered for each portion of
password.
18. Immediately following the PPB Lock Status command write the
SecSi Sector Exit command before attempting to verify, program,
or erase the PPBs.
9. Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at
addresses 0-3.
34
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 16 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is com-
plete or in progress. The device also provides a hard-
ware-based output signal, RY/BY#, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ15–DQ0 may be still
invalid. Valid data on DQ15–DQ0 will appear on suc-
cessive read cycles.
Table 16 shows the outputs for Data# Polling on DQ7.
Figure 6 shows the Data# Polling algorithm. Figure 20
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether a bank is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the final
WE# pulse in the command sequence.
START
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then that bank returns to the
read mode.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Yes
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the
bank returns to the read mode. If not all selected sec-
tors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ15–DQ0 on the following read cycles. Just prior to
the completion of an Embedded Program or Erase op-
eration, DQ7 may change asynchronously with
DQ15–DQ0 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
November 20, 2003
Am49PDL640AG
35
P R E L I M I N A R Y
DQ6 also toggles during the erase-suspend-program
RY/BY#: Ready/Busy#
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
Table 16 shows the outputs for Toggle Bit I on DQ6.
Figure 7 shows the toggle bit algorithm. Figure 21 in
the “Flash AC Characteristics” section shows the tog-
gle bit timing diagrams. Figure 22 shows the differ-
ences between DQ2 and DQ6 in graphical form. See
also the subsection on DQ2: Toggle Bit II.
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or one of the banks is in the erase-sus-
pend-read mode.
START
Read Byte
(DQ7–DQ0)
Address =VA
Table 16 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
Read Byte
(DQ7–DQ0)
Address =VA
No
Toggle Bit
= Toggle?
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Yes
No
DQ5 = 1?
Yes
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro-
tected.
Read Byte Twice
(DQ7–DQ0)
Address = VA
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Figure 7. Toggle Bit Algorithm
36
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
the toggle bit and DQ5 through successive read cy-
DQ2: Toggle Bit II
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 7).
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 16 to compare out-
puts for DQ2 and DQ6.
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 21 shows the toggle bit timing diagram. Figure
22 shows the differences between DQ2 and DQ6 in
graphical form.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ15–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ15–DQ0 on the fol-
lowing read cycle.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
Table 16 shows the status of DQ3 relative to the other
status bits.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
November 20, 2003
Am49PDL640AG
37
P R E L I M I N A R Y
Table 15. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend-
Read
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
38
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
PSRAM POWER DOWN
Deep Power Down Exit Sequence
CE1# = V = or V
IH
,
IL
CE2 = V
IH
Deep Power
Down Mode
CE2 = V
IH
IL
CE2 = V
Initial State
(Wait 200 µs)
Power
Up
CE2 = V , CE1# = V
IH
or UB#, LB# = V
IH
IH
Active
CE1# = V
CE2 = V
Power Up Sequence
UB# and LB#
or/and LB# =V
IH
IL
,
,
Standby
Mode
IL
Note:For Si-7 pSRAM, Deep Power-Down Standby is not available.
Figure 8. State Diagram
Table 16. Standby Mode Characteristics
Wait
Time
(µs)
Power Mode
Standby
Memory Cell Data
Valid
Standby Current (µA)
100
10
0
Deep Power Down
Invalid
200
November 20, 2003
Am49PDL640AG
39
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C
20 ns
20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . . –25°C to +85°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
–2.0 V
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
20 ns
Figure 9. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 9. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 10.
20 ns
VCC
+2.0 V
2. Minimum DC input voltage on pins RESET#, and
WP#/ACC is –0.5 V. During voltage transitions,
WP#/ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 9. Maximum DC input
voltage on pin RESET# is +12.5 V which may overshoot
to +14.0 V for periods up to 20 ns. Maximum DC input
voltage on WP#/ACC is +9.5 V which may overshoot to
+12.0 V for periods up to 20 ns.
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 10. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Light Industrial (L) Devices
Ambient Temperature (TA) . . . . . . . . . –25°C to +85°C
V
CCf/VCCs Supply Voltages
VCCf/VCCs for standard voltage range . .2.7 V to 3.1 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
40
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Parameter
Parameter Description
Test Conditions
Min
Typ
Max
Unit
Symbol
VIN = VSS to VCC
,
ILI
Input Load Current
1.0
35
µA
µA
µA
VCC = VCC max
ILIT
ILO
RESET# Input Load Current
Output Leakage Current
VCC = VCC max; VID= 12.5 V
VOUT = VSS to VCC, OE# = VIH
VCC = VCC max
1.0
5 MHz
10
25
15
20
45
30
CE# = VIL, OE# = VIH, VCC
= VCC max
ICC1
VCC Active Read Current (Notes 1, 2)
mA
10 MHz
ICC2
ICC3
ICC4
VCC Active Write Current (Notes 2, 3)
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
CE# = VIL, OE# = VIH, WE# = VIL
mA
µA
µA
CE#, RESET#, WP#/ACC = VIO 0.3 V
RESET# = VSS 0.3 V
1
1
5
5
VIH = VIO 0.3 V;
VIL = VSS 0.3 V
ICC5
ICC6
ICC7
ICC8
Automatic Sleep Mode (Notes 2, 4)
1
5
µA
mA
mA
mA
VCC Active Read-While-Program Current
(Notes 1, 2)
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
Word
Word
21
21
17
45
45
35
VCC Active Read-While-Erase Current
(Notes 1, 2)
VCC Active Program-While-Erase-
Suspended Current (Notes 2, 5)
VIL
VIH
Input Low Voltage
–0.5
0.8
V
Input High Voltage
V
CC+0.3
2
V
V
VHH
VID
Voltage for ACC Program Acceleration
VCC = 3.0 V 10%
VCC = 3.0 V 10%
8.5
9.5
Voltage for Autoselect and Temporary
Sector Unprotect
11.5
12.5
0.4
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCCS
V
V
V
V
V
IO–0.1
I
I
OH = –100 µA, VCCf = VCCS
OH = –2.0 mA, VCC = VCCS
VOH
Output High Voltage
2.4
VLKO
Low VCC Lock-Out Voltage (Note 5)
2.3
2.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at
VIH.
4. Automatic sleep mode enables the low power mode when
addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 200 nA.
2. Maximum ICC specifications are tested with VCC = VCCmax
3. CC active while Embedded Erase or Embedded Program is in
progress.
.
5. Not 100% tested.
I
November 20, 2003
Am49PDL640AG
41
P R E L I M I N A R Y
pSRAM DC AND OPERATING CHARACTERISTICS (NOTE 1)
Parameter
Symbol
Parameter Description
Input Leakage Current
Test Conditions
VIN = VSS to VCC
Min
–1.0
–1.0
Typ
Max
1.0
Unit
µA
ILI
CE#1s = VIH, CE2s = VIL or OE# =
VIH or WE# = VIL, VIO= VSS to VCC
ILO
Output Leakage Current
1.0
µA
Cycle time = Min., 100% duty
IIO = 0 mA, CE#1 ≤ 0.2 V,
CE2 ≥ VDD -0.2 V, VIN ≤ 0.2 V
or VIN ≥ VDD -0.2 V
Operating Current at Minimum
Cycle Time
ICC1
s
s
30
Cycle time = 1 µs, 100% duty
IIO = 0 mA, CE#1 = VIL,
CE2 = VIH, VIN = VIH or VIL
Operating Current at Maximum
Cycle Time
ICC2
3
–0.2
(Note 2)
VIL
VIH
Input Low Voltage
Input High Voltage
0.6
V
V
VCC+0.2
(Note 1)
2.2
2.4
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
0.4
V
V
IOH = –1.0 mA
CE#1s = VIH, CE2 = VIL, Other
inputs = VIH or VIL
ISB
ISB1
ISBD
Standby Current (TTL)
0.3
100
10
mA
µA
µA
CE1# = VDD -0.2 V and
CE2 = VDD -0.2 V,
Other inputs = VSS ~ VCC
Standby Current (CMOS)
Deep Power Down (Note 4)
CE2 ≤ 0.2 V,
Other Inputs = VSS ~ VCC
Notes:
1. Overshoot: VCC + 2.0 V in case of pulse width ≤ 20 ns.
2. Undershoot: -2.0 V in case of pulse width ≤ 20 ns.
3. Not 100% Tested
4. For Si-7 pSRAM, Deep Power-down Standby is not available.
42
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
TEST CONDITIONS
Table 17. Test Specifications
3.0 V
Test Condition
70, 85
Unit
Output Load
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
November 20, 2003
Am49PDL640AG
43
P R E L I M I N A R Y
AC CHARACTERISTICS
pSRAM CE#s Timing
Parameter
Test Setup
AllSpeeds
Unit
JEDEC
Std
Description
—
tCCR
CE#s Recover Time
—
Min
0
ns
CE#
tCCR
tCCR
CE2#
Figure 13. Timing Diagram for Alternating
Between pSRAM to Flash
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Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Read-Only Operations
Parameter
Speed Options
70
JEDEC
tAVAV
Std. Description
Test Setup
85
85
85
85
30
30
30
30
Unit
ns
tRC
Read Cycle Time (Note 1)
Min
70
70
70
25
25
25
25
tAVQV
tACC Address to Output Delay
CE#, OE# = VIL
OE# = VIL
Max
Max
Max
Max
Max
Max
ns
tELQV
tCE
Chip Enable to Output Delay
ns
tPACC Page Access Time
ns
tGLQV
tEHQZ
tGHQZ
tOE
tDF
tDF
Output Enable to Output Delay
ns
Chip Enable to Output High Z (Notes 1, 3)
Output Enable to Output High Z (Notes 1, 3)
ns
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
4
5
ns
ns
ns
Read
0
Output Enable Hold Time
(Note 1)
tOEH
Toggle and
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 18 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to
the data bus driven to VCC/2 is taken as tDF.
.
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
November 20, 2003
Am49PDL640AG
45
P R E L I M I N A R Y
AC CHARACTERISTICS
Same Page
Ab
A21
-
-
A3
A0
A2
Ad
Aa
tACC
Ac
tPACC
tPACC
tPACC
Data
Qa
Qb
Qc
Qd
CE# or CE2#
OE#
Figure 15. Page Read Operation Timings
46
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
Max
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#f, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#f, OE#
RESET#
tRP
Figure 16. Reset Timings
November 20, 2003
Am49PDL640AG
47
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
70
70
85
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
85
tAVWL
0
15
45
0
ns
Address Setup Time to OE# low during toggle bit
polling
tASO
tAH
Min
Min
Min
ns
ns
ns
tWLAX
Address Hold Time
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
35
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Max
0
0
ns
ns
ns
ns
ns
µs
µs
sec
µs
ns
ns
CE# Hold Time
tWP
Write Pulse Width
35
30
0
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
tWHWH1
tWHWH1
tWHWH2
tWHWH1 Programming Operation (Note 2)
tWHWH1 Accelerated Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
6
4
0.2
50
0
tVCS
tRB
VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
tBUSY
90
Notes:
1. Not 100% tested.
2. See the “Deep Power Down Mode” section for more information.
48
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#f
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY/BY#
V
CCf
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address..
Figure 17. Program Operation Timings
VHH
VIL or VIH
WP#/ACC
VIL or VIH
tVHH
tVHH
Figure 18. Accelerated Program Timing Diagram
November 20, 2003
Am49PDL640AG
49
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
tWC
VA
Addresses
CE#f
2AAh
SADD
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
f
Notes:
1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 19. Chip/Sector Erase Operation Timings
50
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
tWC
Valid PA
tWC
tRC
tWC
Valid PA
Valid RA
Valid PA
Addresses
tAH
tCPH
tACC
tCE
CE#f
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
Data
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE#f Controlled Write Cycles
Figure 20. Back-to-back Read/Write Cycle Timings
tRC
Addresses
CE#f
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 21. Data# Polling Timings (During Embedded Algorithms)
November 20, 2003
Am49PDL640AG
51
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
tAHT
tAS
Addresses
CE#f
tAHT
tASO
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 22. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 23. DQ2 vs. DQ6
52
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
tVHH
Description
All Speed Options
Unit
ns
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
250
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
Min
Min
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
tRRB
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#f
WE#
tRRB
tRSP
RY/BY#
Figure 24. Temporary Sector Unprotect Timing Diagram
November 20, 2003
Am49PDL640AG
53
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
V
ID
IH
V
RESET#
SADD,
A6, A1, A0
Valid*
Valid*
Valid*
Status
Sector/Sector Block Protect or Unprotect
60h 60h
Verify
40h
Data
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
CE#f
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address.
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram
54
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Flash Alternate CE#f Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
70
70
85
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
85
tAVWL
tELAX
tDVEH
tEHDX
0
45
35
0
ns
tAH
ns
tDS
ns
tDH
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
0
0
ns
ns
ns
ns
CE# Pulse Width
CE# Pulse Width High
35
30
tCPH
Programming Operation
(Note 2)
tWHWH1
tWHWH1
Typ
6
µs
tWHWH1
tWHWH2
1. Not 100% tested.
2. See the “Deep Power Down Mode” section for more information.
tWHWH1
Accelerated Programming Operation (Note 2)
Typ
Typ
4
µs
tWHWH2
Sector Erase Operation (Note 2)
0.2
sec
November 20, 2003
Am49PDL640AG
55
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SADD for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#f
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SADD = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device..
Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings
56
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Power Up Time (Etron pSRAM only)
200 µs
VCCs
CE2s
CE#1s
Figure 27. Power Up
VCCS Slew Rate (Etron pSRAM only)
VCCS
dV/dt ≤ 58 V/ms
0
t
Notes:
1. At any time during Power Up, the VCCS slew rate (i.e. rate of change) must not exceed 58 V/ms (alternately, it must exceed
17 µs/V).
2. Power up and Slew Rate requirements apply to Etron pSRAM only.
Figure 28. VCCS Slew Rate
November 20, 2003
Am49PDL640AG
57
P R E L I M I N A R Y
pSRAM Read Cycle
Speed
Parameter
Description
Symbol
Unit
70
70
70
70
35
70
85
85
85
85
40
85
tRC
tAA
CO1, tCO2
tOE
Read Cycle Time
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Max
Max
Max
Max
Min
t
Chip Enable to Output
Output Enable Access Time
tBA
LB#s, UB#s to Access Time
tLZ12
tBLZ
tOLZ
tHZ1
Chip Enable Low to Low-Z Output
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB#s, LB#s Disable to High-Z Output
Output Disable to High-Z Output
Output Data Hold from Address Change
10
10
5
Min
Min
Max
Max
Max
Min
25
25
25
35
35
35
tBHZ
tOHZ
tOH
10
58
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Read Cycle
Read Cycle 1-Addressed Controlled
Address
tRC
tAA
tOH
tOH
Data Valid
Previous Data Valid
Data Out
Note:
1. CE1# = OE# = VIL, CE2 = WE# = VIH, UB# or/and LB# = VIL
Figure 29. pSRAM Read Cycle–Address Controlled
t
RC
Address
t
AA
t
OH
t
CO
t
LZ
CE1#
t
HZ
t
BA
t
BLZ
UB#, LB#
t
t
BHZ
OE
OE#
t
OHZ
t
OLZ
High-Z
High-Z
Data Out
Data Valid
Note:
1. CE2 = WE# = VIH
Figure 30. pSRAM Read Cycle–CS1# Controlled
November 20, 2003
Am49PDL640AG
59
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Write Cycle
Speed
Parameter
Description
Symbol
Unit
70
70
60
85
85
70
tWC
tCw
tAS
Write Cycle Time
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Setup Time
0
tAW
tBW
tWP
tWR
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Min
Min
Min
Min
Min
Max
Min
Min
min
60
60
50
70
70
60
Write Recovery Time
0
0
tWHZ
Write to Output High-Z
ns
20
30
30
30
tDW
tDH
tOW
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
ns
ns
ns
0
5
60
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
tWC
Address
tWR
tAW
tCW
CE#1s
tBW
UB#, LB#
WE#
tWP
tAS
tDW
Data Valid
tDH
High-Z
High-Z
Data In
tWHZ
tOW
Data Out
Data Undefined
Note:
1. CE2s = VIH
2. CE2s = WE# = VIH
Figure 31. pSRAM Write Cycle–WE# Controlled
tWC
Address
tWR
tAW
tAS
tCW
CE#1s
tBW
UB#, LB#
WE#
tWP
tDW
Data Valid
tDH
Data In
High-Z
Data Out
Note:
1. CE2s = VIH
2. CE2s = WE# = VIH
Figure 32. pSRAM Write Cycle–CS1# Controlled
Am49PDL640AG
November 20, 2003
61
P R E L I M I N A R Y
PSRAM AC CHARACTERISTICS
tWC
Address
tWR
tAW
tCW
CE#1s
UB#, LB#
tBW
tAS
tWP
WE#
tDW
Data Valid
tDH
Data In
High-Z
Data Out
Note:
1. CE2s = VIH
2. CE2s = WE# = VIH
Figure 33. pSRAM Write Cycle–UB#, LB# Controlled
200 µs
1 µs
CE2s
Mode
Wake Up
Deep Power
Down Mode
Suspend
Normal Operation
Normal Operation
CE#1s
Figure 34. Deep Power Down Mode
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Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
PSRAM AC CHARACTERISTICS
≥ 15 µs
CE1#
WE #
< tRC
Address
Note:Applies to Etron pSRAM only.
Figure 35. Abnormal Timing
≥ 15 µs
CE1#
WE#
≥ tRC
Address
Note:Applies to Etron pSRAM only.
Figure 36. Avoidable Timing 1
≥ 15 µs
CE1#
WE#
≥ tRC
< tRC
Address
Note:Applies to Etron pSRAM only.
Figure 37. Avoidable Timing 2
November 20, 2003
Am49PDL640AG
63
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
sec
sec
Comments
Sector Erase Time
Chip Erase Time
0.4
56
5
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Word Program Time
7
210
µs
Accelerated Word Program Time
Chip Program Time (Note 3)
Notes:
4
120
84
µs
28
sec
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables
Table 14 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including RESET#)
–1.0 V
13 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
11
Max
14
Unit
pF
CIN
COUT
CIN2
Output Capacitance
VOUT = 0
VIN = 0
12
16
pF
Control Pin Capacitance
WP#/ACC Pin Capacitance
14
16
pF
CIN3
VIN = 0
17
20
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
64
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
FLK073—73-Ball Fine-Pitch Grid Array 13 x 9 mm
A
D
D1
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E1
E
B
5
4
eE
3
2
1
L
J
H
G
F
E
D
C
B
A
M
K
INDEX MARK
10
PIN A1
CORNER
7
PIN A1
CORNER
SD
0.15
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
6
73X
b
0.15
0.08
M
C
C
A B
M
NOTES:
PACKAGE
JEDEC
FLK 073
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
13.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
1.40
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
0.98
---
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.08
BODY THICKNESS
BODY SIZE
D
13.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
72
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.30
0.35
0.40
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9,
B2,B3,B4,B7,B8,B9
C2,C9,C10,D1,D10,E1,E10,
F5,F6,G5,G6,H1,H10
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
DEPOPULATED SOLDER BALLS
J1,J10,K1,K2,K9,K10,
L2,L3,L4,L7,L8,L9
M2,M3,M4,M5,M6,M7,M8,M9
3278 \ 16-038.14c
November 20, 2003
Am49PDL640AG
65
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (February 21, 2003)
Initial Release
Revision A+1 (March 14, 2003)
Ordering Information
Corrected typo in temperature range.
Revision A+2 (April 4, 2003)
Ordering Information
Corrected typo in temperature range.
Corrected OPNs
Revision A+3 (April 7, 2003)
Ordering Information
Corrected typo in temperature range.
Revision A+4 (August 5, 2003)
Figure 28. VCCS Slew Rate
Added Figure.
Revision A+5 (November 20, 2003)
Distinctive Characteristics, Pseudo SRAM
Features
Added bullet regarding pSRAM vendors.
Ordering Information
Added Si-7 pSRAM option.
Device Bus Operations
Added Note 10.
pSRAM Power Down
Added Note.
pSRAM DC and Operating Characteristics
Added Note 4.
pSRAM AC Characteristics
Added Note to diagrams.
Trademarks
Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
66
Am49PDL640AG
November 20, 2003
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