AM29LV640MU112WHI [AMD]
64 Megabit (4 M x 16-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with; 64兆位(4M ×16位)的MirrorBit 3.0伏特,只有统一部门快闪记忆体与型号: | AM29LV640MU112WHI |
厂家: | AMD |
描述: | 64 Megabit (4 M x 16-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with |
文件: | 总58页 (文件大小:1118K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29LV640MU
Data Sheet
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For More Information
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ADVANCE INFORMATION
Am29LV640MU
64 Megabit (4 M x 16-Bit) MirrorBit
3.0 Volt-only Uniform Sector Flash Memory with
VersatileI/O Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
— 4-word page read buffer
— 16-word write buffer
■ Single power supply operation
— 3 V for read, erase, and program operations
■ Low power consumption (typical values at 3.0 V, 5
MHz)
■ VersatileI/O control
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
— Device generates data output voltages and tolerates
data input voltages on the CE# and DQ inputs/outputs
as determined by the voltage on the VIO pin; operates
from 1.65 to 3.6 V
■ Package options
■ Manufactured on 0.23 µm MirrorBit process
— 63-ball Fine-Pitch BGA
— 64-ball Fortified BGA
technology
■ SecSi (Secured Silicon) Sector region
SOFTWARE & HARDWARE FEATURES
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number,
accessible through a command sequence
■ Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— May be programmed and locked at the factory or by
the customer
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
■ Flexible sector architecture
— Data# polling & toggle bits provide status
— One hundred twenty-eight 32 Kword sectors
— Unlock Bypass Program command reduces overall
multiple-word programming time
■ Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■ Minimum 100,000 erase cycle guarantee per sector
■ 20-year data retention at 125°C
■ Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
PERFORMANCE CHARACTERISTICS
■ High performance
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
— 90 ns access time
— ACC (high voltage) input accelerates programming
time for higher throughput during system production
— 25 ns page read times
— 0.5 s typical sector erase time
— Hardware reset input (RESET#) resets device
— 22 µs typical effective write buffer word programming
time: 16-word write buffer reduces overall
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
programming time for multiple-word/byte updates
Publication# 25301 Rev: C Amendment/1
Issue Date: June 12, 2003
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.6/13/03
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV640MU is a 64 Mbit, 3.0 volt single power
supply flash memory device organized as 4,194,304
words. The device has a 16-bit only data bus, and can
be programmed either in the host system or in stan-
dard EPROM programmers.
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the VIO pin.
Refer to the Ordering Information section for valid VIO
options.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (VCC) and an I/O voltage range (VIO), as
specified in the Product Selector Guide and the Order-
ing Information sections. The device is offered in a
63-ball Fine-Pitch BGA or 64-ball Fortified BGA pack-
age. Each device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The Program
Suspend/Program Resume feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a VCC input, a high-voltage accelerated program
(ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
The SecSi (Secured Silicon) Sector provides a
128-word area for code or data that can be perma-
nently protected. Once this sector is protected, no fur-
ther changes within the sector can occur.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter-
mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
The VersatileI/O™ (VIO) control allows the host sys-
tem to set the voltage levels that the device generates
2
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
MIRRORBIT 64 MBIT DEVICE FAMILY
Sector
Architecture
Device
Bus
x8
Packages
VIO
Yes
No
RY/BY#
Yes
WP#, ACC
ACC only
WP# Protection
48-pin TSOP (std. & rev. pinout),
63-ball FBGA
LV065MU
LV640MT/B
LV640MH/L
LV641MH/L
LV640MU
Uniform (64 Kbyte)
No WP#
Boot (8 x 8 Kbyte
at top & bottom)
48-pin TSOP, 63-ball Fine-pitch BGA,
64-ball Fortified BGA
2 x 8 Kbyte
top or bottom
x8/x16
Yes
WP#/ACC pin
WP#/ACC pin
56-pin TSOP (std. & rev. pinout),
64 Fortified BGA
1 x 64 Kbyte
high or low
x8/x16 Uniform (64 Kbyte)
Yes
Yes
Yes
Yes
Separate WP#
and ACC pins
1 x 32 Kword
top or bottom
x16
x16
Uniform (32 Kword)
Uniform (32 Kword)
48-pin TSOP (std. & rev. pinout)
No
63-ball Fine-pitch BGA,
64-ball Fortified BGA
Yes
ACC only
No WP#
RELATED DOCUMENTS
To download related documents, click on the following
links or go to www.amd.com→Flash Memory→Prod-
uct Information→MirrorBit→Flash Information→Tech-
nical Documentation.
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
AMD MirrorBit™ White Paper
Migrating from Single-byte to Three-byte Device IDs
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Migration from Am29LV640DU to MirrorBit
Am29LV640MU
June 12, 2003
Am29LV640MU
3
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
MirrorBit 64 Mbit Device Family . . . . . . . . . . . . . . 3
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Special Package Handling Instructions ....................................7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations .....................................................10
Erase Suspend/Erase Resume Commands ...........................30
Figure 7. Erase Operation.............................................................. 30
Command Definitions ............................................................. 31
Table 10. Command Definitions...................................................... 31
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling .................................................................32
Figure 8. Data# Polling Algorithm .................................................. 32
RY/BY#: Ready/Busy#............................................................ 33
DQ6: Toggle Bit I ....................................................................33
Figure 9. Toggle Bit Algorithm........................................................ 34
DQ2: Toggle Bit II ...................................................................34
Reading Toggle Bits DQ6/DQ2 ...............................................34
DQ5: Exceeded Timing Limits ................................................35
DQ3: Sector Erase Timer .......................................................35
DQ1: Write-to-Buffer Abort .....................................................35
Table 11. Write Operation Status ................................................... 35
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 36
Figure 10. Maximum Negative Overshoot Waveform ................... 36
Figure 11. Maximum Positive Overshoot Waveform..................... 36
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. Test Setup.................................................................... 38
Table 12. Test Specifications ......................................................... 38
Key to Switching Waveforms. . . . . . . . . . . . . . . . 38
Figure 13. Input Waveforms and
Measurement Levels...................................................................... 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Read-Only Operations ...........................................................39
Figure 14. Read Operation Timings............................................... 39
Figure 15. Page Read Timings ...................................................... 40
Hardware Reset (RESET#) ....................................................41
Figure 16. Reset Timings............................................................... 41
Erase and Program Operations ..............................................42
Figure 17. Program Operation Timings.......................................... 43
Figure 18. Accelerated Program Timing Diagram.......................... 43
Figure 19. Chip/Sector Erase Operation Timings .......................... 44
Figure 20. Data# Polling Timings
VersatileIO (V ) Control .....................................................10
IO
Requirements for Reading Array Data ...................................10
Page Mode Read ....................................................................11
Writing Commands/Command Sequences ............................11
Write Buffer .............................................................................11
Accelerated Program Operation .............................................11
Autoselect Functions ..............................................................11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ...........................................................11
RESET#: Hardware Reset Pin ...............................................12
Output Disable Mode ..............................................................12
Table 2. Sector Address Table ........................................................13
Autoselect Mode..................................................................... 15
Table 3. Autoselect Codes, (High Voltage Method) .......................15
Sector Group Protection and Unprotection .............................16
Table 4. Sector Group Protection/Unprotection Address Table .....16
Temporary Sector Group Unprotect .......................................17
Figure 1. Temporary Sector Group Unprotect Operation................ 17
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18
SecSi (Secured Silicon) Sector Flash Memory Region ..........19
Table 5. SecSi Sector Contents ......................................................19
Figure 3. SecSi Sector Protect Verify.............................................. 20
Hardware Data Protection ......................................................20
Low VCC Write Inhibit ............................................................20
Write Pulse “Glitch” Protection ...............................................20
Logical Inhibit ..........................................................................20
Power-Up Write Inhibit ............................................................20
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 6. CFI Query Identification String .............................. 21
Table 7. System Interface String......................................................21
Table 8. Device Geometry Definition................................... 22
Table 9. Primary Vendor-Specific Extended Query............. 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................24
Reset Command .....................................................................24
Autoselect Command Sequence ............................................24
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..25
Word Program Command Sequence .....................................25
Unlock Bypass Command Sequence .....................................25
Write Buffer Programming ......................................................25
Accelerated Program ..............................................................26
Figure 4. Write Buffer Programming Operation............................... 27
Figure 5. Program Operation .......................................................... 28
Program Suspend/Program Resume Command Sequence ...28
Figure 6. Program Suspend/Program Resume............................... 29
Chip Erase Command Sequence ...........................................29
Sector Erase Command Sequence ........................................29
(During Embedded Algorithms)...................................................... 45
Figure 21. Toggle Bit Timings
(During Embedded Algorithms)...................................................... 46
Figure 22. DQ2 vs. DQ6................................................................. 46
Temporary Sector Unprotect ..................................................47
Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 47
Figure 24. Sector Group Protect and Unprotect Timing Diagram.. 48
Alternate CE# Controlled Erase and Program Operations .....49
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 50
Erase And Programming Performance. . . . . . . . 51
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 51
TSOP Pin and FIne-pitch BGA Package
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 53
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
13 x 11 mm Package ..............................................................53
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
12 x 11 mm Package ..............................................................54
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
4
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
Am29LV640MU
112R
90R
101R
(VIO = 2.7–3.6 (VIO = 1.65–3.6
120R
(VIO = 1.65–3.6
V)
V
V
CC =3.0–3.6
(VIO
=
3.0–3.6 V)
V)
V)
Speed
Option
101
(VIO = 2.7–3.6
V)
112
(VIO = 1.65–3.6
V)
120
(VIO = 1.65–3.6
V)
VCC =2.7–3.6
V
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page access time
90
90
100
100
110
110
120
120
25
25
30
30
30
30
40
40
30
30
40
40
(tPACC
)
Max. OE# Access Time (ns)
1. See “AC Characteristics” for full specifications.
2. For the Am29LV640MU device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes
only. Please use OPNs as listed when placing orders.
BLOCK DIAGRAM
DQ0–DQ15
RY/BY#
VCC
VSS
VIO
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
ACC
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A21–A0
June 12, 2003
Am29LV640MU
5
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
64-Ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
NC
H8
NC
NC
NC
VIO
VSS
NC
NC
A7
B7
C7
D7
E7
F7
G7
H7
A13
A12
A14
A15
A16
NC
DQ15
VSS
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
DQ6
A10
A11
DQ7
DQ14
DQ13
A5
B5
C5
D5
E5
F5
G5
H5
WE# RESET#
A21
A19
DQ5
DQ12
VCC
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY#
ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
NC
H1
NC
NC
NC
NC
NC
VIO
NC
6
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
63-Ball Fine-Pitch BGA
Top View, Balls Facing Down
L8
M8
A8
B8
NC
NC
NC*
NC*
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
VSS
NC
NC
NC*
NC*
A13
A12
A14
A15
A16
VIO
DQ15
C6
A9
D6
A8
E6
F6
G6
H6
J6
K6
A10
A11
DQ7
DQ14
DQ13
DQ6
C5
D5
E5
F5
G5
H5
J5
K5
VCC
WE# RESET#
A21
A19
DQ5
DQ12
DQ4
C4
D4
E4
F4
G4
H4
J4
K4
RY/BY#
ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
C3
A7
D3
E3
A6
F3
A5
G3
H3
J3
K3
A17
DQ0
DQ8
DQ9
DQ1
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
J2
K2
L2
M2
A2
VSS
CE#
OE#
NC*
NC*
NC*
A1
B1
L1
M1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
NC*
NC*
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (TSOP, BGA, SSOP, PDIP,
PLCC). The package and/or data integrity may be
June 12, 2003
Am29LV640MU
7
A D V A N C E I N F O R M A T I O N
PIN DESCRIPTION
LOGIC SYMBOL
A21–A0
= 22 Address inputs
22
DQ15–DQ0 = 15 Data inputs/outputs
A21–A0
16
CE#
= Chip Enable input
DQ15–DQ0
CE#
OE#
WE#
OE#
= Output Enable input
= Write Enable input
WE#
ACC
= Programming Acceleration input
= Hardware Reset Pin input
= Ready/Busy output
ACC
RESET#
RY/BY#
VCC
RESET#
VIO
RY/BY#
= 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VIO
VSS
NC
= Output Buffer power
= Device Ground
= Pin Not Connected Internally
8
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29LV640M
U
120R
PC
I
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
PACKAGE TYPE
PC
=
64-Ball Fortified Ball Grid Array,
1.0 mm pitch, 13 x 11 mm package (LAA064)
WH
=
63-Ball Fine Pitch Ball Grid Array,
0.80 mm pitch, 12 x 11 mm package (FBE063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE
U
=
Uniform sector device
DEVICE NUMBER/DESCRIPTION
Am29LV640MU
64 Megabit (4 M x 16-Bit) MirrorBit Uniform Sector Flash Memory
with VersatileIO Control, 3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations for
Fortified or Fine-Pitch BGA Package
Valid Combinations list configurations planned to be supported in volume for
this device. Consult the local AMD sales office to confirm availability of spe-
cific valid combinations and to check on newly released combinations.
Speed
(ns)
VIO
VCC
Range Range
Order Number
Package Marking
WHI L640MU90R
PCI L640MU90N
WHI L640MU01V
PCI L640MU01P
WHI L640MU11V
PCI L640MU11P
WHI, L640MU12V
PCI L640MU12P
WHI, L640MU01R
PCI L640MU01N
WHI, L640MU11R
PCI L640MU11N
WHI, L640MU12R
PCI L640MU12N
3.0–
3.6 V
3.0–
3.6 V
Am29LV640MU90R
I
I
I
I
I
I
I
90
2.7–
3.6 V
Am29LV640MU101
Am29LV640MU112
Am29LV640MU120
Am29LV640MU101R
Am29LV640MU112R
Am29LV640MU120R
100
110
120
100
110
120
1.65–
3.6 V
2.7–
3.6 V
1.65–
3.6 V
2.7–
3.6 V
3.0–
3.6 V
1.65–
3.6 V
1.65–
3.6 V
Note:
For the Am29LV640MU device, the last numeric digit in the speed option (e.g.
101, 112, 120) is used for internal purposes only. Use OPNs as listed when
placing orders.
June 12, 2003
Am29LV640MU
9
A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Addresses
(Note 2)
DQ0–
DQ15
Operation
CE#
OE# WE# RESET#
ACC
X
Read
L
L
L
L
H
H
H
L
L
H
H
AIN
AIN
AIN
DOUT
Write (Program/Erase)
Accelerated Program
X
(Note 3)
(Note 3)
H
VHH
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
X
H
X
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
High-Z
High-Z
X
SA, A6=L, A3=L,
A2=L, A1=H, A0=L
Sector Group Protect (Note 2)
L
L
X
H
H
X
L
L
X
VID
VID
VID
X
X
X
(Note 3)
(Note 3)
(Note 3)
Sector Group Unprotect
(Note 2)
SA, A6=H, A3=L,
A2=L, A1=H, A0=L
Temporary Sector Group
Unprotect
AIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
trol and gates array data to the output pins. WE#
should remain at VIH.
VersatileIO (VIO) Control
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. See “Ordering Informa-
tion” on page 9 for VIO options on this device.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
For example, a VI/O of 1.65–3.6 volts allows for I/O at
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
Requirements for Reading Array Data
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing spec-
ifications and to Figure 13 for the timing diagram.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
10
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
Refer to the DC Characteristics table for the active
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal op-
eration. Note that the ACC pin must not be at VHH for
operations other than accelerated programming, or
device damage may result.
current specification for reading array data.
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words. The appropriate page is se-
lected by the higher address bits A(max)–A2. Address
bits A1–A0 determine the specific word within a page.
This is an asynchronous operation; the microproces-
sor supplies the specific word location.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VIO ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VIO ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The “Word
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-
acteristics section contains timing specification tables
and timing diagrams for write operations.
Refer to the DC Characteristics table for the standby
current specification.
Automatic Sleep Mode
Write Buffer
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
Write Buffer Programming allows the system to write a
maximum of 16 words in one programming operation.
This results in faster effective programming time than
the standard programming algorithms. See “Write
Buffer” for more information.
this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
June 12, 2003
Am29LV640MU
11
A D V A N C E I N F O R M A T I O N
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current. If RESET# is held at VIL
but not within VSS±0.3 V, the standby current will be
greater.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
12
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table
16-bit
16-bit
Address Range
Address Range
(in hexadecimal)
Sector
SA0
A21–A15
(in hexadecimal)
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
Sector
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
A21–A15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
June 12, 2003
Am29LV640MU
13
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table (Continued)
16-bit
16-bit
Address Range
Address Range
(in hexadecimal)
Sector
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
A21–A15
(in hexadecimal)
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
Sector
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
A21–A15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Note: All sectors are 32 Kwords in size.
14
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
In addition, when verifying sector protection, the sector
Autoselect Mode
address must appear on the appropriate highest order
address bits (see Table 2). Table 3 shows the remain-
ing address bits that are don’t care. When all neces-
sary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10. This method
does not require VID. Refer to the Autoselect Com-
mand Sequence section for more information.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A3, A2, A1, and A0 must be as shown in Table 3.
Table 3. Autoselect Codes, (High Voltage Method)
A21
to
A14
to
A8
to
A5
to
A3
to
Description
CE# OE# WE#
A9
A6
A1
A0
DQ15 to DQ0
A15
A10
A7
A4
A2
VID
Manufacturer ID: AMD
Cycle 1
L
L
L
L
H
H
X
X
X
L
X
L
L
L
L
H
L
0001h
227Eh
2213h
2201h
L
VID
Cycle 2
X
X
X
L
X
H
H
H
H
Cycle 3
H
Sector Protection
Verification
XX01h (protected),
XX00h (unprotected)
VID
VID
L
L
L
L
H
H
SA
X
X
X
X
X
L
L
X
X
L
L
H
H
L
SecSi Sector Indicator Bit
(DQ7)
XX98h (factory locked),
XX18h (not factory locked)
H
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
June 12, 2003
Am29LV640MU
15
A D V A N C E I N F O R M A T I O N
Table 4. Sector Group Protection/Unprotection
Address Table
Sector Group Protection and
Unprotection
Sector Group
A21–A17
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Table 4). The hardware sector
group unprotection feature re-enables both program
and erase operations in previously protected sector
groups. Sector group protection/unprotection can be
implemented via two methods.
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
Sector protection/unprotection requires VID on the RE-
SET# pin only, and can be implemented either in-sys-
tem or via programming equipment. Figure 2 shows
the algorithms and Figure 23 shows the timing dia-
gram. This method uses standard microprocessor bus
cycle timing. For sector group unprotect, all unpro-
tected sector groups must first be protected prior to
the first sector group unprotect write cycle.
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and
protecting sector groups at its factory prior to shipping
the device through AMD’s ExpressFlash™ Service.
Contact an AMD representative for details.
It is possible to determine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.
Note: All sector groups are 128 Kwords in size.
16
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 4).
START
This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID. During this mode, for-
merly protected sector groups can be programmed or
erased by selecting the sector group addresses. Once
VID is removed from the RESET# pin, all the previ-
ously protected sector groups are protected again.
Figure 1 shows the algorithm, and Figure 22 shows
the timing diagrams, for this feature.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect
Completed (Note 2)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group
Unprotect Operation
June 12, 2003
Am29LV640MU
17
A D V A N C E I N F O R M A T I O N
START
START
PLSCNT = 1
PLSCNT = 1
RESET# = VID
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 µs
Wait 1 µs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6–A0 = 1xx0010
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
Read from
sector group address
with A6–A0
= 0xx0010
Increment
PLSCNT
A6–A0 = 1xx0010
No
No
PLSCNT
= 25?
Read from
sector group
address with
Data = 01h?
Yes
A6–A0 = 1xx0010
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Am29LV640MU
18
June 12, 2003
A D V A N C E I N F O R M A T I O N
Factory Locked: SecSi Sector Programmed and
SecSi (Secured Silicon) Sector Flash
Memory Region
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. See Table 5 for
SecSi Sector addressing.
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
vices are then shipped from AMD’s factory with the
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to program the
sector after receiving the device. The customer-lock-
able version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indi-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 128-word SecSi sector.
The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass meth-
ods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The SecSi sector address space in this device is allo-
cated as follows:
Table 5. SecSi Sector Contents
SecSi Sector
Address Range
Standard
Factory Locked Factory Locked
ExpressFlash
Customer
Lockable
The SecSi Sector area can be protected using one of
the following procedures:
ESN or
000000h–000007h
000008h–00007Fh
ESN
determined by
customer
Determined by
customer
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
Determined by
customer
Unavailable
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.
■ To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 3.
Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
June 12, 2003
Am29LV640MU
19
A D V A N C E I N F O R M A T I O N
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
START
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Low VCC Write Inhibit
RESET# =
VIH or VID
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
Wait 1 µs
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
greater than VLKO
.
Write reset
command
A1 = 1, A0 = 0
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
SecSi Sector
Protect Verify
complete
Read from SecSi
Sector address
with A6 = 0,
Logical Inhibit
A1 = 1, A0 = 0
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Figure 3. SecSi Sector Protect Verify
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
mand definitions). In addition, the following hardware
20
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
given in Tables 6–9. To terminate reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the de-
vice to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/flash/cfi. Al-
ternatively, contact an AMD representative for copies
of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
Table 6. CFI Query Identification String
Description
Addresses (x16)
Data
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
Primary OEM Command Set
13h
14h
0002h
0000h
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 7. System Interface String
Description
Addresses (x16)
Data
V
CC Min. (write/erase)
1Bh
0027h
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
June 12, 2003
Am29LV640MU
21
A D V A N C E I N F O R M A T I O N
Table 8. Device Geometry Definition
Addresses (x16)
Data
Description
27h
0017h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
(00h not supported)
2Ah
2Bh
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Ch
0001h
2Dh
2Eh
2Fh
30h
007Fh
0000h
0000h
0001h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
35h
36h
37h
38h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
22
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
Table 9. Primary Vendor-Specific Extended Query
Addresses (x16)
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0008h
Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
0002h
0004h
0001h
0004h
0000h
0000h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top
Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top
WP# protect
4Fh
50h
0000h
0001h
Program Suspend
00h = Not Supported, 01h = Supported
June 12, 2003
Am29LV640MU
23
A D V A N C E I N F O R M A T I O N
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 10 defines the valid register command
sequences. Writing incorrect address and data values
or writing them in the improper sequence may place
the device in an unknown state. A reset command is
then required to return the device to reading array
data.
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
Note that if DQ1 goes high during a Write Buffer Pro-
gramming operation, the system must write the
Write-to-Buffer-Abort Reset command sequence to
reset the device for the next operation.
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to read several identifier codes at specific ad-
dresses:
Identifier Code
Manufacturer ID
A7:A0
00h
Device ID, Cycle 1
01h
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode
if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode.
See the next section, Reset Command, for more infor-
mation.
Device ID, Cycle 2
0Eh
Device ID, Cycle 3
0Fh
SecSi Sector Factory Protect
Sector Protect Verify
03h
(SA)02h
Note: The device ID is read over three cycles. SA = Sector Address
Table 10 shows the address and data requirements.
This method is an alternative to that shown in Table 3,
which is intended for PROM programmers and re-
quires VID on address pin A9. The autoselect com-
mand sequence may be written to an address that is
either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
24
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
The device then enters the unlock bypass mode. A
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 10 shows the require-
ments for the command sequence.
The SecSi Sector region provides a secured data area
containing an 8-word random Electronic Serial Num-
ber (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the de-
vice to normal operation. Table 10 shows the address
and data requirements for both command sequences.
See also “SecSi (Secured Silicon) Sector Flash
Memory Region” for further information.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 10 shows the address
and data requirements for the word program com-
mand sequence.
Write Buffer Programming
Write Buffer Programming allows the system write to a
maximum of 16 words in one programming operation.
This results in faster effective programming time than
the standard programming algorithms. The Write
Buffer Programming command sequence is initiated
by first writing two unlock cycles. This is followed by a
third write cycle containing the Write Buffer Load com-
mand written at the Sector Address in which program-
ming will occur. The fourth cycle writes the sector
address and the number of word locations, minus one,
to be programmed. For example, if the system will pro-
gram 6 unique address locations, then 05h should be
written to the device. This tells the device how many
write buffer addresses will be loaded with data and
therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot
exceed the size of the write buffer or the operation will
abort.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Write Operation
Status section for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
The fifth cycle writes the first address location and
data to be programmed. A write-buffer-page is se-
lected by address bits AMAX–A4. All subsequent ad-
dress/data pairs must fall within the
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be per-
formed across multiple write-buffer pages. This also
means that Write Buffer Programming cannot be per-
formed across multiple sectors. If the system attempts
to load programming data outside of the selected
write-buffer page, the operation will abort.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
June 12, 2003
Am29LV640MU
25
A D V A N C E I N F O R M A T I O N
system must therefore account for loading a ■ Write an Address/Data pair to
a
different
write-buffer location more than once. The counter
decrements for each data load operation, not for each
unique write-buffer-address location. Additionally, the
last data loaded prior to the Program Buffer to Flash
command will be programmed into the device. Note
also that if an address location is loaded more than
once into the buffer, the final data loaded for that ad-
dress will be programmed.
write-buffer-page than the one selected by the
Starting Address during the write buffer data load-
ing stage of the operation.
■ Write data other than the Confirm Command after
the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset
command sequence must be written to reset the de-
vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-Abort Reset command sequence is re-
quired when using Write-Buffer-Programming features
in Unlock Bypass mode.
Once the specified number of write buffer locations
have been loaded, the system must then write the Pro-
gram Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write
Buffer Programming.
Accelerated Program
The device offers accelerated program operations
through the ACC pin. When the system asserts VHH on
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the
ACC pin must not be at VHH for operations other than
accelerated programming, or device damage may re-
sult.
The write-buffer programming operation can be sus-
pended using the standard program suspend/resume
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be
aborted in the following ways:
Figure 4 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 16 for timing diagrams.
■ Load a value that is greater than the page buffer
size during the Number of Locations to Program
step.
■ Write to an address in a sector different than the
one specified during the Write-Buffer-Load com-
mand.
26
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Yes
Buffer Operation?
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
(Note 1)
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
Read DQ7 - DQ0 at
Last Loaded Address
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this
flowchart location was reached because DQ1=
“1”, then the Write to Buffer operation was
ABORTED. In either case, the proper reset
command must be written before the device can
begin another operation. If DQ1=1, write the
Write-Buffer-Programming-Abort-Reset
Yes
DQ7 = Data?
No
No
command. if DQ5=1, write the Reset command.
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
4. See Table 10 for command sequences required for
write buffer programming.
Read DQ7 - DQ0 with
address = Last Loaded
Address
Yes
(Note 2)
DQ7 = Data?
No
(Note 3)
FAIL or ABORT
PASS
Figure 4. Write Buffer Programming Operation
Am29LV640MU
June 12, 2003
27
A D V A N C E I N F O R M A T I O N
Program Suspend/Program Resume
Command Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Sus-
pend command is written during a programming pro-
cess, the device halts the program operation within 15
µs maximum (5 µs typical) and updates the status bits.
Addresses are not required when writing the Program
Suspend command.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
After the programming operation has been sus-
pended, the system can read array data from any
non-suspended sector. The Program Suspend com-
mand may also be issued during a programming oper-
ation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Sus-
pend or Program Suspend. If a read is needed from
the SecSi Sector area (One-time Program area), then
user must use the proper command sequences to
enter and exit this region.
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect
codes as required. When the device exits the autose-
lect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.
Programming
Completed
Note: See Table 10 for program command sequence.
After the Program Resume command is written, the
device reverts to programming. The system can de-
termine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard pro-
gram operation. See Write Operation Status for more
information.
Figure 5. Program Operation
The system must write the Program Resume com-
mand (address bits are don’t care) to exit the Program
Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ig-
nored. Another Program Suspend command can be
written after the device has resume programming.
28
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to the Write Operation Status section
for information on these status bits.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Command is also valid for
Erase-suspended-program
operations
Wait 15 ms
Autoselect and SecSi Sector
Read data as
required
read operations are also allowed
Figure 6 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Figure 6. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
June 12, 2003
Am29LV640MU
29
A D V A N C E I N F O R M A T I O N
When the Embedded Erase algorithm is complete, the Refer to the Write Operation Status section for infor-
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6,
DQ2, or RY/BY# in the erasing sector. Refer to the
Write Operation Status section for information on
these status bits.
mation on these status bits.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Write Operation Status section for more
information.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writ-
ing this command. Further writes of the Resume com-
mand are ignored. Another Erase Suspend command
can be written after the chip has resumed erasing.
Figure 6 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
When the Erase Suspend command is written during
the sector erase operation, the device requires a typi-
cal of 5 µs (maximum 20 µs) to suspend the erase op-
eration. However, when the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
Erase
algorithm
in progress
No
Data = FFh?
Yes
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Erasure Completed
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 7. Erase Operation
30
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
Command Definitions
Table 10. Command Definitions
Bus Cycles (Notes 1–4)
Command Sequence (Notes)
Read (Note 6)
Addr Data Addr Data
Addr
Data
Addr
Data
Addr Data Addr Data
1
1
4
6
RA
XXX
555
555
RD
F0
Reset (Note 7)
Manufacturer ID
AA
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
Device ID (Note 9)
X0E 2213 X0F 2201
SecSi Sector Factory Protect
(Note 10)
4
4
555
555
AA
AA
2AA
2AA
55
55
555
555
90
90
X03
(Note 10)
00/01
Sector Group Protect Verify
(Note 11)
(SA)X02
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
6
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
AA
AA
AA
AA
29
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
WC
Write to Buffer (Note 12)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
SA
PA
PD
WBL
PD
555
555
XXX
XXX
555
555
BA
AA
AA
A0
90
2AA
2AA
PA
55
55
PD
00
55
55
555
555
F0
20
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
XXX
2AA
2AA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
BA
55
98
Legend:
X = Don’t care
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address . Addresses latch on the falling edge of the
WE# or CE# pulse, whichever happens later.
WC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
10. The data is 98h for factory locked and 18h for not factory locked.
2. All values are in hexadecimal.
11. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
3. Shaded cells indicate read cycles. All others are write cycles.
12. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 21.
4. During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits higher than A11 and
data bits higher than DQ7 are don’t care.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
5. Unless otherwise noted, address bits A21–A11 are don’t cares.
6. No unlock or command cycles required when device is in read
mode.
14. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
15. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
16. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
8. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care, except for RD, PD
and WC. See the Autoselect Command Sequence section for
more information.
17. The Erase Resume command is valid only during the Erase
Suspend mode.
9. The device ID must be read in three cycles.
18. Command is valid when device is ready to read array data or when
device is in autoselect mode.
June 12, 2003
Am29LV640MU
31
A D V A N C E I N F O R M A T I O N
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method
for determining whether a program or erase operation is
complete or in progress. The device also provides a hard-
ware-based output signal, RY/BY#, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 7 shows the Data# Polling algorithm. Figure 19
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Yes
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 8. Data# Polling Algorithm
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Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
After an erase command sequence is written, if all sectors
RY/BY#: Ready/Busy#
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or the device is in the erase-suspend-read
mode.
Table 11 shows the outputs for RY/BY#.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 8 shows the toggle bit algorithm. Figure 20 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 21 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
June 12, 2003
Am29LV640MU
33
A D V A N C E I N F O R M A T I O N
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
START
Read DQ7–DQ0
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare out-
puts for DQ2 and DQ6.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
Figure 8 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 9. Toggle Bit Algorithm
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
34
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 8).
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc-
cessfully completed.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
Table 11 shows the status of DQ3 relative to the other
status bits.
DQ3: Sector Erase Timer
DQ1: Write-to-Buffer Abort
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“1”.
The
system
must
issue
the
Write-to-Buffer-Abort-Reset command sequence to re-
turn the device to reading array data. See Write Buffer
Table 11. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
DQ1 RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program
Suspend
Mode
Program-
Sector
Suspend
Non-Program
Read
Suspended Sector
Erase-Suspended
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Sector
Suspend
Erase
Suspend
Mode
Non-EraseSuspended
Read
Data
Sector
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
June 12, 2003
Am29LV640MU
35
A D V A N C E I N F O R M A T I O N
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
+0.8 V
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
20 ns
A9, OE#, ACC, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
Figure 10. Maximum Negative
Overshoot Waveform
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 9. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 10.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 9. Maximum DC input
voltage on pin A9, OE#, ACC, and RESET# is +12.5 V
which may overshoot to +14.0 V for periods up to 20 ns.
2.0 V
20 ns
20 ns
Figure 11. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC (regulated voltage range) . . . . . . . . . . . 3.0–3.6 V
VCC (full voltage range). . . . . . . . . . . . . . . . . 2.7–3.6 V
VIO (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65–3.0V
Notes:
1. Operating ranges define those limits between which the
functionality of the device is guaranteed.
2. See Ordering Information section for valid VCC/VIO range
combinations. The I/Os cannot go to 3 V when VIO
1.8 V.
=
36
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current (Note 1)
Test Conditions
VIN = VSS to VCC
Min
Typ
Max
±1.0
35
Unit
µA
,
ILI
VCC = VCC max
ILIT
ILO
ILR
A9, ACC Input Load Current
Output Leakage Current
Reset Leakage Current
VCC = VCC max; A9 = 12.5 V
µA
VOUT = VSS to VCC
,
±1.0
µA
VCC = VCC max
VCC = VCC max; RESET# = 12.5 V
35
20
20
µA
5 MHz
CE# = VIL, OE# = VIH
1 MHz
15
15
VCC Active Read Current
(Notes 1, 2)
ICC1
mA
VCC Initial Page Read Current
(Notes 1, 2)
ICC2
ICC3
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
30
10
50
20
mA
mA
VCC Intra-Page Read Current
(Notes 1, 2)
ICC4
ICC5
ICC6
VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH
50
1
60
5
mA
µA
µA
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
CE#, RESET# = VCC ± 0.3 V
RESET# = VSS ± 0.3 V
1
5
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V
ICC7
Automatic Sleep Mode (Notes 2, 4)
1
5
µA
VIL1
VIH1
VIL2
VIH2
Input Low Voltage 1(Notes 5, 6)
Input High Voltage 1 (Notes 5, 6)
Input Low Voltage 2 (Notes 5, 7)
Input High Voltage 2 (Notes 5, 7)
–0.5
0.7 x VCC
–0.5
0.8
V
V
V
V
VCC + 0.5
0.3 x VIO
VIO + 0.5
0.7 x VIO
Voltage for ACC Program
Acceleration
VHH
VID
VCC = 2.7 –3.6 V
11.5
11.5
12.5
V
V
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 2.7 –3.6 V
12.5
VOL
VOH1
VOH2
VLKO
Output Low Voltage (Note 9)
IOL = 4.0 mA, VCC = VCC min = VIO
IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO
0.15 x VIO
V
V
V
V
Output High Voltage
IOH = –100 µA, VCC = VCC min = VIO
VIO–0.4
2.3
Low VCC Lock-Out Voltage (Note 8)
2.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
5. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH
for these connections is VIO + 0.3 V
6. VCC voltage requirements.
7. VIO voltage requirements. VCC = 3 V and VIO = 3 V or 1.8 V. When VIO is at 1.8 V, I/Os cannot operate at 3 V.
8. Not 100% tested.
9. Includes RY/BY#.
June 12, 2003
Am29LV640MU
37
A D V A N C E I N F O R M A T I O N
TEST CONDITIONS
Table 12. Test Specifications
Test Condition All Speeds
Output Load 1 TTL gate
3.3 V
Unit
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels (See Note)
1.5
V
V
Output timing measurement
reference levels
0.5 VIO
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Changing, State Unknown
Don’t Care, Any Change Permitted
Does Not Apply
Center Line is High Impedance State (High Z)
3.0 V
1.5 V
0.5 VIO V
Input
Measurement Level
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 13. Input Waveforms and
Measurement Levels
38
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
JEDE
101,
C
Std. Description
Test Setup
90R 101R
112
112R 120 120R Unit
tAVAV tRC Read Cycle Time (Note 1)
tAVQV tACC Address to Output Delay
tELQV tCE Chip Enable to Output Delay
Min
Max
Max
Max
Max
Max
90
90
90
25
25
100
100
100
30
110
110
110
120
120
120
ns
ns
ns
ns
ns
ns
CE#, OE# =
VIL
OE# = VIL
tPAC
Page Access Time
30
30
40
40
30
30
40
40
C
tGLQV tOE Output Enable to Output Delay
30
Chip Enable to Output High Z (Note
1)
tEHQZ tDF
16
16
Output Enable to Output High Z
tGHQZ tDF
(Note 1)
Max
ns
Output Hold Time From Addresses,
tAXQX tOH
Min
Min
Min
0
0
ns
ns
ns
CE# or OE#, Whichever Occurs First
Read
Output Enable
tOEH Hold Time (Note
Toggle and
Data# Polling
10
1)
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 12 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
Output Valid
HIGH Z
HIGH Z
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
June 12, 2003
Am29LV640MU
39
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Same Page
A21
-
-
A2
A0
A1
Ad
Aa
Ab
Ac
tPACC
tPACC
tPACC
tACC
Data Bus
CE#
Qa
Qb
Qc
Qd
OE#
Note: Toggle A0, A1, A2.
Figure 15. Page Read Timings
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Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
RESET# Pin Low (During Embedded Algorithms)
All Speed Options
Unit
tReady
Max
Max
20
µs
to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 16. Reset Timings
June 12, 2003
Am29LV640MU
41
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R
101
112
120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
90
100
110
120
tAVWL
0
15
45
0
ns
Address Setup Time to OE# low during toggle bit
polling
tASO
tAH
Min
Min
Min
ns
ns
ns
tWLAX
Address Hold Time
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
45
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
tWP
tWPH
CE# Setup Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
CE# Hold Time
Write Pulse Width
35
30
352
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Effective Write Buffer Program Operation, Per
Word (Notes 2, 4)
Typ
22
µs
Accelerated Effective Write Buffer Program
Operation, Per Word (Notes 2, 4)
tWHWH1
tWHWH1
Typ
Typ
Typ
17.6
100
90
µs
µs
µs
Single Word Program Operation (Note 2, 5)
Accelerated Single Word Programming
Operation (Note 2, 5)
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Min
Min
Min
0.5
250
50
0
sec
ns
µs
ns
ns
tVHH
tVCS
tRB
VHH Rise and Fall Time (Note 1)
VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#
WE# High to RY/BY# Low
tBUSY
90
100
110
120
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words programmed.
4. Effective write buffer specification is based upon a 16-word write buffer operation.
5. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
6. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.
42
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
VCC
tVCS
tBUSY
RY/BY#
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 17. Program Operation Timings
VHH
VIL or VIH
ACC
VIL or VIH
tVHH
tVHH
Figure 18. Accelerated Program Timing Diagram
June 12, 2003
Am29LV640MU
43
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note:
SA= sector address (for Sector Erase), VA= Valid Address for reading status data (see “Write Operation Status”).
Figure 19. Chip/Sector Erase Operation Timings
44
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
tRC
Addresses
VA
tACC
tCE
VA
VA
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 20. Data# Polling Timings
(During Embedded Algorithms)
June 12, 2003
Am29LV640MU
45
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
RY/BY#
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 21. Toggle Bit Timings
(During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 22. DQ2 vs. DQ6
46
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector Group Unprotect
tRRB
Min
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 23. Temporary Sector Group Unprotect Timing Diagram
June 12, 2003
Am29LV640MU
47
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Sector Group Protect or Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 24. Sector Group Protect and Unprotect Timing Diagram
48
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
101,
112,
120,
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R
101R
112R
120R Unit
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
90
100
110
120
ns
ns
ns
ns
ns
tAVWL
tELAX
tDVEH
tEHDX
0
45
45
0
tAH
tDS
tDH
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
0
0
ns
ns
ns
ns
CE# Pulse Width
CE# Pulse Width High
45
30
tCPH
Write Buffer Program Operation
(Notes 2, 3)
Typ
Typ
352
22
µs
µs
Effective Write Buffer Program Operation,
Per Word (Notes 2, 4)
tWHWH1
tWHWH1
Accelerated Effective Write Buffer Program
Operation, Per Word (Notes 2, 4)
Typ
Typ
Typ
17.6
100
90
µs
µs
µs
Single Word Program (Note 2, 5)
Accelerated Single Word Programming
Operation (Note 2, 5)
tWHWH2
tWHWH2
tRH
Sector Erase Operation (Note 2)
Typ
Min
0.5
50
sec
ns
RESET # High Time Before Write (Note 1)
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information. Write buffer program is typical per word.
3. For 1–16 words programmed.
4. Effective write buffer specification is based upon a 16-word write buffer operation.
5. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
6. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.
June 12, 2003
Am29LV640MU
49
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings
50
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
Chip Erase Time
0.5
32
15
128
Byte
Word
Byte
100
100
90
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Single Word/Byte Program Time (Note 3)
µs
µs
Accelerated Single Word/Byte Program Time
(Note 3)
Word
90
µs
Total Write Buffer Program Time (Note 4)
Effective Write Buffer Program Time (Note 5)
352
11
µs
Per Byte
Per Word
µs
22
µs
Total Accelerated Effective Write Buffer
Program Time (Note 4)
282
8.8
TBD
TBD
µs
µs
Effective Accelerated Write Buffer PRogram
Time (Note 4)
Byte
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume
that all bits are programmed to 00h.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000
program/erase cycles.
3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
4. For 1-16 words or 1-32 bytes programmed ina single write buffer programming operation.
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 12 and
11 for further information on command definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
June 12, 2003
Am29LV640MU
51
A D V A N C E I N F O R M A T I O N
TSOP PIN AND FINE-PITCH BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
Unit
pF
pF
pF
pF
pF
pF
TSOP
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
Fine-pitch BGA
TSOP
4.2
8.5
5.4
7.5
3.9
COUT
Output Capacitance
Fine-pitch BGA
TSOP
6.5
9
CIN2
Control Pin Capacitance
Fine-pitch BGA
4.7
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
Unit
Years
Years
10
20
Minimum Pattern Data Retention Time
125°C
52
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package
June 12, 2003
Am29LV640MU
53
A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm Package
Dwg rev AF; 10/99
54
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
Autoselect Command
REVISION SUMMARY
Revision A (August 3, 2001)
Initial release as abbreviated Advance Information
data sheet.
Substituted text with ID code table for easier refer-
ence.
Revision A+1 (September 12, 2001)
Table 10, Command Definitions
Global
Combined Notes 4 and 5 from Revision B. Corrected
number of cycles indicated for Write-to-Buffer and Au-
toselect Device ID command sequences.
Changed description of chip-scale package from
63-ball FBGA to 64-ball Fortified BGA.
Ordering Information
Revision B+2 (August 5, 2002)
Changed package part number designation from WH
to PC.
MIRRORBIT 64 MBIT Device Family
Added 64 Fortified BGA to LV640MU device.
Physical Dimensions
Added the TS056 and LAA064 packages.
Alternate CE# Controlled Erase and Program
Operations
Revision A+2 (October 3, 2001)
Added tRH parameter to table.
Global
Erase and Program Operations
Added information for WP# protected devices
(LV640MH/L). Clarified VCC and VIO ranges.
Added tBUSY parameter to table.
Connection Diagrams
Figure 16. Program Operation Timings
Changed RFU (reserved for future use) to NC (no con-
nection). Added 63-ball FBGA drawing.
Added RY/BY# to waveform.
TSOP and BGA PIN Capacitance
Ordering Information
Added the FBGA package.
Added H and L valid combinations for WP# protected
devices. Changed voltage operating range for 90 ns
device.
Program Suspend/Program Resume Command
Sequence
Revision B (March 19, 2002)
Changed 15 µs typical to maximum and added 5 µs
Global
typical.
Expanded data sheet to full specification version.
Starting with this revision, the data sheet will only con-
tain specifications for the Am29LV640MU part num-
ber. For Am29LV640MH/L part number specifications,
refer to publication number 26191.
Erase Suspend/Erase Resume Commands
Changed typical from 20 µs to 5 µs and added a maxi-
mum of 20 µs.
Revision B+3 (September 10, 2002)
Revision B+1 (April 26, 2002)
Product Selector Guide
Global
Added Note 2.
Deleted references to word mode.
Ordering Information
MirrorBit 64 Mbit Device Family
Added Note 1.
Deleted Am29LV641MT/B.
Connection Diagram
Figure 2, In-System Sector Group
Protect/Unprotect Algorithms
Deleted A-1 from Pin G7.
Sector Erase Command Sequence
Modified to show A2, A3 address requirements.
Deleted statement that describes the outcome of when
the Embedded Erase operation is in progress.
Sector Protection/Unprotection
Deleted references to alternate method of sector pro-
tection.
June 12, 2003
Am29LV640MU
55
A D V A N C E I N F O R M A T I O N
Ordering Information
Revision B+4 (February 16, 2003)
Removed note from sector architecture.
Distinctive Characteristics
Table 3. Autoselect Codes, (High Voltage Method)
Corrected performance characteristics.
Updated DQ15 to DQ0 for Sector Protection Verifica-
tion and SecSi Sector Indicator Bit.
Product Selector Guide
Added note 2.
SecSi (Secured Silicon) Sector Flash Memory
Region
Ordering Information
Corrected Valid Combination to reflect speed option
changes.
Updated second bullet in Customer Lockable section.
Added Figure 3.
Added Note.
Command Definitions
AC Characteristics
Updated first paragraph.
Removed 90R speed option.
Table 3. Autoselect Codes, (High Voltage Method)
Table 10. Command Definitions
Added Note
Input values in the tWHWH1 and tWHWH2 parameters in
the Erase and Program Options table that were previ-
ously TBD. Also added notes 5 and 6.
Corrected Note #10 to read 98h for factory locked and
18h for not factory locked.
Operating Ranges
Input values in the tWHWH1 and tWHWH2 parameters in
the Alternate CE# Controlled Erase and Program Op-
tions table that were previously TBD. Also added
notes 5 and 6.
Added a VCC for regulated voltage and added stan-
dard voltage range title for remaining VCC.
CMOS Compatible
Erase and Programming Performance
Added ILR parameter symbol.
Input values into table that were previously TBD.
Updated ICC parameter symbol.
Added note 4.
Revision C+1 (June 12, 2003)
Revision C (March 11, 2003)
Ordering Information
Added 90R speed grade, modified note.
Product Selector Guide and AC Characteristics,
Read Only Operations Table
Erase and Programming Performance
Added seperate values for the 112 and 120 ns speed
options in the Page access times and OE# access
time.
Modified table, inserted values for Typical.
Trademarks
Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
56
Am29LV640MU
June 12, 2003
Representatives in U.S. and Canada
Sales Offices and Representatives
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North America
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Advanced Micro Devices reserves the right to make changes in its product without notice
in order to improve design or performance characteristics.The performance
characteristics listed in this document are guaranteed by specific tests, guard banding,
design and other practices common to the industry. For specific testing details, contact
your local AMD sales representative.The company assumes no responsibility for the use of
any circuits described herein.
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©2003 Advanced Micro Devices, Inc.
01/03
Printed in USA
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