AM29BDS128HE9VFI_技术文档

Am29BDS128H/Am29BDS640H

Data Sheet

RETIRED

PRODUCT

(AM29BDS40H ONLY)

(

The Am29BDS640H has been retired and is not recommended for designs. For new designs,

S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for speci-

fications and ordering information. The Am29BDS128H is available and is not affected by this revi-

sion.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary. Future routine revisions will occur when appropriate, and changes will

be noted in a revision summary.

Continuity of Ordering Part Numbers

Spansion continues to support the Am29BDS640H part numbers. To order these products, please

use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 27024 Revision B Amendment 3 Issue Date May 10, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29BDS128H/Am29BDS640H

128 or 64 Megabit (8 M or 4 M x 16-Bit)

CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

The Am29BDS640H has been retired and is not recommended for designs. For new designs, S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for

specifications and ordering information. The Am29BDS128H is available and is not affected by this revision.

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

HARDWARE FEATURES

■

Single 1.8 volt read, program and erase (1.65 to 1.95 volt)

Manufactured on 0.13 µm process technology

VersatileIO™ (V_IO) Feature

■

Handshaking feature

—

Provides host system with minimum possible latency by

monitoring RDY

—

Reduced Wait-state handshaking option further reduces

initial access cycles required for burst accesses beginning on

even addresses

—

Device generates data output voltages and tolerates data

input voltages as determined by the voltage on the V_IOpin

1.8V compatible I/O signals

—

■

Hardware reset input (RESET#)

Hardware method to reset the device for reading array data

WP# input

Write protect (WP#) function allows protection of the four

■

Simultaneous Read/Write operation

—

Data can be continuously read from one bank while

executing erase/program functions in other bank

Zero latency between read and write operations

Four bank architecture:

—

highest and four lowest 4 kWord boot sectors, regardless of

sector protect status

128 Mb has 16/48/48/16 Mbit banks

■

Persistent Sector Protection

64 Mb has 8/24/24/8 Mbit banks

—

A command sector protection method to lock combinations of

individual sectors and sector groups to prevent program or

erase operations within that sector

■

Programable Burst Interface

—

2 Modes of Burst Read Operation

Linear Burst: 8, 16, and 32 words with wrap-around

Continuous Sequential Burst

—

Sectors can be locked and unlocked in-system at V_CClevel

■

Password Sector Protection

■

SecSi^TM(Secured Silicon) Sector region

—

A sophisticated sector protection method to lock

combinations of individual sectors and sector groups to

prevent program or erase operations within that sector using

a user-defined 64-bit password

—

Up to 128 words accessible through a command sequence

Up to 64 factory-locked words

Up to 64 customer-lockable words

Sector Architecture

ACC input: Acceleration function reduces programming

time; all sectors locked when ACC = V_IL

—

Banks A and D each contain both 4 Kword sectors and 32

Kword sectors; Banks B and C contain ninety-six 32 Kword

sectors

■

CMOS compatible inputs, CMOS compatible outputs

Low V_CCwrite inhibit

—

Sixteen 4 Kword boot sectors

Half of the boot sectors are at the top of the address range;

half are at the bottom of address range

SOFTWARE FEATURES

■

Minimum 1 million erase cycle guarantee per sector

20-year data retention at 125°C

■

Supports Common Flash Memory Interface (CFI)

■

Software command set compatible with JEDEC 42.4

standards

—

Reliable operation for the life of the system

■

80-ball FBGA package (128 Mb) or 64-ball FBGA (64 Mb)

package

—

Backwards compatible with Am29F and Am29LV families

■

Data# Polling and toggle bits

—

Provides a software method of detecting program and erase

operation completion

PERFORMANCE CHARCTERISTICS

■

Read access times at 75/66/54 MHz (C_L=30 pF)

Erase Suspend/Resume

—

Burst access times of 9.3/11/13.5 ns at industrial

temperature range

—

Suspends an erase operation to read data from, or program

data to, a sector that is not being erased, then resumes the

erase operation

—

Synchronous latency of 49/56/69 ns

Asynchronous random access times of 45/50/55 ns

■

Unlock Bypass Program command

■

Power dissipation (typical values, C_L= 30 pF)

—

Reduces overall programming time when issuing multiple

program command sequences

—

Burst Mode Read: 10 mA

Simultaneous Operation: 25 mA

Program/Erase: 15 mA

Burst Suspend/Resume

—

Suspends a burst operation to allow system use of the

address and data bus, than resumes the burst at the previous

state

Standby mode: 0.2 µA

Publication# 27024

Rev: B Amendment: 3

Issue Date: May 10, 2006

D A T A S H E E T

GENERAL DESCRIPTION

The Am29BDS128H/Am29BDS640H is a 128 or 64 Mbit, 1.8

Volt-only, simultaneous Read/Write, Burst Mode Flash mem-

ory device, organized as 8,388,608 or 4,194,304 words of 16

bits each. This device uses a single V_CCof 1.65 to 1.95 V to

read, program, and erase the memory array. A 12.0-volt V_HH

on ACC may be used for faster program performance if de-

sired. The device can also be programmed in standard

EPROM programmers.

The clock polarity feature provides system designers a

choice of active clock edges, either rising or falling. The ac-

tive clock edge initiates burst accesses and determines

when data will be output.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply Flash standard. Com-

mands are written to the command register using standard

microprocessor write timing. Register contents serve as in-

puts to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch ad-

dresses and data needed for the programming and erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

At 75 MHz, the device provides a burst access of 9.3 ns at

30 pF with a latency of 49 ns at 30 pF. At 66 MHz, the device

provides a burst access of 11 ns at 30 pF with a latency of

56 ns at 30 pF. At 54 MHz, the device provides a burst ac-

cess of 13.5 ns at 30 pF with a latency of 69ns at 30 pF. The

device operates within the industrial temperature range of

-40°C to +85°C. The device is offered in FBGA packages.

The Erase Suspend/Erase Resume feature enables the

user to put erase on hold for any period of time to read data

from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved. If a

read is needed from the SecSi Sector area (One Time Pro-

gram area) after an erase suspend, then the user must use

the proper command sequence to enter and exit this region.

The Simultaneous Read/Write architecture provides simul-

taneous operation by dividing the memory space into four

banks. The device can improve overall system performance

by allowing a host system to program or erase in one bank,

then immediately and simultaneously read from another

bank, with zero latency. This releases the system from wait-

ing for the completion of program or erase operations.

The hardware RESET# pin terminates any operation in

progress and resets the internal state machine to reading

array data. The RESET# pin may be tied to the system reset

circuitry. A system reset would thus also reset the device,

enabling the system microprocessor to read boot-up firm-

ware from the Flash memory device.

The device is divided as shown in the following table:

Quantity

Bank

128 Mb

64 Mb

8

Size

The host system can detect whether a program or erase op-

eration is complete by using the device status bit DQ7

(Data# Polling) and DQ6/DQ2 (toggle bits). After a program

or erase cycle has been completed, the device automatically

returns to reading array data.

8

4 Kwords

32 Kwords

4 Kwords

A

31

96

31

8

15

48

15

8

B

C

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

D

Hardware data protection measures include a low V_CCde-

tector that automatically inhibits write operations during

power transitions. The device also offers two types of data

protection at the sector level. When at V_IL, WP# locks the

four highest and four lowest boot sectors.

The VersatileIO™ (V_IO) control allows the host system to set

the voltage levels that the device generates at its data out-

puts and the voltages tolerated at its data inputs to the same

voltage level that is asserted on the V_IOpin.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power con-

sumption is greatly reduced in both modes.

The device uses Chip Enable (CE#), Write Enable (WE#),

Address Valid (AVD#) and Output Enable (OE#) to control

asynchronous read and write operations. For burst opera-

tions, the device additionally requires Ready (RDY), and

Clock (CLK). This implementation allows easy interface with

minimal glue logic to a wide range of microprocessors/micro-

controllers for high performance read operations.

AMD Flash technology combines years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunnelling. The data is programmed using

hot electron injection.

The burst read mode feature gives system designers flexibil-

ity in the interface to the device. The user can preset the

burst length and wrap through the same memory space, or

read the flash array in continuous mode.

2

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram of Simultaneous

Low V Write Inhibit .............................................................. 24

CC

Write Pulse “Glitch” Protection ................................................ 24

Logical Inhibit .......................................................................... 24

Power-Up Write Inhibit ............................................................ 24

Table 8. CFI Query Identification String ......................................... 24

Table 9. System Interface String .................................................... 25

Table 10. Device Geometry Definition ........................................... 25

Table 11. Primary Vendor-Specific Extended Query ..................... 26

Table 12. Am29BDS128H Sector Address Table .......................... 27

Table 13. Am29BDS640H Sector Address Table .......................... 31

Command Definitions . . . . . . . . . . . . . . . . . . . . . 33

Reading Array Data ................................................................ 33

Set Configuration Register Command Sequence ...................33

Figure 3. Synchronous/Asynchronous State Diagram ................... 33

Read Mode Setting ................................................................. 33

Programmable Wait State Configuration ................................ 33

Table 14. Programmable Wait State Settings ................................ 34

Reduced Wait-state Handshaking Option ............................... 34

Table 15. Wait States for Reduced Wait-state Handshaking ........ 34

Standard Handshaking Option ................................................ 35

Table 16. Wait States for Standard Handshaking .......................... 35

Read Mode Configuration ....................................................... 35

Table 17. Read Mode Settings ....................................................... 35

Burst Active Clock Edge Configuration ................................... 35

RDY Configuration .................................................................. 35

Table 18. Configuration Register ................................................... 36

Reset Command ..................................................................... 36

Autoselect Command Sequence ............................................ 36

Table 19. Autoselect Data .............................................................. 37

Enter SecSi™ Sector/Exit SecSi Sector

Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7

Special Handling Instructions for FBGA Package .................... 8

Input/Output Descriptions . . . . . . . . . . . . . . . . . . .9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . .10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11

Table 1. Device Bus Operations ....................................................11

Requirements for Asynchronous Read

Operation (Non-Burst) ............................................................ 11

Requirements for Synchronous (Burst) Read Operation ........ 11

8-, 16-, and 32-Word Linear Burst with Wrap Around ............ 12

Table 2. Burst Address Groups .......................................................12

Burst Suspend/Resume .......................................................... 12

Configuration Register ............................................................ 13

Reduced Wait-state Handshaking Option .............................. 13

Simultaneous Read/Write Operations with Zero Latency ....... 13

Writing Commands/Command Sequences ............................ 13

Accelerated Program Operation ............................................. 14

Autoselect Mode ..................................................................... 14

Table 3. Autoselect Codes (High Voltage Method) ........................15

Table 4. Am29BDS128H Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................16

Table 5. Am29BDS640H Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................17

Sector/Sector Block Protection and Unprotection .................. 17

Sector Protection .................................................................... 17

Selecting a Sector Protection Mode ....................................... 17

Persistent Sector Protection ................................................... 18

Persistent Protection Bit (PPB) ............................................... 18

Persistent Protection Bit Lock (PPB Lock) ............................. 18

Dynamic Protection Bit (DYB) ................................................ 18

Table 6. Sector Protection Schemes ...............................................19

Persistent Sector Protection Mode Locking Bit ...................... 19

Password Protection Mode ..................................................... 19

Password and Password Mode Locking Bit ........................... 20

64-bit Password ...................................................................... 20

Persistent Protection Bit Lock ................................................. 20

High Voltage Sector Protection .............................................. 20

Standby Mode ........................................................................ 20

Automatic Sleep Mode ........................................................... 21

RESET#: Hardware Reset Input ............................................. 21

Output Disable Mode .............................................................. 21

Figure 1. Temporary Sector Unprotect Operation........................... 21

Figure 2. In-System Sector Protection/

Command Sequence .............................................................. 37

Program Command Sequence ............................................... 37

Unlock Bypass Command Sequence ..................................... 37

Figure 4. Program Operation ......................................................... 38

Chip Erase Command Sequence ........................................... 38

Sector Erase Command Sequence ........................................ 38

Erase Suspend/Erase Resume Commands ........................... 39

Figure 5. Erase Operation.............................................................. 40

Password Program Command ................................................ 40

Password Verify Command .................................................... 40

Password Protection Mode Locking Bit Program Command .. 40

Persistent Sector Protection Mode Locking Bit Program Com-

mand ....................................................................................... 40

SecSi Sector Protection Bit Program Command ....................41

PPB Lock Bit Set Command ................................................... 41

DYB Write Command ............................................................. 41

Password Unlock Command .................................................. 41

Figure 6. PPB Program Algorithm.................................................. 42

PPB Program Command ........................................................ 43

All PPB Erase Command ........................................................ 43

Figure 7. PPB Erase Algorithm ...................................................... 44

DYB Write Command ............................................................. 45

PPB Status Command ............................................................ 45

PPB Lock Bit Status Command .............................................. 45

DYB Status Command ............................................................ 45

Command Definitions ............................................................. 46

Table 20. Memory Array Command Definitions ............................ 46

Table 21. Sector Protection Command Definitions ....................... 47

Sector Unprotection Algorithms ...................................................... 22

SecSi™ (Secured Silicon) Sector

Flash Memory Region ............................................................ 23

Factory-Locked Area (64 words) ............................................ 23

Table 7. SecSi^TMSector Addresses ...............................................23

Customer-Lockable Area (64 words) ...................................... 23

SecSi Sector Protection Bits ................................................... 23

Hardware Data Protection ...................................................... 23

Write Protect (WP#) ................................................................ 24

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

3

D A T A S H E E T

cess................................................................................................ 63

Write Operation Status . . . . . . . . . . . . . . . . . . . . .48

DQ7: Data# Polling ................................................................. 48

Figure 8. Data# Polling Algorithm ................................................... 48

DQ6: Toggle Bit I .................................................................... 49

Figure 9. Toggle Bit Algorithm......................................................... 50

DQ2: Toggle Bit II ................................................................... 50

Table 22. DQ6 and DQ2 Indications ...............................................51

Reading Toggle Bits DQ6/DQ2 .............................................. 51

DQ5: Exceeded Timing Limits ................................................ 51

DQ3: Sector Erase Timer ....................................................... 51

Table 23. Write Operation Status ....................................................52

Absolute Maximum Ratings . . . . . . . . . . . . . . . . .53

Figure 10. Maximum Negative Overshoot Waveform ..................... 53

Figure 11. Maximum Positive Overshoot Waveform....................... 53

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 53

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .54

CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . .54

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 12. Test Setup...................................................................... 55

Table 24. Test Specifications ..........................................................55

Key to Switching Waveforms . . . . . . . . . . . . . . . 55

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 55

Figure 13. Input Waveforms and Measurement Levels .................. 55

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 27. Standard Handshake Burst Suspend at Address 3Fh (Start-

ing Address 3Dh or Earlier)............................................................ 64

Figure 28. Standard Handshake Burst Suspend at Address 3Eh/3Fh

(Without a Valid Initial Access)....................................................... 64

Figure 29. Standard Handshake Burst Suspend at Address 3Eh/3Fh

(with 1 Access CLK)....................................................................... 65

Figure 30. Read Cycle for Continuous Suspend............................ 65

Asynchronous Mode Read .................................................... 66

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 31. Asynchronous Mode Read with Latched Addresses .... 67

Figure 32. Asynchronous Mode Read............................................ 67

Figure 33. Reset Timings............................................................... 68

Erase/Program Operations ..................................................... 69

Figure 34. Asynchronous Program Operation Timings: AVD# Latched

Addresses ...................................................................................... 70

Figure 35. Asynchronous Program Operation Timings: WE# Latched

Addresses ...................................................................................... 71

Figure 36. Synchronous Program Operation Timings: WE# Latched

Addresses ...................................................................................... 72

Figure 37. Synchronous Program Operation Timings: CLK Latched

Addresses ...................................................................................... 73

Figure 38. Chip/Sector Erase Command Sequence...................... 74

Figure 39. Accelerated Programming Timing................................. 75

Figure 40. Data# Polling Timings (During Embedded Algorithm) .. 76

Figure 41. Toggle Bit Timings (During Embedded Algorithm)........ 76

Figure 42. Synchronous Data Polling Timings/Toggle Bit Timings 77

Figure 43. DQ2 vs. DQ6................................................................. 77

Temporary Sector Unprotect .................................................. 78

Figure 44. Temporary Sector Unprotect Timing Diagram .............. 78

Figure 45. Sector/Sector Block Protect and

V

Power-up ......................................................................... 56

CC

Figure 14. V_CCPower-up Diagram ................................................. 56

CLK Characterization ............................................................. 56

Figure 15. CLK Characterization..................................................... 56

Synchronous/Burst Read ....................................................... 57

Figure 16. CLK Synchronous Burst Mode Read (rising active CLK) ...

.........................................................................................................58

Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock)

.........................................................................................................58

Figure 18. Synchronous Burst Mode Read..................................... 59

Figure 19. 8-word Linear Burst with Wrap Around.......................... 59

Figure 20. Linear Burst with RDY Set One Cycle Before Data ....... 60

Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at

an Even Address............................................................................. 61

Figure 22. Reduced Wait-state Handshake Burst Suspend/Resume at

an Odd Address .............................................................................. 61

Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at

Address 3Eh (or Offset from 3Eh)................................................... 62

Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume at

Address 3Fh (or Offset from 3Fh by a Multiple of 64)..................... 62

Figure 25. Standard Handshake Burst Suspend Prior to Initial Access

.........................................................................................................63

Figure 26. Standard Handshake Burst Suspend at or after Initial Ac-

Unprotect Timing Diagram ............................................................. 79

Figure 46. Latency with Boundary Crossing .................................. 80

Figure 47. Latency with Boundary Crossing

into Program/Erase Bank............................................................... 81

Figure 48. Example of Wait States Insertion.................................. 82

Figure 49. Back-to-Back Read/Write Cycle Timings...................... 83

Erase and Programming Performance . . . . . . . 84

BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 84

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 85

VBB080—80-ball Fine-Pitch Ball Grid Array (BGA) 11.5 x

9 mm Package ........................................................................ 85

VBD064—64-ball Fine-Pitch Ball Grid Array (BGA) 9 x

8 mm Package ........................................................................ 86

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 87

4

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Part Number

Am29BDS128H/Am29BDS640H

Burst Frequency

66 MHz

E8, E9

54 MHz

D8, D9

Speed Option

V_CC, V_IO= 1.65 – 1.95 V

Max Initial Synchronous Access Time, ns (T_IACC

)

56

69

Reduced Wait-state Handshaking; Even Address

Max Initial Synchronous Access Time, ns (T_IACC

Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking

Max Burst Access Time, ns (T_BACC

Max Asynchronous Access Time, ns (T_ACC

Max CE# Access Time, ns (T_CE

Max OE# Access Time, ns (T_OE

)

71

11

87.5

13.5

)

50

55

)

11

13.5

Note: Speed Options ending in “8” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous

accesses for even addresses. Speed Options ending in “9” indicate the “standard handshaking” option. See the AC

Characteristics section of this data sheet for full specifications.

BLOCK DIAGRAM

V_CC

DQ15–DQ0

V_SS

V_IO

RDY

Buffer

RDY

Erase Voltage

Generator

Input/Output

Buffers

WE#

State

Control

RESET#

WP#

Command

Register

ACC

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

CE#

OE#

Y-Decoder

Y-Gating

V_CC

Detector

Timer

Cell Matrix

X-Decoder

Burst

State

Control

Burst

Address

Counter

AVD#

CLK

Amax–A0

Note: A_max= A22 (128 Mb) or A21 (64 Mb)

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

5

D A T A S H E E T

BLOCK DIAGRAM OF SIMULTANEOUS

OPERATION CIRCUIT

V

CC

V

SS

V

IO

Bank A Address

DQ15–DQ0

Bank A

Amax–A0

X-Decoder

OE#

Bank B Address

DQ15–DQ0

Bank B

WP#

ACC

X-Decoder

Amax–A0

STATE

CONTROL

&

COMMAND

REGISTER

RESET#

WE#

DQ15–DQ0

Status

CE#

AVD#

RDY

Control

Amax–A0

DQ15–DQ0

X-Decoder

Bank C

DQ15–DQ0

Bank C Address

Amax –A0

X-Decoder

Bank D

Bank D Address

DQ15–DQ0

6

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

CONNECTION DIAGRAM

80-ball Fine-Pitch Ball Grid Array

Top View, Balls Facing Down

(Am29BDS128H only)

C8

D8

E8

F8

G8

H8

J8

K8

L8

M8

NC

A8

B8

NC

A22

NC

V_IO

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

NC

V_SS

NC

A13

A12

A14

A15

A16

NC

DQ15

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

V_CC

WE# RESET#

A21

A19

DQ5

DQ12

DQ4

C4

D4

E4

F4

G4

H4

J4

K4

RDY

ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

NC

A2

B2

V_SS

CE#

OE#

NC

J1

A1

B1

C1

D1

E1

F1

G1

H1

K1

L1

M1

NC

V_CC

CLK

WP#

AVD#

V_IO

V_SS

NC

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

7

D A T A S H E E T

64-ball Fine-Pitch Ball Grid Array

Top View, Balls Facing Down

(Am29BDS640H only)

A8

B8

C8

D8

E8

F8

G8

NC

H8

NC

V_IO

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

V_SS

A13

A12

A14

A15

A16

NC

DQ15

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

A10

A11

DQ7

DQ14

DQ13

DQ6

A5

B5

C5

D5

E5

F5

G5

H5

V_CC

WE# RESET#

A21

A19

DQ5

DQ12

DQ4

A4

B4

C4

D4

E4

F4

G4

H4

RDY

ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

V_SS

CE#

OE#

G1

A1

B1

C1

D1

E1

F1

H1

NC

V_CC

CLK

WP#

AVD#

V_IO

V_SS

NC

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory products

in FBGA packages.

8

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

INPUT/OUTPUT DESCRIPTIONS

Amax–A0

=

Address inputs

Amax = A22 (128 Mb) or A21 (64 Mb)

AVD#

=

Address Valid input. Indicates to

device that the valid address is

present on the address inputs

(Amax–A0).

DQ15–DQ0 = Data input/output

CE#

OE#

WE#

=

Chip Enable input. Asynchronous

relative to CLK for the Burst mode.

Low = for asynchronous mode,

indicates valid address; for burst

mode, causes starting address to be

latched.

=

Output Enable input. Asynchronous

relative to CLK for the Burst mode.

=

Write Enable input.

High = device ignores address inputs

V

Device Power Supply

(1.65 – 1.95 V).

RESET#

WP#

=

Hardware reset input. Low = device

resets and returns to reading array

data

CC

=

Input & Output Buffer Power Supply

(1.65 – 1.95 V).

IO

Hardware write protect input. At V ,

IL

disables program and erase functions

in the four highest and four lowest

=

Ground

SS

NC

No Connect; not connected internally

Ready output;

sectors. At V , does not protect any

IH

sectors.

RDY

ACC

=

At V , accelerates programming;

automatically places device in unlock

HH

In Synchronous Mode, indicates the

status of the Burst read.

bypass mode. At V , locks all sectors.

IL

Low = data invalid. High = data valid.

Should be at V for all other

IH

conditions.

In Asynchronous Mode, indicates the

status of the internal program and

erase function.

LOGIC SYMBOL

Low = program/erase in progress.

23 or 22

High Impedance = program/erase

completed.

Amax–A0

16

DQ15–DQ0

CLK

WP#

CLK

=

CLK is not required in asynchronous

mode. In burst mode, after the initial

word is output, subsequent active

edges of CLK increment the internal

address counter.

ACC

CE#

OE#

WE#

RDY

RESET#

AVD#

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

9

D A T A S H E E T

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following:

Am29BDS 128 VK

H

E

8

I

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

I

=

PACKAGE TYPE

VK = 80-Ball Fine-Pitch Ball Grid Array (BGA)

0.80 mm pitch, 11.5 x 9 mm package (VBB080)

VF = 80-Ball Fine-Pitch Ball Grid Array (BGA)

0.80 mm pitch, 11.5 x 9mm, Pb-free Package (VBB080)

VM = 64-Ball Fine-Pitch Ball Grid Array (BGA)

0.80 mm pitch, 8 X 9 mm package (VBD064)

V

8

9

AND HANDSHAKING OPTIONS

IO

=

V_IO= 1.8 V, reduced wait-state handshaking enabled

V_IO= 1.8 V, standard handshaking

SPEED

E

D

=

66 MHz

54 MHz

PROCESS TECHNOLOGY

0.13 µm

H

=

DENSITY

128 = 128 Mbit (8 M x 16-bit)

64 64 Mbit (4 M x 16-bit)

=

DEVICE FAMILY

Am29BDS

CMOS Flash Memory, Simultaneous Read/Write,

Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase

Valid Combinations

Burst Frequency

Order Number

Package Marking

BS128HE8V

BS128HE9V

BS128HD8V

BS128HD9V

BS128HE8VF

BS128HE9VF

BS128HD8VF

BS128HD9VF

BS640HE8V

BS640HE9V

BS640HD8V

BS640HD9V

(MHz)

Density

Am29BDS128HE8

Am29BDS128HE9

Am29BDS128HD8

Am29BDS128HD9

Am29BDS128HE8

Am29BDS128HE9

Am29BDS128HD8

Am29BDS128HD9

Am29BDS640HE8

Am29BDS640HE9

Am29BDS640HD8

Am29BDS640HD9

66

VKI

VFI

VMI

54

66

54

66

54

128 Mbit

64 Mbit

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

10

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus opera-

tions, the inputs and control levels they require, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Device Bus Operations

CLK

(See

Operation

CE#

L

OE#

L

WE#

H

Amax–0

Addr In

HIGH Z

DQ15–0 RESET# Note) AVD#

Asynchronous Read - Addresses Latched

Asynchronous Read - Addresses Steady State

Asynchronous Write

I/O

H

L

X

L

H

L

H

L

I/O

Synchronous Write

L

H

L

I/O

Standby (CE#)

H

X

HIGH Z

X

Hardware Reset

X

Burst Read Operations

Load Starting Burst Address

L

X

L

H

Addr In

HIGH Z

X

H

L

Advance Burst to next address with

appropriate Data presented on the Data Bus

Burst

Data Out

H

X

Terminate current Burst read cycle

H

X

HIGH Z

Terminate current Burst read cycle via

RESET#

X

Terminate current Burst read cycle and start

new Burst read cycle

L

X

H

HIGH Z

I/O

H

Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.

Note: Default active edge of CLK is the rising edge.

The internal state machine is set for reading array data

in asynchronous mode upon device power-up, or after

a hardware reset. This ensures that no spurious alter-

ation of the memory content occurs during the power

transition.

Requirements for Asynchronous Read

Operation (Non-Burst)

To read data from the memory array, the system must

first assert a valid address on Amax–A0, while driving

AVD# and CE# to V . WE# should remain at V . The

IL

IH

rising edge of AVD# latches the address. The data will

appear on DQ15–DQ0. Since the memory array is

divided into four banks, each bank remains enabled for

read access until the command register contents are

altered.

Requirements for Synchronous (Burst)

Read Operation

The device is capable of continuous sequential burst

operation and linear burst operation of a preset length.

When the device first powers up, it is enabled for asyn-

chronous read operation.

Address access time (t

) is equal to the delay from

ACC

stable addresses to valid output data. The chip enable

Prior to entering burst mode, the system should deter-

mine how many wait states are desired for the initial

access time (t ) is the delay from the stable

CE

addresses and stable CE# to valid data at the outputs.

word (t

) of each burst access, what mode of burst

The output enable access time (t ) is the delay from

IACC

OE

operation is desired, which edge of the clock will be the

the falling edge of OE# to valid data at the output.

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

11

D A T A S H E E T

active clock edge, and how the RDY signal will transi-

8-, 16-, and 32-Word Linear Burst with Wrap Around

tion with valid data. The system would then write the

configuration register command sequence. See “Set

Configuration Register Command Sequence” section

on page 33 and “Command Definitions” section on

page 33 for further details.

The remaining three modes are of the linear wrap

around design, in which a fixed number of words are

read from consecutive addresses. In each of these

modes, the burst addresses read are determined by

the group within which the starting address falls. The

groups are sized according to the number of words

read in a single burst sequence for a given mode (see

Table 2.)

Once the system has written the “Set Configuration

Register” command sequence, the device is enabled

for synchronous reads only.

The initial word is output t

the first CLK cycle. Subsequent words are output t

after the active edge of

IACC

Table 2. Burst Address Groups

BACC

after the active edge of each successive clock cycle,

which automatically increments the internal address

counter. Note that the device has a fixed internal

address boundary that occurs every 64 words, starting

at address 00003Fh. During the time the device is out-

putting data at this fixed internal address boundary

(address 00003Fh, 00007Fh, 0000BFh, etc.), a two

cycle latency occurs before data appears for the next

address (address 000040h, 000080h, 0000C0h, etc.).

The RDY output indicates this condition to the system

by pulsing low. For standard handshaking devices,

there is no two cycle latency between 3Fh and 40h (or

offset from these values by a multiple of 64) if the

latched address was 3Eh or 3Fh or offset from these

values by a multiple of 64). See Figure 46, “Latency

with Boundary Crossing,” on page 80.

Mode

8-word

16-word

32-word

Group Size Group Address Ranges

8 words

16 words

32 words

0-7h, 8-Fh, 10-17h,...

0-Fh, 10-1Fh, 20-2Fh,...

00-1Fh, 20-3Fh, 40-5Fh,...

As an example: if the starting address in the 8-word

mode is 39h, the address range to be read would be

38-3Fh, and the burst sequence would be

39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence

begins with the starting address written to the device,

but wraps back to the first address in the selected

group. In a similar fashion, the 16-word and 32-word

Linear Wrap modes begin their burst sequence on the

starting address written to the device, and then wrap

back to the first address in the selected address group.

Note that in these three burst read modes the

address pointer does not cross the boundary that

occurs every 64 words; thus, no wait states are

inserted (except during the initial access).

For reduced wait-state handshaking devices, if the

address latched is 3Eh or 3Fh (or offset from these

values by a multiple of 64) two additional cycle latency

occurs prior to the initial access and the two cycle

latency between 3Fh and 40h (or offset from these

values by a multiple of 64) will not occur.

The RDY pin indicates when data is valid on the bus.

The devices can wrap through a maximum of 128

words of data (8 words up to 16 times, 16 words up to

8 times, or 32 words up to 4 times) before requiring a

new synchronous access (latching of a new address).

The device will continue to output sequential burst

data, wrapping around to address 000000h after it

reaches the highest addressable memory location,

until the system drives CE# high, RESET# low, or

AVD# low in conjunction with a new address. See

Table 1, “Device Bus Operations,” on page 11.

Burst Suspend/Resume

The Burst Suspend/Resume feature allows the system

to temporarily suspend a synchronous burst operation

during the initial access (before data is available) or

after the device is outputting data. When the burst

operation is suspended, any previously latched internal

data and the current state are retained.

If the host system crosses the bank boundary while

reading in burst mode, and the device is not program-

ming or erasing, a two-cycle latency will occur as

described above in the subsequent bank. If the host

system crosses the bank boundary while the device is

programming or erasing, the device will provide read

status information. The clock will be ignored. After the

host has completed status reads, or the device has

completed the program or erase operation, the host

can restart a burst operation using a new address and

AVD# pulse.

Burst Suspend requires CE# to be asserted, WE#

de-asserted, and the initial address latched by AVD# or

the CLK edge. Burst Suspend occurs when OE# is

de-asserted. See Figure 21, “Reduced Wait-state

Handshake Burst Suspend/Resume at an Even

Address,” on page 61, Figure 22, “Reduced Wait-state

Handshake Burst Suspend/Resume at an Odd

Address,” on page 61, Figure 23, “Reduced Wait-state

Handshake Burst Suspend/Resume at Address 3Eh

(or Offset from 3Eh),” on page 62, Figure 24, “Reduced

Wait-state Handshake Burst Suspend/Resume at

If the clock frequency is less than 6 MHz during a burst

mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

12

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Address 3Fh (or Offset from 3Fh by a Multiple of 64),”

Simultaneous Read/Write Operations with

Zero Latency

on page 62, Figure 25, “Standard Handshake Burst

Suspend Prior to Initial Access,” on page 63, Figure 26,

“Standard Handshake Burst Suspend at or after Initial

Access,” on page 63, Figure 27, “Standard Handshake

Burst Suspend at Address 3Fh (Starting Address 3Dh

or Earlier),” on page 64, Figure 28, “Standard Hand-

shake Burst Suspend at Address 3Eh/3Fh (Without a

Valid Initial Access),” on page 64, and Figure 29, “Stan-

dard Handshake Burst Suspend at Address 3Eh/3Fh

(with 1 Access CLK),” on page 65.

This device is capable of reading data from one bank of

memory while programming or erasing in another bank

of memory. An erase operation may also be suspended

to read from or program to another location within the

same bank (except the sector being erased).

Figure 49, “Back-to-Back Read/Write Cycle Timings,”

on page 83 shows how read and write cycles may be

initiated for simultaneous operation with zero latency.

Refer to the DC Characteristics table for

read-while-program and read-while-erase current

specifications.

Burst plus Burst Suspend should not last longer than

t

without re-latching an address or crossing an

RCC

address boundary. To resume the burst access, OE#

must be re-asserted. The next active CLK edge will

resume the burst sequence where it had been sus-

pended. See Figure 30, “Read Cycle for Continuous

Suspend,” on page 65.

Writing Commands/Command Sequences

The device has the capability of performing an asyn-

chronous or synchronous write operation. While the

device is configured in Asynchronous read it is able to

perform Asynchronous write operations only. CLK is

ignored in the Asynchronous programming mode.

When in the Synchronous read mode configuration, the

device is able to perform both Asynchronous and Syn-

chronous write operations. CLK and WE# address

latch is supported in the Synchronous programming

mode. During a synchronous write operation, to write a

command or command sequence (which includes pro-

gramming data to the device and erasing sectors of

The RDY pin is only controlled by CE#. RDY will remain

active and is not placed into a high-impedance state

when OE# is de-asserted.

Configuration Register

The device uses a configuration register to set the

various burst parameters: number of wait states, burst

read mode, active clock edge, RDY configuration, and

synchronous mode active.

memory), the system must drive AVD# and CE# to V ,

IL

and OE# to V when providing an address to the

IH

Reduced Wait-state Handshaking Option

device, and drive WE# and CE# to V , and OE# to V

IL

IH

The device can be equipped with a reduced wait-state

handshaking feature that allows the host system to

simply monitor the RDY signal from the device to deter-

mine when the initial word of burst data is ready to be

read. The host system should use the programmable

wait state configuration to set the number of wait states

for optimal burst mode operation. The initial word of

burst data is indicated by the rising edge of RDY after

OE# goes low.

when writing commands or data. During an asynchro-

nous write operation, the system must drive CE# and

WE# to V and OE# to V when providing an address,

IL

IH

command, and data. Addresses are latched on the last

falling edge of WE# or CE#, while data is latched on the

1st rising edge of WE# or CE#. The asynchronous and

synchronous programing operation is independent of

the Set Device Read Mode bit in the Configuration

Register (see Table 18, “Configuration Register,” on

page 36).

The presence of the reduced wait-state handshaking

feature may be verified by writing the autoselect

command sequence to the device. See “Autoselect

Command Sequence” for details.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are

required to program a word, instead of four.

For optimal burst mode performance on devices

without the reduced wait-state handshaking option, the

host system must set the appropriate number of wait

states in the flash device depending on clock frequency

and the presence of a boundary crossing. See “Set

Configuration Register Command Sequence” section

on page 33 section for more information. The device

will automatically delay RDY and data by one additional

clock cycle when the starting address is odd.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 12, “Am29BDS128H

Sector Address Table,” on page 27 indicates the

address space that each sector occupies. The device

address space is divided into four banks: Banks B and

C contain only 32 Kword sectors, while Banks A and D

contain both 4 Kword boot sectors in addition to 32

Kword sectors. A “bank address” is the address bits

required to uniquely select a bank. Similarly, a “sector

address” is the address bits required to uniquely select

a sector.

The autoselect function allows the host system to

determine whether the flash device is enabled for

reduced wait-state handshaking. See the “Autoselect

Command Sequence” section for more information.

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

13

D A T A S H E E T

I

in the “DC Characteristics” section on page 54

ming algorithm. However, the autoselect codes can

also be accessed in-system through the command

register.

CC2

represents the active current specification for the write

mode. The AC Characteristics section contains timing

specification tables and timing diagrams for write oper-

ations.

When using programming equipment, the autoselect

mode requires V on address pin A9. Address pins

ID

must be as shown in Table 3, “Autoselect Codes (High

Voltage Method),” on page 15. In addition, when verify-

ing sector protection, the sector address must appear

on the appropriate highest order address bits (see

Table 4, “Am29BDS128H Boot Sector/Sector Block

Addresses for Protection/Unprotection,” on page 16).

Table 3 shows the remaining address bits that are

don’t care. When all necessary bits have been set as

required, the programming equipment may then read

the corresponding identifier code on DQ15–DQ0.

However, the autoselect codes can also be accessed

in-system through the command register, for instances

when the device is erased or programmed in a system

without access to high voltage on the A9 pin. The com-

mand sequence is illustrated in Table 20, “Memory

Array Command Definitions,” on page 46. Note that if a

Bank Address (BA) is asserted during the third write

cycle of the autoselect command, the host system can

read autoselect data that bank and then immediately

read array data from the other bank, without exiting the

autoselect mode.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. ACC is primarily intended to

allow faster manufacturing throughput at the factory.

If the system asserts V on this input, the device auto-

HH

matically enters the aforementioned Unlock Bypass

mode and uses the higher voltage on the input to

reduce the time required for program operations. The

system would use a two-cycle program command

sequence as required by the Unlock Bypass mode.

Removing V from the ACC input returns the device

HH

to normal operation. Note that sectors must be

unlocked prior to raising ACC to V . Note that the

HH

ACC pin must not be at V for operations other than

HH

accelerated programming, or device damage may

result. In addition, the ACC pin must not be left floating

or unconnected; inconsistent behavior of the device

may result.

When at V , ACC locks all sectors. ACC should be at

IL

V

for all other conditions.

IH

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 20, “Memory

Array Command Definitions,” on page 46. This method

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output from the internal regis-

ter (which is separate from the memory array) on

DQ15–DQ0. This mode is primarily intended for pro-

gramming equipment to automatically match a device

to be programmed with its corresponding program-

does not require V . Autoselect mode may only be en-

ID

tered and used when in the asynchronous read mode.

Refer to the “Autoselect Command Sequence” section

on page 36 for more information.

14

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Table 3. Autoselect Codes (High Voltage Method)

Amax A11

to to

A5

to

DQ15

Description

CE# OE# WE# RESET# A12 A10 A9 A8 A7 A6 A4 A3 A2 A1 A0

to DQ0

Manufacturer ID:

AMD

V_ID

L

H

X

L

X

L

H

L

0001h

227Eh

Read Cycle 1

Read Cycle 2

2218h (128 Mb)

221Eh (64 Mb)

H

X

2200h (128 Mb)

2201h (64 Mb)

Read Cycle 3

H

L

H

L

H

L

Sector Protection

Verification

0001h (protected),

0000h (unprotected)

SA

DQ15 - DQ8 = 0

DQ7 - Factory Lock Bit

1 = Locked, 0 = Not Locked

DQ6 -Customer Lock Bit

1 = Locked, 0 = Not Locked

DQ5 = Handshake Bit

1 = Reduced wait-state

Handshake, 0 = Standard

Handshake

V_ID

Indicator Bits

L

H

X

L

X

L

H

L

DQ4 - DQ0 = 0

Hardware Sector

Group Protection

0001h (protected),

0000h (unprotected)

V_ID

L

H

SA

X

Legend: L = Logic Low = V , H = Logic High = V , BA = Bank Address,

IL

IH

SA = Sector Address, X = Don’t care.

Notes:

1. The autoselect codes may also be accessed in-system via command sequences.

2. PPB Protection Status is shown on the data bus

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

15

D A T A S H E E T

Table 4. Am29BDS128H Boot Sector/Sector Block

Sector/

Addresses for Protection/Unprotection

Sector

A22–A12

Sector Block Size

SA131-SA134

SA135-SA138

SA139-SA142

SA143-SA146

SA147-SA150

SA151–SA154

SA155–SA158

SA159–SA162

SA163–SA166

SA167–SA170

SA171–SA174

SA175–SA178

SA179–SA182

SA183–SA186

SA187–SA190

SA191–SA194

SA195–SA198

SA199–SA202

SA203–SA206

SA207–SA210

SA211–SA214

SA215–SA218

SA219–SA222

SA223–SA226

SA227–SA230

SA231–SA234

SA235–SA238

SA239–SA242

SA243–SA246

SA247–SA250

SA251–SA254

SA255–SA258

SA259

011111XXXXX

100000XXXXX

100001XXXXX

100010XXXXX

100011XXXXX

100100XXXXX

100101XXXXX

100110XXXXX

100111XXXXX

101000XXXXX

101001XXXXX

101010XXXXX

101011XXXXX

101100XXXXX

101101XXXXX

101110XXXXX

101111XXXXX

110000XXXXX

110001XXXXX

110010XXXXX

110011XXXXX

110100XXXXX

110101XXXXX

110110XXXXX

110111XXXXX

111000XXXXX

111001XXXXX

111010XXXXX

111011XXXXX

111100XXXXX

111101XXXXX

111110XXXXX

11111100XXX

11111101XXX

11111110XXX

11111111000

11111111001

11111111010

11111111011

11111111100

11111111101

11111111110

11111111111

128 (4x32) Kwords

32 Kwords

Sector/

Sector Block Size

Sector

SA0

A22–A12

00000000000

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

00000001XXX

00000010XXX

00000011XXX

000001XXXXX

000010XXXXX

000011XXXXX

000100XXXXX

000101XXXXX

000110XXXXX

000111XXXXX

001000XXXXX

001001XXXXX

001010XXXXX

001011XXXXX

001100XXXXX

001101XXXXX

001110XXXXX

001111XXXXX

010000XXXXX

010001XXXXX

010010XXXXX

010011XXXXX

010100XXXXX

010101XXXXX

010110XXXXX

010111XXXXX

011000XXXXX

011001XXXXX

011010XXXXX

011011XXXXX

011100XXXXX

011101XXXXX

011110XXXXX

4 Kwords

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11–SA14

SA15–SA18

SA19–SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51–SA54

SA55–SA58

SA59–SA62

SA63–SA66

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

128 (4x32) Kwords

SA260

32 Kwords

SA261

32 Kwords

SA262

4 Kwords

SA263

4 Kwords

SA264

4 Kwords

SA265

4 Kwords

SA266

4 Kwords

SA267

4 Kwords

SA268

4 Kwords

SA269

4 Kwords

16

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Table 5. Am29BDS640H Boot Sector/Sector Block

Sector/

Addresses for Protection/Unprotection

Sector

SA135

SA136

SA137

SA138

SA139

SA140

SA141

A21–A12

Sector Block Size

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

4 Kwords

Sector/

Sector

SA0

A21–A12

Sector Block Size

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

1111100XXX

1111101XXX

1111110XXX

1111111000

4 Kwords

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

Sector/Sector Block Protection and Un-

protection

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

The hardware sector protection feature disables both

programming and erase operations in any sector. The

hardware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11–SA14

SA15–SA18

SA19–SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51–SA54

SA55–SA58

SA59–SA62

SA63–SA66

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

SA131

128 (4x32) Kwords

32 Kwords

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table 4,

“Am29BDS128H Boot Sector/Sector Block Addresses

for Protection/Unprotection,” on page 16

Sector Protection

The Am29BDSxxxH family features several levels of

sector protection, which can disable both the program

and erase operations in certain sectors or sector

groups:

Persistent Sector Protection

A command sector protection method that replaces

the old 12 V controlled protection method.

Password Sector Protection

A highly sophisticated protection method that requires

a password before changes to certain sectors or sec-

tor groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase

operations in the outermost sectors.

The WP# Hardware Protection feature is always avail-

able, independent of the software managed protection

method chosen.

Selecting a Sector Protection Mode

All parts default to operate in the Persistent Sector

Protection mode. The customer must then choose if

the Persistent or Password Protection method is most

desirable. There are two one-time programmable

non-volatile bits that define which sector protection

method will be used. If the customer decides to con-

tinue using the Persistent Sector Protection method,

they must set the Persistent Sector Protection Mode

SA132

32 Kwords

SA133

32 Kwords

SA134

4 Kwords

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

17

D A T A S H E E T

Locking Bit. This will permanently set the part to op-

dividual PPBs are programmable. It is the responsibil-

ity of the user to perform the preprogramming

operation. Otherwise, an already erased sector PPBs

has the potential of being over-erased. There is no

hardware mechanism to prevent sector PPBs

over-erasure.

erate only using Persistent Sector Protection. If the

customer decides to use the password method, they

must set the Password Mode Locking Bit. This will

permanently set the part to operate only using pass-

word sector protection.

It is important to remember that setting either the Per-

sistent Sector Protection Mode Locking Bit or the

Password Mode Locking Bit permanently selects the

protection mode. It is not possible to switch between

the two methods once a locking bit has been set. It is

important that one mode is explicitly selected

when the device is first programmed, rather than

relying on the default mode alone. This is so that it

is not possible for a system program or virus to later

set the Password Mode Locking Bit, which would

cause an unexpected shift from the default Persistent

Sector Protection Mode into the Password Protection

Mode.

Persistent Protection Bit Lock (PPB Lock)

A global volatile bit. When set to “1”, the PPBs cannot

be changed. When cleared (“0”), the PPBs are

changeable. There is only one PPB Lock bit per de-

vice. The PPB Lock is cleared after power-up or hard-

ware reset. There is no command sequence to unlock

the PPB Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector.

After power-up or hardware reset, the contents of all

DYBs is “0”. Each DYB is individually modifiable

through the DYB Write Command.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at the factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

When the parts are first shipped, the PPBs are

cleared. The DYBs and PPB Lock are defaulted to

power up in the cleared state – meaning the PPBs are

changeable.

When the device is first powered on the DYBs power

up cleared (sectors not protected). The Protection

State for each sector is determined by the logical OR

of the PPB and the DYB related to that sector. For the

sectors that have the PPBs cleared, the DYBs control

whether or not the sector is protected or unprotected.

By issuing the DYB Write command sequences, the

DYBs will be set or cleared, thus placing each sector in

the protected or unprotected state. These are the

so-called Dynamic Locked or Unlocked states. They

are called dynamic states because it is very easy to

switch back and forth between the protected and un-

protected conditions. This allows software to easily

protect sectors against inadvertent changes yet does

not prevent the easy removal of protection when

changes are needed. The DYBs maybe set or cleared

as often as needed.

It is possible to determine whether a sector is pro-

tected or unprotected. See “Autoselect Command Se-

quence” section on page 36 for details.

Persistent Sector Protection

The Persistent Sector Protection method replaces the

old 12 V controlled protection method while at the

same time enhancing flexibility by providing three dif-

ferent sector protection states:

■ Persistently Locked—A sector is protected and

cannot be changed.

■ Dynamically Locked—The sector is protected and

can be changed by a simple command

■ Unlocked—The sector is unprotected and can be

changed by a simple command

In order to achieve these states, three types of “bits”

are going to be used:

The PPBs allow for a more static, and difficult to

change, level of protection. The PPBs retain their state

across power cycles because they are Non-Volatile.

Individual PPBs are set with a command but must all

be cleared as a group through a complex sequence of

program and erasing commands. The PPBs are also

limited to 100 erase cycles.

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is as-

signed to a maximum four sectors (“Am29BDS128H

Boot Sector/Sector Block Addresses for Protec-

tion/Unprotection” section on page 16). All 4 Kbyte

boot-block sectors have individual sector Persistent

Protection Bits (PPBs) for greater flexibility. Each PPB

is individually modifiable through the PPB Program

Command.

The PBB Lock bit adds an additional level of protec-

tion. Once all PPBs are programmed to the desired

settings, the PPB Lock may be set to “1”. Setting the

PPB Lock disables all program and erase commands

to the Non-Volatile PPBs. In effect, the PPB Lock Bit

locks the PPBs into their current state. The only way to

clear the PPB Lock is to go through a power cycle.

Note: If a PPB requires erasure, all of the sector PPBs

must first be preprogrammed prior to PPB erasing. All

PPBs erase in parallel, unlike programming where in-

18

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

System boot code can determine if any changes to the

In summary, if the PPB is set, and the PPB lock is set,

the sector is protected and the protection can not be

removed until the next power cycle clears the PPB

lock. If the PPB is cleared, the sector can be dynami-

cally locked or unlocked. The DYB then controls

whether or not the sector is protected or unprotected.

PPB are needed e.g. to allow new system code to be

downloaded. If no changes are needed then the boot

code can set the PPB Lock to disable any further

changes to the PPBs during system operation.

The WP# write protect pin adds a final level of hard-

ware protection to the four highest and four lowest 4

Kbyte sectors. When this pin is low it is not possible to

change the contents of these four sectors. These sec-

tors generally hold system boot code. So, the WP# pin

can prevent any changes to the boot code that could

override the choices made while setting up sector pro-

tection during system initialization.

If the user attempts to program or erase a protected

sector, the device ignores the command and returns to

read mode. A program command to a protected sector

enables status polling for approximately t

before

PSP

the device returns to read mode without having modi-

fied the contents of the protected sector. An erase

command to a protected sector enables status polling

for approximately t

to read mode without having erased the protected sec-

tor.

after which the device returns

SEA

It is possible to have sectors that have been persis-

tently locked, and sectors that are left in the dynamic

state. The sectors in the dynamic state are all unpro-

tected. If there is a need to protect some of them, a

simple DYB Write command sequence is all that is

necessary. The DYB write command for the dynamic

sectors switch the DYBs to signify protected and un-

protected, respectively. If there is a need to change the

status of the persistently locked sectors, a few more

steps are required. First, the PPB Lock bit must be dis-

abled by either putting the device through a power-cy-

cle, or hardware reset. The PPBs can then be

changed to reflect the desired settings. Setting the

PPB lock bit once again will lock the PPBs, and the de-

vice operates normally again.

The programming of the DYB, PPB, and PPB lock for a

given sector can be verified by writing a

DYB/PPB/PPB lock verify command to the device.

Persistent Sector Protection Mode

Locking Bit

Like the password mode locking bit, a Persistent Sec-

tor Protection mode locking bit exists to guarantee that

the device remain in software sector protection. Once

set, the Persistent Sector Protection locking bit pre-

vents programming of the password protection mode

locking bit. This guarantees that a hacker could not

place the device in password protection mode.

Note: to achieve the best protection, it’s recommended

to execute the PPB lock bit set command early in the

boot code, and protect the boot code by holding WP#

Password Protection Mode

= V .

IL

The Password Sector Protection Mode method allows

an even higher level of security than the Persistent

Sector Protection Mode. There are two main differ-

ences between the Persistent Sector Protection and

the Password Sector Protection Mode:

Table 6. Sector Protection Schemes

PPB

■ When the device is first powered on, or comes out

of a reset cycle, the PPB Lock bit is set to the

locked state, rather than cleared to the unlocked

state.

DYB

PPB

Lock

Sector State

Unprotected—PPB and DYB are

changeable

0

■ The only means to clear the PPB Lock bit is by writ-

ing a unique 64-bit Password to the device.

Unprotected—PPB not

changeable, DYB is changeable

0

1

The Password Sector Protection method is otherwise

identical to the Persistent Sector Protection method.

0

1

0

1

0

1

0

1

0

1

Protected—PPB and DYB are

changeable

A 64-bit password is the only additional tool utilized in

this method.

The password is stored in a one-time programmable

(OTP) region of the flash memory. Once the Password

Mode Locking Bit is set, the password is permanently

set with no means to read, program, or erase it. The

password is used to clear the PPB Lock bit. The Pass-

word Unlock command must be written to the flash,

along with a password. The flash device internally

compares the given password with the pre-pro-

Protected—PPB not

changeable, DYB is changeable

Table 6 contains all possible combinations of the DYB,

PPB, and PPB lock relating to the status of the sector.

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

19

D A T A S H E E T

grammed password. If they match, the PPB Lock bit is

Password Verify command from reading the contents

of the password on the pins of the device.

cleared, and the PPBs can be altered. If they do not

match, the flash device does nothing. There is a

built-in 2 µs delay for each “password check.” This

delay is intended to thwart any efforts to run a program

that tries all possible combinations in order to crack

the password.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile

bit that reflects the state of the Password Mode Lock-

ing Bit after power-up reset. If the Password Mode

Lock Bit is also set, after a hardware reset (RESET#

asserted) or a power-up reset the ONLY means for

clearing the PPB Lock Bit in Password Protection

Mode is to issue the Password Unlock command. Suc-

cessful execution of the Password Unlock command

clears the PPB Lock Bit, allowing for sector PPBs

modifications. Asserting RESET#, taking the device

through a power-on reset, or issuing the PPB Lock Bit

Set command sets the PPB Lock Bit to a “1”.

Password and Password Mode Locking Bit

In order to select the Password sector protection

scheme, the customer must first program the pass-

word. It is recommended that the password be

somehow correlated to the unique Electronic Serial

Number (ESN) of the particular flash device. Each ESN

is different for every flash device; therefore each pass-

word should be different for every flash device. While

programming in the password region, the customer

may perform Password Verify operations.

If the Password Mode Locking Bit is not set, including

Persistent Protection Mode, the PPB Lock Bit is

cleared after power-up or hardware reset. The PPB

Lock Bit can be set by issuing the PPB Lock Bit Set

command. Once set the only means for clearing the

PPB Lock Bit is by issuing a hardware or power-up re-

set. The Password Unlock command is ignored in Per-

sistent Protection Mode.

Once the desired password is programmed in, the

customer must then set the Password Mode Locking

Bit. This operation achieves two objectives:

1. It permanently sets the device to operate using the

Password Protection Mode. It is not possible to re-

verse this function.

2. It also disables all further commands to the pass-

word region. All program, and read operations are

ignored.

High Voltage Sector Protection

Sector protection and unprotection may also be imple-

mented using programming equipment. The procedure

Both of these objectives are important, and if not care-

fully considered, may lead to unrecoverable errors.

The user must be sure that the Password Protection

method is desired when setting the Password Mode

Locking Bit. More importantly, the user must be sure

that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations

are disabled, there is no means to verify what the

password is afterwards. If the password is lost after

setting the Password Mode Locking Bit, there will be

no way to clear the PPB Lock bit.

requires high voltage (V ) to be placed on the

ID

RESET# pin. Refer to Figure 2, “In-System Sector Pro-

tection/ Sector Unprotection Algorithms,” on page 22

for details on this procedure. Note that for sector unpro-

tect, all unprotected sectors must be first protected

prior to the first sector write cycle. Once the Password

Mode Locking bit or Persistent Protection Locking bit

are set, the high voltage sector protect/unprotect capa-

bility is disabled.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The Password Mode Locking Bit, once set, prevents

reading the 64-bit password on the DQ bus and further

password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit

is programmed, the Persistent Sector Protection Lock-

ing Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

The device enters the CMOS standby mode when the

CE# and RESET# inputs are both held at V

0.2 V.

CC

The device requires standard access time (t ) for read

access, before it is ready to read data.

CE

64-bit Password

The 64-bit Password is located in its own memory

space and is accessible through the use of the Pass-

word Program and Verify commands (see “Password

Program Command” section on page 40 and “Pass-

word Verify Command” section on page 40). The

password function works in conjunction with the Pass-

word Mode Locking Bit, which when set, prevents the

If the device is deselected during erasure or program-

ming, the device draws active current until the opera-

tion is completed.

I

in the “DC Characteristics” section on page 54

CC3

represents the standby current specification.

20

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Embedded Algorithms) before the device is ready to

Automatic Sleep Mode

read data again. If RESET# is asserted when a

program or erase operation is not executing, the reset

The automatic sleep mode minimizes Flash device

energy consumption. While in asynchronous mode, the

device automatically enables this mode when

operation is completed within a time of t

(not

READY

during Embedded Algorithms). The system can read

data t after RESET# returns to V .

addresses remain stable for t

+ 60 ns. The auto-

ACC

RH

IH

matic sleep mode is independent of the CE#, WE#, and

OE# control signals. Standard address access timings

provide new data when addresses are changed. While

in sleep mode, output data is latched and always avail-

able to the system. While in synchronous mode, the

device automatically enables this mode when either the

Refer to the “AC Characteristics” section on page 68 for

RESET# parameters and to Figure 33, “Reset Tim-

ings,” on page 68 for the timing diagram.

Output Disable Mode

When the OE# input is at V , output from the device is

first active CLK level is greater than t

or the CLK

IH

ACC

disabled. The outputs are placed in the high imped-

ance state.

runs slower than 5 MHz. Note that a new burst opera-

tion is required to provide new data.

I

in the “DC Characteristics” section on page 54

Figure 1. Temporary Sector Unprotect Operation

CC6

represents the automatic sleep mode current specifica-

tion.

START

RESET#: Hardware Reset Input

The RESET# input provides a hardware method of

resetting the device to reading array data. When

RESET# = V_ID

(Note 1)

RESET# is driven low for at least a period of t , the

RP

device immediately terminates any operation in

progress, tristates all outputs, resets the configuration

register, and ignores all read/write commands for the

duration of the RESET# pulse. The device also resets

the internal state machine to reading array data. The

operation that was interrupted should be reinitiated

once the device is ready to accept another command

sequence, to ensure data integrity.

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V

0.2 V, the device

). If RESET# is held

SS

draws CMOS standby current (I

CC4

at V but not within V

0.2 V, the standby current will

IL

SS

be greater.

Notes:

RESET# may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

1. All protected sectors unprotected (If WP# = V_IL,

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once

again.

If RESET# is asserted during a program or erase oper-

ation, the device requires a time of t

(during

READY

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

21

D A T A S H E E T

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

PLSCNT = 1

RESET# = V_ID

Wait 1 ms

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

Yes

Set up first sector

address

A7–A0 =

00000010

Sector Unprotect:

Write 60h to sector

address with

A7:A0 =

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

01000010

Reset

PLSCNT = 1

Increment

PLSCNT

with A7–A0 =

00000010

Wait 1.5 ms

Verify Sector

Unprotect: Write

40h to sector

address with

Read from

sector address

with A7–A0 =

00000010

Increment

PLSCNT

A7–A0 =

00000010

No

PLSCNT

= 25?

Read from

sector address

Data = 01h?

Yes

with A7–A0 =

00000010

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Unprotect

Algorithm

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms

22

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

can be programmed and locked only once. Note that

SecSi™ (Secured Silicon) Sector

Flash Memory Region

the accelerated programming (ACC) and unlock by-

pass functions are not available when programming

the SecSi Sector.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN) The 128-word SecSi sector is divided into 64

factory-lockable words that can be programmed and

locked by the customer. The SecSi sector is located at

addresses 000000h-00007Fh in both Persistent Pro-

tection mode and Password Protection mode. It uses

indicator bits (DQ6, DQ7) to indicate the fac-

tory-locked and customer-locked status of the part.

The Customer-lockable SecSi Sector area can be pro-

tected using one of the following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V or V . This

IH

ID

allows in-system protection of the SecSi Sector Re-

gion without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi™ Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the boot sectors. This

mode of operation continues until the system issues

the Exit SecSi Sector command sequence, or until

power is removed from the device. On power-up, or

following a hardware reset, the device reverts to send-

ing commands to the normal address space.

■ Write the three-cycle Enter SecSi Sector Secure

Region command sequence, and then use the alter-

nate method of sector protection described in the

High Voltage Sector Protection section.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

Factory-Locked Area (64 words)

The factory-locked area of the SecSi Sector

(000000h-00003Fh) is locked when the part is

shipped, whether or not the area was programmed at

the factory. The SecSi Sector Factory-locked Indicator

Bit (DQ7) is permanently set to a “1”. AMD offers the

ExpressFlash service to program the factory-locked

area with a random ESN, a customer-defined code, or

any combination of the two. Because only AMD can

program and protect the factory-locked area, this

method ensures the security of the ESN once the

product is shipped to the field. Contact an AMD repre-

sentative for details on using the AMD ExpressFlash

service.

SecSi Sector Protection Bits

The SecSi Sector Protection Bits prevent program-

ming of the SecSi Sector memory area. Once set, the

SecSi Sector memory area contents are non-modifi-

able.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 20, “Memory

Array Command Definitions,” on page 46 for command

definitions).

TM

Table 7. SecSi Sector Addresses

Sector Size

Address Range

The device offers two types of data protection at the

sector level:

Am29BDS128H/

Am29BDS640H

128 words

000000h–00007Fh

■ The PPB and DYB associated command se-

quences disables or re-enables both program and

erase operations in any sector or sector group.

Factory-Locked Area

64 words

000000h–00003Fh

000040h–00007Fh

Customer-Lockable Area

Customer-Lockable Area (64 words)

■ When WP# is at V , the four outermost sectors are

IL

locked.

The customer-lockable area of the SecSi Sector

(000040h-00007Fh) is shipped unprotected, which al-

lows the customer to program and optionally lock the

area as appropriate for the application. The SecSi

Sector Customer-locked Indicator Bit (DQ6) is shipped

as “0” and can be permanently locked to “1” by issuing

the SecSi Protection Bit Program Command. The

SecSi Sector can be read any number of times, but

■ When ACC is at V , all sectors are locked.

IL

The following hardware data protection measures

prevent accidental erasure or programming, which

might otherwise be caused by spurious system level

signals during V

tions, or from system noise.

power-up and power-down transi-

CC

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

23

D A T A S H E E T

CE# and WE# must be a logical zero while OE# is a

Write Protect (WP#)

logical one.

The Write Protect feature provides a hardware method

of protecting the four outermost sectors. This function

is provided by the WP# pin and overrides the previ-

ously discussed Sector Protection/Unprotection

method.

Power-Up Write Inhibit

If WE# = CE# = RESET# = V and OE# = V during

IL

IH

power up, the device does not accept commands on

the rising edge of WE#. The internal state machine is

automatically reset to the read mode on power-up.

If the system asserts V on the WP# pin, the device

IL

disables program and erase functions in the eight “out-

ermost” 4 Kword boot sectors.

COMMON FLASH MEMORY INTERFACE

(CFI)

If the system asserts V on the WP# pin, the device

IH

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-indepen-

dent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families.

Flash vendors can standardize their existing interfaces

for long-term compatibility.

reverts to whether the boot sectors were last set to be

protected or unprotected. That is, sector protection or

unprotection for these sectors depends on whether

they were last protected or unprotected using the

method described in “PPB Program Command” sec-

tion on page 43.

Note that the WP# pin must not be left floating or un-

connected; inconsistent behavior of the device may re-

sult.

This device enters the CFI Query mode when the

system writes the CFI Query command, 98h, to

address 55h any time the device is ready to read array

data. The system can read CFI information at the

addresses given in Tables 8-11. To terminate reading

CFI data, the system must write the reset command.

Low V Write Inhibit

CC

When V

is less than V

, the device does not

LKO

CC

accept any write cycles. This protects data during V

CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets to reading array data. Subsequent writes

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 8-11. The

system must write the reset command to return the

device to the autoselect mode.

are ignored until V is greater than V

. The system

CC

LKO

must provide the proper signals to the control inputs to

prevent unintentional writes when V is greater than

CC

V

.

LKO

Write Pulse “Glitch” Protection

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the AMD

site at the following URL:

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

http://www.amd.com/flash/cfi.

Write cycles are inhibited by holding any one of OE# =

Alternatively, contact an AMD representative for copies

V , CE# = V or WE# = V . To initiate a write cycle,

IL

IH

Table 8. CFI Query Identification String

Description

Addresses

Data

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

Primary OEM Command Set

13h

14h

0002h

0000h

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

24

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Table 9. System Interface String

Addresses

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0017h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0019h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0004h

0000h

0009h

0000h

0004h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V

_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 10. Device Geometry Definition

Description

Addresses

Data

Device Size = 2^Nbyte

BDS128H = 0018h; BDS640H = 0017h

27h

001xh

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

00xDh

0000h

0001h

Erase Block Region 2 Information

Address 31h: BDS128H = 00FDh; BDS640H = 007Dh

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

Erase Block Region 4 Information

39h

3Ah

3Bh

3Ch

0000h

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

25

D A T A S H E E T

Table 11. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

000Ch

Silicon Technology (Bits 5-2) 0011 = 0.13 µm

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0001h

0000h

0007h

00x7h

0001h

0000h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

07 = Advanced Sector Protection

Simultaneous Operation: number of Sectors in all banks except boot block

BDS128H = 00E7h; BDS640H = 0077h

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

00B5h

00C5h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh

50h

57h

0001h

0000h

0004h

Boot Sector Flag

Program Suspend. 00h = not supported

Bank Organization: X = Number of banks

58h

59h

5Ah

5Bh

0027h / 0017h

0060h / 0030h

0027h / 0017h

Bank A – Bank D Region Information. X = Number of sectors in bank.

Address: 58h = Bank A; 59h = Bank B; 5Ah = Bank C; 5Bh = Bank D

Data: BDS128H / BDS640H

26

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Table 12. Am29BDS128H Sector Address Table

Bank Sector

SA0

Sector Size

4 Kwords

(x16) Address Range

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

Bank Sector

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Sector Size

32 Kwords

(x16) Address Range

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

27

D A T A S H E E T

Table 12. Am29BDS128H Sector Address Table (Continued)

Bank Sector

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

Sector Size

32 Kwords

(x16) Address Range

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

Bank Sector

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

Sector Size

32 Kwords

(x16) Address Range

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

28

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Table 12. Am29BDS128H Sector Address Table (Continued)

Bank Sector

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

Sector Size

32 Kwords

(x16) Address Range

400000h–407FFFh

408000h–40FFFFh

410000h–417FFFh

418000h–41FFFFh

420000h–427FFFh

428000h–42FFFFh

430000h–437FFFh

438000h–43FFFFh

440000h–447FFFh

448000h–44FFFFh

450000h–457FFFh

458000h–45FFFFh

460000h–467FFFh

468000h–46FFFFh

470000h–477FFFh

478000h–47FFFFh

480000h–487FFFh

488000h–48FFFFh

490000h–497FFFh

498000h–49FFFFh

4A0000h–4A7FFFh

4A8000h–4AFFFFh

4B0000h–4B7FFFh

4B8000h–4BFFFFh

4C0000h–4C7FFFh

4C8000h–4CFFFFh

4D0000h–4D7FFFh

4D8000h–4DFFFFh

4E0000h–4E7FFFh

4E8000h–4EFFFFh

4F0000h–4F7FFFh

4F8000h–4FFFFFh

Bank Sector

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

Sector Size

32 Kwords

(x16) Address Range

500000h–507FFFh

508000h–50FFFFh

510000h–517FFFh

518000h–51FFFFh

520000h–527FFFh

528000h–52FFFFh

530000h–537FFFh

538000h–53FFFFh

540000h–547FFFh

548000h–54FFFFh

550000h–557FFFh

558000h–55FFFFh

560000h–567FFFh

568000h–56FFFFh

570000h–577FFFh

578000h–57FFFFh

580000h–587FFFh

588000h–58FFFFh

590000h–597FFFh

598000h–59FFFFh

5A0000h–5A7FFFh

5A8000h–5AFFFFh

5B0000h–5B7FFFh

5B8000h–5BFFFFh

5C0000h–5C7FFFh

5C8000h–5CFFFFh

5D0000h–5D7FFFh

5D8000h–5DFFFFh

5E0000h–5E7FFFh

5E8000h–5EFFFFh

5F0000h–5F7FFFh

5F8000h–5FFFFFh

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

29

D A T A S H E E T

Table 12. Am29BDS128H Sector Address Table (Continued)

Bank Sector

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

Sector Size

32 Kwords

(x16) Address Range

600000h–607FFFh

608000h–60FFFFh

610000h–617FFFh

618000h–61FFFFh

620000h–627FFFh

628000h–62FFFFh

630000h–637FFFh

638000h–63FFFFh

640000h–647FFFh

648000h–64FFFFh

650000h–657FFFh

658000h–65FFFFh

660000h–667FFFh

668000h–66FFFFh

670000h–677FFFh

678000h–67FFFFh

680000h–687FFFh

688000h–68FFFFh

690000h–697FFFh

698000h–69FFFFh

6A0000h–6A7FFFh

6A8000h–6AFFFFh

6B0000h–6B7FFFh

6B8000h–6BFFFFh

6C0000h–6C7FFFh

6C8000h–6CFFFFh

6D0000h–6D7FFFh

6D8000h–6DFFFFh

6E0000h–6E7FFFh

6E8000h–6EFFFFh

6F0000h–6F7FFFh

6F8000h–6FFFFFh

Bank Sector

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

SA259

SA260

SA261

SA262

SA263

SA264

SA265

SA266

SA267

SA268

SA269

Sector Size

32 Kwords

4 Kwords

(x16) Address Range

700000h–707FFFh

708000h–70FFFFh

710000h–717FFFh

718000h–71FFFFh

720000h–727FFFh

728000h–72FFFFh

730000h–737FFFh

738000h–73FFFFh

740000h–747FFFh

748000h–74FFFFh

750000h–757FFFh

758000h–75FFFFh

760000h–767FFFh

768000h–76FFFFh

770000h–777FFFh

778000h–77FFFFh

780000h–787FFFh

788000h–78FFFFh

790000h–797FFFh

798000h–79FFFFh

7A0000h–7A7FFFh

7A8000h–7AFFFFh

7B0000h–7B7FFFh

7B8000h–7BFFFFh

7C0000h–7C7FFFh

7C8000h–7CFFFFh

7D0000h–7D7FFFh

7D8000h–7DFFFFh

7E0000h–7E7FFFh

7E8000h–7EFFFFh

7F0000h–7F7FFFh

7F8000h–7F8FFFh

7F9000h–7F9FFFh

7FA000h–7FAFFFh

7FB000h–7FBFFFh

7FC000h–7FCFFFh

7FD000h–7FDFFFh

7FE000h–7FEFFFh

7FF000h–7FFFFFh

4 Kwords

30

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Table 13. Am29BDS640H Sector Address Table

Bank

Sector Sector Size

Address Range

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

Bank

Sector

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Sector Size

32 Kwords

Address Range

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

SA0

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

31

D A T A S H E E T

Table 13. Am29BDS640H Sector Address Table

Bank

Sector Sector Size

Address Range

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

Bank

Sector

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

Sector Size

32 Kwords

4 Kwords

Address Range

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

32 Kwords

4 Kwords

32

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 20, “Memory Array Command Defini-

tions,” on page 46 defines the valid register command

sequences. Writing incorrect address and data values

or writing them in the improper sequence may place the

device in an unknown state. The system must write the

reset command to return the device to reading array

data. Refer to the AC Characteristics section for timing

diagrams.

be C0h, address bits A11–A0 should be 555h, and

address bits A19–A12 set the code to be latched. The

device will power up or after a hardware reset with the

default setting, which is in asynchronous mode. The

register must be set before the device can enter syn-

chronous mode. The configuration register can not be

changed during device operations (program, erase, or

sector lock).

Reading Array Data

Power-up/

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data in asynchronous mode. Each bank is

ready to read array data after completing an Embedded

Program or Embedded Erase algorithm.

Hardware Reset

Asynchronous Read

Mode Only

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read data

from any non-erase-suspended sector within the same

bank. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data from any non-erase-suspended sector

within the same bank. See the “Erase Suspend/Erase

Resume Commands” section on page 39 for more

information.

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(D15 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(D15 = 1)

Synchronous Read

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase operation,

or if the bank is in the autoselect mode. See the “Reset

Command” section on page 36 for more information.

Mode Only

Figure 3. Synchronous/Asynchronous State

Diagram

See also “Requirements for Asynchronous Read Oper-

ation (Non-Burst)” section on page 11 and “Require-

ments for Synchronous (Burst) Read Operation”

section on page 11 for more information. The Asyn-

chronous Read and Synchronous/Burst Read tables

provide the read parameters, and Figure 16, “CLK Syn-

chronous Burst Mode Read (rising active CLK),” on

page 58, Figure 18, “Synchronous Burst Mode Read,”

on page 59, and Figure 31, “Asynchronous Mode Read

with Latched Addresses,” on page 67 show the timings.

Read Mode Setting

On power-up or hardware reset, the device is set to be

in asynchronous read mode. This setting allows the

system to enable or disable burst mode during system

operations. Address A19 determines this setting: “1” for

asynchronous mode, “0” for synchronous mode.

Programmable Wait State Configuration

The programmable wait state feature informs the

device of the number of clock cycles that must elapse

after AVD# is driven active before data will be available.

This value is determined by the input frequency of the

device. Address bits A14–A12 determine the setting

(see Table 14, “Programmable Wait State Settings,” on

page 34).

Set Configuration Register Command Se-

quence

The device uses a configuration register to set the

various burst parameters: number of wait states, burst

read mode, active clock edge, RDY configuration, and

synchronous mode active. The configuration register

must be set before the device will enter burst mode.

The wait state command sequence instructs the device

to set a particular number of clock cycles for the initial

access in burst mode. The number of wait states that

should be programmed into the device is directly

related to the clock frequency.

The configuration register is loaded with a three-cycle

command sequence. The first two cycles are standard

unlock sequences. On the third cycle, the data should

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

33

D A T A S H E E T

Table 14. Programmable Wait State Settings

Total Initial Access

address bits A14–A12 to 010 for the system/device to

execute at maximum speed.

Table 15 describes the typical number of clock cycles

(wait states) for various conditions.

A14

A13

A12

Cycles

0

2

Table 15. Wait States for Reduced Wait-state

Handshaking

0

1

3

0

1

0

4

System

Frequency

Range

Device

Speed

Rating

0

1

5

Even Initial

Address

Odd Initial

Address

1

0

6

6–22 MHz

22–28 MHz

28–43 MHz

43–54 MHz

6–28 MHz

28–35 MHz

35–53 MHz

53–66 MHz

2

3

4

2

3

4

2

3

4

5

2

3

4

5

1

0

1

7 (default)

Reserved

D

1

0

(54 MHz)

1

Notes:

1. Upon power-up or hardware reset, the default setting is

seven wait states.

E

2. RDY will default to being active with data when the Wait

State Setting is set to a total initial access cycle of 2.

(66 MHz)

It is recommended that the wait state command

sequence be written, even if the default wait state value

is desired, to ensure the device is set as expected. A

hardware reset will set the wait state to the default set-

ting.

Notes:

1. If the latched address is 3Eh or 3Fh (or an address offset

from either address by a multiple of 64), add two access

cycles to the values listed.

2. In the 8-, 16-, and 32-word burst modes, the address

pointer does not cross 64-word boundaries (3Fh, or

addresses offset from 3Fh by a multiple of 64).

Reduced Wait-state Handshaking Option

If the device is equipped with the reduced wait-state

handshaking option, the host system should set

3. Typical initial access cycles may vary depending on

system margin requirements.

34

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

the starting location. The sixteen- and thirty-two linear

Standard Handshaking Option

wrap around modes operate in a fashion similar to the

eight-word mode.

For optimal burst mode performance on devices with

the standard handshaking option, the host system

must set the appropriate number of wait states in the

flash device depending on the clock frequency.

Table 17 shows the address bits and settings for the

four read modes.

Table 16 describes the typical number of clock cycles

(wait states) for various conditions with A14-A12 set to

101.

Table 17. Read Mode Settings

Address Bits

Burst Modes

A16

0

A15

0

Table 16. Wait States for Standard Handshaking

Continuous

Typical No. of Clock

Conditions at Address

Cycles after AVD# Low

8-word linear wrap around

16-word linear wrap around

32-word linear wrap around

0

1

Initial address

7

1

0

Initial address is 3E or 3Fh (or

offset from these addresses by

a multiple of 64) and is at

boundary crossing*

1

7

Note: Upon power-up or hardware reset the default setting is

continuous.

* In the 8-, 16- and 32-word burst read modes, the address

pointer does not cross 64-word boundaries (addresses

which are multiples of 3Fh).

Burst Active Clock Edge Configuration

By default, the device will deliver data on the rising

edge of the clock after the initial synchronous access

time. Subsequent outputs will also be on the following

rising edges, barring any delays. The device can be set

so that the falling clock edge is active for all synchro-

nous accesses. Address bit A17 determines this set-

ting; “1” for rising active, “0” for falling active.

The autoselect function allows the host system to

determine whether the flash device is enabled for

handshaking. See the “Autoselect Command

Sequence” section on page 36 for more information.

Read Mode Configuration

RDY Configuration

The device supports four different read modes: contin-

uous mode, and 8, 16, and 32 word linear wrap around

modes. A continuous sequence begins at the starting

address and advances the address pointer until the

burst operation is complete. If the highest address in

the device is reached during the continuous burst read

mode, the address pointer wraps around to the lowest

address.

By default, the device is set so that the RDY pin will

output V whenever there is valid data on the outputs.

OH

The device can be set so that RDY goes active one

data cycle before active data. Address bit A18 deter-

mines this setting; “1” for RDY active with data, “0” for

RDY active one clock cycle before valid data. In asyn-

chronous mode, RDY is an open-drain output.

For example, an eight-word linear read with wrap

around begins on the starting address written to the

device and then advances to the next 8 word boundary.

The address pointer then returns to the 1st word after

the previous eight word boundary, wrapping through

Configuration Register

Table 18 shows the address bits that determine the

configuration register settings for various device func-

tions.

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

35

D A T A S H E E T

Table 18. Configuration Register

Address BIt

Function

Settings (Binary)

Set Device

0 = Synchronous Read (Burst Mode) Enabled

A19

Read Mode 1 = Asynchronous Mode (default)

0 = RDY active one clock cycle before data

1 = RDY active with data (default)

A18

A17

RDY

0 = Burst starts and data is output on the falling edge of CLK

1 = Burst starts and data is output on the rising edge of CLK (default)

Clock

Synchronous Mode

00 = Continuous (default)

A16

A15

Read Mode

01 = 8-word linear with wrap around

10 = 16-word linear with wrap around

11 = 32-word linear with wrap around

000 = Data is valid on the 2th active CLK edge after AVD# transition to V_IH

001 = Data is valid on the 3th active CLK edge after AVD# transition to V_IH

010 = Data is valid on the 4th active CLK edge after AVD# transition to V_IH

011 = Data is valid on the 5th active CLK edge after AVD# transition to V_IH

100 = Data is valid on the 6th active CLK edge after AVD# transition to V_IH

101 = Data is valid on the 7th active CLK edge after AVD# transition to V_IH(default)

A14

A13

A12

Programmable

Wait State

110 = Reserved

111 = Reserved

Note:Device will be in the default state upon power-up or hardware reset.

If DQ5 goes high during a program or erase operation,

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the bank to which

the system was writing to the read mode. Once erasure

begins, however, the device ignores reset commands

until the operation is complete.

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 20, “Memory Array Command Definitions,” on

page 46 shows the address and data requirements.

The autoselect command sequence may be written to

an address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command

may not be written while the device is actively program-

ming or erasing in the other bank.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins (prior to the third cycle).

This resets the bank to which the system was writing to

the read mode. If the program command sequence is

written to a bank that is in the Erase Suspend mode,

writing the reset command returns that bank to the

erase-suspend-read mode. Once programming

begins, however, the device ignores reset commands

until the operation is complete.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the

autoselect command. The bank then enters the

autoselect mode. No subsequent data will be made

available if the autoselect data is read in synchronous

mode. The system may read at any address within the

same bank any number of times without initiating

another autoselect command sequence. Read com-

mands to other banks will return data from the array.

The following table describes the address require-

ments for the various autoselect functions, and the

resulting data. BA represents the bank address, and

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to the read mode. If a bank entered

the autoselect mode while in the Erase Suspend mode,

writing the reset command returns that bank to the

erase-suspend-read mode.

36

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

SA represents the sector address. The device ID is

read in three cycles.

Table 19. Autoselect Data

next, which in turn initiate the Embedded Program

algorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 20, “Memory Array

Command Definitions,” on page 46 shows the address

and data requirements for the program command

sequence.

Description

Address

Read Data

Manufacturer

ID

(BA) + 00h

0001h

Device ID,

Word 1

227Eh (BDS128H)

221Eh (BDS640H)

(BA) + 01h

(BA) + 0Eh

(BA) + 0Fh

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and addresses

are no longer latched. The system can determine the

status of the program operation by monitoring DQ7 or

DQ6/DQ2. Refer to the “Write Operation Status”

section on page 48 for information on these status bits.

Device ID,

Word 2

2218h (BDS128H)

2201h (BDS640H)

Device ID,

Word 3

2200h

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should be

reinitiated once that bank has returned to the read

mode, to ensure data integrity.

Sector

Protection

Verification

0001h (locked),

0000h (unlocked)

(SA) + 02h

DQ15 - DQ8 = 0

DQ7: Factory Lock Bit

1 = Locked, 0 = Not Locked

DQ6: Customer Lock Bit

1 = Locked, 0 = Not Locked

DQ5: Handshake Bit

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from

“0” back to a “1.” Attempting to do so may cause that

bank to set DQ5 = 1, or cause the DQ7 and DQ6 status

bit to indicate the operation was successful. However,

a succeeding read will show that the data is still “0.”

Only erase operations can convert a “0” to a “1.”

Indicator Bits (BA) + 03h

1 = Reduced Wait-state

Handshake,

0 = Standard Handshake

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to prima-

rily program to a bank faster than using the standard

program command sequence. The unlock bypass

command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The

device then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass

program command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. The host system may also ini-

tiate the chip erase and sector erase sequences in the

unlock bypass mode. The erase command sequences

are four cycles in length instead of six cycles. Table 20,

“Memory Array Command Definitions,” on page 46

shows the requirements for the unlock bypass

command sequences. The Unlock Bypass Reset

command is required to return to reading array data

when the bank is in the unlock bypass mode.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured data area

containing a random, eight word electronic serial num-

ber (ESN). The system can access the SecSi Sector

region by issuing the three-cycle Enter SecSi Sector

command sequence. The device continues to access

the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The

Exit SecSi Sector command sequence returns the de-

vice to normal operation. The SecSi Sector is not ac-

cessible when the device is executing an Embedded

Program or embedded Erase algorithm. Table 20,

“Memory Array Command Definitions,” on page 46

shows the address and data requirements for both

command sequences.

Program Command Sequence

Programming is a four-bus-cycle operation. The

program command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

During the unlock bypass mode, only the Read, Unlock

Bypass Program, Unlock Bypass Sector Erase, Unlock

Bypass Chip Erase, and Unlock Bypass Reset com-

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

37

D A T A S H E E T

mands are valid. To exit the unlock bypass mode, the

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 20,

“Memory Array Command Definitions,” on page 46

shows the address and data requirements for the chip

erase command sequence.

system must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

bank address and the data 90h. The second cycle

need only contain the data 00h. The bank then returns

to the read mode.

The device offers accelerated program operations

through the ACC input. When the system asserts V

HH

on this input, the device automatically enters the

Unlock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

ACC input to accelerate the operation.

When the Embedded Erase algorithm is complete, that

bank returns to the read mode and addresses are no

longer latched. The system can determine the status of

the erase operation by using DQ7 or DQ6/DQ2. Refer

to the “Write Operation Status” section on page 48 for

information on these status bits.

Figure 4, “Program Operation,” on page 38 illustrates

the algorithm for the program operation. Refer to the

Erase/Program Operations table in the AC Character-

istics section for parameters, and Figure 34, “Asyn-

chronous Program Operation Timings: AVD# Latched

Addresses,” on page 70 and Figure 36, “Synchronous

Program Operation Timings: WE# Latched Addresses,”

on page 72 for timing diagrams.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that

occurs, the chip erase command sequence should be

reinitiated once that bank has returned to reading array

data, to ensure data integrity.

The host system may also initiate the chip erase

command sequence while the device is in the unlock

bypass mode. The command sequence is two cycles

cycles in length instead of six cycles. See Table 20,

“Memory Array Command Definitions,” on page 46 for

details on the unlock bypass command sequences.

START

Write Program

Command Sequence

Figure 5, “Erase Operation,” on page 40 illustrates the

algorithm for the erase operation. Refer to the

Erase/Program Operations table in the AC Character-

istics section for parameters and timing diagrams.

Data Poll

from System

Embedded

Program

algorithm

in progress

Sector Erase Command Sequence

Verify Data?

No

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 20, “Memory Array

Command Definitions,” on page 46 shows the address

and data requirements for the sector erase command

sequence.

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

Note: See Table 20 for program command sequence.

Figure 4. Program Operation

After the command sequence is written, a sector erase

Chip Erase Command Sequence

time-out of no less than t

occurs. During the

SEA

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

time-out period, additional sector addresses and sector

erase commands may be written. Loading the sector

erase buffer may be done in any sequence, and the

38

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

number of sectors may be from one sector to all sec-

tors. The time between these additional cycles must be

less than t , otherwise erasure may begin. Any

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system

to interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. The bank address is required when writing

this command. This command is valid only during the

SEA

sector erase address and command following the

exceeded time-out, t may or may not be accepted.

SEA,

It is recommended that processor interrupts be dis-

abled during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the

last Sector Erase command is written. Any command

other than Sector Erase or Erase Suspend during the

time-out period resets that bank to the read mode. The

system must rewrite the command sequence and any

additional addresses and commands.

sector erase operation, including the minimum t

SEA

time-out period during the sector erase command

sequence. The Erase Suspend command is ignored if

written during the chip erase operation or Embedded

Program algorithm.

When the Erase Suspend command is written during

the sector erase operation, the device requires a

The system can monitor DQ3 to determine if the sector

erase timer has timed out (See “DQ3: Sector Erase

Timer” section on page 51.) The time-out begins from

the rising edge of the final WE# pulse in the command

sequence.

maximum of t

to suspend the erase operation. How-

ESL

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded Erase

operation is in progress, the system can read data from

the non-erasing bank. The system can determine the

status of the erase operation by reading DQ7 or

DQ6/DQ2 in the erasing bank. Refer to the “Write

Operation Status” section on page 48 for information

on these status bits.

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The

system can read data from or program data to any

sector not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at any

address within erase-suspended sectors produces

status information on DQ7–DQ0. The system can use

DQ7, or DQ6 and DQ2 together, to determine if a

sector is actively erasing or is erase-suspended. Refer

to the Figure , “Write Operation Status,” on page 48 for

information on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that

occurs, the sector erase command sequence should

be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard program operation. Refer to the

“Write Operation Status” section on page 48 for more

information.

The host system may also initiate the sector erase

command sequence while the device is in the unlock

bypass mode. The command sequence is four cycles

cycles in length instead of six cycles. The Unlock

Bypass Reset Command is required to return to

reading array data when the bank is in the unlock

bypass mode.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

“Autoselect Mode” section on page 14 and “Autoselect

Command Sequence” section on page 36 for details.

To resume the sector erase operation, the system must

write the Erase Resume command. The bank address

of the erase-suspended bank is required when writing

this command. Further writes of the Resume command

Figure 5, “Erase Operation,” on page 40 illustrates the

algorithm for the erase operation. Refer to the

Erase/Program Operations table in the Figure , “AC

Characteristics,” on page 69 for parameters and timing

diagrams.

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

39

D A T A S H E E T

are ignored. Another Erase Suspend command can be

written after the chip has resumed erasing.

ing as a “0”. The password is all Fs when shipped from

the factory. All 64-bit password combinations are valid

as a password.

START

Password Verify Command

The Password Verify Command is used to verify the

Password. The Password is verifiable only when the

Password Mode Locking Bit is not programmed. If the

Password Mode Locking Bit is programmed and the

user attempts to verify the Password, the device will al-

ways drive all Fs onto the DQ data bus.

Write Erase

Command Sequence

Data Poll

from System

Also, the device will not operate in Simultaneous Oper-

ation when the Password Verify command is executed.

Only the password is returned regardless of the bank

address. The lower two address bits (A1–A0) are valid

during the Password Verify. Writing the SecSi Sector

Exit command returns the device back to normal oper-

ation.

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Password Protection Mode Locking Bit

Program Command

Erasure Completed

The Password Protection Mode Locking Bit Program

Command programs the Password Protection Mode

Locking Bit, which prevents further verifies or updates

to the password. Once programmed, the Password

Protection Mode Locking Bit cannot be erased and the

Persistent Protection Mode Locking Bit program cir-

cuitry is disabled, thereby forcing the device to remain

in the Password Protection Mode. After issuing

“PL/68h” at the fourth bus cycle, the device requires a

time out period of approximately 150 µs for program-

ming the Password Protection Mode Locking Bit. Then

by writing “PL/48h” at the fifth bus cycle, the device

outputs verify data at DQ0. If DQ0 = 1, then the Pass-

word Protection Mode Locking Bit is programmed. If

not, the system must repeat this program sequence

from the fourth cycle of “PL/68h”. Exiting the Password

Protection Mode Locking Bit Program command is ac-

complished by writing the SecSi Sector Exit command

or Read/Reset command.

Notes:

1. See Table 20 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 5. Erase Operation

Password Program Command

The Password Program Command permits program-

ming the password that is used as part of the hard-

ware protection scheme. The actual password is

64-bits long. 4 Password Program commands are re-

quired to program the password. The user must enter

the unlock cycle, password program command (38h)

and the program address/data for each portion of the

password when programming. There are no provisions

for entering the 2-cycle unlock cycle, the password

program command, and all the password data. There

is no special addressing order required for program-

ming the password. Also, when the password is under-

going programming, Simultaneous Operation is

disabled. Read operations to any memory location will

return the programming status. Once programming is

complete, the user must issue a Read/Reset com-

mand to return the device to normal operation. Once

the Password is written and verified, the Password

Mode Locking Bit must be set in order to prevent verifi-

cation. The Password Program Command is only ca-

pable of programming “0”s. Programming a “1” after a

cell is programmed as a “0” results in a time-out by the

Embedded Program Algorithm™ with the cell remain-

Persistent Sector Protection Mode

Locking Bit Program Command

The Persistent Sector Protection Mode Locking Bit

Program Command programs the Persistent Sector

Protection Mode Locking Bit, which prevents the Pass-

word Mode Locking Bit from ever being programmed.

By disabling the program circuitry of the Password

Mode Locking Bit, the device is forced to remain in the

Persistent Sector Protection mode of operation, once

this bit is set. After issuing “SMPL/68h” at the fourth

bus cycle, the device requires a time out period of ap-

proximately 150 µs for programming the Persistent

Protection Mode Locking Bit. Then by writing

“SMPL/48h” at the fifth bus cycle, the device outputs

verify data at DQ0. If DQ0 = 1, then the Persistent Pro-

40

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

tection Mode Locking Bit is programmed. If not, the command is accomplished by writing the Read/Reset

system must repeat this program sequence from the

fourth cycle of “PL/68h”. Exiting the Persistent Protec-

tion Mode Locking Bit Program command is accom-

plished by writing the SecSi Sector Exit command or

Reset command.

command.

Password Unlock Command

The Password Unlock command is used to clear the

PPB Lock Bit so that the PPBs can be unlocked for

modification, thereby allowing the PPBs to become ac-

cessible for modification. The exact password must be

entered in order for the unlocking function to occur.

This command cannot be issued any faster than 2 µs

at a time to prevent a hacker from running through the

all 64-bit combinations in an attempt to correctly match

a password. If the command is issued before the 2 µs

execution window for each portion of the unlock, the

command will be ignored.

SecSi Sector Protection Bit Program

Command

To protect the SecSi Sector, write the SecSi Sector

Protect command sequence while in the SecSi Sector

mode. After issuing “OPBP/48h” at the fourth bus cy-

cle, the device requires a time out period of approxi-

mately 150 µs to protect the SecSi Sector. Then, by

writing “OPBP/48” at the fifth bus cycle, the device out-

puts verify data at DQ0. If DQ0 = 1, then the SecSi

Sector is protected. If not, then the system must re-

peat this program sequence from the fourth cycle of

“OPBP/48h”.

The Password Unlock function is accomplished by

writing Password Unlock command and data to the de-

vice to perform the clearing of the PPB Lock Bit. The

password is 64 bits long, so the user must write the

Password Unlock command 4 times. A1 and A0 are

used for matching. Writing the Password Unlock com-

mand is not address order specific. The lower address

A1–A0= 00, the next Password Unlock command is to

A1–A0= 01, then to A1–A0= 10, and finally to A1–A0=

11.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the

PPB Lock bit if it is cleared either at reset or if the

Password Unlock command was successfully exe-

cuted. There is no PPB Lock Bit Clear command.

Once the PPB Lock Bit is set, it cannot be cleared un-

less the device is taken through a power-on clear or

the Password Unlock command is executed. Upon set-

ting the PPB Lock Bit, the PPBs are latched into the

DYBs. If the Password Mode Locking Bit is set, the

PPB Lock Bit status is reflected as set, even after a

power-on reset cycle. Exiting the PPB Lock Bit Set

command is accomplished by writing the SecSi Sector

Exit command, only while in the Persistent Sector Pro-

tection Mode.

Once the Password Unlock command is entered for all

four words, the RDY pin goes LOW indicating that the

device is busy. Approximately 1 µs is required for each

portion of the unlock. Once the first portion of the

password unlock completes (RDY is not driven and

DQ6 does not toggle when read), the Password Un-

lock command is issued again, only this time with the

next part of the password. Four Password Unlock com-

mands are required to successfully clear the PPB

Lock Bit. As with the first Password Unlock command,

the RDY signal goes LOW and reading the device re-

sults in the DQ6 pin toggling on successive read oper-

ations until complete. It is the responsibility of the

microprocessor to keep track of the number of Pass-

word Unlock commands, the order, and when to read

the PPB Lock bit to confirm successful password un-

lock. In order to relock the device into the Password

Mode, the PPB Lock Bit Set command can be re-is-

sued. Exiting the Password Unlock Command is ac-

complished by writing SecSi Sector Exit command.

DYB Write Command

The DYB Write command is used to set or clear a DYB

for a given sector. The high order address bits

(Amax–A11) are issued at the same time as the code

01h or 00h on DQ7-DQ0. All other DQ data bus pins

are ignored during the data write cycle. The DYBs are

modifiable at any time, regardless of the state of the

PPB or PPB Lock Bit. The DYBs are cleared at

power-up or hardware reset. Exiting the DYB Write

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

41

D A T A S H E E T

Figure 6. PPB Program Algorithm

Am29BDS128H/Am29BDS640H

42

27024B3 May 10, 2006

D A T A S H E E T

ing a specific PPB. Unlike the PPB program, no spe-

PPB Program Command

cific sector address is required. However, when the

PPB erase command is written (60h), all Sector PPBs

are erased in parallel. If the PPB Lock Bit is set, the

ALL PPB Erase command will not execute and the

command will time-out without erasing the PPBs. After

issuing “WP/60h” at the fourth bus cycle, the device re-

quires a time out period of approximately 1.5 ms to

erase the PPB. Writing “SBA+WP/40h” at the fifth bus

cycle produces verify data at DQ0. If DQ0 = 0, the

PPB is erased. If not, the system must repeat this pro-

gram sequence from the fourth cycle of “WP/60h”.

The PPB Program command is used to program, or

set, a given PPB. Each PPB is individually pro-

grammed (but is bulk erased with the other PPBs).

The specific sector address (Amax–A12) are written at

the same time as the program command 60h. If the

PPB Lock Bit is set and the correspondingly PPB is

set for the sector, the PPB Program command will not

execute and the command will time out without pro-

gramming the PPB. After issuing “SBA+WP/68h” at

the fourth bus cycle, the device requires a time out pe-

riod of approximately 150 µs to program the PPB.

Writing “SBA+WP/48” at the fifth bus cycle produces

verify data at DQ0. If DQ0 = 1, the PPB is pro-

grammed. If not, the system must repeat this program

sequence from the fourth cycle of “SBA+WP/68h”.

It is the responsibility of the system to preprogram all

PPBs prior to issuing the All PPB Erase command. If

the system attempts to erase a cleared PPB, over-era-

sure may occur, making it difficult to program the PPB

at a later time. Also note that the total number of PPB

program/erase cycles is limited to 100 cycles. Cycling

the PPBs beyond 100 cycles is not guaranteed.

The PPB Program command does not follow the

Embedded Program algorithm. Writing the SecSi

Sector Exit command or Read/Reset command return

the device back to normal operation.

Writing the SecSi Sector Exit command or Read/Re-

set command return the device to normal operation.

All PPB Erase Command

The All PPB Erase command is used to erase all

PPBs in bulk. There is no means for individually eras-

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

43

D A T A S H E E T

Figure 7. PPB Erase Algorithm

Am29BDS128H/Am29BDS640H

44

27024B3 May 10, 2006

D A T A S H E E T

tor Exit command return the device to normal opera-

DYB Write Command

tion.

The DYB Write command is used for setting the DYB,

which is a volatile bit that is cleared at hardware reset.

There is one DYB per sector. If the PPB is set, the sec-

tor is protected regardless of the value of the DYB. If

the PPB is cleared, setting the DYB to a 1 protects the

sector from programs or erases. Since this is a volatile

bit, removing power or resetting the device will clear

the DYBs. Writing Read/Reset command returns the

device to normal operations.

PPB Lock Bit Status Command

The programming of the PPB Lock Bit for a given sec-

tor can be verified by writing a PPB Lock Bit status ver-

ify command to the device. Read/Reset and SecSi

Sector Exit return the device to normal operation.

DYB Status Command

The programming of the DYB for a given sector can be

verified by writing a DYB Status command to the de-

vice. Writing SecSi Sector Exit command returns the

device to normal operation.

PPB Status Command

The programming of the PPB for a given sector can be

verified by writing a PPB status verify command to the

device. Writing Read/Reset command and SecSi Sec-

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

45

D A T A S H E E T

Command Definitions

Table 20. Memory Array Command Definitions

Bus Cycles (Notes 1–6)

First

Addr

Second

Third

Addr

Fourth

Addr

Fifth

Sixth

Addr

Command Sequence

(Notes)

Data

RD

F0

Addr

Data

Addr

Data

Asynchronous Read (7)

Reset (8)

1

4

6

4

6

3

2

1

2

1

3

1

RA

XXX

555

XX

Manufacturer ID

Device ID (9, 10)*

Sector Lock Verify (12)*

Indicator Bits (13)*

Program

AA

A0

80

2AA

PA

55

PD

30

10

BA+555

SA+555

BA+555

555

90

A0

80

20

BA+X00

BA+X01

SA+X02

BA+X03

PA

0001

227E

(12)*

(13)*

Data

AA

BA+X0E

(10)*

BA+X0F

(11)*

Chip Erase

555

2AA

55

555

SA

10

30

Sector Erase

555

AA

Entry

555

Program (14, 15)

Sector Erase (14, 15)

Erase (14, 15)

XX

SA

XX

80

XXX

CFI (14, 15)

XX

98

Reset (20)

XX

90

XXX

2AA

00

55

Erase Suspend (16)

Erase Resume (17)

Set Configuration Register (18)

CFI Query (19)

BA

B0

30

BA

555

55

AA

98

(CR)555

C0

* For actual hexadecimal data values, refer to the note number indicated.

Legend:

X = Don’t care

SA = Address of the sector to be verified (in autoselect mode) or erased.

Address bits Amax–A12 uniquely select any sector.

BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for

which command is being written.

SLA = Address of the sector to be locked. Set sector address (SA) and

either A6 = 1 for unlocked or A6 = 0 for locked.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch

on the rising edge of the AVD# pulse or active edge of CLK which ever

comes first.

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

CR = Configuration Register address bits A19–A12.

Notes:

1. See Table 1 for description of bus operations.

13. DQ15–DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 = Not

Locked), DQ6: Customer Lock Bit (1 = Locked, 0 = Not Locked),

DQ5: Handshake Bit (1 = Reduced wait-state Handshake, 0 =

Standard Handshake), DQ4–DQ0 = 0

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles. All others are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences, except

for RD and PD.

14. The Unlock Bypass command sequence is required prior to this

command sequence.

5. Unless otherwise noted, address bits Amax–A12 are don’t cares.

15. The Unlock Bypass Reset command is required to return to reading

array data when the bank is in the unlock bypass mode.

6. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state. The

system must write the reset command to return the device to

reading array data.

16. The system may read and program in non-erasing sectors, or enter

the autoselect mode, when in the Erase Suspend mode. The Erase

Suspend command is valid only during a sector erase operation,

and requires the bank address.

7. No unlock or command cycles required when bank is reading array

data.

17. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

8. The Reset command is required to return to reading array data (or to

the erase-suspend-read mode if previously in Erase Suspend) when

a bank is in the autoselect mode, or if DQ5 goes high (while the

bank is providing status information) or performing sector

lock/unlock.

18. See “Set Configuration Register Command Sequence” for details.

This command is unavailable in Unlock Bypass mode.

19. Command is valid when device is ready to read array data or when

device is in autoselect mode.

9. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address. See the

Autoselect Command Sequence section for more information.

20. The Unlock Bypass Reset command is required to exit this mode

before sending any other commands to the device. The only

commands that are allowed in the Unlock Bypass mode are the

Entry and exit (Reset), Program, Erase, Sector Erase and CFI.

10. BDS128H: 2218h; BDS640H: 221Eh.

11. BDS128H: 2200h; BDS640H: 2201h

12. The data is 0000h for an unlocked sector and 0001h for a locked

sector

46

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Table 21. Sector Protection Command Definitions

Bus Cycles (Notes 1–6)

First

Second

Third

Addr

Fourth

Fifth

Addr

Sixth

Data Addr Data

Seventh

Command Sequence

(Notes)

Addr Data Addr Data

Data

88

Addr

Data

Addr Data

Entry

Exit

3

4

555

AA

2AA

55

555

90

XX

00

68

Protection Bit

Program (8, 9)

6

555

AA

2AA

55

555

60

SA+OW

48

OW

RD(0)

Program (11)

Verify (11)

4

7

6

555

AA

2AA

55

555

38

C8

28

60

XX[0–3]

XX0

PD[0–3]

PD0

Unlock (11)

Program (8, 9)

XX1

PD1

48

XX2

XX

PD2

XX3

PD3

SBA+WP

68

SBA+WP

RD(0)

All Erase

SBA+

WPE

6

555

AA

2AA

55

555

60

WPE

60

40

XX

RD(0)

(8, 10, 12)

Status (13)

Set

4

3

4

555

AA

2AA

55

BA+555

555

90

78

58

48

58

SBA+WP

RD(0)

Status (8)

Write

BA+555

555

SA

RD(1)

X1

Erase

555

X0

Status

BA+555

RD(0)

Locking Bit Program

(8, 9)

6

555

AA

2AA

55

555

60

PL

SL

68

PL

SL

48

PL

SL

RD(0)

Locking Bit Program

(8, 9)

Legend:

X = Don’t care

PWA = Password Address. Address bits A1 and A0 are used to select

each 16-bit portion of the 64-bit entity.

PA = Address of the memory location to be programmed. Addresses latch

on the rising edge of the AVD# pulse or active edge of CLK which ever

comes first.

PL = Address (A7–A0) is (00001010)

RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1.

If unprotected, DQ0 = 0.

SA = Address of the sector to be verified (in autoselect mode) or erased.

Address bits Amax–A12 uniquely select any sector.

RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1.

If unprotected, DQ1 = 0.

BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for

which command is being written.

SBA = Sector address block to be protected.

SL = Address (A7–A0) is (00010010)

SLA = Address of the sector to be locked. Set sector address (SA) and

either A6 = 1 for unlocked or A6 = 0 for locked.

WD= Write Data. See “Configuration Register” definition for specific write

data

OW = Address (A7–A0) is (00011010).

PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations

that represent the 64-bit password.

WP = Address (A7–A0) is (00000010)

WPE = Address (A7–A0) is (01000010)

Notes:

1. See Table 1 for description of bus operations.

9. The fourth cycle programs the addressed locking bit. The fifth and

sixth cycles are used to validate whether the bit has been fully

programmed. If DQ0 (in the sixth cycle) reads 0, the program

command must be issued and verified again.

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles. All others are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences, except

for RD, PD, WD, PWD, and PD3–PD0.

10. The fourth cycle erases all PPBs. The fifth and sixth cycles are used

to validate whether the bits have been fully erased. If DQ0 (in the

sixth cycle) reads 1, the erase command must be issued and verified

again.

5. Unless otherwise noted, address bits Amax–A12 are don’t cares.

6. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state. The

system must write the reset command to return the device to

reading array data.

11. The entire four bus-cycle sequence must be entered for each portion

of the password.

12. Before issuing the erase command, all PPBs should be programmed

in order to prevent over-erasure of PPBs.

7. No unlock or command cycles required when bank is reading array

data.

13. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not

set.

8. Not supported in Synchronous Read Mode, command mode verify

are always asynchronous read operations.

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

47

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a program or erase operation: DQ2, DQ3,

DQ5, DQ6, and DQ7. Table 23, “Write Operation

Status,” on page 52 and the following subsections

describe the function of these bits. DQ7 and DQ6 each

offers a method for determining whether a program or

erase operation is complete or in progress.

invalid. Valid data on DQ7-DQ0 will appear on succes-

sive read cycles.

Table 23, “Write Operation Status,” on page 52 shows

the outputs for Data# Polling on DQ7. Figure 8, “Data#

Polling Algorithm,” on page 48 shows the Data# Polling

algorithm. Figure 40, “Data# Polling Timings

(During Embedded Algorithm),” on page 76 in the AC

Characteristics section shows the Data# Polling timing

diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Program or Erase algo-

rithm is in progress or completed, or whether a bank is

in Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately t , then that bank returns to the read

PSP

mode.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately t , then the

ASP

bank returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the

selected sectors that are protected. However, if the

system reads DQ7 at an address within a protected

sector, the status may not be valid.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ6–DQ0 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ6-DQ0 may be still

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 8. Data# Polling Algorithm

48

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

cause DQ6 to toggle. When the operation is complete,

RDY: Ready

DQ6 stops toggling.

The RDY is a dedicated output that, when the device is

configured in the Synchronous mode, indicates (when

at logic low) the system should wait 1 clock cycle before

expecting the next word of data. The RDY pin is only

controlled by CE#. Using the RDY Configuration

Command Sequence, RDY can be set so that a logic

low indicates the system should wait 2 clock cycles

before expecting valid data.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 toggles

for approximately t

time, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

, all sectors protected toggle

ASP

The following conditions cause the RDY output to be

low: during the initial access (in burst mode), and after

the boundary that occurs every 64 words beginning

with the 64th address, 3Fh.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the

system must also use DQ2 to determine which sectors

are erasing or erase-suspended. Alternatively, the

system can use DQ7 (see the subsection on DQ7:

Data# Polling).

When the device is configured in Asynchronous Mode,

the RDY is an open-drain output pin which indicates

whether an Embedded Algorithm is in progress or com-

pleted. The RDY status is valid after the rising edge of

the final WE# pulse in the command sequence.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is in high imped-

ance (Ready), the device is in the read mode, the

standby mode, or in the erase-suspend-read mode.

Table 23, “Write Operation Status,” on page 52 shows

the outputs for RDY.

If a program address falls within a protected sector,

DQ6 toggles for approximately t

after the program

PSP

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded

Program algorithm is complete.

DQ6: Toggle Bit I

See the following for additional information: Figure 9,

“Toggle Bit Algorithm,” on page 50, “DQ6: Toggle Bit I”

on page 49, Figure 41, “Toggle Bit Timings

(During Embedded Algorithm),” on page 76 (toggle bit

timing diagram), and Table 22, “DQ6 and DQ2 Indica-

tions,” on page 51.

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address in the

same bank, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

Toggle Bit I on DQ6 requires either OE# or CE# to be

deasserted and reasserted to show the change in

state.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

49

D A T A S H E E T

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

START

Read Byte

(DQ7-DQ0)

Address = VA

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. But DQ2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ6, by com-

parison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both

status bits are required for sector and mode informa-

tion. Refer to Table 22, “DQ6 and DQ2 Indications,” on

page 51 to compare outputs for DQ2 and DQ6.

Read Byte

(DQ7-DQ0)

Address = VA

No

DQ6 = Toggle?

Yes

See the following for additional information: Figure 9,

“Toggle Bit Algorithm,” on page 50, “DQ6: Toggle Bit I”

on page 49, Figure 41, “Toggle Bit Timings

(During Embedded Algorithm),” on page 76, and

Table 22, “DQ6 and DQ2 Indications,” on page 51.

No

DQ5 = 1?

Yes

Read Byte Twice

(DQ7-DQ0)

Adrdess = VA

No

DQ6 = Toggle?

Yes

FAIL

PASS

Note:The system should recheck the toggle bit even if DQ5 =

“1” because the toggle bit may stop toggling as DQ5 changes

to “1.” See the subsections on DQ6 and DQ2 for more

information.

Figure 9. Toggle Bit Algorithm

50

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

Table 22. DQ6 and DQ2 Indications

If device is

and the system reads

then DQ6

and DQ2

programming,

at any address,

toggles,

does not toggle.

at an address within a sector

selected for erasure,

toggles,

also toggles.

does not toggle.

toggles.

actively erasing,

at an address within sectors not

selected for erasure,

at an address within a sector

selected for erasure,

does not toggle,

returns array data,

toggles,

erase suspended,

at an address within sectors not

returns array data. The system can read

from any sector not selected for erasure.

selected for erasure,

programming in

erase suspend

at any address,

is not applicable.

Reading Toggle Bits DQ6/DQ2

DQ5: Exceeded Timing Limits

Refer to Figure 9, “Toggle Bit Algorithm,” on page 50 for

the following discussion. Whenever the system initially

begins reading toggle bit status, it must read DQ7–DQ0

at least twice in a row to determine whether a toggle bit

is toggling. Typically, the system would note and store

the value of the toggle bit after the first read. After the

second read, the system would compare the new value

of the toggle bit with the first. If the toggle bit is not tog-

gling, the device has completed the program or erase

operation. The system can read array data on

DQ7–DQ0 on the following read cycle.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1,” indicating that

the program or erase cycle was not successfully com-

pleted.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can change a

“0” back to a “1.” Under this condition, the device halts

the operation, and when the timing limit has been

exceeded, DQ5 produces a “1.”

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not completed the operation successfully,

and the system must write the reset command to return

to reading array data.

Under both these conditions, the system must write the

reset command to return to the read mode (or to the

erase-suspend-read mode if a bank was previously in

the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sectors

are selected for erasure, the entire time-out also

applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches

from a “0” to a “1.” If the time between additional sector

erase commands from the system can be assumed to

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (Figure 9, “Toggle

Bit Algorithm,” on page 50).

be less than t

, the system need not monitor DQ3.

SEA

See also “Sector Erase Command Sequence” on

page 38.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all

further commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

51

D A T A S H E E T

device will accept additional sector erase commands.

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

To ensure the command has been accepted, the

system software should check the status of DQ3 prior

to and following each subsequent sector erase com-

Table 23 shows the status of DQ3 relative to the other

status bits.

Table 23. Write Operation Status

DQ7

(Note 2)

DQ5

(Note 1)

DQ2

(Note 2)

RDY (Note

5)

Status

DQ6

DQ3

N/A

1

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

High

Impedance

1

No toggle

0

N/A

Toggle

Suspended Sector

Erase-Suspend-

Read (Note 4)

Erase

Suspend

Mode

Non-Erase

High

Impedance

Data

0

Data

N/A

Data

N/A

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

0

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

4. The system may read either asynchronously or synchronously (burst) while in erase suspend.

5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This

is available in the Asynchronous mode only.

52

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground:

All Inputs and I/Os except

as noted below (Note 1). . . . . . . –0.5 V to V + 0.5 V

–0.5 V

–2.0 V

IO

V

(Note 1). . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

CC

IO

20 ns

A9, RESET#, ACC (Note 1) . . . . .–0.5 V to +12.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Notes:

Figure 10. Maximum Negative

Overshoot Waveform

1. Minimum DC voltage on input or I/Os is –0.5 V. During

voltage transitions, inputs or I/Os may undershoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 10.

Maximum DC voltage on input or I/Os is V_CC+ 0.5 V.

During voltage transitions outputs may overshoot to V_CC

+ 2.0 V for periods up to 20 ns. See Figure 11.

20 ns

V_CC

2. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

+2.0 V

V_CC

+0.5 V

3. Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the de-

vice at these or any other conditions above those indicated

in the operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating condi-

tions for extended periods may affect device reliability.

1.0 V

20 ns

Figure 11. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C

A

Supply Voltages

V

Supply Voltages . . . . . . . . . . .+1.65 V to +1.95 V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . V_CC≥ V –100 mV

IO

V

Supply Voltages. . . . . . . . . . . +1.65 V to +1.95 V

IO

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

53

D A T A S H E E T

DC CHARACTERISTICS

CMOS COMPATIBLE

Parameter Description

Test Conditions Note: 1 & 2

Min

Typ

Max

1

Unit

µA

I_LI

Input Load Current

V_IN= V_SSto V_CC, V_CC= V_CCmax

V_OUT= V_SSto V_CC, V_CC= V_CCmax

I_LO

Output Leakage Current

1

µA

CE# = V_IL, OE# = V_IH,

WE# = V_IH, burst length 54 MHz

= 8

9

8

7

17

15.5

14

mA

CE# = V_IL, OE# = V_IH,

WE# = V_IH, burst length 54 MHz

= 16

I_CCB

V_CCActive burst Read Current

CE# = V_IL, OE# = V_IH,

WE# = V_IH, burst length 54 MHz

= Continuous

I_IO1

V_IONon-active Output

OE# = V_IH

1

40

30

15

5

µA

mA

µA

10 MHz

20

10

3.5

15

0.2

1

V_CCActive Asynchronous Read

Current (Note 3)

CE# = V_IL, OE# = V_IH,

WE# = V_IH

I_CC1

5 MHz

1 MHz

CE# = V_IL, OE# = V_IH, ACC = V_IH

CE# = RESET# = V_CC0.2 V

RESET# = V_IL,CLK = V_IL

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (Note 4)

V_CCStandby Current (Note 5)

V_CCReset Current

40

µA

V_CCActive Current

(Read While Write)

I_CC5

I_CC6

CE# = V_IL, OE# = V_IH

25

60

mA

V_CCSleep Current

1

7

5

40

15

µA

mA

V

V_ACC

Accelerated Program Current

(Note 6)

CE# = V_IL, OE# = V_IH,

V_ACC= 12.0 0.5 V

I_ACC

V_CC

10

V_IL

V_IH

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

V_IO= 1.8 V

–0.4

0.4

V_IO= 1.8 V

V_IO– 0.4

V_IO+ 0.4

0.1

V

V_OL

V_OH

I_OL= 100 µA, V_IO= V_CC= V_{CC min}

V

I_OH= –100 µA, V_IO= V_CC= V_{CC min}V_IO– 0.1

V

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_CC= 1.8 V

11.5

12.5

V

V_HH

Voltage for Accelerated Program

Low V_CCLock-out Voltage

11.5

1.0

12.5

1.4

V

V_LKO

Note:

1. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

2. V_IO= V_CC

3. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

4. I_CCactive while Embedded Erase or Embedded Program is in progress.

5. Device enters automatic sleep mode when addresses are stable for t_ACC+ 60 ns. Typical sleep mode current is equal to I_CC3

6. Total current during accelerated programming is the sum of V_ACCand V_CCcurrents.

.

54

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

TEST CONDITIONS

Table 24. Test Specifications

Test Condition All Speed Options Unit

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

Device

Under

Test

Input Rise and Fall Times

Input Pulse Levels

3

ns

V

0.0–V_IO

C

L

Input timing measurement

reference levels

V_IO/2

V

Output timing measurement

reference levels

V_IO/2

Figure 12. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

SWITCHING WAVEFORMS

V_IO

All Inputs and Outputs

V_IO/2

Input

Measurement Level

Output

0.0 V

Figure 13. Input Waveforms and Measurement Levels

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

55

D A T A S H E E T

AC CHARACTERISTICS

Power-up

V

CC

Parameter

t_VCS

Description

V_CCSetup Time

Test Setup

Speed

50

Unit

µs

Min

t_VIOS

V_IOSetup Time

50

µs

t_RSTH

RESET# Low Hold Time

50

µs

t_VCS

V_CC

f

t_VIOS

V_IOf

t_RSTH

RESET#

Figure 14.

V

Power-up Diagram

CC

Notes:

1.

V

≥ V –100 mV and V ramp rate exceeds 1 V/100 µs.

IO CC

CC

2. If the V ramp rate is less than 1 V /100 µs, a hardware reset will be required.

CC

CLK Characterization

Parameter

f_CLK

t_CLK

t_CH

Description

CLK Frequency

66 MHz

66

54 MHz

54

Unit

Max

Min

MHz

ns

CLK Period

CLK High Time

CLK Low Time

CLK Rise Time

CLK Fall Time

15

18.5

Min

6.0

3

7.4

3

ns

t_CL

t_CR

Max

t_CF

t

CLK

t

CL

CH

CLK

t

CF

CR

Figure 15. CLK Characterization

Am29BDS128H/Am29BDS640H

56

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

Synchronous/Burst Read

Parameter

Description

66 MHz

54 MHz

Unit

JEDEC

Standard

Latency (Even address in Reduced wait-state

Handshaking mode)

t_IACC

Max

56

69

ns

Latency (Standard Handshaking or Odd

address in Reduced wait-state Handshaking

mode

t_IACC

71

11

87.5

13.5

ns

Burst Access Time Valid Clock to Output

Delay

t_BACC

t_ACS

t_ACH

t_BDH

t_CR

Address Setup Time to CLK (Note )

Address Hold Time from CLK (Note )

Data Hold Time from Next Clock Cycle

Chip Enable to RDY Valid

Output Enable to Output Valid

Chip Enable to High Z

Min

Max

Min

Max

Min

Max

Min

Max

4

6

5

7

ns

ms

3

4

11

8

13.5

10

5

t_OE

t_CEZ

t_OEZ

t_CES

t_RDYS

t_RACC

t_AAS

t_AAH

t_CAS

t_AVC

t_AVD

t_ACC

t_CKA

t_CKZ

t_OES

t_RCC

Output Enable to High Z

CE# Setup Time to CLK

8

4

RDY Setup Time to CLK

Ready Access Time from CLK

Address Setup Time to AVD# (Note )

Address Hold Time to AVD# (Note )

CE# Setup Time to AVD#

AVD# Low to CLK

4

5

11

4

13.5

5

6

7

0

4

5

12

55

13.5

10

5

AVD# Pulse

10

50

11

8

Access Time

CLK to access resume

CLK to High Z

Output Enable Setup Time

Read cycle for continuous suspend

4

1

Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

57

D A T A S H E E T

AC CHARACTERISTICS

t_CEZ

t_CES

7 cycles for initial access shown.

CE#f

1

2

3

4

5

6

7

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Addresses

Data

Aa

t_BACC

t_ACH

Hi-Z

t_IACC

t_ACC

Da

Da + 1

Da + n

t_OEZ

OE#

RDY

t_CR

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 16. CLK Synchronous Burst Mode Read (rising active CLK)

t_CEZ

4 cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Aa

Addresses

Data

t_BACC

t_ACH

Hi-Z

t_IACC

Da

Da + 1

Da + n

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_OE

t_CR

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active falling edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock)

58

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

t_CEZ

7 cycles for initial access shown.

t_CAS

CE#

1

2

3

4

5

6

7

CLK

t_AVC

AVD#

t_AVD

t_AAS

t_BDH

Addresses

Data

Aa

t_BACC

t_AAH

Hi-Z

t_IACC

Da

Da + 1

Da + n

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_CR

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 18. Synchronous Burst Mode Read

7

cycles for initial access shown.

t_CES

CE#

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

A6

Addresses

Data

t_BACC

t_ACH

t_IACC

t_ACC

D6

D7

D0

D1

D5

D6

OE#

RDY

t_CR

t_RACC

t_OE

Hi-Z

t_RDYS

Note: Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0–D7 in data waveform indicate

the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in

range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command sequence

has been written with A18=1; device will output RDY with valid data.

Figure 19. 8-word Linear Burst with Wrap Around

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

59

D A T A S H E E T

AC CHARACTERISTICS

t_CEZ

6

wait cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

6

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Aa

Addresses

t_BACC

t_ACH

Hi-Z

Data

t_IACC

Da

Da+1

Da+2

Da+3

Da + n

t_ACC

t_OEZ

t_RACC

OE#

t_CR

t_OE

Hi-Z

RDY

t_RDYS

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY one cycle before valid data.

Figure 20. Linear Burst with RDY Set One Cycle Before Data

60

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

Suspend

Resume

x

x+2

x+3

x+4

x+6

x+7

x+8

x+1

x+5

CLK

AVD#

t

OES

Addresses

t

CKA

t

CKZ

OE#

Data

D(24)

D(20)

D(23)

D(22)

D(20)

D(21)

RDY

t

RACC

t

RACC

Note: Figure is for any even address other than 3Eh (or multiple thereof).

Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at an Even Address

Suspend

Resume

x+1

x

x+2

x+3

x+4

x+6

x+7

x+8

x+5

CLK

AVD#

t

OES

Addresses

t

CKA

t

CKZ

OE#

Data

D(27)

D(23)

D(25)

D(26)

D(25)

D(23)

D(24)

RDY

t

RACC

t

RACC

Note: Figure is for any odd address other than 3Fh (or multiple thereof).

Figure 22. Reduced Wait-state Handshake Burst Suspend/Resume at an Odd Address

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

61

D A T A S H E E T

AC CHARACTERISTICS

Resume

Suspend

x+1

x+2

x+3

x+4

x+5

x+7

x+8

x+9

x

x+6

x+10

CLK

AVD#

t

OES

t

OES

Addresses

OE#

t

CKA

t

CKZ

D(41)

D(42)

D(41)

D(3E)

D(41)

D(3E)

D(3F)

D(40)

D(3F)

D(41)

D(3F)

Data

RDY

t

RACC

Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Eh (or Offset from 3Eh)

Resume

x+1

Suspend

x+2

x+3

x+4

x+5

x+7

x+8

x+9

x

x+6

x+10

CLK

AVD#

t

OES

t

OES

Addresses

OE#

t

CKA

t

CKZ

D(41)

D(43)

D(42)

D(3F)

RACC

D(41)

D(3F)

D(41)

D(40)

D(41)

D(3F)

Data

RDY

t

RACC

t

RACC

Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Fh (or Offset from 3Fh by

a Multiple of 64)

62

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

Resume

Suspend

x

x+2

x+3

x+4

x+6

x+7

x+8

1

2

6

5

x+1

3

4

7

x+5

CLK

AVD#

t

OES

A(n)

Addresses

t

CKA

OE#

Data(1)

D(n)

D(n+2)

D(n+1)

3F

D(3F)

3F

D(40)

t

ACC

RDY(1)

t

RACC

D(n+2) D(n+3) D(n+4) D(n+5)

Data(2)

RDY(2)

D(n+1)

D(n)

D(n+6)

t

RACC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) RDY goes low during the two-cycle latency during a boundary crossing.

2) RDY stays high when a burst sequence crosses no boundaries.

Figure 25. Standard Handshake Burst Suspend Prior to Initial Access

Resume

Suspend

x

1

6

9

x+2

5

x+1

2

3

4

7

8

x+3

CLK

AVD#

t_OES

Addresses

OE#(1)

A(n)

t_CKA

t_CKZ

D(n)

D(n+1)

Data(1)

RDY(1)

t_ACC

t_RACC

OE#(2)

Data(2)

D(n+2)

D(n+1)

D(n)

D(n+1)

t_RACC

RDY(2)

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Burst suspend during the initial synchronous access

2) Burst suspend after one clock cycle following the initial synchronous access

Figure 26. Standard Handshake Burst Suspend at or after Initial Access

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63

D A T A S H E E T

AC CHARACTERISTICS

Resume

x+1

Suspend

x

x+2

x+5

x+4

x+3

1

2

6

9

5

3

4

7

8

CLK

AVD#

t_OES

A(3D)

Addresses

t_CKA

OE#

Data

t_CKZ

D(3F)

D(3F) D(4D)

D(3D)

D(3E)

D(3F)

t_ACC

t_RACC

RDY

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

Figure 27. Standard Handshake Burst Suspend at Address 3Fh (Starting Address 3Dh or Earlier)

Resume

Suspend

5

x

1

2

3

6

7

x+1

x+2

x+3

4

x+4

x+5

x+6

8

CLK

AVD#

t_OES

A(3E)

Addresses(1)

t_OES

t_CKA

OE#

t_CKZ

D(40)

D(3F)

D(41)

D(42)

D(3E)

Data(1)

RDY(1)

t_ACC

t_RACC

Addresses(2)

A(3F)

Data(2)

RDY(2)

D(41)

D(3F)

t_RACC

D(40)

D(42)

D(43)

D(3F)

t

t_RACC

RACC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Address is 3Eh or offset by a multiple of 64 (40h).

2) Address is 3Fh or offset by a multiple of 64 (40h).

Figure 28. Standard Handshake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access)

64

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

Suspend

8

Resume

x+1

5

1

2

3

6

7

4

9

x

x+2

x+3

x+4

x+5

x+6

CLK

AVD#

t

OES

A(3E)

Addresses(1)

OE#

t_OES

t

CKA

t

CKZ

D(40)

Data(1)

D(3F)

RACC

D(41)

D(42)

D(3E)

t

ACC

RDY(1)

(Even)

t

RACC

t

RACC

t

Addresses(2)

Data(2)

A(3F)

D(3F)

D(41)

D(42)

D(40)

D(43)

D(40)

RACC

RDY(2)

(Odd)

t

RACC

t

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Address is 3Eh or offset by a multiple of 64 (40h)

2) Address is 3Fh or offset by a multiple of 64 (40h)

Figure 29. Standard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK)

Resume

x+1

Suspend

x

x+2

x+3

x+4

x+6

x+7

x+8

1

6

5

2

3

4

7

x+5

CLK

t

RCC

AVD#

t

OES

A(n)

Addresses

OE#

t

CKA

Data(1)

RDY

D(n)

D(n+2)

D(n+1)

D(3F) D(3F)

D(3F)

D(40)

t

ACC

t

RACC

D(n)

???

Data(2)

CE#

t

RCC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Device crosses a page boundary prior to t_RCC

.

2) Device neither crosses a page boundary nor latches a new address prior to t_RCC

.

Figure 30. Read Cycle for Continuous Suspend

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65

D A T A S H E E T

AC CHARACTERISTICS

Asynchronous Mode Read

Parameter

JEDEC Standard Description

75 MHz

45

66 MHz

50

54 MHz

Unit

ns

t_CE

t_ACC

t_AVDP

Access Time from CE# Low

Asynchronous Access Time (Note 1)

AVD# Low Time

Max

55

12

5

Max

Min

45

50

ns

10

4

ns

t_AAVDSAddress Setup Time to Rising Edge of AVD

ns

t_AAVDHAddress Hold Time from Rising Edge of AVD Min

5.5

8.5

6

11

0

7

ns

t_OE

Output Enable to Output Valid

Max

Min

13.5

ns

Read

ns

Output Enable Hold

t_OEH

Toggle and

Data# Polling

Time

Min

8

10

ns

t_OEZ

t_CAS

Output Enable to High Z (Note 2)

CE# Setup Time to AVD#

Max

Min

ns

0

Notes:

1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.

2. Not 100% tested.

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D A T A S H E E T

AC CHARACTERISTICS

CE#

t_OE

OE#

t_OEH

WE#

Data

t_CE

t_OEZ

Valid RD

t_ACC

RA

Addresses

AVD#

t_AAVDH

t_CAS

t_AVDP

t_AAVDS

Note: RA = Read Address, RD = Read Data.

Figure 31. Asynchronous Mode Read with Latched Addresses

CE#

OE#

t_OE

t_OEH

WE#

Data

t_CE

t_OEZ

Valid RD

t_ACC

RA

Addresses

AVD#

Note: RA = Read Address, RD = Read Data.

Figure 32. Asynchronous Mode Read

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Am29BDS128H/Am29BDS640H

67

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

All Speed

Options

JEDEC

Std

Description

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Readyw

Max

20

μs

RESET# Pin Low (NOT During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

RESET# Pulse Width

Min

500

200

20

ns

μs

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

t_RPD

Note: Not 100% tested.

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

CE#, OE#

RESET#

t_Readyw

t_RP

Figure 33. Reset Timings

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27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

Erase/Program Operations

Parameter

JEDEC Standard Description

75 MHz

66 MHz

54 MHz

Unit

t_AVAV

t_WC

Write Cycle Time (Note 1)

Min

45

50

55

5

ns

Address Setup

Time (Notes 2,

3)

Synchronous

Asynchronous

4

t_AVWL

t_AS

ns

0

6

Address Hold

Time (Notes 2,

3)

Synchronous

Asynchronous

5.5

15

7

t_WLAX

t_AH

Min

20

t_AVDP

t_DS

AVD# Low Time

Data Setup Time

Data Hold Time

Min

10

20

12

45

ns

t_DVWH

t_WHDX

t_GHWL

t_DH

0

t_GHWL

t_CAS

t_CH

Read Recovery Time Before Write

CE# Setup Time to AVD#

CE# Hold Time

t_WHEH

t_WLWH

t_WHWL

t_WP

Write Pulse Width

20

30

20

t_WPH

t_SR/W

t_VID

Write Pulse Width High

15

20

0

Latency Between Read and Write Operations Min

V_ACCRise and Fall Time

Min

500

V_ACCSetup Time (During Accelerated

Programming)

t_VIDS

1

µs

t_VCS

t_CS

V_CCSetup Time

Min

Max

Typ

50

0

µs

ns

µs

t_ELWL

CE# Setup Time to WE#

t_AVSW

t_AVHW

t_ACS

t_ACH

t_AVHC

t_CSW

t_SEA

AVD# Setup Time to WE#

AVD# Hold Time to WE#

4

5

7

5

Address Setup Time to CLK (Notes 2, 3)

Address Hold Time to CLK (Notes 2, 3)

AVD# Hold Time to CLK

5.5

6

4

Clock Setup Time to WE#

Sector Erase Accept Timeout

Erase Suspend Latency

5

50

t_ESL

35

t_ASP

Toggle Time During Sector Protection

100

Toggle Time During Programming within a

Protected Sector

t_PSP

Typ

1

µs

Notes:

1. Not 100% tested.

program operation timing, addresses are latched on the first of either

the falling edge of WE# or the active edge of CLK.

2. Asynchronous mode allows both Asynchronous and Synchronous

program operation. Synchronous mode allows both Asynchronous

and Synchronous program operation.

4. See the “Erase and Programming Performance” section for more

information.

3. In asynchronous program operation timing, addresses are latched

on the falling edge of WE# or rising edge of AVD#. In synchronous

5. Does not include the preprogramming time.

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69

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

PA

VA

Addresses

Data

555h

In

Complete

A0h

PD

t_DS

t_DH

Progress

CE#f

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V_CC

f

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. Amax–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V_ILor V_IH.

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.

Figure 34. Asynchronous Program Operation Timings: AVD# Latched Addresses

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Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVSW

t_AVHW

AVD#

t_AVDP

t_AS

t_AH

Addresses

Data

555h

VA

PA

In

A0h

Complete

PD

Progress

t_DS

t_DH

CE#f

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V

_CCf

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. Amax–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V_ILor V_IH.

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.

Figure 35. Asynchronous Program Operation Timings: WE# Latched Addresses

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71

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_ACS

t_ACH

AVD#

t_AVDP

Addresses

555h

PA

VA

In

Data

Complete

A0h

PD

t_DS

t_DH

Progress

t_CAS

CE#f

OE#

t_CH

t_CSW

t_WP

WE#

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

f

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. Amax–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The

Configuration Register must be set to the Synchronous Read Mode.

Figure 36. Synchronous Program Operation Timings: WE# Latched Addresses

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Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_AS

t_AH

AVD#

t_AVDP

Addresses

555h

PA

VA

In

Data

Complete

A0h

PD

t_DS

t_DH

Progress

t_CAS

CE#f

t_CH

OE#

WE#

t_CSW

t_WP

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

f

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. Amax–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The

Configuration Register must be set to the Synchronous Read Mode.

Figure 37. Synchronous Program Operation Timings: CLK Latched Addresses

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73

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

SA

555h for

chip erase

VA

Addresses

Data

2AAh

10h for

chip erase

In

Complete

55h

30h

Progress

t_DS

t_DH

CE#

t_CH

OE#

WE#

t_WP

t_WHWH2

t_CS

t_WPH

t_WC

t_VCS

V_CC

Figure 38. Chip/Sector Erase Command Sequence

Notes:

1. SA is the sector address for Sector Erase.

2. Address bits Amax–A12 are don’t cares during unlock cycles in the command sequence.

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27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

CE#

AVD#

WE#

Addresses

Data

PA

Don't Care

A0h

PD

Don't Care

OE#

t_VIDS

1 μs

V

ID

ACC

t_VID

V

or V

IH

IL

Note: Use setup and hold times from conventional program operation.

Figure 39. Accelerated Programming Timing

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

75

D A T A S H E E T

AC CHARACTERISTICS

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

t_OEH

WE#

t_ACC

VA

Addresses

Data

VA

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,

and Data# Polling will output true data.

3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 40. Data# Polling Timings (During Embedded Algorithm)

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

Addresses

Data

VA

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,

the toggle bits will stop toggling.

3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 41. Toggle Bit Timings (During Embedded Algorithm)

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Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

CE#

CLK

AVD#

Addresses

OE#

VA

t_IACC

Data

Status Data

RDY

Notes:

1. The timings are similar to synchronous read timings.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the

toggle bits will stop toggling.

3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one

clock cycle before data.

Figure 42. Synchronous Data Polling Timings/Toggle Bit Timings

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 43. DQ2 vs. DQ6

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77

D A T A S H E E T

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RDY High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

RDY

t_RRB

t_RSP

Figure 44. Temporary Sector Unprotect Timing Diagram

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Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

V

ID

IH

V

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 45. Sector/Sector Block Protect and

Unprotect Timing Diagram

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Am29BDS128H/Am29BDS640H

79

D A T A S H E E T

AC CHARACTERISTICS)

Address boundary occurs every 64 words, beginning at address

00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

C65

41

C66

42

C67

43

CLK

3C

Address (hex)

(stays high)

AVD#

RDY(1)

RDY(2)

t_RACC

latency

t_RACC

latency

Data

D60

D61

D62

D63

D64

D65

D66

D67

Notes:

1. RDY active with data (A18 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing

a bank in the process of performing an erase or program.

4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at

the boundary crossing.

Figure 46. Latency with Boundary Crossing

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Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

Address boundary occurs every 64 words, beginning at address

00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

CLK

3C

Address (hex)

(stays high)

AVD#

RDY(1)

RDY(2)

t_RACC

latency

t_RACC

latency

Data

Invalid

D60

D61

D62

D63

Read Status

OE#,

CE#

(stays low)

Notes:

1. RDY active with data (A18 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a

bank in the process of performing an erase or program.

Figure 47. Latency with Boundary Crossing

into Program/Erase Bank

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81

D A T A S H E E T

AC CHARACTERISTICS

Data

D0

D1

Rising edge of next clock cycle

following last wait state triggers

next burst data

AVD#

OE#

total number of clock cycles

following AVD# falling edge

1

2

0

3

1

4

5

6

4

7

5

CLK

2

3

number of clock cycles

programmed

Wait State Decoding Addresses:

A14, A13, A12 = “111” ⇒ Reserved

A14, A13, A12 = “110” ⇒ Reserved

A14, A13, A12 = “101” ⇒ 5 programmed, 7 total

A14, A13, A12 = “100” ⇒ 4 programmed, 6 total

A14, A13, A12 = “011” ⇒ 3 programmed, 5 total

A14, A13, A12 = “010” ⇒ 2 programmed, 4 total

A14, A13, A12 = “001” ⇒ 1 programmed, 3 total

A14, A13, A12 = “000” ⇒ 0 programmed, 2 total

Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.

Figure 48. Example of Wait States Insertion

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Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

AC CHARACTERISTICS

Last Cycle in

Program or

Sector Erase

Read status (at least two cycles) in same bank

and/or array data from other bank

Begin another

write or program

command sequence

Command Sequence

t_WC

t_RC

t_WC

CE#

OE#

t_OE

t_OEH

t_GHWL

WE#

Data

t_WPH

t_OEZ

t_WP

t_DS

t_ACC

t_OEH

t_DH

PD/30h

RD

AAh

t_SR/W

RA

Addresses

AVD#

PA/SA

t_AS

RA

555h

t_AH

Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking

the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information.

Figure 49. Back-to-Back Read/Write Cycle Timings

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83

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

Comments

32 Kword

4 Kword

128 Mb

64 Mb

0.4

0.2

103

54

5

Sector Erase Time

s

Excludes 00h programming prior to erasure

(Note 4)

s

Chip Erase Time

Word Programming Time

9

210

120

226.5

114

99

µs

s

Accelerated Word Programming Time

4

Excludes system level overhead (Note 5)

128 Mb

75.5

38

Chip Programming Time

(Note 3)

64 Mb

s

128 Mb

33

s

Accelerated Chip

Programming Time

64 Mb

17

30

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V_CC, 1 million cycles. Additionally,

programming typicals assumes a checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 1.65 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 20, “Memory Array Command Definitions,” on page 46 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1 million cycles.

BGA BALL CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

4.2

5.4

3.9

Max

5.0

6.5

4.7

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

84

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

PHYSICAL DIMENSIONS

VBB080—80-ball Fine-Pitch Ball Grid Array (BGA) 11.5 x 9 mm Package

D

D1

A

e

0.05

(2X)

C

8

7

6

5

4

3

2

1

e

7

SE

E1

E

M

L

K

J

H

G

F

E

D

C

B

A

A1 CORNER

INDEX MARK

10

7

B

PIN A1

CORNER

6

SD

NXφb

0.05

(2X)

C

φ 0.08

φ 0.15

M

C

C A

B

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.10

C

A2

A

0.08 C

C

A1

SEATING PLANE

NOTES:

PACKAGE

JEDEC

VBB 080

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

11.50 mm x 9.00 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

---

NOM

---

MAX

1.00

---

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

OVERALL THICKNESS

BALL HEIGHT

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.20

0.62

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

---

0.76

BODY THICKNESS

BODY SIZE

11.50 BSC.

9.00 BSC.

8.80 BSC.

5.60 BSC.

12

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

8

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

80

φb

0.30

0.35

0.40

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

0.40 BSC.

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

8. NOT USED.

(A3-A6, B3-B6, L3-L6, -M3-M6) DEPOPULATED SOLDER BALLS

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3233 \ 16-038.9h

Note: BSC is an ANSI standard for Basic Space Centering

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

85

D A T A S H E E T

PHYSICAL DIMENSIONS

VBD064—64-ball Fine-Pitch Ball Grid Array (BGA) 9 x 8 mm Package

D

D1

A

0.05

(2X)

C

8

7

6

5

7

e

SE

E

B

E1

4

3

2

1

H

G

F

E

C

B

A

D

INDEX MARK

10

PIN A1

CORNER

A1 CORNER

SD

6

NXφb

0.05

(2X)

C

φ 0.08

φ 0.15

M

C

TOP VIEW

C A B

BOTTOM VIEW

0.10

C

A2

A

0.08 C

A1

SEATING PLANE

C

SIDE VIEW

NOTES:

PACKAGE

JEDEC

VBD 064

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

8.95 mm x 7.95 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

---

NOM

---

MAX

1.00

0.30

0.76

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

OVERALL THICKNESS

BALL HEIGHT

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.20

0.62

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

---

BODY THICKNESS

BODY SIZE

8.95 BSC.

7.95 BSC.

5.60 BSC.

8

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

8

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

64

φb

0.30

0.35

0.40

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

0.40 BSC.

NONE

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3246 \ 16-038.9

Note: BSC is an ANSI standard for Basic Space Centering

86

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A T A S H E E T

command. Updated PPB Program, Erase, Status com-

REVISION SUMMARY

Revision A (November 5, 2002)

Initial release.

mands to require Sector Block Address (SBA).

DC Characteristics

Updated I , I

, I

IO1 CC1 CC3 CC4 CC6

Revision B (February 2, 2004)

Global

Test Conditions

Updated Input Rise and Fall Times.

Power Up

Incorporated Am29BDS640H specifications from pub-

lication 27241.

V

CC

Added Ramp Rate information.

Removed 1.5 V V option. Changed 80 MHz speed

IO

grade to 75 MHz.

CLK Characterization

In-System Sector Protection/Sector Unprotection

Algorithms

Added section.

Revision B+1 (August 10, 2004)

Global

Changed “Wait 15 ms” to “Wait 1.5 ms.”

Password Protection Mode Locking Bit;

Persistent Sector Protection Mode Locking Bit

Program Command;

Incorporated Am29BDS640H specifications from pub-

lication 27241.

SecSi Sector Protection Bit Program Command;

PPB Program Command; All PPB Erase Command

Updated speed options offered.

Revision B2 (September 30, 2005)

Updated description for these sections.

Ordering Information

Command Definitions

Added package type VF (Pb-free Package (VBB080))

Revision B3 (May 10, 2006)

Changed WP to (01000010). Set Configuration Reg-

ister command is not available in Unlock Bypass Mode

Removed Password Protection Locking Bit Read

command and Persistent Protection Locking Bit Read

Added migration and obsolescence information for

Am29BDS640H. Removed Preliminary designation

from document.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to

you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-

vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-

sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

87


型号：	AM29BDS128HE9VFI
厂家：	AMD
描述：	128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory 128或64兆比特（ 8 M或4米×16位） CMOS 1.8伏只同步读/写，突发模式闪存闪存
文件：	总89页 (文件大小：1587K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29BDS128HE9VFI [AMD]

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