AM29BDS128HF8VKI_技术文档

Am29BDS128H/Am29BDS064H

128 or 64 Megabit (8 M or 4 M x 16-Bit)

CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode

Flash Memory

PRELIMINARY

INFORMATION

Datasheet

Distinctive Characteristics

Power dissipation (typical values, C_L= 30 pF)

— Burst Mode Read: 10 mA

— Simultaneous Operation: 25 mA

— Program/Erase: 15 mA

Architectural Advantages

Single 1.8 volt read, program and erase (1.65 to

1.95 volt)

Manufactured on 0.13 µm process technology

— Standby mode: 0.2 µA

VersatileIO™ (V_IO) Feature

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V_IOpin

Hardware Features

Handshaking feature

— Provides host system with minimum possible latency

by monitoring RDY

— 1.8V compatible I/O signals

Simultaneous Read/Write operation

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

— Four bank architecture:

— Reduced Wait-state handshaking option further

reduces initial access cycles required for burst

accesses beginning on even addresses

Hardware reset input (RESET#)

— Hardware method to reset the device for reading

array data

128 Mb has 16/48/48/16 Mbit banks

64 Mb has 8/24/24/8 Mbit banks

WP# input

Programable Burst Interface

— Write protect (WP#) function allows protection of the

four highest and four lowest 4 kWord boot sectors,

regardless of sector protect status

— 2 Modes of Burst Read Operation

— Linear Burst: 8, 16, and 32 words with wrap-around

— Continuous Sequential Burst

Persistent Sector Protection

TM

SecSi (Secured Silicon) Sector region

— A command sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector

— Up to 128 words accessible through a command

sequence

— Up to 64 factory-locked words

— Up to 64 customer-lockable words

Sector Architecture

— Banks A and D each contain both 4 Kword sectors

and 32 Kword sectors; Banks B and C contain ninety-

six 32 Kword sectors

— Sectors can be locked and unlocked in-system at V_CC

level

Password Sector Protection

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

— Sixteen 4 Kword boot sectors

Half of the boot sectors are at the top of the address

range; half are at the bottom of address range

ACC input: Acceleration function reduces

programming time; all sectors locked when ACC =

V_IL

100,000 erase cycles per sector typical

20 year data retention typical

80-ball FBGA package (128 Mb) or 64-ball FBGA

(64 Mb) package

CMOS compatible inputs, CMOS compatible outputs

Low V_CCwrite inhibit

Performance Characteristics

Software Features

Read access times at 75/66/54 MHz (C_L=30 pF)

— Burst access times of 9.3/11/13.5 ns at industrial

temperature range

Supports Common Flash Memory Interface (CFI)

Software command set compatible with JEDEC

42.4 standards

— Synchronous latency of 49/56/69 ns

— Asynchronous random access times of 45/50/55 ns

— Backwards compatible with Am29F and Am29LV

families

Publication Number 27024 Revision A Amendment 5 Issue Date June 18, 2004

This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the

right to change or discontinue work on this proposed product without notice.

P r e l i m i n a r y I n f o r m a t i o n

Data# Polling and toggle bits

— Provides a software method of detecting program

and erase operation completion

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

Erase Suspend/Resume

Burst Suspend/Resume

— Suspends an erase operation to read data from, or

program data to, a sector that is not being erased,

then resumes the erase operation

— Suspends a burst operation to allow system use of

the address and data bus, than resumes the burst at

the previous state

2

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

General Description

The Am29BDS128H/Am29BDS064H is a 128 or 64 Mbit, 1.8 Volt-only, simulta-

neous Read/Write, Burst Mode Flash memory device, organized as 8,388,608 or

4,194,304 words of 16 bits each. This device uses a single V of 1.65 to 1.95 V

CC

to read, program, and erase the memory array. A 12.0-volt V

on ACC may be

HH

used for faster program performance if desired. The device can also be pro-

grammed in standard EPROM programmers.

At 75 MHz, the device provides a burst access of 9.3 ns at 30 pF with a latency

of 49 ns at 30 pF. At 66 MHz, the device provides a burst access of 11 ns at 30

pF with a latency of 56 ns at 30 pF. At 54 MHz, the device provides a burst access

of 13.5 ns at 30 pF with a latency of 69ns at 30 pF. The device operates within

the industrial temperature range of -40°C to +85°C. The device is offered in

FBGA packages.

The Simultaneous Read/Write architecture provides simultaneous operation

by dividing the memory space into four banks. The device can improve overall

system performance by allowing a host system to program or erase in one bank,

then immediately and simultaneously read from another bank, with zero latency.

This releases the system from waiting for the completion of program or erase op-

erations.

The device is divided as shown in the following table:

Quantity

Bank

128 Mb

64 Mb

8

Size

8

4 Kwords

32 Kwords

4 Kwords

A

31

96

31

8

15

48

15

8

B

C

D

The VersatileIO™ (V ) control allows the host system to set the voltage levels

IO

that the device generates at its data outputs and the voltages tolerated at its data

inputs to the same voltage level that is asserted on the V pin.

IO

The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#)

and Output Enable (OE#) to control asynchronous read and write operations. For

burst operations, the device additionally requires Ready (RDY), and Clock (CLK).

This implementation allows easy interface with minimal glue logic to a wide range

of microprocessors/microcontrollers for high performance read operations.

The burst read mode feature gives system designers flexibility in the interface to

the device. The user can preset the burst length and wrap through the same

memory space, or read the flash array in continuous mode.

The clock polarity feature provides system designers a choice of active clock

edges, either rising or falling. The active clock edge initiates burst accesses and

determines when data will be output.

The device is entirely command set compatible with the JEDEC 42.4 single-

power-supply Flash standard. Commands are written to the command regis-

ter using standard microprocessor write timing. Register contents serve as inputs

to an internal state-machine that controls the erase and programming circuitry.

Write cycles also internally latch addresses and data needed for the programming

and erase operations. Reading data out of the device is similar to reading from

other Flash or EPROM devices.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

3

P r e l i m i n a r y I n f o r m a t i o n

The Erase Suspend/Erase Resume feature enables the user to put erase on

hold for any period of time to read data from, or program data to, any sector that

is not selected for erasure. True background erase can thus be achieved. If a read

is needed from the SecSi Sector area (One Time Program area) after an erase

suspend, then the user must use the proper command sequence to enter and exit

this region.

The hardware RESET# pin terminates any operation in progress and resets the

internal state machine to reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also reset the device, enabling

the system microprocessor to read boot-up firmware from the Flash memory de-

vice.

The host system can detect whether a program or erase operation is complete by

using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After

a program or erase cycle has been completed, the device automatically returns

to reading array data.

The sector erase architecture allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low V detector that automat-

CC

ically inhibits write operations during power transitions. The device also offers

two types of data protection at the sector level. When at V , WP# locks the four

IL

highest and four lowest boot sectors.

The device offers two power-saving features. When addresses have been stable

for a specified amount of time, the device enters the automatic sleep mode.

The system can also place the device into the standby mode. Power consump-

tion is greatly reduced in both modes.

The device electrically erases all bits within a sector simultaneously via Fowler-

Nordheim tunnelling. The data is programmed using hot electron injection.

4

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Table of Contents

Table 11. Primary Vendor-Specific Extended Query ................ 27

Table 12. Am29BDS128H Sector Address Table ..................... 28

Table 13. Am29BDS064H Sector Address Table ..................... 32

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .7

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block Diagram of Simultaneous Operation

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 34

Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Reading Array Data ........................................................................................... 34

Set Configuration Register Command Sequence .....................................34

Figure 3. Synchronous/Asynchronous State Diagram.............. 34

Read Mode Setting .........................................................................................34

Programmable Wait State Configuration ............................................... 34

Table 14. Programmable Wait State Settings ......................... 35

Reduced Wait-state Handshaking Option .............................................. 35

Table 15. Wait States for Reduced Wait-state Handshaking .... 35

Standard Handshaking Option ................................................................... 35

Table 16. Wait States for Standard Handshaking ................... 35

Read Mode Configuration ........................................................................... 36

Table 17. Read Mode Settings ............................................. 36

Burst Active Clock Edge Configuration .................................................. 36

RDY Configuration ........................................................................................36

Table 18. Configuration Register .......................................... 37

Reset Command ................................................................................................. 37

Autoselect Command Sequence .................................................................... 37

Table 19. Autoselect Data ................................................... 38

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................38

Program Command Sequence ........................................................................38

Unlock Bypass Command Sequence ........................................................38

Figure 4. Program Operation............................................... 39

Chip Erase Command Sequence ...................................................................39

Sector Erase Command Sequence ................................................................ 39

Erase Suspend/Erase Resume Commands ..................................................40

Figure 5. Erase Operation................................................... 41

Password Program Command ........................................................................41

Password Verify Command ..............................................................................41

Password Protection Mode Locking Bit Program Command ...............41

Persistent Sector Protection Mode Locking Bit Program Command .41

SecSi Sector Protection Bit Program Command ......................................42

PPB Lock Bit Set Command ............................................................................42

DYB Write Command ......................................................................................42

Password Unlock Command ..........................................................................42

PPB Program Command ..................................................................................42

Figure 6. PPB Program Algorithm......................................... 43

All PPB Erase Command ..................................................................................43

Figure 7. All PPB Erase Algorithm......................................... 43

DYB Write Command ......................................................................................43

PPB Status Command .......................................................................................44

PPB Lock Bit Status Command ......................................................................44

DYB Status Command ......................................................................................44

Command Definitions .......................................................................................44

Table 20. Memory Array Command Definitions ..................... 44

Table 21. Sector Protection Command Definitions ................. 46

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations .......................................... 10

Requirements for Asynchronous Read Operation (Non-Burst) .......... 10

Requirements for Synchronous (Burst) Read Operation .......................10

8-, 16-, and 32-Word Linear Burst with Wrap Around ....................... 11

Table 2. Burst Address Groups ............................................ 11

Burst Suspend/Resume ....................................................................................... 11

Configuration Register ...................................................................................... 12

Reduced Wait-state Handshaking Option .................................................. 12

Simultaneous Read/Write Operations with Zero Latency .................... 12

Writing Commands/Command Sequences ................................................. 12

Accelerated Program Operation ....................................................................13

Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Autoselect Codes (High Voltage Method) ................. 14

Table 4. Am29BDS128H Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 15

Table 5. Am29BDS064H Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 16

Sector/Sector Block Protection and Unprotection .................................. 16

Sector Protection ........................................................................................... 16

Selecting a Sector Protection Mode ..........................................................17

Persistent Sector Protection ............................................................................17

Persistent Protection Bit (PPB) ...................................................................17

Persistent Protection Bit Lock (PPB Lock) ..............................................17

Dynamic Protection Bit (DYB) ....................................................................17

Table 6. Sector Protection Schemes ..................................... 18

Persistent Sector Protection Mode Locking Bit ........................................ 18

Password Protection Mode ............................................................................. 19

Password and Password Mode Locking Bit ................................................ 19

64-bit Password ................................................................................................... 19

Persistent Protection Bit Lock ........................................................................ 19

High Voltage Sector Protection .....................................................................20

Standby Mode ......................................................................................................20

Automatic Sleep Mode .....................................................................................20

RESET#: Hardware Reset Input ................................................................20

Output Disable Mode ...................................................................................20

Figure 1. Temporary Sector Unprotect Operation.................... 21

Figure 2. In-System Sector Protection/Sector Unprotection

Algorithms ........................................................................ 22

SecSi™ (Secured Silicon) Sector

Flash Memory Region ........................................................................................23

Factory-Locked Area (64 words) ..............................................................23

Table 7. SecSi^TMSector Addresses ........................................ 23

Customer-Lockable Area (64 words) ......................................................23

SecSi Sector Protection Bits ........................................................................23

Hardware Data Protection ..........................................................................23

Write Protect (WP#) ....................................................................................... 24

Write Operation Status . . . . . . . . . . . . . . . . . . . . 47

DQ7: Data# Polling ............................................................................................47

Figure 8. Data# Polling Algorithm........................................ 48

DQ6: Toggle Bit I ...............................................................................................48

Figure 9. Toggle Bit Algorithm............................................. 49

DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 22. DQ6 and DQ2 Indications ..................................... 50

Reading Toggle Bits DQ6/DQ2 .....................................................................50

DQ5: Exceeded Timing Limits ........................................................................50

DQ3: Sector Erase Timer ................................................................................50

Table 23. Write Operation Status ......................................... 51

Low V Write Inhibit ................................................................................. 24

CC

Write Pulse “Glitch” Protection ............................................................... 24

Logical Inhibit .................................................................................................. 24

Power-Up Write Inhibit ............................................................................... 24

Common Flash Memory Interface (CFI) . . . . . . 24

Table 8. CFI Query Identification String ................................ 25

Table 9. System Interface String.......................................... 25

Table 10. Device Geometry Definition ................................... 26

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

5

P r e l i m i n a r y I n f o r m a t i o n

Figure 27. Standard Handshake Burst Suspend at address 3Fh

(starting address 3Dh or earlier).......................................... 63

Figure 28. Standard Handshake Burst Suspend at address

3Eh/3Fh (without a valid Initial Access) ................................ 63

AC Characteristics ............................................................................................64

Figure 29. Standard Handshake Burst Suspend at address

3Eh/3Fh (with 1 Access CLK)............................................... 64

Figure 30. Read Cycle for Continuous Suspend ...................... 64

Asynchronous Mode Read ............................................................................. 65

Figure 31. Asynchronous Mode Read with Latched Addresses... 66

Figure 32. Asynchronous Mode Read .................................... 66

Figure 33. Reset Timings .................................................... 67

Erase/Program Operations ..............................................................................68

Figure 34. Asynchronous Program Operation Timings: AVD#

Latched Addresses............................................................. 69

Figure 35. Asynchronous Program Operation Timings: WE#

Latched Addresses............................................................. 70

Figure 36. Synchronous Program Operation Timings: WE#

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 51

Figure 10. Maximum Negative Overshoot Waveform............... 52

Figure 11. Maximum Positive Overshoot Waveform................. 52

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 52

Industrial (I) Devices ......................................................................................52

Supply Voltages ................................................................................................52

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 53

CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . .53

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 12. Test Setup ......................................................... 54

Table 24. Test Specifications ............................................... 54

Key to Switching Waveforms . . . . . . . . . . . . . . . 54

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 54

Figure 13. Input Waveforms and Measurement Levels............. 54

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .55

V

Power-up ......................................................................................................55

CC

Figure 14. V_CCPower-up Diagram ........................................ 55

Latched Addresses............................................................. 71

Figure 37. Synchronous Program Operation Timings: CLK Latched

Addresses......................................................................... 72

Figure 38. Chip/Sector Erase Command Sequence ................. 73

Figure 39. Accelerated Unlock Bypass Programming Timing..... 74

Figure 40. Data# Polling Timings (During Embedded Algorithm) 75

Figure 41. Toggle Bit Timings (During Embedded Algorithm) ... 75

Figure 42. Synchronous Data Polling Timings/Toggle Bit Timings76

Figure 43. DQ2 vs. DQ6...................................................... 76

Temporary Sector Unprotect ........................................................................ 77

Figure 44. Temporary Sector Unprotect Timing Diagram ......... 77

Figure 45. Sector/Sector Block Protect and Unprotect

Timing Diagram................................................................. 78

Figure 46. Latency with Boundary Crossing ........................... 79

Figure 47. Latency with Boundary Crossing

into Program/Erase Bank .................................................... 80

Figure 48. Example of Wait States Insertion.......................... 81

Figure 49. Back-to-Back Read/Write Cycle Timings................. 82

CLK Characterization ........................................................................................55

Figure 15. CLK Characterization ........................................... 55

Synchronous/Burst Read .................................................................................56

Figure 16. CLK Synchronous Burst Mode Read

(Rising Active CLK)............................................................. 57

Figure 17. CLK Synchronous Burst Mode Read

(Falling Active Clock).......................................................... 57

Figure 18. Synchronous Burst Mode Read.............................. 58

Figure 19. 8-word Linear Burst with Wrap Around................... 58

Figure 20. Linear Burst with RDY Set One Cycle Before Data.... 59

Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume

at an even address............................................................. 60

Figure 22. Reduced Wait-state Handshake Burst Suspend/Resume

at an odd address .............................................................. 60

Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume

at address 3Eh (or offset from 3Eh)...................................... 61

Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume

at address 3Fh (or offset from 3Fh by a multiple of 64)........... 61

Figure 25. Standard Handshake Burst Suspend prior to

Erase and Programming Performance . . . . . . . . 83

BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . 83

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 84

Initial Access ..................................................................... 62

Figure 26. Standard Handshake Burst Suspend at or after

Initial Access ..................................................................... 62

6

Am29BDS128H/Am29BDS064H

27024_00_A5_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Product Selector Guide

Part Number

Am29BDS128H/Am29BDS064H

Burst Frequency

75 MHz

F8, F9

66 MHz

E8, E9

54 MHz

D8, D9

V

, V = 1.65 –

IO

CC

Speed Option

1.95 V

Max Initial Synchronous Access Time, ns (T_IACC

)

49

56

69

Reduced Wait-state Handshaking; Even Address

Max Initial Synchronous Access Time, ns (T_IACC

Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking

Max Burst Access Time, ns (T_BACC

Max Asynchronous Access Time, ns (T_ACC

Max CE# Access Time, ns (T_CE

Max OE# Access Time, ns (T_OE

)

62

71

11

87.5

13.5

)

9.3

)

45

50

55

)

9.3

11

13.5

Note: Speed Options ending in “8” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous

accesses for even addresses. Speed Options ending in “9” indicate the “standard handshaking” option. See the AC

Characteristics section of this data sheet for full specifications.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

7

P r e l i m i n a r y I n f o r m a t i o n

Block Diagram

V_CC

V_SS

V_IO

DQ15–DQ0

RDY

Buffer

RDY

Erase Voltage

Generator

Input/Output

Buffers

WE#

RESET#

WP#

State

Control

ACC

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

CE#

OE#

Y-Decoder

Y-Gating

V_CC

Detector

Timer

Cell Matrix

X-Decoder

Burst

State

Control

Burst

Address

Counter

AVD#

CLK

Amax–A0

Note: A

= A22 (128 Mb) or A21 (64 Mb)

max

8

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Block Diagram of Simultaneous Operation Circuit

V

CC

V

SS

V

IO

Bank A Address

DQ15–DQ0

Bank A

Amax–A0

X-Decoder

OE#

Bank B Address

DQ15–DQ0

Bank B

WP#

ACC

X-Decoder

Amax–A0

STATE

CONTROL

&

COMMAND

REGISTER

RESET#

WE#

DQ15–DQ0

Status

CE#

AVD#

RDY

Control

Amax–A0

DQ15–DQ0

X-Decoder

Bank C

DQ15–DQ0

Bank C Address

Amax –A0

X-Decoder

Bank D

Bank D Address

DQ15–DQ0

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

9

P r e l i m i n a r y I n f o r m a t i o n

Device Bus Operations

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory

location. The register is composed of latches that

store the commands, along with the address and data

information needed to execute the command. The

contents of the register serve as inputs to the internal

state machine. The state machine outputs dictate the

function of the device. Table 1 lists the device bus op-

erations, the inputs and control levels they require,

and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Device Bus Operations

CLK

(See

Operation

CE#

OE#

L

WE# Amax–0 DQ15–0 RESET# Note) AVD#

Asynchronous Read - Addresses Latched

Asynchronous Read - Addresses Steady State

Asynchronous Write

L

H

L

Addr In

HIGH Z

I/O

H

L

X

L

H

I/O

Synchronous Write

L

H

L

I/O

Standby (CE#)

H

X

HIGH Z

X

Hardware Reset

X

Burst Read Operations

Load Starting Burst Address

L

X

L

H

Addr In

HIGH Z

X

H

L

Advance Burst to next address with

appropriate Data presented on the Data Bus

Burst

Data Out

H

X

Terminate current Burst read cycle

H

X

HIGH Z

Terminate current Burst read cycle via

RESET#

X

Terminate current Burst read cycle and start

new Burst read cycle

L

X

H

HIGH Z

I/O

H

Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.

Note: Default active edge of CLK is the rising edge.

The output enable access time (t ) is the delay from

the falling edge of OE# to valid data at the output.

Requirements for Asynchronous Read

Operation (Non-Burst)

OE

The internal state machine is set for reading array

data in asynchronous mode upon device power-up, or

after a hardware reset. This ensures that no spurious

alteration of the memory content occurs during the

power transition.

To read data from the memory array, the system must

first assert a valid address on Amax–A0, while driving

AVD# and CE# to V . WE# should remain at V . The

IL

IH

rising edge of AVD# latches the address. The data will

appear on DQ15–DQ0. Since the memory array is di-

vided into four banks, each bank remains enabled for

read access until the command register contents are

altered.

Requirements for Synchronous (Burst)

Read Operation

The device is capable of continuous sequential burst

operation and linear burst operation of a preset

length. When the device first powers up, it is enabled

for asynchronous read operation.

Address access time (t

stable addresses to valid output data. The chip enable

) is equal to the delay from

ACC

access time (t ) is the delay from the stable ad-

CE

dresses and stable CE# to valid data at the outputs.

10

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Prior to entering burst mode, the system should de-

termine how many wait states are desired for the

initial word (t ) of each burst access, what mode of

completed the program or erase operation, the host

can restart a burst operation using a new address and

AVD# pulse.

IACC

burst operation is desired, which edge of the clock will

be the active clock edge, and how the RDY signal will

transition with valid data. The system would then

write the configuration register command sequence.

See “Set Configuration Register Command Sequence”

section on page 34 and “Command Definitions” sec-

tion on page 34 for further details.

If the clock frequency is less than 6 MHz during a burst

mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

8-, 16-, and 32-Word Linear Burst with

Wrap Around

The remaining three modes are of the linear wrap

around design, in which a fixed number of words are

read from consecutive addresses. In each of these

modes, the burst addresses read are determined by

the group within which the starting address falls. The

groups are sized according to the number of words

read in a single burst sequence for a given mode (see

Table 2.)

Once the system has written the “Set Configuration

Register” command sequence, the device is enabled

for synchronous reads only.

The initial word is output t

after the active edge of

IACC

the first CLK cycle. Subsequent words are output

after the active edge of each successive clock

t

BACC

cycle, which automatically increments the internal ad-

dress counter. Note that the device has a fixed internal

address boundary that occurs every 64 words, start-

ing at address 00003Fh. During the time the device is

outputting data at this fixed internal address bound-

ary (address 00003Fh, 00007Fh, 0000BFh, etc.), a

two cycle latency occurs before data appears for the

next address (address 000040h, 000080h, 0000C0h,

etc.). The RDY output indicates this condition to the

system by pulsing low. For standard handshaking de-

vices, there is no two cycle latency between 3Fh and

40h (or offset from these values by a multiple of 64)

if the latched address was 3Eh or 3Fh or offset from

these values by a multiple of 64). See Figure 46, “La-

tency with Boundary Crossing,” on page 79.

Table 2. Burst Address Groups

Mode

8-word

16-word

32-word

Group Size Group Address Ranges

8 words

16 words

32 words

0-7h, 8-Fh, 10-17h,...

0-Fh, 10-1Fh, 20-2Fh,...

00-1Fh, 20-3Fh, 40-5Fh,...

As an example: if the starting address in the 8-word

mode is 39h, the address range to be read would be

38-3Fh, and the burst sequence would be 39-3A-3B-

3C-3D-3E-3F-38h-etc. The burst sequence begins

with the starting address written to the device, but

wraps back to the first address in the selected group.

In a similar fashion, the 16-word and 32-word Linear

Wrap modes begin their burst sequence on the start-

ing address written to the device, and then wrap back

to the first address in the selected address group.

Note that in these three burst read modes the

address pointer does not cross the boundary

that occurs every 64 words; thus, no wait states

are inserted (except during the initial access).

For reduced wait-state handshaking devices, if the ad-

dress latched is 3Eh or 3Fh (or offset from these

values by a multiple of 64) two additional cycle latency

occurs prior to the initial access and the two cycle la-

tency between 3Fh and 40h (or offset from these

values by a multiple of 64) will not occur.

The device will continue to output sequential burst

data, wrapping around to address 000000h after it

reaches the highest addressable memory location,

until the system drives CE# high, RESET# low, or

AVD# low in conjunction with a new address. See

Table 1, “Device Bus Operations,” on page 10.

The RDY pin indicates when data is valid on the bus.

The devices can wrap through a maximum of 128

words of data (8 words up to 16 times, 16 words up

to 8 times, or 32 words up to 4 times) before requiring

a new synchronous access (latching of a new

address).

If the host system crosses the bank boundary while

reading in burst mode, and the device is not program-

ming or erasing, a two-cycle latency will occur as

described above in the subsequent bank. If the host

system crosses the bank boundary while the device is

programming or erasing, the device will provide read

status information. The clock will be ignored. After the

host has completed status reads, or the device has

Burst Suspend/Resume

The Burst Suspend/Resume feature allows the system

to temporarily suspend a synchronous burst operation

during the initial access (before data is available) or

after the device is outputting data. When the burst op-

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

11

P r e l i m i n a r y I n f o r m a t i o n

eration is suspended, any previously latched internal

data and the current state are retained.

The presence of the reduced wait-state handshaking

feature may be verified by writing the autoselect com-

mand sequence to the device. See “Autoselect

Command Sequence” for details.

Burst Suspend requires CE# to be asserted, WE# de-

asserted, and the initial address latched by AVD# or

the CLK edge. Burst Suspend occurs when OE# is de-

asserted. See Figure 21, “Reduced Wait-state Hand-

shake Burst Suspend/Resume at an even address,” on

page 60, Figure 22, “Reduced Wait-state Handshake

Burst Suspend/Resume at an odd address,” on

page 60, Figure 23, “Reduced Wait-state Handshake

Burst Suspend/Resume at address 3Eh (or offset from

3Eh),” on page 61, Figure 24, “Reduced Wait-state

Handshake Burst Suspend/Resume at address 3Fh (or

offset from 3Fh by a multiple of 64),” on page 61,

Figure 25, “Standard Handshake Burst Suspend prior

to Initial Access,” on page 62, Figure 26, “Standard

Handshake Burst Suspend at or after Initial Access,”

on page 62, Figure 27, “Standard Handshake Burst

Suspend at address 3Fh (starting address 3Dh or ear-

lier),” on page 63, Figure 28, “Standard Handshake

Burst Suspend at address 3Eh/3Fh (without a valid

Initial Access),” on page 63, and Figure 29, “Standard

Handshake Burst Suspend at address 3Eh/3Fh (with 1

Access CLK),” on page 64.

For optimal burst mode performance on devices with-

out the reduced wait-state handshaking option, the

host system must set the appropriate number of wait

states in the flash device depending on clock fre-

quency and the presence of a boundary crossing. See

“Set Configuration Register Command Sequence” sec-

tion on page 34 section for more information. The

device will automatically delay RDY and data by one

additional clock cycle when the starting address is

odd.

The autoselect function allows the host system to de-

termine whether the flash device is enabled for

reduced wait-state handshaking. See the “Autoselect

Command Sequence” section for more information.

Simultaneous Read/Write Operations

with Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in another

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 49, “Back-to-Back Read/Write Cycle

Timings,” on page 82 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. Refer to the DC Characteristics table for read-

while-program and read-while-erase current

specifications.

Burst plus Burst Suspend should not last longer than

t

without re-latching an address or crossing an ad-

RCC

dress boundary. To resume the burst access, OE#

must be re-asserted. The next active CLK edge will re-

sume the burst sequence where it had been

suspended. See Figure 30, “Read Cycle for Continu-

ous Suspend,” on page 64.

The RDY pin is only controlled by CE#. RDY will remain

active and is not placed into a high-impedance state

when OE# is de-asserted.

Writing Commands/Command

Sequences

Configuration Register

The device has the capability of performing an asyn-

chronous or synchronous write operation. While the

device is configured in Asynchronous read it is able to

perform Asynchronous write operations only. CLK is

ignored in the Asynchronous programming mode.

When in the Synchronous read mode configuration,

the device is able to perform both Asynchronous and

Synchronous write operations. CLK and WE# address

latch is supported in the Synchronous programming

mode. During a synchronous write operation, to write

a command or command sequence (which includes

programming data to the device and erasing sectors

of memory), the system must drive AVD# and CE# to

V , and OE# to V when providing an address to the

The device uses a configuration register to set the var-

ious burst parameters: number of wait states, burst

read mode, active clock edge, RDY configuration, and

synchronous mode active.

Reduced Wait-state Handshaking Option

The device can be equipped with a reduced wait-state

handshaking feature that allows the host system to

simply monitor the RDY signal from the device to de-

termine when the initial word of burst data is ready to

be read. The host system should use the programma-

ble wait state configuration to set the number of wait

states for optimal burst mode operation. The initial

word of burst data is indicated by the rising edge of

RDY after OE# goes low.

IL

IH

device, and drive WE# and CE# to V , and OE# to V

IL

IH

when writing commands or data. During an asynchro-

nous write operation, the system must drive CE# and

12

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

WE# to V and OE# to V when providing an ad-

ing or unconnected; inconsistent behavior of the

device may result.

IL

IH

dress, command, and data. Addresses are latched on

the last falling edge of WE# or CE#, while data is

latched on the 1st rising edge of WE# or CE#. The

asynchronous and synchronous programing operation

is independent of the Set Device Read Mode bit in the

Configuration Register (see Table 18, “Configuration

Register,” on page 37).

When at V , ACC locks all sectors. ACC should be at

IL

V

for all other conditions.

IH

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output from the internal reg-

ister (which is separate from the memory array) on

DQ15–DQ0. This mode is primarily intended for pro-

gramming equipment to automatically match a device

to be programmed with its corresponding program-

ming algorithm. However, the autoselect codes can

also be accessed in-system through the command

register.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word, instead of four.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 12, “Am29BDS128H

Sector Address Table,” on page 28 indicates the ad-

dress space that each sector occupies. The device

address space is divided into four banks: Banks B and

C contain only 32 Kword sectors, while Banks A and D

contain both 4 Kword boot sectors in addition to 32

Kword sectors. A “bank address” is the address bits

required to uniquely select a bank. Similarly, a “sector

address” is the address bits required to uniquely se-

lect a sector.

When using programming equipment, the autoselect

mode requires V on address pin A9. Address pins

ID

must be as shown in Table 3, “Autoselect Codes (High

Voltage Method),” on page 14. In addition, when ver-

ifying sector protection, the sector address must

appear on the appropriate highest order address bits

(see Table 4, “Am29BDS128H Boot Sector/Sector

Block Addresses for Protection/Unprotection,” on

page 15). Table 3 shows the remaining address bits

that are don’t care. When all necessary bits have been

set as required, the programming equipment may

then read the corresponding identifier code on DQ15–

DQ0. However, the autoselect codes can also be ac-

cessed in-system through the command register, for

instances when the device is erased or programmed in

a system without access to high voltage on the A9 pin.

The command sequence is illustrated in Table 20,

“Memory Array Command Definitions,” on page 44.

Note that if a Bank Address (BA) is asserted during the

third write cycle of the autoselect command, the host

system can read autoselect data that bank and then

immediately read array data from the other bank,

without exiting the autoselect mode.

I

in the “DC Characteristics” section on page 53

CC2

represents the active current specification for the

write mode. The AC Characteristics section contains

timing specification tables and timing diagrams for

write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. ACC is primarily intended to

allow faster manufacturing throughput at the factory.

If the system asserts V on this input, the device au-

HH

tomatically enters the aforementioned Unlock Bypass

mode and uses the higher voltage on the input to re-

duce the time required for program operations. The

system would use a two-cycle program command se-

quence as required by the Unlock Bypass mode.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 20, “Memory

Array Command Definitions,” on page 44. This

Removing V

from the ACC input returns the device

HH

to normal operation. Note that sectors must be un-

locked prior to raising ACC to V . Note that the ACC

pin must not be at V

HH

for operations other than ac-

HH

method does not require V . Autoselect mode may

celerated programming, or device damage may

result. In addition, the ACC pin must not be left float-

ID

only be entered and used when in the asynchronous

read mode. Refer to the “Autoselect Command Se-

quence” section on page 37 for more information.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

13

P r e l i m i n a r y I n f o r m a t i o n

Table 3. Autoselect Codes (High Voltage Method)

Amax A11

to to

A5

to

DQ15

Description

CE# OE# WE# RESET# A12 A10 A9 A8 A7 A6 A4 A3 A2 A1 A0

to DQ0

Manufacturer ID:

Spansion

V_ID

L

H

X

L

X

L

H

L

0001h

227Eh

Read Cycle 1

Read Cycle 2

2218h (128 Mb)

221Eh (64 Mb)

H

X

2200h (128 Mb)

2201h (64 Mb)

Read Cycle 3

H

L

H

L

H

L

Sector Protection

Verification

0001h (protected),

0000h (unprotected)

SA

DQ15 - DQ8 = 0

DQ7 - Factory Lock Bit

1 = Locked, 0 = Not Locked

DQ6 -Customer Lock Bit

1 = Locked, 0 = Not Locked

DQ5 = Handshake Bit

1 = Reduced wait-state

Handshake, 0 = Standard

Handshake

V_ID

Indicator Bits

L

H

X

L

X

L

H

L

DQ4 - DQ0 = 0

Hardware Sector

Group Protection

0001h (protected),

0000h (unprotected)

V_ID

SA

X

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, BA =

Bank Address, SA = Sector Address, X = Don’t care.

Notes:

1. The autoselect codes may also be accessed in-system via command sequences.

2. PPB Protection Status is shown on the data bus

14

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Table 4. Am29BDS128H Boot Sector/Sector Block

Sector/

Addresses for Protection/Unprotection

Sector

A22–A12

Sector Block Size

SA131-SA134

SA135-SA138

SA139-SA142

SA143-SA146

SA147-SA150

SA151–SA154

SA155–SA158

SA159–SA162

SA163–SA166

SA167–SA170

SA171–SA174

SA175–SA178

SA179–SA182

SA183–SA186

SA187–SA190

SA191–SA194

SA195–SA198

SA199–SA202

SA203–SA206

SA207–SA210

SA211–SA214

SA215–SA218

SA219–SA222

SA223–SA226

SA227–SA230

SA231–SA234

SA235–SA238

SA239–SA242

SA243–SA246

SA247–SA250

SA251–SA254

SA255–SA258

SA259

011111XXXXX

100000XXXXX

100001XXXXX

100010XXXXX

100011XXXXX

100100XXXXX

100101XXXXX

100110XXXXX

100111XXXXX

101000XXXXX

101001XXXXX

101010XXXXX

101011XXXXX

101100XXXXX

101101XXXXX

101110XXXXX

101111XXXXX

110000XXXXX

110001XXXXX

110010XXXXX

110011XXXXX

110100XXXXX

110101XXXXX

110110XXXXX

110111XXXXX

111000XXXXX

111001XXXXX

111010XXXXX

111011XXXXX

111100XXXXX

111101XXXXX

111110XXXXX

11111100XXX

11111101XXX

11111110XXX

11111111000

128 (4x32) Kwords

32 Kwords

Sector/

Sector Block Size

Sector

SA0

A22–A12

00000000000

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

00000001XXX

00000010XXX

00000011XXX

000001XXXXX

000010XXXXX

000011XXXXX

000100XXXXX

000101XXXXX

000110XXXXX

000111XXXXX

001000XXXXX

001001XXXXX

001010XXXXX

001011XXXXX

001100XXXXX

001101XXXXX

001110XXXXX

001111XXXXX

010000XXXXX

010001XXXXX

010010XXXXX

010011XXXXX

010100XXXXX

010101XXXXX

010110XXXXX

010111XXXXX

011000XXXXX

011001XXXXX

011010XXXXX

011011XXXXX

011100XXXXX

011101XXXXX

011110XXXXX

4 Kwords

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11–SA14

SA15–SA18

SA19–SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51–SA54

SA55–SA58

SA59–SA62

SA63–SA66

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

128 (4x32) Kwords

SA260

32 Kwords

SA261

32 Kwords

SA262

4 Kwords

SA263

11111111001

4 Kwords

SA264

11111111010

4 Kwords

SA265

11111111011

4 Kwords

SA266

11111111100

4 Kwords

SA267

11111111101

4 Kwords

SA268

11111111110

4 Kwords

SA269

11111111111

4 Kwords

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

15

P r e l i m i n a r y I n f o r m a t i o n

Table 5. Am29BDS064H Boot Sector/Sector Block

Sector/

Addresses for Protection/Unprotection

Sector

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

SA131

A21–A12

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

1111100XXX

1111101XXX

1111110XXX

1111111000

Sector Block Size

128 (4x32) Kwords

32 Kwords

Sector/

Sector

SA0

A21–A12

Sector Block Size

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

4 Kwords

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11–SA14

SA15–SA18

SA19–SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51–SA54

SA55–SA58

SA59–SA62

SA63–SA66

128 (4x32) Kwords

SA132

32 Kwords

SA133

32 Kwords

SA134

4 Kwords

SA135

1111111001

4 Kwords

SA136

1111111010

4 Kwords

SA137

1111111011

4 Kwords

SA138

1111111100

4 Kwords

SA139

1111111101

4 Kwords

SA140

1111111110

4 Kwords

SA141

1111111111

4 Kwords

Sector/Sector Block Protection and Unprotection

The hardware sector protection feature disables both

programming and erase operations in any sector. The

hardware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

and erase operations in certain sectors or sector

groups:

Persistent Sector Protection

A command sector protection method that replaces

the old 12 V controlled protection method.

Password Sector Protection

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that

are protected or unprotected at the same time (see

Table 4, “Am29BDS128H Boot Sector/Sector Block

Addresses for Protection/Unprotection,” on page 15

A highly sophisticated protection method that requires

a password before changes to certain sectors or sector

groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase

operations in the outermost sectors.

Sector Protection

The WP# Hardware Protection feature is always avail-

able, independent of the software managed protection

method chosen.

The Am29WSxxxH family features several levels of

sector protection, which can disable both the program

16

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Selecting a Sector Protection Mode

Persistent Protection Bit (PPB)

All parts default to operate in the Persistent Sector

Protection mode. The customer must then choose if

the Persistent or Password Protection method is most

desirable. There are two one-time programmable

non-volatile bits that define which sector protection

method will be used. If the customer decides to con-

tinue using the Persistent Sector Protection method,

they must set the Persistent Sector Protection

Mode Locking Bit. This will permanently set the part

to operate only using Persistent Sector Protection. If

the customer decides to use the password method,

they must set the Password Mode Locking Bit. This

will permanently set the part to operate only using

password sector protection.

A single Persistent (non-volatile) Protection Bit is as-

signed to a maximum four sectors (“Am29BDS128H

Boot Sector/Sector Block Addresses for Protection/

Unprotection” section on page 15). All 4 Kbyte boot-

block sectors have individual sector Persistent Protec-

tion Bits (PPBs) for greater flexibility. Each PPB is

individually modifiable through the PPB Program

Command.

Note: If a PPB requires erasure, all of the sector PPBs

must first be preprogrammed prior to PPB erasing. All

PPBs erase in parallel, unlike programming where in-

dividual PPBs are programmable. It is the

responsibility of the user to perform the preprogram-

ming operation. Otherwise, an already erased sector

PPBs has the potential of being over-erased. There is

no hardware mechanism to prevent sector PPBs over-

erasure.

It is important to remember that setting either the

Persistent Sector Protection Mode Locking Bit or

the Password Mode Locking Bit permanently se-

lects the protection mode. It is not possible to switch

between the two methods once a locking bit has been

set. It is important that one mode is explicitly

selected when the device is first programmed,

rather than relying on the default mode alone.

This is so that it is not possible for a system program

or virus to later set the Password Mode Locking Bit,

which would cause an unexpected shift from the de-

fault Persistent Sector Protection Mode into the

Password Protection Mode.

Persistent Protection Bit Lock (PPB Lock)

A global volatile bit. When set to “1”, the PPBs cannot

be changed. When cleared (“0”), the PPBs are

changeable. There is only one PPB Lock bit per device.

The PPB Lock is cleared after power-up or hardware

reset. There is no command sequence to unlock the

PPB Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector.

After power-up or hardware reset, the contents of all

DYBs is “0”. Each DYB is individually modifiable

through the DYB Write Command.

The device is shipped with all sectors unprotected.

Spansion offers the option of programming and pro-

tecting sectors at the factory prior to shipping the

device through Spansion’s Programming Service.

Contact the local sales representative for details.

When the parts are first shipped, the PPBs are cleared.

The DYBs and PPB Lock are defaulted to power up in

the cleared state – meaning the PPBs are changeable.

It is possible to determine whether a sector is pro-

tected or unprotected. See “Autoselect Command

Sequence” section on page 37 for details.

When the device is first powered on the DYBs power

up cleared (sectors not protected). The Protection

State for each sector is determined by the logical OR

of the PPB and the DYB related to that sector. For the

sectors that have the PPBs cleared, the DYBs control

whether or not the sector is protected or unprotected.

By issuing the DYB Write command sequences, the

DYBs will be set or cleared, thus placing each sector in

the protected or unprotected state. These are the so-

called Dynamic Locked or Unlocked states. They

are called dynamic states because it is very easy to

switch back and forth between the protected and un-

protected conditions. This allows software to easily

protect sectors against inadvertent changes yet does

not prevent the easy removal of protection when

Persistent Sector Protection

The Persistent Sector Protection method replaces the

old 12 V controlled protection method while at the

same time enhancing flexibility by providing three dif-

ferent sector protection states:

Persistently Locked—A sector is pro-

tected and cannot be changed.

Dynamically Locked—The sector is pro-

tected and can be changed by a simple

command

Unlocked—The sector is unprotected and

can be changed by a simple command

In order to achieve these states, three types of “bits”

are going to be used:

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

17

P r e l i m i n a r y I n f o r m a t i o n

changes are needed. The DYBs maybe set or cleared

Table 6. Sector Protection Schemes

as often as needed.

PPB

The PPBs allow for a more static, and difficult to

change, level of protection. The PPBs retain their state

across power cycles because they are Non-Volatile.

Individual PPBs are set with a command but must all

be cleared as a group through a complex sequence of

program and erasing commands. The PPBs are also

limited to 100 erase cycles.

DYB

PPB

Lock

Sector State

Unprotected—PPB and DYB are

changeable

0

Unprotected—PPB not

changeable, DYB is changeable

0

1

0

1

0

1

0

1

0

1

0

1

Protected—PPB and DYB are

changeable

The PBB Lock bit adds an additional level of protec-

tion. Once all PPBs are programmed to the desired

settings, the PPB Lock may be set to “1”. Setting the

PPB Lock disables all program and erase commands to

the Non-Volatile PPBs. In effect, the PPB Lock Bit locks

the PPBs into their current state. The only way to clear

the PPB Lock is to go through a power cycle. System

boot code can determine if any changes to the PPB are

needed e.g. to allow new system code to be down-

loaded. If no changes are needed then the boot code

can set the PPB Lock to disable any further changes to

the PPBs during system operation.

Protected—PPBnotchangeable,

DYB is changeable

Table 6 contains all possible combinations of the DYB,

PPB, and PPB lock relating to the status of the sector.

In summary, if the PPB is set, and the PPB lock is set,

the sector is protected and the protection can not be

removed until the next power cycle clears the PPB

lock. If the PPB is cleared, the sector can be dynami-

cally locked or unlocked. The DYB then controls

whether or not the sector is protected or unprotected.

The WP# write protect pin adds a final level of hard-

ware protection to the four highest and four lowest 4

Kbyte sectors. When this pin is low it is not possible to

change the contents of these four sectors. These sec-

tors generally hold system boot code. So, the WP# pin

can prevent any changes to the boot code that could

override the choices made while setting up sector pro-

tection during system initialization.

If the user attempts to program or erase a protected

sector, the device ignores the command and returns

to read mode. A program command to a protected

sector enables status polling for approximately 1 µs

before the device returns to read mode without having

modified the contents of the protected sector. An

erase command to a protected sector enables status

polling for approximately 50 µs after which the device

returns to read mode without having erased the pro-

tected sector.

It is possible to have sectors that have been persis-

tently locked, and sectors that are left in the dynamic

state. The sectors in the dynamic state are all unpro-

tected. If there is a need to protect some of them, a

simple DYB Write command sequence is all that is

necessary. The DYB write command for the dynamic

sectors switch the DYBs to signify protected and un-

protected, respectively. If there is a need to change

the status of the persistently locked sectors, a few

more steps are required. First, the PPB Lock bit must

be disabled by either putting the device through a

power-cycle, or hardware reset. The PPBs can then be

changed to reflect the desired settings. Setting the

PPB lock bit once again will lock the PPBs, and the de-

vice operates normally again.

The programming of the DYB, PPB, and PPB lock for a

given sector can be verified by writing a DYB/PPB/PPB

lock verify command to the device.

Persistent Sector Protection Mode

Locking Bit

Like the password mode locking bit, a Persistent Sec-

tor Protection mode locking bit exists to guarantee

that the device remain in software sector protection.

Once set, the Persistent Sector Protection locking bit

prevents programming of the password protection

mode locking bit. This guarantees that a hacker could

not place the device in password protection mode.

Note: to achieve the best protection, it’s recom-

mended to execute the PPB lock bit set command

early in the boot code, and protect the boot code by

holding WP# = V .

IL

18

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Both of these objectives are important, and if not

Password Protection Mode

carefully considered, may lead to unrecoverable er-

rors. The user must be sure that the Password

Protection method is desired when setting the Pass-

word Mode Locking Bit. More importantly, the user

must be sure that the password is correct when the

Password Mode Locking Bit is set. Due to the fact that

read operations are disabled, there is no means to

verify what the password is afterwards. If the pass-

word is lost after setting the Password Mode Locking

Bit, there will be no way to clear the PPB Lock bit.

The Password Sector Protection Mode method allows

an even higher level of security than the Persistent

Sector Protection Mode. There are two main differ-

ences between the Persistent Sector Protection and

the Password Sector Protection Mode:

When the device is first powered on, or

comes out of a reset cycle, the PPB Lock bit

is set to the locked state, rather than

cleared to the unlocked state.

The only means to clear the PPB Lock bit is

by writing a unique 64-bit Password to

the device.

The Password Mode Locking Bit, once set, prevents

reading the 64-bit password on the DQ bus and fur-

ther password programming. The Password Mode

Locking Bit is not erasable. Once Password Mode Lock-

ing Bit is programmed, the Persistent Sector

Protection Locking Bit is disabled from programming,

guaranteeing that no changes to the protection

scheme are allowed.

The Password Sector Protection method is otherwise

identical to the Persistent Sector Protection method.

A 64-bit password is the only additional tool utilized in

this method.

The password is stored in a one-time programma-

ble (OTP) region of the flash memory. Once the

Password Mode Locking Bit is set, the password is per-

manently set with no means to read, program, or

erase it. The password is used to clear the PPB Lock

bit. The Password Unlock command must be written to

the flash, along with a password. The flash device in-

ternally compares the given password with the pre-

programmed password. If they match, the PPB Lock

bit is cleared, and the PPBs can be altered. If they do

not match, the flash device does nothing. There is a

built-in 2 µs delay for each “password check.” This

delay is intended to thwart any efforts to run a pro-

gram that tries all possible combinations in order to

crack the password.

64-bit Password

The 64-bit Password is located in its own memory

space and is accessible through the use of the Pass-

word Program and Verify commands (see “Password

Program Command” section on page 41 and “Pass-

word Verify Command” section on page 41). The

password function works in conjunction with the Pass-

word Mode Locking Bit, which when set, prevents the

Password Verify command from reading the contents

of the password on the pins of the device.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile bit

that reflects the state of the Password Mode Locking

Bit after power-up reset. If the Password Mode Lock

Bit is also set, after a hardware reset (RESET# as-

serted) or a power-up reset the ONLY means for

clearing the PPB Lock Bit in Password Protection Mode

is to issue the Password Unlock command. Successful

execution of the Password Unlock command clears the

PPB Lock Bit, allowing for sector PPBs modifications.

Asserting RESET#, taking the device through a

power-on reset, or issuing the PPB Lock Bit Set com-

mand sets the PPB Lock Bit to a “1”.

Password and Password Mode Locking Bit

In order to select the Password sector protection

scheme, the customer must first program the pass-

word. It is recommended that the password be

somehow correlated to the unique Electronic Serial

Number (ESN) of the particular flash device. Each ESN

is different for every flash device; therefore each

password should be different for every flash device.

While programming in the password region, the cus-

tomer may perform Password Verify operations.

Once the desired password is programmed in, the

customer must then set the Password Mode Locking

Bit. This operation achieves two objectives:

If the Password Mode Locking Bit is not set, including

Persistent Protection Mode, the PPB Lock Bit is cleared

after power-up or hardware reset. The PPB Lock Bit

can be set by issuing the PPB Lock Bit Set command.

Once set the only means for clearing the PPB Lock Bit

is by issuing a hardware or power-up reset. The Pass-

word Unlock command is ignored in Persistent

Protection Mode.

1.It permanently sets the device to operate using

the Password Protection Mode. It is not possible

to reverse this function.

2.It also disables all further commands to the

password region. All program, and read opera-

tions are ignored.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

19

P r e l i m i n a r y I n f o r m a t i o n

I

in the “DC Characteristics” section on page 53

High Voltage Sector Protection

Sector protection and unprotection may also be imple-

mented using programming equipment. The

CC6

represents the automatic sleep mode current

specification.

procedure requires high voltage (V ) to be placed on

ID

RESET#: Hardware Reset Input

the RESET# pin. Refer to Figure 2, “In-System Sector

Protection/ Sector Unprotection Algorithms,” on

page 22 for details on this procedure. Note that for

sector unprotect, all unprotected sectors must be first

protected prior to the first sector write cycle. Once the

Password Mode Locking bit or Persistent Protection

Locking bit are set, the high voltage sector protect/

unprotect capability is disabled.

The RESET# input provides a hardware method of re-

setting the device to reading array data. When

RESET# is driven low for at least a period of t , the

RP

device immediately terminates any operation in

progress, tristates all outputs, resets the configura-

tion register, and ignores all read/write commands for

the duration of the RESET# pulse. The device also re-

sets the internal state machine to reading array data.

The operation that was interrupted should be reiniti-

ated once the device is ready to accept another

command sequence, to ensure data integrity.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V ± 0.2 V, the device

SS

draws CMOS standby current (I

). If RESET# is held

CC4

at V but not within V ± 0.2 V, the standby current

will be greater.

IL

SS

The device enters the CMOS standby mode when the

CE# and RESET# inputs are both held at V ± 0.2 V.

CC

RESET# may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware

from the Flash memory.

The device requires standard access time (t ) for

read access, before it is ready to read data.

CE

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

If RESET# is asserted during a program or erase op-

eration, the device requires a time of t

(during

READY

I

in the “DC Characteristics” section on page 53

CC3

Embedded Algorithms) before the device is ready to

read data again. If RESET# is asserted when a pro-

gram or erase operation is not executing, the reset

represents the standby current specification.

Automatic Sleep Mode

operation is completed within a time of t

(not

READY

The automatic sleep mode minimizes Flash device en-

ergy consumption. While in asynchronous mode, the

device automatically enables this mode when ad-

during Embedded Algorithms). The system can read

data t after RESET# returns to V

.

IH

RH

Refer to the “AC Characteristics” section on page 67

for RESET# parameters and to Figure 33, “Reset Tim-

ings,” on page 67 for the timing diagram.

dresses remain stable for t

+ 60 ns. The automatic

ACC

sleep mode is independent of the CE#, WE#, and OE#

control signals. Standard address access timings pro-

vide new data when addresses are changed. While in

sleep mode, output data is latched and always avail-

able to the system. While in synchronous mode, the

device automatically enables this mode when either

Output Disable Mode

When the OE# input is at V , output from the device

IH

is disabled. The outputs are placed in the high imped-

ance state.

the first active CLK level is greater than t

or the

ACC

CLK runs slower than 5 MHz. Note that a new burst

operation is required to provide new data.

20

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Figure 1. Temporary Sector Unprotect Operation

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP# = V_IL

outermost boot sectors will remain protected).

,

2. All previously protected sectors are protected once

again.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

21

P r e l i m i n a r y I n f o r m a t i o n

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

PLSCNT = 1

RESET# = V_ID

Wait 1 ms

unprotect address

No

First Write

Cycle = 60h?

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

Yes

Set up first sector

address

A7–A0 =

00000010

Sector Unprotect:

Write 60h to sector

address with

A7:A0 =

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

01000010

Reset

PLSCNT = 1

Increment

PLSCNT

with A7–A0 =

00000010

Wait 1.5 ms

Verify Sector

Unprotect: Write

40h to sector

address with

Read from

sector address

with A7–A0 =

00000010

Increment

PLSCNT

A7–A0 =

00000010

No

PLSCNT

= 25?

Read from

sector address

Data = 01h?

Yes

with A7–A0 =

00000010

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Unprotect

Algorithm

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms

22

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

tor Customer-locked Indicator Bit (DQ6) is shipped as

SecSi™ (Secured Silicon) Sector

Flash Memory Region

“0” and can be permanently locked to “1” by issuing

the SecSi Protection Bit Program Command. The

SecSi Sector can be read any number of times, but

can be programmed and locked only once. Note that

the accelerated programming (ACC) and unlock by-

pass functions are not available when programming

the SecSi Sector.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN) The 128-word SecSi sector is divided into 64

factory-lockable words that can be programmed and

locked by the customer. The SecSi sector is located at

addresses 000000h-00007Fh in both Persistent Pro-

tection mode and Password Protection mode. It uses

indicator bits (DQ6, DQ7) to indicate the factory-

locked and customer-locked status of the part.

The Customer-lockable SecSi Sector area can be pro-

tected using one of the following procedures:

Write the three-cycle Enter SecSi Sector

Region command sequence, and then fol-

low the in-system sector protect algorithm

as shown in Figure 2, except that RESET#

The system accesses the SecSi Sector through a com-

mand sequence (see “Enter SecSi™ Sector/Exit SecSi

Sector Command Sequence”). After the system has

written the Enter SecSi Sector command sequence, it

may read the SecSi Sector by using the addresses

normally occupied by the boot sectors. This mode of

operation continues until the system issues the Exit

SecSi Sector command sequence, or until power is re-

moved from the device. On power-up, or following a

hardware reset, the device reverts to sending com-

mands to the normal address space.

may be at either V or V . This allows in-

IH

ID

system protection of the SecSi Sector Re-

gion without raising any device pin to a

high voltage. Note that this method is only

applicable to the SecSi Sector.

Write the three-cycle Enter SecSi Sector

Secure Region command sequence, and

then use the alternate method of sector

protection described in the High Voltage

Sector Protection section.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region

command sequence to return to reading and writing

the remainder of the array.

Factory-Locked Area (64 words)

The factory-locked area of the SecSi Sector

(000000h-00003Fh) is locked when the part is

shipped, whether or not the area was programmed at

the factory. The SecSi Sector Factory-locked Indicator

Bit (DQ7) is permanently set to a “1”. The Spansion

Programming service may program the factory-locked

area with a random ESN, a customer-defined code, or

any combination of the two. Because only Spansion

can program and protect the factory-locked area, this

method ensures the security of the ESN once the

product is shipped to the field. Contact a local sales

representative for details on using the Spansion Pro-

gramming service.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

SecSi Sector Protection Bits

The SecSi Sector Protection Bits prevent program-

ming of the SecSi Sector memory area. Once set, the

SecSi Sector memory area contents are non-

modifiable.

Table 7. SecSi^TMSector Addresses

Hardware Data Protection

Sector Size

Address Range

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 20, “Mem-

ory Array Command Definitions,” on page 44 for

command definitions).

Am29BDS128H/

Am29BDS064H

128 words

000000h–00007Fh

Factory-Locked Area

64 words

000000h–00003Fh

000040h–00007Fh

Customer-Lockable Area

Customer-Lockable Area (64 words)

The device offers two types of data protection at the

sector level:

The customer-lockable area of the SecSi Sector

(000040h-00007Fh) is shipped unprotected, which al-

lows the customer to program and optionally lock the

area as appropriate for the application. The SecSi Sec-

The PPB and DYB associated command se-

quences disables or re-enables both pro-

gram and erase operations in any sector or

sector group.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

23

P r e l i m i n a r y I n f o r m a t i o n

When WP# is at V , the four outermost

IL

sectors are locked.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

When ACC is at V , all sectors are locked.

IL

= V , CE# = V or WE# = V . To initiate a write cy-

IL

IH

The following hardware data protection measures pre-

vent accidental erasure or programming, which might

otherwise be caused by spurious system level signals

cle, CE# and WE# must be a logical zero while OE# is

a logical one.

during V

power-up and power-down transitions, or

Power-Up Write Inhibit

CC

from system noise.

If WE# = CE# = RESET# = V and OE# = V during

IL

IH

power up, the device does not accept commands on

the rising edge of WE#. The internal state machine is

automatically reset to the read mode on power-up.

Write Protect (WP#)

The Write Protect feature provides a hardware method

of protecting the four outermost sectors. This function

is provided by the WP# pin and overrides the previ-

ously discussed Sector Protection/Unprotection

method.

Common Flash Memory Interface

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

If the system asserts V on the WP# pin, the device

disables program and erase functions in the eight

“outermost” 4 Kword boot sectors.

IL

If the system asserts V on the WP# pin, the device

IH

reverts to whether the boot sectors were last set to be

protected or unprotected. That is, sector protection or

unprotection for these sectors depends on whether

they were last protected or unprotected using the

method described in “PPB Program Command” section

on page 42.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 8-11. To terminate reading CFI data,

the system must write the reset command.

Note that the WP# pin must not be left floating or un-

connected; inconsistent behavior of the device may

result.

Low V_CCWrite Inhibit

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 8-11. The

system must write the reset command to return the

device to the autoselect mode.

When V

is less than V

, the device does not ac-

CC

LKO

cept any write cycles. This protects data during V

CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to reading array data. Subse-

quent writes are ignored until V

is greater than

CC

For further information, please refer to the CFI Speci-

fication and CFI Publication 100, available via the

Spansion site at the following URL:

V

. The system must provide the proper signals to

LKO

the control inputs to prevent unintentional writes

when V is greater than V

.

LKO

CC

http://www.amd.com/flash/cfi.

Write Pulse “Glitch” Protection

Alternatively, contact an AMD representative for cop-

ies of these documents.

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

24

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Table 8. CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

Table 9. System Interface String

Addresses

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0017h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0019h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0004h

0000h

0009h

0000h

0004h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^N

µs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

25

P r e l i m i n a r y I n f o r m a t i o n

Table 10. Device Geometry Definition

Addresses

Data

Description

Device Size = 2^Nbyte

BDS128H = 0018h; BDS640H = 0017h

27h

001xh

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

00xDh

0000h

0001h

Erase Block Region 2 Information

Address 31h: BDS128H = 00FDh; BDS640H = 007Dh

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

Erase Block Region 4 Information

39h

3Ah

3Bh

3Ch

0000h

26

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Table 11. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

000Ch

Silicon Technology (Bits 5-2) 0011 = 0.13 µm

Erase Suspend

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0001h

0000h

0007h

00x7h

0001h

0000h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

07 = Advanced Sector Protection

Simultaneous Operation: number of Sectors in all banks except boot block

BDS128H = 00E7h; BDS640H = 0077h

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

00B5h

00C5h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh

50h

57h

0001h

0000h

0004h

Boot Sector Flag

Program Suspend. 00h = not supported

Bank Organization: X = Number of banks

58h

59h

5Ah

5Bh

0027h / 0017h

0060h / 0030h

0027h / 0017h

Bank A – Bank D Region Information. X = Number of sectors in bank.

Address: 58h = Bank A; 59h = Bank B; 5Ah = Bank C; 5Bh = Bank D

Data: BDS128H / BDS640H

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

27

P r e l i m i n a r y I n f o r m a t i o n

Table 12. Am29BDS128H Sector Address Table

Bank

Sector

SA0

Sector Size

4 Kwords

(x16) Address Range

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

Bank

Sector

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Sector Size

32 Kwords

(x16) Address Range

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

28

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Table 12. Am29BDS128H Sector Address Table (Continued)

Bank

Sector

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

Sector Size

32 Kwords

(x16) Address Range

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

Bank

Sector

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

Sector Size

32 Kwords

(x16) Address Range

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

29

P r e l i m i n a r y I n f o r m a t i o n

Table 12. Am29BDS128H Sector Address Table (Continued)

Bank

Sector

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

Sector Size

32 Kwords

(x16) Address Range

400000h–407FFFh

408000h–40FFFFh

410000h–417FFFh

418000h–41FFFFh

420000h–427FFFh

428000h–42FFFFh

430000h–437FFFh

438000h–43FFFFh

440000h–447FFFh

448000h–44FFFFh

450000h–457FFFh

458000h–45FFFFh

460000h–467FFFh

468000h–46FFFFh

470000h–477FFFh

478000h–47FFFFh

480000h–487FFFh

488000h–48FFFFh

490000h–497FFFh

498000h–49FFFFh

4A0000h–4A7FFFh

4A8000h–4AFFFFh

4B0000h–4B7FFFh

4B8000h–4BFFFFh

4C0000h–4C7FFFh

4C8000h–4CFFFFh

4D0000h–4D7FFFh

4D8000h–4DFFFFh

4E0000h–4E7FFFh

4E8000h–4EFFFFh

4F0000h–4F7FFFh

4F8000h–4FFFFFh

Bank

Sector

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

Sector Size

32 Kwords

(x16) Address Range

500000h–507FFFh

508000h–50FFFFh

510000h–517FFFh

518000h–51FFFFh

520000h–527FFFh

528000h–52FFFFh

530000h–537FFFh

538000h–53FFFFh

540000h–547FFFh

548000h–54FFFFh

550000h–557FFFh

558000h–55FFFFh

560000h–567FFFh

568000h–56FFFFh

570000h–577FFFh

578000h–57FFFFh

580000h–587FFFh

588000h–58FFFFh

590000h–597FFFh

598000h–59FFFFh

5A0000h–5A7FFFh

5A8000h–5AFFFFh

5B0000h–5B7FFFh

5B8000h–5BFFFFh

5C0000h–5C7FFFh

5C8000h–5CFFFFh

5D0000h–5D7FFFh

5D8000h–5DFFFFh

5E0000h–5E7FFFh

5E8000h–5EFFFFh

5F0000h–5F7FFFh

5F8000h–5FFFFFh

30

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Table 12. Am29BDS128H Sector Address Table (Continued)

Bank

Sector

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

Sector Size

32 Kwords

(x16) Address Range

600000h–607FFFh

608000h–60FFFFh

610000h–617FFFh

618000h–61FFFFh

620000h–627FFFh

628000h–62FFFFh

630000h–637FFFh

638000h–63FFFFh

640000h–647FFFh

648000h–64FFFFh

650000h–657FFFh

658000h–65FFFFh

660000h–667FFFh

668000h–66FFFFh

670000h–677FFFh

678000h–67FFFFh

680000h–687FFFh

688000h–68FFFFh

690000h–697FFFh

698000h–69FFFFh

6A0000h–6A7FFFh

6A8000h–6AFFFFh

6B0000h–6B7FFFh

6B8000h–6BFFFFh

6C0000h–6C7FFFh

6C8000h–6CFFFFh

6D0000h–6D7FFFh

6D8000h–6DFFFFh

6E0000h–6E7FFFh

6E8000h–6EFFFFh

6F0000h–6F7FFFh

6F8000h–6FFFFFh

Bank

Sector

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

SA259

SA260

SA261

SA262

SA263

SA264

SA265

SA266

SA267

SA268

SA269

Sector Size

32 Kwords

4 Kwords

(x16) Address Range

700000h–707FFFh

708000h–70FFFFh

710000h–717FFFh

718000h–71FFFFh

720000h–727FFFh

728000h–72FFFFh

730000h–737FFFh

738000h–73FFFFh

740000h–747FFFh

748000h–74FFFFh

750000h–757FFFh

758000h–75FFFFh

760000h–767FFFh

768000h–76FFFFh

770000h–777FFFh

778000h–77FFFFh

780000h–787FFFh

788000h–78FFFFh

790000h–797FFFh

798000h–79FFFFh

7A0000h–7A7FFFh

7A8000h–7AFFFFh

7B0000h–7B7FFFh

7B8000h–7BFFFFh

7C0000h–7C7FFFh

7C8000h–7CFFFFh

7D0000h–7D7FFFh

7D8000h–7DFFFFh

7E0000h–7E7FFFh

7E8000h–7EFFFFh

7F0000h–7F7FFFh

7F8000h–7F8FFFh

7F9000h–7F9FFFh

7FA000h–7FAFFFh

7FB000h–7FBFFFh

7FC000h–7FCFFFh

7FD000h–7FDFFFh

7FE000h–7FEFFFh

7FF000h–7FFFFFh

4 Kwords

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

31

P r e l i m i n a r y I n f o r m a t i o n

Table 13. Am29BDS064H Sector Address Table

Bank

Sector Sector Size

Address Range

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

Bank

Sector

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Sector Size

32 Kwords

Address Range

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

SA0

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

32

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Table 13. Am29BDS064H Sector Address Table

Bank

Sector Sector Size

Address Range

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

Bank

Sector

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

Sector Size

32 Kwords

4 Kwords

Address Range

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

32 Kwords

4 Kwords

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

33

P r e l i m i n a r y I n f o r m a t i o n

Command Definitions

Writing specific address and data commands or se-

quences into the command register initiates device

operations. Table 20, “Memory Array Command Defi-

nitions,” on page 44 defines the valid register

command sequences. Writing incorrect address and

data values or writing them in the improper sequence

may place the device in an unknown state. The sys-

tem must write the reset command to return the

device to reading array data. Refer to the AC Charac-

teristics section for timing diagrams.

synchronous mode active. The configuration register

must be set before the device will enter burst mode.

The configuration register is loaded with a three-cycle

command sequence. The first two cycles are standard

unlock sequences. On the third cycle, the data should

be C0h, address bits A11–A0 should be 555h, and ad-

dress bits A19–A12 set the code to be latched. The

device will power up or after a hardware reset with the

default setting, which is in asynchronous mode. The

register must be set before the device can enter syn-

chronous mode. The configuration register can not be

changed during device operations (program, erase, or

sector lock).

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data in asynchronous mode. Each bank is

ready to read array data after completing an Embed-

ded Program or Embedded Erase algorithm.

Power-up/

Hardware Reset

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-suspend-

read mode, after which the system can read data from

any non-erase-suspended sector within the same

bank. After completing a programming operation in

the Erase Suspend mode, the system may once again

read array data from any non-erase-suspended sector

within the same bank. See the “Erase Suspend/Erase

Resume Commands” section on page 40 for more

information.

Asynchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(D15 = 1)

Synchronous Mode

(D15 = 0)

The system must issue the reset command to return

a bank to the read (or erase-suspend-read) mode if

DQ5 goes high during an active program or erase op-

eration, or if the bank is in the autoselect mode. See

the “Reset Command” section on page 37 for more

information.

Synchronous Read

Mode Only

See also “Requirements for Asynchronous Read Oper-

ation (Non-Burst)” section on page 10 and

“Requirements for Synchronous (Burst) Read Opera-

tion” section on page 10 for more information. The

Asynchronous Read and Synchronous/Burst Read ta-

bles provide the read parameters, and Figure 16,

“CLK Synchronous Burst Mode Read (Rising Active

CLK),” on page 57, Figure 18, “Synchronous Burst

Mode Read,” on page 58, and Figure 31, “Asynchro-

nous Mode Read with Latched Addresses,” on page 66

show the timings.

Figure 3. Synchronous/Asynchronous State

Diagram

Read Mode Setting

On power-up or hardware reset, the device is set to be

in asynchronous read mode. This setting allows the

system to enable or disable burst mode during system

operations. Address A19 determines this setting: “1”

for asynchronous mode, “0” for synchronous mode.

Programmable Wait State Configuration

The programmable wait state feature informs the de-

vice of the number of clock cycles that must elapse

after AVD# is driven active before data will be avail-

able. This value is determined by the input frequency

of the device. Address bits A14–A12 determine the

Set Configuration Register Command

Sequence

The device uses a configuration register to set the var-

ious burst parameters: number of wait states, burst

read mode, active clock edge, RDY configuration, and

34

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

setting (see Table 14, “Programmable Wait State Set-

tings,” on page 35).

Table 15. Wait States for Reduced Wait-state

Handshaking

The wait state command sequence instructs the de-

vice to set a particular number of clock cycles for the

initial access in burst mode. The number of wait states

that should be programmed into the device is directly

related to the clock frequency.

System

Device

Speed

Rating

Frequency Even Initial Odd Initial

Range

Address

6

–22 MHz

2

3

4

2

3

4

2

3

4

2

3

4

5

2

3

4

5

2

3

4

5

22–

28–

43–

28 MHz

43 MHz

54 MHz

D

Table 14. Programmable Wait State Settings

(54 MHz)

TotalInitialAccess

A14

0

A13

0

A12

0

Cycles

6–28 MHz

2

28–

35–

53–

35 MHz

53 MHz

66 MHz

E

0

1

3

(66 MHz)

0

1

0

4

5

0

1

6–30 MHz

1

0

6

30–

45–

61–

45 MHz

61 MHz

75 MHz

F

1

0

1

7 (default)

Reserved

(75 MHz)

1

0

1

1. If the latched address is 3Eh or 3Fh (or an address

offset from either address by a multiple of 64), add

two access cycles to the values listed.

1. Upon power-up or hardware reset, the default setting

is seven wait states.

2. RDY will default to being active with data when the

Wait State Setting is set to a total initial access cycle

of 2.

2. In the 8-, 16-, and 32-word burst modes, the address

pointer does not cross 64-word boundaries (3Fh, or

addresses offset from 3Fh by a multiple of 64).

3. Typical initial access cycles may vary depending on

system margin requirements.

It is recommended that the wait state command se-

quence be written, even if the default wait state value

is desired, to ensure the device is set as expected. A

hardware reset will set the wait state to the default

setting.

Standard Handshaking Option

For optimal burst mode performance on devices with

the standard handshaking option, the host system

must set the appropriate number of wait states in the

flash device depending on the clock frequency.

Reduced Wait-state Handshaking Option

If the device is equipped with the reduced wait-state

handshaking option, the host system should set ad-

dress bits A14–A12 to 010 for the system/device to

execute at maximum speed.

Table 16 describes the typical number of clock cycles

(wait states) for various conditions with A14-A12 set

to 101.

Table 15 describes the typical number of clock cycles

(wait states) for various conditions.

Table 16. Wait States for Standard Handshaking

Typical No. of Clock

Conditions at Address

Cycles after AVD# Low

Initial address

7

Initial address is 3E or 3Fh (or

offset from these addresses by

a multiple of 64) and is at

boundary crossing*

7

* In the 8-, 16- and 32-word burst read modes, the address

pointer does not cross 64-word boundaries (addresses

which are multiples of 3Fh).

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

35

P r e l i m i n a r y I n f o r m a t i o n

The autoselect function allows the host system to de-

Burst Active Clock Edge Configuration

termine whether the flash device is enabled for

handshaking. See the “Autoselect Command Se-

quence” section on page 37 for more information.

By default, the device will deliver data on the rising

edge of the clock after the initial synchronous access

time. Subsequent outputs will also be on the following

rising edges, barring any delays. The device can be

set so that the falling clock edge is active for all syn-

chronous accesses. Address bit A17 determines this

setting; “1” for rising active, “0” for falling active.

Read Mode Configuration

The device supports four different read modes: con-

tinuous mode, and 8, 16, and 32 word linear wrap

around modes. A continuous sequence begins at the

starting address and advances the address pointer

until the burst operation is complete. If the highest

address in the device is reached during the continuous

burst read mode, the address pointer wraps around to

the lowest address.

RDY Configuration

By default, the device is set so that the RDY pin will

output V

whenever there is valid data on the out-

OH

puts. The device can be set so that RDY goes active

one data cycle before active data. Address bit A18 de-

termines this setting; “1” for RDY active with data, “0”

for RDY active one clock cycle before valid data. In

asynchronous mode, RDY is an open-drain output.

For example, an eight-word linear read with wrap

around begins on the starting address written to the

device and then advances to the next 8 word bound-

ary. The address pointer then returns to the 1st word

after the previous eight word boundary, wrapping

through the starting location. The sixteen- and thirty-

two linear wrap around modes operate in a fashion

similar to the eight-word mode.

Configuration Register

Table 18 shows the address bits that determine the

configuration register settings for various device

functions.

Table 17 shows the address bits and settings for the

four read modes.

Table 17. Read Mode Settings

Address Bits

Burst Modes

A16

0

A15

0

Continuous

8-word linear wrap around

16-word linear wrap around

32-word linear wrap around

0

1

0

1

Note: Upon power-up or hardware reset the default setting

is continuous.

36

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Table 18. Configuration Register

Address BIt

Function

Settings (Binary)

Set Device

Read Mode

0 = Synchronous Read (Burst Mode) Enabled

1 = Asynchronous Mode (default)

A19

0 = RDY active one clock cycle before data

1 = RDY active with data (default)

A18

A17

RDY

0 = Burst starts and data is output on the falling edge of CLK

1 = Burst starts and data is output on the rising edge of CLK (default)

Clock

Synchronous Mode

00 = Continuous (default)

A16

A15

Read Mode

01 = 8-word linear with wrap around

10 = 16-word linear with wrap around

11 = 32-word linear with wrap around

000 = Data is valid on the 2th active CLK edge after AVD# transition to V_IH

001 = Data is valid on the 3th active CLK edge after AVD# transition to V_IH

010 = Data is valid on the 4th active CLK edge after AVD# transition to V_IH

011 = Data is valid on the 5th active CLK edge after AVD# transition to V_IH

100 = Data is valid on the 6th active CLK edge after AVD# transition to V_IH

101 = Data is valid on the 7th active CLK edge after AVD# transition to V_IH(default)

A14

A13

A12

Programmable

Wait State

110 = Reserved

111 = Reserved

Note:Device will be in the default state upon power-up or hardware reset.

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure

begins, however, the device ignores reset commands

until the operation is complete.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 20, “Memory Array Command Definitions,” on

page 44 shows the address and data requirements.

The autoselect command sequence may be written to

an address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command

may not be written while the device is actively pro-

gramming or erasing in the other bank.

The reset command may be written between the se-

quence cycles in a program command sequence

before programming begins (prior to the third cycle).

This resets the bank to which the system was writing

to the read mode. If the program command sequence

is written to a bank that is in the Erase Suspend mode,

writing the reset command returns that bank to the

erase-suspend-read mode. Once programming be-

gins, however, the device ignores reset commands

until the operation is complete.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The bank then enters the

autoselect mode. No subsequent data will be made

available if the autoselect data is read in synchronous

mode. The system may read at any address within the

same bank any number of times without initiating an-

other autoselect command sequence. Read

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

37

P r e l i m i n a r y I n f o r m a t i o n

commands to other banks will return data from the ar-

shows the address and data requirements for both

ray. The following table describes the address

requirements for the various autoselect functions, and

the resulting data. BA represents the bank address,

and SA represents the sector address. The device ID

is read in three cycles.

command sequences.

Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 20, “Memory Array

Command Definitions,” on page 44 shows the address

and data requirements for the program command

sequence.

Table 19. Autoselect Data

Description

Address

Read Data

Manufacturer

ID

(BA) +

00h

0001h

Device ID,

Word

(BA) +

01h

227Eh (BDS128H)

227Eh (BDS640H)

Device ID,

Word 2

(BA) +

0Eh

2218h (BDS128H)

221Eh (BDS640H)

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can

determine the status of the program operation by

monitoring DQ7 or DQ6/DQ2. Refer to the “Write Op-

eration Status” section on page 47 for information on

these status bits.

2200h (BDS128H)

2201h (BDS640H)

Device ID,

Word 3

(BA) +

0Fh

Sector

Protection

Verification

(SA) +

02h

0001h (locked),

0000h (unlocked)

DQ15 - DQ8 = 0

DQ7: Factory Lock Bit

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity.

1 = Locked, 0 = Not Locked

DQ6: Customer Lock Bit

1 = Locked, 0 = Not Locked

DQ5: Handshake Bit

(BA) +

03h

Indicator Bits

1 = Reduced Wait-state

Handshake,

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from

“0” back to a “1.” Attempting to do so may cause that

bank to set DQ5 = 1, or cause the DQ7 and DQ6 sta-

tus bit to indicate the operation was successful.

However, a succeeding read will show that the data is

still “0.” Only erase operations can convert a “0” to a

“1.”

0 = Standard Handshake

The system must write the reset command to return

to the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pri-

marily program to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

The device then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

The SecSi Sector region provides a secured data area

containing a random, eight word electronic serial

number (ESN). The system can access the SecSi Sec-

tor region by issuing the three-cycle Enter SecSi

Sector command sequence. The device continues to

access the SecSi Sector region until the system issues

the four-cycle Exit SecSi Sector command sequence.

The Exit SecSi Sector command sequence returns the

device to normal operation. The SecSi Sector is not

accessible when the device is executing an Embedded

Program or embedded Erase algorithm. Table 20,

“Memory Array Command Definitions,” on page 44

38

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

with the initial two unlock cycles required in the stan-

Chip Erase Command Sequence

dard program command sequence, resulting in faster

total programming time. The host system may also

initiate the chip erase and sector erase sequences in

the unlock bypass mode. The erase command se-

quences are four cycles in length instead of six cycles.

Table 20, “Memory Array Command Definitions,” on

page 44 shows the requirements for the unlock by-

pass command sequences.

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the

entire memory for an all zero data pattern prior to

electrical erase. The system is not required to provide

any controls or timings during these operations.

Table 20, “Memory Array Command Definitions,” on

page 44 shows the address and data requirements for

the chip erase command sequence.

During the unlock bypass mode, only the Read, Un-

lock Bypass Program, Unlock Bypass Sector Erase,

Unlock Bypass Chip Erase, and Unlock Bypass Reset

commands are valid. To exit the unlock bypass mode,

the system must issue the two-cycle unlock bypass

reset command sequence. The first cycle must contain

the bank address and the data 90h. The second cycle

need only contain the data 00h. The bank then returns

to the read mode.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7 or DQ6/DQ2.

Refer to the “Write Operation Status” section on page

47 for information on these status bits.

The device offers accelerated program operations

through the ACC input. When the system asserts V

HH

on this input, the device automatically enters the Un-

lock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command se-

quence. The device uses the higher voltage on the

ACC input to accelerate the operation.

Any commands written during the chip erase opera-

tion are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the chip erase command sequence should

be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

Figure 4, “Program Operation,” on page 39 illustrates

the algorithm for the program operation. Refer to the

Erase/Program Operations table in the AC Character-

istics section for parameters, and Figure 34,

“Asynchronous Program Operation Timings: AVD#

Latched Addresses,” on page 69 and Figure 36, “Syn-

chronous Program Operation Timings: WE# Latched

Addresses,” on page 71 for timing diagrams.

The host system may also initiate the chip erase com-

mand sequence while the device is in the unlock

bypass mode. The command sequence is two cycles in

length instead of six cycles. See Table 20, “Memory

Array Command Definitions,” on page 44 for details on

the unlock bypass command sequences.

START

Figure 5, “Erase Operation,” on page 41 illustrates the

algorithm for the erase operation. Refer to the Erase/

Program Operations table in the AC Characteristics

section for parameters and timing diagrams.

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then

followed by the address of the sector to be erased,

and the sector erase command. Table 20, “Memory

Array Command Definitions,” on page 44 shows the

address and data requirements for the sector erase

command sequence.

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 20 for program command

sequence.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

Figure 4. Program Operation

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

39

P r e l i m i n a r y I n f o r m a t i o n

an all zero data pattern prior to electrical erase. The

teristics,” on page 68 for parameters and timing

system is not required to provide any controls or tim-

ings during these operations.

diagrams.

Erase Suspend/Erase Resume Commands

After the command sequence is written, a sector erase

time-out of no less than 50 µs occurs. During the

time-out period, additional sector addresses and sec-

tor erase commands may be written. Loading the

sector erase buffer may be done in any sequence, and

the number of sectors may be from one sector to all

sectors. The time between these additional cycles

must be less than 50 µs, otherwise erasure may be-

gin. Any sector erase address and command following

the exceeded time-out may or may not be accepted.

It is recommended that processor interrupts be dis-

abled during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the

last Sector Erase command is written. Any command

other than Sector Erase or Erase Suspend during the

time-out period resets that bank to the read mode.

The system must rewrite the command sequence and

any additional addresses and commands.

The Erase Suspend command, B0h, allows the system

to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writ-

ing this command. This command is valid only during

the sector erase operation, including the minimum 50

µs time-out period during the sector erase command

sequence. The Erase Suspend command is ignored if

written during the chip erase operation or Embedded

Program algorithm.

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 35 µs to suspend the erase operation.

However, when the Erase Suspend command is writ-

ten during the sector erase time-out, the device

immediately terminates the time-out period and sus-

pends the erase operation.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See “DQ3: Sector Erase

Timer” section on page 50.) The time-out begins from

the rising edge of the final WE# pulse in the command

sequence.

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors produces

status information on DQ7–DQ0. The system can use

DQ7, or DQ6 and DQ2 together, to determine if a sec-

tor is actively erasing or is erase-suspended. Refer to

the Figure , “Write Operation Status,” on page 47 for

information on these status bits.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

termine the status of the erase operation by reading

DQ7 or DQ6/DQ2 in the erasing bank. Refer to the

“Write Operation Status” section on page 47 for infor-

mation on these status bits.

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard program operation. Refer to

the “Write Operation Status” section on page 47 for

more information.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that

occurs, the sector erase command sequence should

be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

“Autoselect Mode” section on page 13 and “Autoselect

Command Sequence” section on page 37 for details.

The host system may also initiate the sector erase

command sequence while the device is in the unlock

bypass mode. The command sequence is four cycles

cycles in length instead of six cycles.

To resume the sector erase operation, the system

must write the Erase Resume command. The bank ad-

dress of the erase-suspended bank is required when

writing this command. Further writes of the Resume

command are ignored. Another Erase Suspend com-

Figure 5, “Erase Operation,” on page 41 illustrates the

algorithm for the erase operation. Refer to the Erase/

Program Operations table in the Figure , “AC Charac-

40

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

mand can be written after the chip has resumed

erasing.

after a cell is programmed as a “0” results in a time-

out by the Embedded Program Algorithm™ with the

cell remaining as a “0”. The password is all Fs when

shipped from the factory. All 64-bit password combi-

nations are valid as a password.

START

Password Verify Command

Write Erase

Command Sequence

The Password Verify Command is used to verify the

Password. The Password is verifiable only when the

Password Mode Locking Bit is not programmed. If the

Password Mode Locking Bit is programmed and the

user attempts to verify the Password, the device will

always drive all Fs onto the DQ data bus.

Data Poll

from System

Embedded

Erase

algorithm

in progress

Also, the device will not operate in Simultaneous Op-

eration when the Password Verify command is

executed. Only the password is returned regardless of

the bank address. The lower two address bits (A1–A0)

are valid during the Password Verify. Writing the SecSi

Sector Exit command returns the device back to nor-

mal operation.

No

Data = FFh?

Yes

Erasure Completed

Password Protection Mode Locking Bit

Program Command

Notes:

The Password Protection Mode Locking Bit Program

Command programs the Password Protection Mode

Locking Bit, which prevents further verifies or updates

to the password. Once programmed, the Password

Protection Mode Locking Bit cannot be erased and the

Persistent Protection Mode Locking Bit program cir-

cuitry is disabled, thereby forcing the device to remain

in the Password Protection Mode. After issuing “PL/

68h” at the fourth bus cycle, the device requires a

time out period of approximately 150 µs for program-

ming the Password Protection Mode Locking Bit. Then

by writing “PL/48h” at the fifth bus cycle, the device

outputs verify data at DQ0. If DQ0 = 1, then the Pass-

word Protection Mode Locking Bit is programmed. If

not, the system must repeat this program sequence

from the fourth cycle of “PL/68h”. Exiting the Pass-

word Protection Mode Locking Bit Program command

is accomplished by writing the SecSi Sector Exit or the

Read/Reset command.

1. See Table 20 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 5. Erase Operation

Password Program Command

The Password Program Command permits program-

ming the password that is used as part of the

hardware protection scheme. The actual password is

64-bits long. 4 Password Program commands are re-

quired to program the password. The user must enter

the unlock cycle, password program command (38h)

and the program address/data for each portion of the

password when programming. There are no provi-

sions for entering the 2-cycle unlock cycle, the

password program command, and all the password

data. There is no special addressing order required for

programming the password. Also, when the password

is undergoing programming, Simultaneous Operation

is disabled. Read operations to any memory location

will return the programming status. Once program-

ming is complete, the user must issue a Read/Reset

command to return the device to normal operation.

Once the Password is written and verified, the Pass-

word Mode Locking Bit must be set in order to prevent

verification. The Password Program Command is only

capable of programming “0”s. Programming a “1”

Persistent Sector Protection Mode

Locking Bit Program Command

The Persistent Sector Protection Mode Locking Bit Pro-

gram Command programs the Persistent Sector

Protection Mode Locking Bit, which prevents the Pass-

word Mode Locking Bit from ever being programmed.

By disabling the program circuitry of the Password

Mode Locking Bit, the device is forced to remain in the

Persistent Sector Protection mode of operation, once

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

41

P r e l i m i n a r y I n f o r m a t i o n

this bit is set. After issuing “SMPL/68h” at the fourth

Password Unlock Command

bus cycle, the device requires a time out period of ap-

proximately 150 µs for programming the Persistent

Protection Mode Locking Bit. Then by writing “SMPL/

48h” at the fifth bus cycle, the device outputs verify

data at DQ0. If DQ0 = 1, then the Persistent Protec-

tion Mode Locking Bit is programmed. If not, the

system must repeat this program sequence from the

fourth cycle of “PL/68h”. Exiting the Persistent Protec-

tion Mode Locking Bit Program command is

accomplished by writing the SecSi Sector Exit com-

mand or Read/Reset command.

The Password Unlock command is used to clear the

PPB Lock Bit so that the PPBs can be unlocked for

modification, thereby allowing the PPBs to become ac-

cessible for modification. The exact password must be

entered in order for the unlocking function to occur.

This command cannot be issued any faster than 2 µs

at a time to prevent a hacker from running through

the all 64-bit combinations in an attempt to correctly

match a password. If the command is issued before

the 2 µs execution window for each portion of the un-

lock, the command will be ignored.

The Password Unlock function is accomplished by

writing Password Unlock command and data to the de-

vice to perform the clearing of the PPB Lock Bit. The

password is 64 bits long, so the user must write the

Password Unlock command 4 times. A1 and A0 are

used for matching. Writing the Password Unlock com-

mand is not address order specific. The lower address

A1–A0= 00, the next Password Unlock command is to

A1–A0= 01, then to A1–A0= 10, and finally to A1–

A0= 11.

SecSi Sector Protection Bit Program

Command

To protect the SecSi Sector, write the SecSi Sector

Protect command sequence while in the SecSi Sector

mode. After issuing “OPBP/48h” at the fourth bus cy-

cle, the device requires a time out period of

approximately 150 µs to protect the SecSi Sector.

Then, by writing “OPBP/48” at the fifth bus cycle, the

device outputs verify data at DQ0. If DQ0 = 1, then

the SecSi Sector is protected. If not, then the system

must repeat this program sequence from the fourth

cycle of “OPBP/48h”.

Once the Password Unlock command is entered for all

four words, the RDY pin goes LOW indicating that the

device is busy. Approximately 1 µs is required for each

portion of the unlock. Once the first portion of the

password unlock completes (RDY is not driven and

DQ6 does not toggle when read), the Password Unlock

command is issued again, only this time with the next

part of the password. Four Password Unlock com-

mands are required to successfully clear the PPB Lock

Bit. As with the first Password Unlock command, the

RDY signal goes LOW and reading the device results

in the DQ6 pin toggling on successive read operations

until complete. It is the responsibility of the micropro-

cessor to keep track of the number of Password

Unlock commands, the order, and when to read the

PPB Lock bit to confirm successful password unlock. In

order to relock the device into the Password Mode, the

PPB Lock Bit Set command can be re-issued.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the PPB

Lock bit if it is cleared either at reset or if the Password

Unlock command was successfully executed. There is

no PPB Lock Bit Clear command. Once the PPB Lock

Bit is set, it cannot be cleared unless the device is

taken through a power-on clear or the Password Un-

lock command is executed. Upon setting the PPB Lock

Bit, the PPBs are latched into the DYBs. If the Pass-

word Mode Locking Bit is set, the PPB Lock Bit status

is reflected as set, even after a power-on reset cycle.

Exiting the PPB Lock Bit Set command is accomplished

by writing the SecSi Sector Exit command, only while

in the Persistent Sector Protection Mode.

DYB Write Command

Exiting the Password Unlock command is accom-

plished by writing SecSi Sector Exit command.

The DYB Write command is used to set or clear a DYB

for a given sector. The high order address bits (Amax–

A11) are issued at the same time as the code 01h or

00h on DQ7-DQ0. All other DQ data bus pins are ig-

nored during the data write cycle. The DYBs are

modifiable at any time, regardless of the state of the

PPB or PPB Lock Bit. The DYBs are cleared at power-

up or hardware reset. Exiting the DYB Write command

is accomplished by writing the Read/Reset command.

PPB Program Command

The PPB Program command is used to program, or

set, a given PPB. Each PPB is individually programmed

(but is bulk erased with the other PPBs). The specific

sector address (Amax–A12) are written at the same

time as the program command 60h. If the PPB Lock

Bit is set and the correspondingly PPB is set for the

sector, the PPB Program command will not execute

42

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

and the command will time out without programming

erased. If not, the system must repeat this program

sequence from the fourth cycle of “WP/60h”.

the PPB. After issuing “SBA+WP/68h” at the fourth

bus cycle, the device requires a time out period of ap-

proximately 150 µs to program the PPB. Writing

“SBA+WP/48” at the fifth bus cycle produces verify

data at DQ0. If DQ0 = 1, the PPB is programmed. If

not, the system must repeat this program sequence

from the fourth cycle of “SBA+WP/68h”.

It is the responsibility of the system to preprogram all

PPBs prior to issuing the All PPB Erase command. If

the system attempts to erase a cleared PPB, over-era-

sure may occur, making it difficult to program the PPB

at a later time. Also note that the total number of PPB

program/erase cycles is limited to 100 cycles. Cycling

the PPBs beyond 100 cycles is not guaranteed.

The PPB Program command does not follow the Em-

bedded Program algorithm. Writing the SecSi Sector

Exit or Read/Reset command returns the device back

to normal operation.

Writing the SecSi Sector Exit or the Read/Reset com-

mand returns the device to normal operation.

Figure 6. PPB Program Algorithm

All PPB Erase Command

The All PPB Erase command is used to erase all PPBs

in bulk. There is no means for individually erasing a

specific PPB. Unlike the PPB program, no specific sec-

tor address is required. However, when the PPB erase

command is written (60h), all Sector PPBs are erased

in parallel. If the PPB Lock Bit is set, the ALL PPB Erase

command will not execute and the command will

time-out without erasing the PPBs. After issuing “WP/

60h” at the fourth bus cycle, the device requires a

time out period of approximately 1.5 ms to erase the

PPB. Writing “SBA+WP/40h” at the fifth bus cycle pro-

duces verify data at DQ0. If DQ0 = 0, the PPB is

Figure 7. All PPB Erase Algorithm

DYB Write Command

The DYB Write command is used for setting the DYB,

which is a volatile bit that is cleared at hardware reset.

There is one DYB per sector. If the PPB is set, the sec-

tor is protected regardless of the value of the DYB. If

the PPB is cleared, setting the DYB to a 1 protects the

sector from programs or erases. Since this is a volatile

bit, removing power or resetting the device will clear

the DYBs.

Writing the Read/Reset command returns the device

to normal operation.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

43

P r e l i m i n a r y I n f o r m a t i o n

PPB Status Command

DYB Status Command

The programming of the PPB for a given sector can be

verified by writing a PPB status verify command to the

device.

The programming of the DYB for a given sector can be

verified by writing a DYB Status command to the

device.

Writing the Read/Reset command returns the device

to normal operation.

Writing the Read/Reset command and the SecSi Sec-

tor Exit command returns the device to normal

operation.

PPB Lock Bit Status Command

The programming of the PPB Lock Bit for a given sec-

tor can be verified by writing a PPB Lock Bit status

verify command to the device.

Command Definitions

Table 20. Memory Array Command Definitions

Bus Cycles (Notes 1–6)

Third Fourth

Command Sequence

(Notes)

First

Second

Fifth

Addr Data

Sixth

Addr Data

Dat

a

Addr Data Addr Data

Addr

Data

Asynchronous Read (7)

Reset (8)

1

4

6

4

RA

RD

F0

XXX

555

Manufacturer ID

AA

2AA

55

BA+555

SA+555

90

BA+X00

BA+X01

SA+X02

0001

227E

(12)*

Device ID (9, 10)*

Sector Lock Verify (12)*

BA+X0E (10)* BA+X0F (11)*

Indicator Bits (13)*

4

555

AA

2AA

55

BA+555

90

BA+X03

(13)*

Program

4

6

3

2

1

2

1

3

1

555

XX

AA

A0

80

98

90

B0

30

AA

98

2AA

PA

55

PD

30

10

555

A0

80

20

PA

Data

AA

Chip Erase

555

2AA

55

555

SA

10

30

Sector Erase

AA

Entry

Program (14, 15)

Sector Erase (14, 15)

Erase (14, 15)

CFI (14, 15)

XX

SA

XX

XXX

XX

Reset

XX

XXX

2AA

00

55

Erase Suspend (16)

Erase Resume (17)

Set Configuration Register (18)

CFI Query (19)

BA

555

55

(CR)555

C0

* For actual hexadecimal data values, refer to the note number indicated.

Legend:

X = Don’t care

SA = Address of the sector to be verified (in autoselect mode)

or erased. Address bits Amax–A12 uniquely select any sector.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

BA = Address of the bank (BDS128H: A22–A20; BDS640H:

A21–A19) for which command is being written.

PA = Address of the memory location to be programmed.

Addresses latch on the rising edge of the AVD# pulse or active

edge of CLK which ever comes first.

SLA = Address of the sector to be locked. Set sector address

(SA) and either A6 = 1 for unlocked or A6 = 0 for locked.

CR = Configuration Register address bits A19–A12.

PD = Data to be programmed at location PA. Data latches on

the rising edge of WE# or CE# pulse, whichever happens first.

Notes:

1. See Table 1 for description of bus operations.

3. Shaded cells indicate read cycles. All others are write

cycles.

2. All values are in hexadecimal.

44

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

4. Data bits DQ15–DQ8 are don’t care in command

12.The data is 0000h for an unlocked sector and 0001h for a

locked sector

sequences, except for RD and PD.

5. Unless otherwise noted, address bits Amax–A12 are don’t

cares.

13.DQ15–DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 =

Not Locked), DQ6: Customer Lock Bit (1 = Locked, 0 =

Not Locked), DQ5: Handshake Bit (1 = Reduced wait-

state Handshake, 0 = Standard Handshake), DQ4–DQ0 =

0.

6. Writing incorrect address and data values or writing them

in the improper sequence may place the device in an

unknown state. The system must write the reset

command to return the device to reading array data.

14.The Unlock Bypass command sequence is required prior

to this command sequence.

7. No unlock or command cycles required when bank is

reading array data.

15.The Unlock Bypass Reset command is required to return

to reading array data when the bank is in the unlock

bypass mode.

8. The Reset command is required to return to reading

array data (or to the erase-suspend-read mode if

previously in Erase Suspend) when a bank is in the

autoselect mode, or if DQ5 goes high (while the bank is

providing status information) or performing sector lock/

unlock.

16.The system may read and program in non-erasing

sectors, or enter the autoselect mode, when in the Erase

Suspend mode. The Erase Suspend command is valid

only during a sector erase operation, and requires the

bank address.

9. The fourth cycle of the autoselect command sequence is

a read cycle. The system must provide the bank address.

See the Autoselect Command Sequence section for more

information.

17. The Erase Resume command is valid only during the

Erase Suspend mode, and requires the bank address.

18.See “Set Configuration Register Command Sequence” for

details. This command is unavailable in Unlock Bypass

mode.

10. BDS128H: 2218h; BDS640H: 221Eh.

11. BDS128H: 2200h; BDS640H: 2201h

19.Command is valid when device is ready to read array

data or when device is in autoselect mode.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

45

P r e l i m i n a r y I n f o r m a t i o n

Command Definitions

Table 21. Sector Protection Command Definitions

Bus Cycles (Notes 1–6)

Command Sequence

(Notes)

First

Second

Third

Fourth

Fifth

Sixth

Seventh

Dat Add Dat

Dat

Dat Add

Add Dat

Addr

Data

Addr

Data

a

r

a

r

a

Entry

Exit

3

4

555

AA

2AA

55

555

88

90

XX

00

68

Protection Bit

Program (8, 9)

6

4

555

AA

2AA

55

555

60

38

SA+OW

48

OW RD(0)

XX[0–

3]

Program (11)

PD[0–3]

XX[0–

3]

Verify (11)

4

7

6

555

AA

2AA

55

555

C8

28

60

PD[0–3]

PD0

Unlock (11)

Program (8, 9)

XX0

XX1

PD1 XX2

PD2

XX3 PD3

SBA+W

P

SBA+W

P

68

48

40

XX

RD(0)

All Erase

(8, 10, 12)

SBA+W

PE

6

555

AA

2AA

55

555

60

WPE

60

RD(0)

BA+55

5

SBA+W

P

Status (13)

Set

4

3

4

555

AA

2AA

55

90

78

58

RD(0)

555

BA+55

5

Status (8)

SA

RD(1)

Write

Erase

4

555

AA

2AA

55

555

48

SA

X1

X0

BA+55

5

Status

4

555

AA

2AA

55

58

SA

RD(0)

Locking Bit Program

(8, 9)

6

555

AA

2AA

55

555

60

PL

68

PL

SL

48

PL

SL

RD(0)

Locking Bit Program

(8, 9)

6

555

AA

2AA

55

60

SL

68

Legend:

X = Don’t care

PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of

CLK which ever comes first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector.

BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for which command is being written.

SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked.

OW = Address (A7–A0) is (00011010).

PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit password.

PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.

PL = Address (A7–A0) is (00001010)

RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1.

If unprotected, DQ0 = 0.

RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1.

If unprotected, DQ1 = 0.

SBA = Sector address block to be protected.

SL = Address (A7–A0) is (00010010)

46

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

WD= Write Data. See “Configuration Register” definition for specific write data

WP = Address (A7–A0) is (00000010)

WPE = Address (A7-A0) is (01000010)

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles. All others are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PD3–PD0.

5. Unless otherwise noted, address bits Amax–A12 are don’t cares.

6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown

state. The system must write the reset command to return the device to reading array data.

7. No unlock or command cycles required when bank is reading array data.

8. Regardless of CLK and AVD# interaction or Control Register bit 15 setting, command mode verifies are always asynchronous

read operations.

9. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been

fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again.

10. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If

DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again.

11. The entire four bus-cycle sequence must be entered for each portion of the password.

12. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs.

13. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set.

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

Write Operation Status

The device provides several bits to determine the sta-

tus of a program or erase operation: DQ2, DQ3, DQ5,

mation on DQ7.

DQ6, and DQ7. Table 23, “Write Operation Status,” on

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then

the bank returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the

system reads DQ7 at an address within a protected

sector, the status may not be valid.

page 51 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offers a

method for determining whether a program or erase

operation is complete or in progress.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Program or Erase

algorithm is in progress or completed, or whether a

bank is in Erase Suspend. Data# Polling is valid after

the rising edge of the final WE# pulse in the command

sequence.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ6–DQ0 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may

read the status or valid data. Even if the device has

completed the program or erase operation and DQ7

has valid data, the data outputs on DQ6-DQ0 may be

still invalid. Valid data on DQ7-DQ0 will appear on suc-

cessive read cycles.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the Em-

bedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within

a protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then that bank returns to the read

mode.

Table 23, “Write Operation Status,” on page 51 shows

the outputs for Data# Polling on DQ7. Figure 8,

“Data# Polling Algorithm,” on page 48 shows the

Data# Polling algorithm. Figure 40, “Data# Polling

Timings (During Embedded Algorithm),” on page 75

in the AC Characteristics section shows the Data#

Polling timing diagram.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, or if the bank enters the Erase

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

47

P r e l i m i n a r y I n f o r m a t i o n

after the boundary that occurs every 64 words begin-

ning with the 64th address, 3Fh.

When the device is configured in Asynchronous Mode,

the RDY is an open-drain output pin which indicates

whether an Embedded Algorithm is in progress or

completed. The RDY status is valid after the rising

edge of the final WE# pulse in the command

sequence.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is in high im-

pedance (Ready), the device is in the read mode, the

standby mode, or in the erase-suspend-read mode.

Table 23, “Write Operation Status,” on page 51 shows

the outputs for RDY.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress in the same bank, and is valid after the rising

edge of the final WE# pulse in the command sequence

(prior to the program or erase operation), and during

the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. When the operation is complete, DQ6

stops toggling.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected.

Figure 8. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that

is, the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on DQ7: Data# Polling).

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.RDY:

Ready

The RDY is a dedicated output that, when the device

is configured in the Synchronous mode, indicates

(when at logic low) the system should wait 1 clock

cycle before expecting the next word of data. The RDY

pin is only controlled by CE#. Using the RDY Configu-

ration Command Sequence, RDY can be set so that a

logic low indicates the system should wait 2 clock cy-

cles before expecting valid data.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 ms after the program

command sequence is written, then returns to reading

array data.

The following conditions cause the RDY output to be

low: during the initial access (in burst mode), and

48

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, in-

dicates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in

progress), or whether that sector is erase-suspended.

Toggle Bit II is valid after the rising edge of the final

WE# pulse in the command sequence.

See the following for additional information: Figure 9,

“Toggle Bit Algorithm,” on page 49, “DQ6: Toggle Bit

I” on page 48, Figure 41, “Toggle Bit Timings

(During Embedded Algorithm),” on page 75 (toggle

bit timing diagram), and Table 22, “DQ6 and DQ2 In-

dications,” on page 50.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. But DQ2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. DQ6, by

comparison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both sta-

tus bits are required for sector and mode information.

Refer to Table 22, “DQ6 and DQ2 Indications,” on

page 50 to compare outputs for DQ2 and DQ6.

Toggle Bit I on DQ6 requires either OE# or CE# to be

deasserted and reasserted to show the change in

state.

START

Read Byte

(DQ7-DQ0)

Address = VA

Read Byte

(DQ7-DQ0)

Address = VA

See the following for additional information: Figure 9,

“Toggle Bit Algorithm,” on page 49, See “DQ6: Toggle

Bit I” on page 48., Figure 41, “Toggle Bit Timings

(During Embedded Algorithm),” on page 75, and

Table 22, “DQ6 and DQ2 Indications,” on page 50.

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Byte Twice

(DQ7-DQ0)

Adrdess = VA

No

DQ6 = Toggle?

Yes

FAIL

PASS

Note:The system should recheck the toggle bit even

if DQ5 = “1” because the toggle bit may stop toggling

as DQ5 changes to “1.” See the subsections on DQ6

and DQ2 for more information.

Figure 9. Toggle Bit Algorithm

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

49

P r e l i m i n a r y I n f o r m a t i o n

Table 22. DQ6 and DQ2 Indications

If device is

and the system reads

then DQ6

and DQ2

programming,

at any address,

toggles,

does not toggle.

at an address within a sector

selected for erasure,

toggles,

also toggles.

does not toggle.

toggles.

actively erasing,

erase suspended,

at an address within sectors not

selected for erasure,

at an address within a sector

selected for erasure,

does not toggle,

returns array data,

toggles,

at an address within sectors not

returns array data. The system can read

from any sector not selected for erasure.

selected for erasure,

programming in

erase suspend

at any address,

is not applicable.

Reading Toggle Bits DQ6/DQ2

DQ5: Exceeded Timing Limits

Refer to Figure 9, “Toggle Bit Algorithm,” on page 49

for the following discussion. Whenever the system ini-

tially begins reading toggle bit status, it must read

DQ7–DQ0 at least twice in a row to determine

whether a toggle bit is toggling. Typically, the system

would note and store the value of the toggle bit after

the first read. After the second read, the system

would compare the new value of the toggle bit with

the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1,” indicating that

the program or erase cycle was not successfully

completed.

The device may output a “1” on DQ5 if the system

tries to program a “1” to a location that was previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

However, if after the initial two read cycles, the sys-

tem determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no

longer toggling, the device has successfully completed

the program or erase operation. If it is still toggling,

the device did not completed the operation success-

fully, and the system must write the reset command

to return to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sec-

tors are selected for erasure, the entire time-out also

applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches

from a “0” to a “1.” If the time between additional sec-

tor erase commands from the system can be assumed

to be less than 50 µs, the system need not monitor

DQ3. See also “Sector Erase Command Sequence” on

page 39.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the

previous paragraph. Alternatively, it may choose to

perform other system tasks. In this case, the system

must start at the beginning of the algorithm when it

returns to determine the status of the operation

(Figure 9, “Toggle Bit Algorithm,” on page 49).

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

50

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

ther commands (except Erase Suspend) are ignored

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

Table 23 shows the status of DQ3 relative to the other

status bits.

Table 23. Write Operation Status

DQ5

(Note

1)

DQ7

DQ2

(Note 2)

RDY

(Note 5)

Status

(Note 2)

DQ7#

0

DQ6

DQ3

N/A

1

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

0

No toggle

Toggle

0

Standard

Mode

High

Impedanc

e

Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

Erase-Suspend-

Read (Note 4)

Erase

Suspend

Mode

High

Impedanc

e

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

Erase-Suspend-Program

DQ7#

Toggle

0

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for

further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded

Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

4. The system may read either asynchronously or synchronously (burst) while in erase suspend.

5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in

progress. This is available in the Asynchronous mode only.

Absolute Maximum Ratings

Storage Temperature

Plastic Packages –65°C to +150°C

V

(Note 1)

–0.5 V to +2.5 V

CC

IO

Ambient Temperature

with Power Applied–65°C to +125°C

A9, RESET#, ACC (Note 1)–0.5 V to +12.5 V

Output Short Circuit Current (Note 3)100

mA

Voltage with Respect to Ground:

All Inputs and I/Os except

as noted below (Note 1)–0.5 V to V + 0.5 V

IO

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot V_SSto –

2.0 V for periods of up to 20 ns. See Figure 10. Maximum DC voltage on input or I/Os is V_CC+ 0.5 V. During voltage

transitions outputs may overshoot to V_CC+ 2.0 V for periods up to 20 ns. See Figure 11.

2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater

than one second.

3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at these or any other conditions above those indicated in the

operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions

for extended periods may affect device reliability.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

51

P r e l i m i n a r y I n f o r m a t i o n

Operating Ranges

20 ns

Industrial (I) Devices

+0.8 V

Ambient Temperature (T )–40°C to +85°C

A

–0.5 V

–2.0 V

Supply Voltages

V

Supply Voltages+1.65 V to +1.95 V

CC

IO

≥ V –100 mV

IO

Supply Voltages +1.65 V to +1.95 V

20 ns

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

Figure 10. Maximum Negative

Overshoot Waveform

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

1.0 V

20 ns

Figure 11. Maximum Positive

Overshoot Waveform

52

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

DC Characteristics

CMOS Compatible

Paramete

r

Description

Test Conditions Note: 1 & 2

V_IN= V_SSto V_CC, V_CC= V_CCmax

V_OUT= V_SSto V_CC, V_CC= V_CCmax

Min

Typ

Max

±1

Unit

µA

I_LI

I_LO

Input Load Current

Output Leakage Current

±1

µA

CE# = V_IL, OE# = V_IH

WE# = V_IH, burst

length = 8

,

54 MHz

75 MHz

54 MHz

75 MHz

54 MHz

75 MHz

9

12

8

17

mA

24

15.5

22

mA

CE# = V_IL, OE# = V_IH

WE# = V_IH, burst

length = 16

I_CCB

V_CCActive burst Read Current

V_IONon-active Output

11

7

CE# = V_IL, OE# = V_IH

WE# = V_IH, burst

length = Continuous

14

10

20

I_IO1

OE# = V_IH

1

40

30

15

5

µA

mA

µA

10 MHz

5 MHz

1 MHz

20

10

3.5

15

0.2

1

V_CCActive Asynchronous Read

Current (Note 3)

CE# = V_IL, OE# = V_IH

WE# = V_IH

,

I_CC1

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (Note 4) CE# = V_IL, OE# = V_IH, ACC = V_IH

40

V_CCStandby Current (Note 5)

V_CCReset Current

CE# = RESET# = V_CC± 0.2 V

RESET# = V_IL,CLK = V_IL

µA

V_CCActive Current

(Read While Write)

I_CC5

I_CC6

CE# = V_IL, OE# = V_IH

25

60

mA

V_CCSleep Current

1

7

5

40

15

µA

mA

V

V_ACC

V_CC

Accelerated Program Current

(Note 6)

CE# = V_IL, OE# = V_IH,

V_ACC= 12.0 ± 0.5 V

I_ACC

10

V_IL

V_IH

V_OL

Input Low Voltage

Input High Voltage

Output Low Voltage

V_IO= 1.8 V

–0.4

0.4

V_IO– 0.4

V_IO+ 0.4

0.1

V

I_OL= 100 µA, V_IO= V_CC= V_{CC min}

V

I_OH= –100 µA, V_IO= V_CC= V_CC

V_OH

Output High Voltage

V_IO– 0.1

11.5

V

min

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_CC= 1.8 V

12.5

V_HH

Voltage for Accelerated Program

Low V_CCLock-out Voltage

11.5

1.0

12.5

1.4

V

V_LKO

Note:

1. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

2. V_IO= V_CC

3. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH

.

4. I_CCactive while Embedded Erase or Embedded Program is in progress.

5. Device enters automatic sleep mode when addresses are stable for t_ACC+ 60 ns. Typical sleep mode current is equal to I_CC3

.

6. Total current during accelerated programming is the sum of V_ACCand V_CCcurrents.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

53

P r e l i m i n a r y I n f o r m a t i o n

Test Conditions

Table 24. Test Specifications

Test Condition

All Speed Options Unit

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

C

Input Rise and Fall Times

Input Pulse Levels

3

ns

V

L

0.0–V_IO

Input timing measurement

reference levels

V_IO/2

V

Output timing measurement

reference levels

Figure 12. Test Setup

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

Switching Waveforms

V_IO

All Inputs and Outputs

V_IO/2

Input

Measurement Level

Output

0.0 V

Figure 13. Input Waveforms and Measurement Levels

54

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

V_CCPower-up

Parameter

t_VCS

Description

V_CCSetup Time

Test Setup

Min

Speed

50

Unit

µs

t_VIOS

V_IOSetup Time

Min

50

µs

t_RSTH

RESET# Low Hold Time

Min

50

µs

t_VCS

V_CC

f

t_VIOS

V_IO

f

t_RSTH

RESET#

Figure 14. V_CCPower-up Diagram

Notes:

1. V_CC≥ V_IO–100 mV and V_CCramp rate exceeds 1 V/100 µs.

2. If the V_CCramp rate is less than 1 V /100 µs, a hardware reset will be required.

CLK Characterization

Parameter

Description

CLK Frequency

75 MHz

75

66 MHz

66

54 MHz

Unit

f_CLK

t_CLK

t_CH

t_CL

Max

Min

54

MHz

ns

CLK Period

CLK High Time

CLK Low Time

CLK Rise Time

CLK Fall Time

13.3

15

18.5

Min

5.3

2.5

6.0

3

7.4

3

ns

t_CR

t_CF

Max

t

CLK

t

CL

CH

CLK

t

CF

CR

Figure 15. CLK Characterization

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

55

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Synchronous/Burst Read

Parameter

JEDEC Standard Description

75 MHz

66 MHz

54 MHz

Unit

Latency (Even address in Reduced

wait-state Handshaking mode)

t_IACC

t_BACC

Max

49

56

69

ns

Latency (Standard Handshaking or

Odd address in Reduced wait-state

Handshaking mode

62

71

11

87.5

13.5

ns

Burst Access Time Valid Clock to

Output Delay

9.3

t_ACS

t_ACH

t_BDH

t_CR

Address Setup Time to CLK (Note )

Address Hold Time from CLK (Note )

Data Hold Time from Next Clock Cycle

Chip Enable to RDY Valid

Output Enable to Output Valid

Chip Enable to High Z

Min

Max

Min

Max

Min

Max

Min

Max

4

3

5

7

ns

ms

5.5

6

4

9.3

11

13.5

10

5

t_OE

t_CEZ

t_OEZ

t_CES

t_RDYS

t_RACC

t_AAS

t_AAH

t_CAS

t_AVC

t_AVD

t_ACC

t_CKA

t_CKZ

t_OES

t_RCC

8

4

Output Enable to High Z

CE# Setup Time to CLK

RDY Setup Time to CLK

5

Ready Access Time from CLK

Address Setup Time to AVD# (Note )

Address Hold Time to AVD# (Note )

CE# Setup Time to AVD#

AVD# Low to CLK

9.3

5.5

11

13.5

5

4

6

0

7

4

5

12

55

13.5

10

5

AVD# Pulse

10

Access Time

45

50

11

CLK to access resume

9.3

CLK to High Z

8

4

Output Enable Setup Time

Read cycle for continuous suspend

1

Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.

56

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

t_CEZ

t_CES

7 cycles for initial access shown.

CE#f

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Addresses

Data

Aa

t_BACC

t_ACH

Hi-Z

t_IACC

t_ACC

Da

Da + 1

Da + n

t_OEZ

OE#

RDY

t_CR

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 16. CLK Synchronous Burst Mode Read (Rising Active CLK)

t_CEZ

4 cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Aa

Addresses

Data

t_BACC

t_ACH

Hi-Z

t_IACC

t_ACC

Da

Da + 1

Da + n

t_OEZ

OE#

RDY

t_RACC

t_OE

t_CR

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from

two cycles to seven cycles. Clock is set for active falling edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock)

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

57

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

t_CEZ

7 cycles for initial access shown.

t_CAS

CE#

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_AAS

t_BDH

Addresses

Data

Aa

t_BACC

t_AAH

Hi-Z

t_IACC

Da

Da + 1

Da + n

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_CR

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed

from two cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 18. Synchronous Burst Mode Read

7

cycles for initial access shown.

t_CES

CE#

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

A6

Addresses

Data

t_BACC

t_ACH

t_IACC

t_ACC

D6

D7

D0

D1

D5

D6

OE#

RDY

t_CR

t_RACC

t_OE

Hi-Z

t_RDYS

Note: Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0–D7 in data

waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting

address in figure is the 7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”.

The Set Configuration Register command sequence has been written with A18=1; device will output RDY with

valid data.

Figure 19. 8-word Linear Burst with Wrap Around

58

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

t_CEZ

6

wait cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

6

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Aa

Addresses

Data

t_BACC

t_ACH

Hi-Z

t_IACC

Da

Da+1

Da+2

Da+3

Da + n

t_ACC

t_OEZ

t_RACC

OE#

RDY

t_CR

t_OE

Hi-Z

t_RDYS

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY one cycle before valid data.

Figure 20. Linear Burst with RDY Set One Cycle Before Data

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

59

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Suspend

Resume

x

x+2

x+3

x+4

x+6

x+7

x+8

x+1

x+5

CLK

AVD#

t

OES

Addresses

t

CKA

t

CKZ

OE#

Data

D(24)

D(20)

D(23)

D(22)

D(20)

D(21)

RDY

t

RACC

t

RACC

Note: Figure is for any even address other than 3Eh (or multiple thereof).

Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at an even address

Suspend

Resume

x+1

x

x+2

x+3

x+4

x+6

x+7

x+8

x+5

CLK

AVD#

t

OES

Addresses

t

CKA

t

CKZ

OE#

Data

D(27)

D(23)

D(25)

D(26)

D(25)

D(23)

D(24)

RDY

t

RACC

t

RACC

Note: Figure is for any odd address other than 3Fh (or multiple thereof).

Figure 22. Reduced Wait-state Handshake Burst Suspend/Resume at an odd address

60

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Resume

x+1

Suspend

x+2

x+3

x+4

x+5

x+7

x+8

x+9

x

x+6

x+10

CLK

AVD#

t

OES

t

OES

Addresses

OE#

t

CKA

t

CKZ

D(41)

D(42)

D(41)

D(3E)

D(41)

D(3E)

D(3F)

D(40)

D(3F)

D(41)

D(3F)

Data

RDY

t

RACC

Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at address 3Eh (or offset from 3Eh)

Resume

x+1

Suspend

x+2

x+3

x+4

x+5

x+7

x+8

x+9

x

x+6

x+10

CLK

AVD#

t

OES

t

OES

Addresses

OE#

t

CKA

t

CKZ

D(41)

D(43)

D(42)

D(3F)

RACC

D(41)

D(3F)

D(41)

D(40)

D(41)

D(3F)

Data

RDY

t

RACC

t

RACC

Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume at address 3Fh (or offset from 3Fh by a multiple of 64)

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

61

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Resume

x+1

Suspend

x

x+2

x+3

x+4

x+6

x+7

x+8

1

2

6

5

3

4

7

x+5

CLK

AVD#

t

OES

A(n)

Addresses

t

CKA

OE#

Data(1)

RDY(1)

D(n)

D(n+2)

D(n+1)

3F

D(3F)

3F

D(40)

t

ACC

t

RACC

D(n+2) D(n+3) D(n+4) D(n+5)

Data(2)

RDY(2)

D(n+1)

D(n)

D(n+6)

t

RACC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) RDY goes low during the two-cycle latency during a boundary crossing.

2) RDY stays high when a burst sequence crosses no boundaries.

Figure 25. Standard Handshake Burst Suspend prior to Initial Access

Resume

Suspend

x

1

6

9

x+2

5

x+1

2

3

4

7

8

x+3

CLK

AVD#

t_OES

Addresses

OE#(1)

A(n)

t_CKA

t_CKZ

D(n)

D(n+1)

Data(1)

RDY(1)

t_ACC

t_RACC

OE#(2)

Data(2)

D(n+2)

D(n+1)

D(n)

D(n+1)

t_RACC

RDY(2)

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Burst suspend during the initial synchronous access

2) Burst suspend after one clock cycle following the initial synchronous access

Figure 26. Standard Handshake Burst Suspend at or after Initial Access

62

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Resume

x+1

Suspend

x

x+2

x+5

x+4

x+3

1

6

9

5

2

3

4

7

8

CLK

AVD#

t_OES

A(3D)

Addresses

OE#

t_CKA

t_CKZ

D(3F)

D(3F) D(4D)

D(3D)

D(3E)

D(3F)

Data

RDY

t_ACC

t_RACC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

Figure 27. Standard Handshake Burst Suspend at address 3Fh (starting address 3Dh or earlier)

Resume

Suspend

5

x

1

2

3

6

7

x+1

x+2

x+3

4

x+4

x+5

x+6

8

CLK

AVD#

t_OES

A(3E)

Addresses(1)

t_OES

t_CKA

OE#

t_CKZ

D(40)

D(3F)

D(41)

D(42)

D(3E)

Data(1)

RDY(1)

t_ACC

t_RACC

Addresses(2)

A(3F)

Data(2)

RDY(2)

D(41)

D(3F)

t_RACC

D(40)

D(42)

D(43)

D(3F)

t

t_RACC

RACC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1. Address is 3Eh or offset by a multiple of 64 (40h)

2. Address is 3Fh or offset by a multiple of 64 (40h)

Figure 28. Standard Handshake Burst Suspend at address 3Eh/3Fh (without a valid Initial Access)

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

63

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Suspend

8

Resume

x+1

5

1

2

3

6

7

4

9

x

x+2

x+3

x+4

x+5

x+6

CLK

AVD#

t

OES

A(3E)

Addresses(1)

OE#

t_OES

t

CKA

t

CKZ

D(40)

Data(1)

D(3F)

RACC

D(41)

D(42)

D(3E)

t

ACC

RDY(1)

(Even)

t

RACC

t

RACC

Addresses(2)

Data(2)

A(3F)

D(3F)

D(41)

D(42)

D(40)

D(43)

D(40)

RACC

RDY(2)

(Odd)

t

RACC

t

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Address is 3Eh or offset by a multiple of 64 (40h)

2) Address is 3Fh or offset by a multiple of 64 (40h)

Figure 29. Standard Handshake Burst Suspend at address 3Eh/3Fh (with 1 Access CLK)

Resume

Suspend

x

x+2

x+3

x+4

x+6

x+7

x+8

1

6

5

x+1

2

3

4

7

x+5

CLK

t

RCC

AVD#

t

OES

A(n)

Addresses

OE#

t

CKA

Data(1)

RDY

D(n)

D(n+2)

D(n+1)

D(3F) D(3F)

D(3F)

D(40)

t

ACC

t

RACC

D(n)

???

Data(2)

CE#

???

t

RCC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Device crosses a page boundary prior to t

RCC

2) Device neither crosses a page boundary nor latches a new address prior to t

RCC

Figure 30. Read Cycle for Continuous Suspend

64

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Asynchronous Mode Read

Parameter

Standar

JEDEC

d

Description

75 MHz

45

66 MHz

50

54 MHz

Unit

ns

t_CE

Access Time from CE# Low

Asynchronous Access Time (Note 1)

AVD# Low Time

Max

Min

Max

Min

55

12

5

t_ACC

45

50

ns

t_AVDP

t_AAVDS

t_AAVDH

t_OE

10

4

ns

Address Setup Time to Rising Edge of AVD

Address Hold Time from Rising Edge of AVD

Output Enable to Output Valid

ns

5.5

8.5

6

11

0

7

ns

13.5

ns

Read

ns

Output Enable Hold

Time

t_OEH

Toggle and

Data# Polling

Min

8

10

ns

t_OEZ

t_CAS

Output Enable to High Z (Note 2)

CE# Setup Time to AVD#

Max

Min

ns

0

Notes:

1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.

2. Not 100% tested.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

65

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

CE#

t_OE

OE#

t_OEH

WE#

Data

t_CE

t_OEZ

Valid RD

t_ACC

RA

Addresses

AVD#

t_AAVDH

t_CAS

t_AVDP

t_AAVDS

Note: RA = Read Address, RD = Read Data.

Figure 31. Asynchronous Mode Read with Latched Addresses

CE#

OE#

t_OE

t_OEH

WE#

Data

t_CE

t_OEZ

Valid RD

t_ACC

RA

Addresses

AVD#

Note: RA = Read Address, RD = Read Data.

Figure 32. Asynchronous Mode Read

66

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Hardware Reset (RESET#)

Parameter

All Speed

Options

JEDEC

Std

Description

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Readyw

Max

35

µs

RESET# Pin Low (NOT During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

RESET# Pulse Width

Min

500

200

20

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

t_RPD

µs

Note: Not 100% tested.

CE#, OE#

t_RH

RESET#

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

CE#, OE#

RESET#

t_Readyw

t_RP

Figure 33. Reset Timings

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

67

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Erase/Program Operations

Parameter

JEDEC

Standard

Description

Write Cycle Time (Note 1)

75 MHz

66 MHz

54 MHz

Unit

t

Min

45

50

55

5

ns

AVAV

WC

Synchronous

Asynchronous

Synchronous

Asynchronous

4

Address Setup Time

t

ns

AVWL

AS

(Notes 2, 3)

0

6

5.5

15

7

Address Hold Time

(Notes 2, 3)

t

Min

WLAX

AH

20

12

t

AVD# Low Time

Min

Typ

10

20

ns

µs

AVDP

t

Data Setup Time

Data Hold Time

45

DVWH

DS

t

0

WHDX

DH

t

Read Recovery Time Before Write

CE# Setup Time to AVD#

GHWL

t

CAS

t

CE# Hold Time

WHEH

CH

t

Write Pulse Width

20

30

20

WLWH

WP

t

Write Pulse Width High

15

20

0

WHWL

WPH

t

Latency Between Read and Write Operations

Programming Operation (Note 4)

SR/W

t

9

WHWH1

t

Accelerated Programming Operation (Note 4)

Sector Erase Operation (Notes 4, 5)

Chip Erase Operation (Notes 4, 5)

4

WHWH1

0.2

104

500

t

Typ

sec

WHWH2

t

V

Rise and Fall Time

Min

ns

µs

ns

VID

ACC

t

V

Setup Time (During Accelerated Programming)

1

50

0

VIDS

ACC

t

V

Setup Time

CC

VCS

t

CE# Setup Time to WE#

AVD# Setup Time to WE#

ELWL

CS

t

4

5

7

5

AVSW

t

AVD# Hold Time to WE#

AVHW

t

Address Setup Time to CLK (Notes 2, 3)

Address Hold Time to CLK (Notes 2, 3)

AVD# Hold Time to CLK

ACS

t

5.5

6

5

ACH

t

4

AVHC

t

Clock Setup Time to WE#

CSW

Notes:

1. Not 100% tested.

2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both

Asynchronous and Synchronous program operation.

3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In

synchronous program operation timing, addresses are latched on the first of either the falling edge of WE# or the active

edge of CLK.

4. See the “Erase and Programming Performance” section for more information.

5. Does not include the preprogramming time.

68

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Program Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

PA

VA

Addresses

Data

555h

In

Complete

A0h

PD

t_DS

t_DH

Progress

CE#f

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V_CCf

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. Amax–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V_ILor V_IH

.

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Reg-

ister.

Figure 34. Asynchronous Program Operation Timings: AVD# Latched Addresses

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

69

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Program Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVSW

t_AVHW

AVD#

t_AVDP

t_AS

t_AH

Addresses

Data

555h

PA

VA

In

A0h

Complete

PD

Progress

t_DS

t_DH

CE#f

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V

_CCf

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. Amax–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V_ILor V_IH

.

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Reg-

ister.

Figure 35. Asynchronous Program Operation Timings: WE# Latched Addresses

70

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_ACS

t_ACH

AVD#

t_AVDP

Addresses

Data

PA

VA

555h

In

Complete

A0h

PD

t_DS

t_DH

Progress

t_CAS

CE#f

t_CH

OE#

WE#

t_CSW

t_WP

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

f

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. Amax–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.

The Configuration Register must be set to the Synchronous Read Mode.

Figure 36. Synchronous Program Operation Timings: WE# Latched Addresses

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

71

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_AS

t_AH

AVD#

t_AVDP

Addresses

555h

PA

VA

In

Data

Complete

A0h

PD

t_DS

t_DH

Progress

t_CAS

CE#f

t_CH

OE#

WE#

t_CSW

t_WP

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

f

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. Amax–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.

The Configuration Register must be set to the Synchronous Read Mode.

Figure 37. Synchronous Program Operation Timings: CLK Latched Addresses

72

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Erase Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

SA

555h for

chip erase

VA

Addresses

Data

2AAh

10h for

chip erase

In

Complete

55h

30h

Progress

t_DS

t_DH

CE#

t_CH

OE#

WE#

t_WP

t_WHWH2

t_CS

t_WPH

t_WC

t_VCS

V_CC

Figure 38. Chip/Sector Erase Command Sequence

Notes:

1. SA is the sector address for Sector Erase.

2. Address bits Amax–A12 are don’t cares during unlock cycles in the command sequence.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

73

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

CE#

AVD#

WE#

Addresses

Data

PA

Don't Care

A0h

Don't Care

PD

Don't Care

OE#

t_VIDS

1 µs

V

ID

ACC

t_VID

or V

IL

IH

Note: Use setup and hold times from conventional program operation.

Figure 39. Accelerated Unlock Bypass Programming Timing

74

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

VA

Addresses

Data

VA

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm

operation is complete, and Data# Polling will output true data.

3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 40. Data# Polling Timings (During Embedded Algorithm)

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

Addresses

Data

VA

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm

operation is complete, the toggle bits will stop toggling.

3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 41. Toggle Bit Timings (During Embedded Algorithm)

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

75

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

CE#

CLK

AVD#

Addresses

OE#

VA

t_IACC

Data

Status Data

RDY

Notes:

1. The timings are similar to synchronous read timings.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the

toggle bits will stop toggling.

3. RDY is active with data (A18 = 0 in the Configuration

Register). When A18 = 1 in the Configuration Register,

RDY is active one clock cycle before data.

Figure 42. Synchronous Data Polling Timings/Toggle Bit Timings

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#

to toggle DQ2 and DQ6.

Figure 43. DQ2 vs. DQ6

76

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RDY High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

RDY

t_RRB

t_RSP

Figure 44. Temporary Sector Unprotect Timing Diagram

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

77

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

V

ID

V

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Protect/Unprotect

Verify

40h

Data

60h

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 45. Sector/Sector Block Protect and Unprotect Timing Diagram

78

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Address boundary occurs every 64 words, beginning at address

00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

C65

41

C66

42

C67

43

CLK

3C

Address (hex)

(stays high)

AVD#

RDY(1)

RDY(2)

t_RACC

latency

t_RACC

latency

Data

D60

D61

D62

D63

D64

D65

D66

D67

Notes:

1. RDY active with data (A18 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the

device not crossing a bank in the process of performing an erase or program.

4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2

cycle latency at the boundary crossing.

Figure 46. Latency with Boundary Crossing

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

79

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Address boundary occurs every 64 words, beginning at address

00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

CLK

3C

Address (hex)

(stays high)

AVD#

RDY(1)

RDY(2)

t_RACC

latency

t_RACC

latency

Data

Invalid

D60

D61

D62

D63

Read Status

OE#,

CE#

(stays low)

Notes:

1. RDY active with data (A18 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device

crossing a bank in the process of performing an erase or program.

Figure 47. Latency with Boundary Crossing

into Program/Erase Bank

80

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Data

D0

D1

Rising edge of next clock cycle

following last wait state triggers

next burst data

AVD#

OE#

total number of clock cycles

following AVD# falling edge

1

2

0

3

1

4

5

6

4

7

5

CLK

2

3

number of clock cycles

programmed

Wait State Decoding Addresses:

A14, A13, A12 = “111” ⇒ Reserved

A14, A13, A12 = “110” ⇒ Reserved

A14, A13, A12 = “101” ⇒ 5 programmed, 7 total

A14, A13, A12 = “100” ⇒ 4 programmed, 6 total

A14, A13, A12 = “011” ⇒ 3 programmed, 5 total

A14, A13, A12 = “010” ⇒ 2 programmed, 4 total

A14, A13, A12 = “001” ⇒ 1 programmed, 3 total

A14, A13, A12 = “000” ⇒ 0 programmed, 2 total

Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is

set to “101”.

Figure 48. Example of Wait States Insertion

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

81

P r e l i m i n a r y I n f o r m a t i o n

AC Characteristics

Last Cycle in

Program or

Sector Erase

Read status (at least two cycles) in same bank

and/or array data from other bank

Begin another

write or program

command sequence

Command Sequence

t_WC

t_RC

t_WC

CE#

OE#

t_OE

t_GHWL

t_OEH

WE#

Data

t_WPH

t_OEZ

t_WP

t_DS

t_ACC

t_OEH

t_DH

PD/30h

RD

AAh

t_SR/W

RA

Addresses

AVD#

PA/SA

t_AS

RA

555h

t_AH

Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank”

while checking the status of the program or erase operation in the “busy” bank. The system should read status

twice to ensure valid information.

Figure 49. Back-to-Back Read/Write Cycle Timings

82

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Erase and Programming Performance

Typ (Note

1)

Parameter

Max (Note 2)

Unit

Comments

32 Kword

4 Kword

128 Mb

64 Mb

0.4

0.2

103

54

5

Sector Erase Time

s

Excludes 00h programming prior to erasure

(Note 4)

s

Chip Erase Time

Word Programming Time

9

210

120

226.5

114

99

µs

s

Accelerated Word Programming Time

4

Excludes system level overhead (Note 5)

128 Mb

75.5

38

Chip Programming Time

(Note 3)

64 Mb

s

128 Mb

33

s

Accelerated Chip

Programming Time

64 Mb

17

30

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V_CC, 100,000 cycles. Additionally,

programming typicals assumes a checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 1.65 V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 20, “Memory Array Command Definitions,” on page 44 for further information on command

definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

BGA Ball Capacitance

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

4.2

5.4

3.9

Max

5.0

6.5

4.7

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

83

P r e l i m i n a r y I n f o r m a t i o n

Revision Summary

Revision A (February 17, 2004)

“Sector Protection Command

Definitions” on page 46

Initial release.

Table 21: Removed “8” from SecSi Sector/Protection

Bit Program row; Removed “8” from Password/Pro-

gram row; Removed “8” from PPB/Password row;

Removed “8” from PPB/All Erase row; Added “E” to

PPB/Fourth ADDR column; Added “E” to PPB/Fifth/

Revision A2 (May 26, 2004)

“Erase Suspend/Erase Resume

Commands” on page 40

Replaced “20µ” with 35µs.

ADDR column; WP

“(01000010)” added “(00000010)”; Added “WPE =

Address (A7-A0) is (01000010).

= Address... removed

“Password Verify Command” on page 41

Replaced “Read/Reset” with SecSi Sector Exit.

“Password and Password Mode Locking

Bit” on page 19

Table 21, “Sector Protection Command

Definitions,” on page 46

Added “or Read/Reset command”.

Removed Note#9 from table notes.

“Persistent Sector Protection Mode

Locking Bit” on page 18

Figure 6, “PPB Program Algorithm,” on

page 43

Added “or Read/Reset command”.

Added table to document.

“PPB Lock Bit Set Command” on page 42

Replaced “Read/Reset” with “SecSi Sector exit”.

Figure 7, “All PPB Erase Algorithm,” on

page 43

Added figure to document.

“Password Unlock Command” on page 42

Added “Exiting the password unlock command is ac-

complished by writing SecSi Sector Exit command”.

Revision A3 (June 1, 2004)

Global changes

“PPB Program Command” on page 42

Updated paragraph styles for consistency.

Added “or Read/Reset command”.

Added table number to all tables without for

consistency.

“All PPB Erase Command” on page 43

“Autoselect Data” on page 38

Changed “DQ0=1” to “DQ0=0”.

Changed Read Data for Device ID Word 1.

Changed Read Data for Device ID Word 3.

added “or Read/Reset command”.

“DYB Write Command” on page 42

Added “Writing Read/Reset command returns the de-

vice to normal operation.

Revision A4 (June 7, 2004)

“Erase Suspend/Erase Resume

Commands” on page 40

Replaced “35ms” with 35µs.

“DYB Status Command” on page 44

Added “Writing Read/Reset command and SecSi Sec-

tor Exit command returns the device to normal

operation.

Revision A5 (June 18, 2004)

Global - Reformatted to include 2 column style.

Added “Writing SecSi Sector Exit command returns

the device to normal operation.

Global - Changed all Helvetica formats to Gills Sans

For AMD.

Added Colophon to document.

84

Am29BDS128H/Am29BDS064H

27024_A5_00_E June 18, 2004

P r e l i m i n a r y I n f o r m a t i o n

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that FASL will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned

uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other

abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice.

This document may contain information on a Spansion product under development by FASL LLC. FASL LLC reserves the right to change or discontinue work

on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness,

operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. FASL

LLC assumes no liability for any damages of any kind arising out of the use of the information in this document.

Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this

publication are for identification purposes only and may be trademarks of their respective companies.

June 18, 2004 27024_A5_00_E

Am29BDS128H/Am29BDS064H

85


型号：	AM29BDS128HF8VKI
厂家：	SPANSION
描述：	Flash, 8MX16, 45ns, PBGA80, FBGA-80
文件：	总85页 (文件大小：2642K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29BDS128HF8VKI [SPANSION]

相关型号：

AM29BDS128HF9VKF

AM29BDS128HF9VKI

AM29BDS320G

AM29BDS320GBC3VMF

AM29BDS320GBC3VMI

AM29BDS320GBC4VMF

AM29BDS320GBC4VMI

AM29BDS320GBC8VMF

AM29BDS320GBC8VMI

AM29BDS320GBC9VMI

AM29BDS320GBD3VMF

AM29BDS320GBD3VMI