PPC440SPE-RNB533C_技术文档

Part Number 440SPe

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

PowerPC 440SPe Embedded Processor

Features

®

• Optional:16 Programmable Galois Field

• PowerPC 440 processor core operating up to

polynomials including 14d and 11d

• XOR Accelerator with DMA controller

• I2O messaging with two DMA controllers

667 MHz with 32KB I- and D-caches (with parity

checking)

• On-chip 256KB SRAM configurable as L2 Cache

or Ethernet Packet/Code store memory

• External Peripheral Bus (16-bit Data, 27-bit

Address) for up to three devices; Bank0=16 MB,

Bank1 and Bank2=128 MB each

• Selectable Processor vs Bus clock ratios (Refer to

the Clocking chapter in the PPC440SPe

Embedded Processor User’s Manual for details)

• One Ethernet 10/100/1000Mbps half- or full-

duplex interface. Operational modes supported

are MII and GMII.

• Support up to 16 GB (4 Chip Selects) of 64-bit/32-

bit SDRAM with ECC

DDR I 266-333-400

DDR II 400-533-667

• Programmable Interrupt Controller supports

interrupts from a variety of sources.

• Three PCI-Express serial interfaces:

one 8 lanes and two 4 lanes - 2.5Gb/s per lane

Root and Endpoint support.

• Programmable General Purpose Timers (GPT)

• Three serial ports (16750 compatible UART)

• Two IIC interfaces

Opaque bridge

• One 64-bit DDR PCI-X interfaces up to 133 MHz

(DDR 266) with support for conventional PCI

• General Purpose I/O (GPIO) interface available

• JTAG interface for board level testing

• Processor can boot from PCI memory

• Optional: High throughput RAID 6 hardware

acceleration, performs XOR and Galois Field P &

Q parity computations, supports up to 255 drives

Description

Designed specifically to address high-end embedded

applications for storage, the PowerPC 440SPe

(PPC440SPe) provides a high-performance, low

power solution that interfaces to a wide range of

peripherals by incorporating on-chip power

Technology: CMOS Cu-11, 0.13mm

Package: 27mm, 675-ball, 1mm pitch, Flip Chip-

Plastic Ball Grid Array (FC-PBGA)

Power (estimated): Less than 14W @533MHz

Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V

management features and lower power dissipation.

This chip contains a high-performance RISC

processor core, a DDR1/DDR2 SDRAM controller,

configurable 256KB SRAM to be used as L2 cache or

software-controlled on-chip memory, three PCI-

Express interfaces, one DDR PCI-X bus interface, a

1Gbps Ethernet interface, an I2O/DMA controller,

control for external ROM and peripherals, optional

RAID 6 acceleration, an XOR DMA unit, serial ports,

IIC interfaces, and general purpose I/O.

AMCC Proprietary

1

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Contents

Preliminary Data Sheet

Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

PPC440SPe Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

On-Chip SRAM/L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DDR PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DDR1/DDR2 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I2O/DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Optional RAID 5 and RAID 6 Acceleration Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

XOR/DMA2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

27mm, 675-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Clock Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Serial Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Figures

Preliminary Data Sheet

Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. PPC440SPe Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. 27mm, 675-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4. Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 6. Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 7. DDR SDRAM Signal Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 8. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 9. DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 10. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 11. DDR SDRAM Read Cycle Timing—Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Tables

Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. DCR Address Map (4KB of Device Configuration Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 5. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 10. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 11. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 12. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 13. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 14. I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 15. I/O Specifications—667MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 16. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 17. DDR SDRAM Read and Write I/O Timing—TSA and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 18. DDR SDRAM Clock to Write DQS Timing—T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

DS

Table 19. DDR SDRAM Write Data to DQS Timing—TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 20. DDR SDRAM I/O Read Timing—T and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

HD

SD

Table 21. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

AMCC Proprietary

3

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Ordering and PVR Information

Preliminary Data Sheet

For information about the availability of the following parts, contact your local sales office. The most current version

of the 440SPe is Revision B. The part numbers for 440SPe Revision B are shown in the following figures.

Order Part Number

(see Notes 1-5)

Rev

Level

Product Name

Package

PVR Value

JTAG ID

PPC440SPe

PPC440SPe-xpBfffC

27mm, 675 FC-PBGA

B

0x53421891

0x14538049

Notes:

1. x = Product Feature

A = RAID6 not enabled (Rev Level B only)

R = RAID6 enabled (Rev Level B only)

2. p = Module Package Type

G = leaded FC-PBGA

N = lead free FC-PGBA (RoHS compliant)

3. B = Chip Revision Level B (2.0)

4. fff = Processor Frequency

533 = 533MHz

667 = 667MHz

5. C = Case Temperature Range of 0°C to +95°C

Each part number contains a revision code. This is the die mask revision number and is included in the part

number for identification purposes only.

The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain

information that uniquely identifies the part. See the PPC440SPe Embedded Processor User’s Manual for details

about accessing these registers.

Note: Raid-enabled versions (Product Feature = R) require a RAID key license.

Figure 1. Order Part Number Key

PPC440SPe-RNB667C

AMCC Part Number

Case Temperature Range

Product Feature

Package

Processor Speed

Revision Level

Note: The example part number above is a RAID6-enabled, lead-free package, at Chip Revision

Level B, at PCI Express core revision level 1.1, capable of running at 667 MHz, and is shipped in

tray packaging.

The part numbers for 440SPe Revision A are shown in the following figure.

Product

Name

Processor

Frequency

Rev

Level

Order Part Number

Package

PVR Value

JTAG ID

PPC440SPe

PPC440SPe-3GA533C

PPC440SPe-3GA667C

533MHz

667MHz

27mm, 675 FC-PBGA

A

0x53421890

0x14538049

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AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

PPC440SPe Functional Block Diagram

Figure 2. PPC440SPe Functional Block Diagram

16 IRQs

Clock,

Power

Mgmt

Control,

Reset

Universal

Interrupt

Controller

Timers

MMU

DCRs

Registers

MAC

UART

IIC

PPC440

Processor Core

GP

Timers

GPIO

DCR Bus

x2

x3

Trace

32KB

I-Cache

JTAG

On-chip Peripheral Bus (OPB)

32KB

D-Cache

PCI-E

IRQ Handler

OPB

Bridge

256 KB

L2 Cache/SRAM

PLB

Arb

Processor Local Bus (PLB)

Low Latency (LL) Segment

High Bandwidth (HB) Segment

Ethernet

10/100/

1000

External

Bus Controller

(EBC)

MAL

MII,

GMII

Memory

Queue

PCI-Express

PCI-E0 PCI-E1 PCI-E2

DDR PCI-X

64-bit

I2O/DMA

Controller

(DMA0 and

DMA1)

XOR/DMA

Accelerator

Unit

DDR 1 and 2

SDRAM Cntl

(DMA2)

64+8

8 lanes 4 lanes 4 lanes

16

The PPC440SPe is a System on a Chip (SOC) designed around the IBM CoreConnect Bus™ Architecture.

Implemented with the Crossbar option, the CoreConnect buses provide:

• Two Master PLB bus 128-bit Data 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the

Read and Write data path (10.6 GB/s total)

• 32-bit OPB interfaces up to 83.33MHz for a maximum throughput of 333MB/s

AMCC Proprietary

5

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Address Maps

Preliminary Data Sheet

The PPC440SPe incorporates two address maps. The first is a fixed processor system memory address map. This

address map defines the possible contents of various processor accessible address regions. The second address

map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the

PPC440SPe processor through the use of mtdcr and mfdcr instructions.

Table 1. System Memory Address Map (Sheet 1 of 2)

Function

Sub Function

DDR SDRAM

Start Address

End Address

Size

16GB

256KB

0000 0000 0000 0000

0000 0004 0000 0000

0000 0004 0004 0000

0000 0004 0010 0000

0000 0004 0010 0100

0000 0004 0010 0200

0000 0003 FFFF FFFF

0000 0004 0003 FFFF

0000 0004 000F FFFF

0000 0004 0010 00FF

0000 0004 0010 01FF

0000 0004 0010 02FF

Local Memory (LL)¹

SRAM

Reserved

I2O Registers

DMA 0 Registers

DMA 1 Registers

256B

3.25K

B

I20/DMA Buffers

0000 0004 0010 0300

0000 0004 0010 0FFF

Internal PLB Interfaces (LL)

Reserved

0000 0004 0010 1000

0000 0004 0020 0000

0000 0004 0020 0400

0000 0004 0030 0000

0000 0004 0030 0100

0000 0004 E000 0000

0000 0004 F000 0000

0000 0004 F000 0200

0000 0004 F000 0208

0000 0004 F000 0300

0000 0004 F000 0308

0000 0004 F000 0400

0000 0004 F000 0420

0000 0004 F000 0500

0000 0004 F000 0520

0000 0004 F000 0600

0000 0004 F000 0608

0000 0004 F000 0700

0000 0004 F000 0780

0000 0004 F000 0800

0000 0004 F000 0900

0000 0004 001F FFFF

0000 0004 0020 03FF

0000 0004 002F FFFF

0000 0004 0030 00FF

0000 0004 DFFF FFFF

0000 0004 EFFF FFFF

0000 0004 F000 01FF

0000 0004 F000 0207

0000 0004 F000 02FF

0000 0004 F000 0307

0000 0004 F000 03FF

0000 0004 F000 041F

0000 0004 F000 04FF

0000 0004 F000 051F

0000 0004 F000 05FF

0000 0004 F000 0607

0000 0004 F000 06FF

0000 0004 F000 077F

0000 0004 F000 07FF

0000 0004 F000 08FF

0000 0004 F000 09FF

XOR/DMA2

Reserved

1KB

256B

256MB

8B

PCI Express Interrupt Handler

Reserved

Internal OPB Peripherals (LL)

EBC Memory⁶

Reserved

UART0

Reserved

UART1

8B

Reserved

IIC0

32B

Reserved

IIC1

32B

Reserved

UART2

8B

Reserved

248B

128B

GPIO Controller Registers

Reserved

Ethernet Controller Registers

Reserved

256B

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AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 1. System Memory Address Map (Sheet 2 of 2)

Function

Sub Function

General Purpose Timers

Reserved

Start Address

End Address

Size

0000 0004 F000 0A00

0000 0004 F000 0B40

0000 0004 FF00 0000

0000 0005 0000 0000

0000 0008 0000 0000

0000 000C 0000 0000

0000 000C 0800 0000

0000 000C 0801 0000

0000 0004 F000 0B3F

0000 0004 FEFF FFFF

0000 0004 FFFF FFFF

0000 0007 FFFF FFFF

0000 000B FFFF FFFF

0000 000C 07FF FFFF

0000 000C 0800 FFFF

0000 000C 0EBF FFFF

320B

Boot ROM^{2, 3}

EBC Bank0

16MB

16GB

64KB

Reserved

Local Memory Alias (HB)

Aliased DDR SDRAM

Reserved

PCIX0 I/O

Reserved

PCIX0 Addressing configuration

Regs

0000 000C 0EC0 0000

0000 000C 0EC0 0007

8B

Reserved

0000 000C 0EC0 0008

0000 000C 0EC8 0000

0000 000C 0EC8 1000

0000 000C 0EC8 1100

0000 000C 0EC8 1200

0000 000C 0ED0 0000

0000 000C 0EE0 0000

0000 000C 1000 0000

0000 000C FF00 0000

0000 000D 0000 0000

0000 0010 0000 0000

0000 000C 0EC7 FFFF

0000 000C 0EC8 0FFF

0000 000C 0EC8 10FF

0000 000C 0EC8 11FF

0000 000C 0ECF FFFF

0000 000C 0EDF FFFF

0000 000C 0FFF FFFF

0000 000C FEFF FFFF

0000 000C FFFF FFFF

0000 000F FFFF FFFF

0FFF FFFF FFFF FFFF

PCIX0 Core Configuration Regs

Reserved

4KB

256B

1MB

PCI Space (HB)

PCIX0 Simple Message Passing

Reserved

PCIX0 Special Cycle

Reserved

PCI Memory (PCI-Express & PCI-X)

PCI-X DDR boot ROM (PCI memory

PCI Memory (PCI-Express & PCI-X)

3.8GB

16MB

12GB

Reserved⁴

Reserved⁵

1000 0000 0000 0000

2000 0000 0000 0000

1FFF FFFF FFFF FFFF

FFFF FFFF FFFF FFFF

PCI Core Space (HB)

PCI Memory (PCI-Express & PCI-X)

Notes:

1. DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.

2. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating

volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.

3. When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at C FF00 0000 (16 MB).

4. Never decoded.

5. Unpredictable results on Read and Write operations.

6. Accessed by means of EBC Peripheral Bank Configuration Registers.

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Preliminary Data Sheet

Table 2. DCR Address Map (4KB of Device Configuration Registers)

Function

Total DCR Address Space¹

Start Address

End Address

Size

1KW (4KB)¹

000

3FF

By function:

Reserved

000

00C

00E

010

012

014

020

030

040

060

080

090

0A0

0B2

0C0

0D0

0E0

0F0

100

120

140

160

168

180

200

00B

00D

00F

011

013

01F

02F

03F

05F

07F

08F

09F

0AF

0BF

0CF

0DF

0EF

0FF

11F

13F

15F

167

17F

1FF

3FF

12W

2W

Clocking Power On Reset

System DCRs

Memory Controller

External Bus Controller

Reserved

2W

12W

16W

32W

16W

14W

16W

32W

8W

SRAM

L2 Controller

Memory Queue

I2O, DMA0 & DMA1

PLB

PLB to OPB Bridge Out

Reserved

Interrupt Controller 0

Interrupt Controller 1

Interrupt Controller 2

Interrupt Controller 3

PCI-Express 0

PCI-Express 1

PCI-Express 2

Power Management

Reserved

24W

128W

512W

Ethernet MAL

Reserved

Notes:

1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a sin-

gle 32-bit (word) register. One KW (1024W) equals 4KB (4096 bytes).

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PowerPC 440SPe Embedded Processor

PowerPC 440 Processor Core

Preliminary Data Sheet

The PowerPC 440 processor core is designed for high-end applications such as RAID controllers, SAN, ISCSI,

routers, switches, printers, set-top boxes, and so on. It is the first processor core to implement the Book E

PowerPC embedded architecture and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.

Features include:

• Up to 800 MHz operation

• PowerPC Book E architecture

• 32KB I-cache, 32KB D-cache

– parity on data and tag address - Checking of parity with error injection

• Three logical regions in D-cache: Locked, Transient, and Normal

• D-cache full-line flush capability

• 41-bit virtual address, 36-bit (64GB) physical address

• Superscalar, out-of-order execution

• Seven-stage pipeline

• Three execution pipelines

• Dynamic branch prediction

• Memory management unit

– 64-entry, full associative, unified TLB with parity

– Separate instruction and data micro-TLBs

– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian

• Debug facilities

– Multiple instruction and data range breakpoints

– Data value compare

– Single step, branch, and trap events

– Non-invasive real-time trace interface

• 24 DSP instructions

– Single cycle multiply and multiply-accumulate

– 32 x 32 integer multiply

Internal Buses

The PowerPC 440SPe features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip

Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores

such as the PowerPC 440 processor core, the DDR SDRAM memory controller, the PCI Express and the DDR

PCI-X bridges connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a

lower bandwidth path for passing status and control information between the processor core and the other on-chip

cores.

The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments

identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU

and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB

segment allows PLB masters DMA, XOR, PCI and PCI Express to exchange large blocks of data with SDRAM,

PCI and PCI Express without interfering with the low latency PLB masters.

Bus features include:

• PLB

– 128-bit implementation of the PLB architecture

– Separate and simultaneous read and write data paths

– 64-bit address

– Simultaneous control, address, and data phases

– Four levels of pipelining

– Byte enable capability supporting unaligned transfers

– 32- and 64-byte burst transfers

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

– 166MHz, maximum 5.2GB/s (simultaneous read and write)

– Processor vs Bus clock ratios of N:1 and N:2

• OPB

– Dynamic bus sizing: 32, 16, and 8-bit data path

– 32-bit address

– 83.33MHz, maximum 333MB/s

• DCR

– Register control bus

– 32-bit data path

– 10-bit address

On-Chip SRAM/L2 Cache

Features include:

• Four banks of 64KB each for a total of 256KB

• Configurable as either L2 cache or SRAM

• Memory cycles supported:

– Single beat read and write, 1 to 16 bytes

– Quadword Read and Write burst for 12-bit master

– Guarded memory accesses on 4KB boundaries

• Sustainable 2.6GB/s peak bandwidth at 166MHz

• Use as an L2 cache improves processor performance and reduces the PLB load

– Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) PLB or by

software

– Data Array and Tag Array parity

– Unified data and instruction cache

– Four-way set associative

– 36-bit addressing

– Full LRU replacement algorithm

– Write through, look aside

• Use as Ethernet packet store allows Ethernet packets to be held for processing by the Ethernet core

PCI Express

Features include:

• Three independent PCI Express interfaces

– One 8 lanes

– Two 4 lanes

– 2.5 GB/sec full duplex per lane

• Compliant with PCI Express base specification 1.0a

• Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)

– Applications compliant with MSI rules are limited to one End Point port per PPC440SPe

• PCI-Express to PCI-Express opaque (Non-Transparent) bridge

• Power Management

• Supports one virtual channel (VC0) no Traffic Class (TC) filtering

• Maximum Payload block size 512 Bytes

• Supports up to 1024 byte maximum Read request size

• Requests supported:

– up to 4 posted outbound Write requests (memory and messages)

– up to 4 posted inbound Write requests

– up to 4 outbound Read requests outstanding on PCI Express

– up to 4 inbound Read requests outstanding on PCI Express

– Outbound I/O request as a PCI Express Root Port

– Inbound I/O request as a PCI Express End Point

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

• Buffering in each PCI Express Port for the following transaction types:

– 4K byte Replay buffer: up to 8 in flight transactions

– 2K bytes for Outbound posted Writes

– 8K bytes for Outbound Reads completion

• 2K prefetch request from first I2O/DMA PLB Master

• 1K prefetch request from 2nd I2O/DMA PLB Master

• 1K prefetch request from first PCIE 4x links

• 1K prefetch request from 2nd PCIE 4x links

• 256 byte from the PPC440

– 2K bytes for Inbound posted Writes

– 2K bytes for Inbound Reads completion

• Parity checking on each buffer

• POM Programmable Outbound Memory Regions: 3 Memory, 1 I/O, 1 Message, 1 config, 1 Internal Regs

• PIM Programmable Inbound Memory Regions: 4 Memory, 1 I/O, 1 Expansion ROM

• INTx Interrupts support (PCI legacy):

– up to 4 INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC

– A/B/C/D INTx types Generation for Endpoints

• MSI - Message Signaled Interrupts

– MSI Generation for End Point

– MSI Termination for Root Ports

– MSI_X Termination for Root Ports

DDR PCI-X Interface

The DDR PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local

memory. The PCI-X interface supports 64-bit PCI-X bus in DDR mode 2. It can be configured for either host or

adapter mode. PCI 32/64-bit legacy mode, compatible with PCI Version 2.3, is also supported.

Features include:

• PCI-X 2.0

– Split transactions

– Frequency to 266MHz

– 32- and 64-bit address/data bus

– ECC supported for 266MHz Mode 2 only

• PCI 2.3 backward compatibility

– Frequency to 66MHz

– 32- and 64-bit bus

• Can be the PCI Host Bus Bridge or an Adapter Device PCI interface

• Optional PCI arbitration function with PCI and PCI-X mode 1, supporting up to four external devices, that can

be disabled for use with an external arbiter

• Support for PLB-based (external to PLB–PCI-X bridge) I2O

• Support for Message Signaled Interrupts (MSI) on both in- and out-bound interrupts

• Simple message passing capability

• Asynchronous to the PLB

• PCI Power Management Version 1.1

• PCI arbitration function with PCI-X Mode 2 support (optional)

• PCI register set addressable both from on-chip processor and PCI device sides

• Ability to boot from PCI-X bus memory

• Error tracking/status

• Supports initiation of transfer to the following address spaces:

– Single beat I/O reads and writes

– Single beat and burst memory reads and writes

– Single beat configuration reads and writes (Type 0 and Type 1)

– Single beat special cycles

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

• PCI-X initialization sequence support (frequency & mode determination)

• Support for unexpected split completions

• Outbound transaction split discard timers

• Vital Product Data (VPD) support

• PCI-X to PCI-Express opaque bridge

DDR1/DDR2 SDRAM Memory Controller

The DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete

devices. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The

DDR2 SDRAM controller interfaces to the PLB through a Memory Queue (MQ) function that includes six high-

speed 1KB FIFO buffers.

Features include:

• Registered and non-registered industry standard DIMMs

• DDR2 400/667 support

• 64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)

• 5.32GB/s peak bandwidth for the 64-bit interface

• 2.66GB/s peak bandwidth for the 32-bit interface

• Four chip (bank) select signals supporting 4 external banks

• CAS latencies of 2, 3, 4, 5, 6, and 7 supported

• Page mode accesses (up to 32 open pages) with configurable paging policy

• Look-ahead request queue with programmable depth of four commands.

• Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current

bank)

• Up to 16GB in four external banks

• Up to 6 MemClkout signals for high loading unbuffered DIMMS.

• Programmable address mapping and timing

• Hardware and software initiated self-refresh

• Sync DRAM configuration by means of mode register and extended mode register set commands

• Power management (self-refresh, suspend, sleep)

• Low Latency & High Bandwidth PLB ports

• Selectable PLB read response (immediate or deferred)

• Programmable Low Latency & High Bandwidth arbitration schemes

• High Bandwidth port has four 1KB read buffers and two 1KB write buffers

• Low Latency port has four 128B read buffers and two 128B write buffers

External Peripheral Bus Controller (EBC)

Features include:

• Support Boot ROM on Bank 0; programmable size 2, 4, 8,16 MB

• Up to three ROM, EPROM, SRAM, Flash memory, and slave peripherals supported

• Burst and non-burst devices

• 16 or 8-bit data bus

• 27-bit address, 128MB address space for Banks 1 & 2

• Peripheral Device pacing with external “Ready”

• Latch data on Ready, synchronous or asynchronous

• Programmable access timing per device

– 256 Wait States for non-burst

– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses

– Programmable CSon, CSoff relative to address

– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS

• Programmable address mapping

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PowerPC 440SPe Embedded Processor

Ethernet Controller Interface

Preliminary Data Sheet

The Ethernet support interfaces to the physical layer, but the PHY is not included on the chip.

Features include:

• One 10/100/1000 interface running in full- and half-duplex modes

– One full Media Independent Interface (MII) with 4-bit parallel data transfer

– One Gigabit Media Independent Interface (GMII)

I2O/DMA Controller

The I20/DMA controller provides support for I20 messaging and two DMA controllers (DMA0 and DMA1). I2O

manages Message Frame Address (MFA) FIFOs or queues in memory in response to I2O register reads and

writes and transfers message frames. The DMAs provide normal memory access support to ease the CPU burden.

I2O features include:

• I2O pull- and push-messaging methods

• Dynamic message frame size

• Programmable FIFO size (4096 64-bit MFAs maximum)

• 64-bit and 32-bit MFA sizes

• Three interrupt gathering methods

• Registered MFA prefetch and posting

• 32-bit inbound and outbound doorbell registers

• Four 32-bit scratch pad registers

DMA features include:

• Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)

• 512-byte buffering

• Simultaneous fill and drain (PLB read/write pipelining)

• Any source PLB address to any destination address

• No memory alignment restrictions on source or destination

• 32-byte command descriptor block

• Maximum transfer size of 16MB

• 64-bit addressing

• 1KB buffering (DMA1 only)

• Prefetch indicators for PCI-X buffer management (DMA1 only)

Optional RAID 5 and RAID 6 Acceleration Hardware

The 440SPe provides integrated acceleration hardware that implements high throughput RAID 5 and RAID 6

algorithms to compute the single parity P for RAID 5, and dual parity P & Q for RAID 6. RAID 5 is used to recover

data in the case of a single disk drive failure, and RAID 6 provides for data recovery if two disk drives fail.

The 440SPe offers a choice of two XOR engines for computing the P parity. The first choice is available with the

XOR/DMA2 acceleration unit and is used for RAID 5. The second choice for XOR parity computation, along with

8

the RAID 6 Galois Field GF(2 )-based polynomial computations, resides inside the Memory Queue functional block

of the Memory Controller unit. The Galois Field polynomial used with the 440SPe is programmable and can be one

of sixteen available irreducible polynomials, including 14d and 11d.

The RAID 5 and RAID 6 parity computations performed in the Memory Queue are assisted by the two-channel

DMA engine of the I2O/DMA controller unit, designated as DMA0 and DMA1. The RAID acceleration hardware

also provides various alternatives for balancing load and performance, depending on customer-specific application

firmware. The two-way crossbar bus architecture can perform data read and write operations simultaneously,

resulting in extremely high throughput.

RAID 6 capability is available only with the RAID-enabled part numbers (PPC440SPe-RpBfffC) as indicated in the

ordering information section of this data sheet.

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

For more information about the RAID 6 implementation, description, and configuration of the acceleration

hardware, refer to the following AMCC documents:

• PowerPC 440SP/440SPe RAID Support Application Note

• PowerPC 440SPe RAID Addendum to the User’s Manual

XOR/DMA2 Controller

The XOR/DMA2 controller performs the XOR functions needed to support RAID 5 applications including parity

generation and check functions used across data stripes in a RAID 5 system.

• Computes a bit-wise XOR on up to 16 data streams with result stored in designated target

• Performs XOR check on up to 16 data streams

• Driven by a linked list Command Block structure specifying control information, source operands, target

operand, status information, and link

• Source and target streams may reside anywhere in PLB address space.

• Provides completion status per Command Block to be handled by software at a later time

• 96-byte and 160-byte Command Block formats are supported

• No memory alignment restrictions on operands or target

• Internal register arrays and data buffers are parity protected

• Can be used as a DMA controller (DMA2) with single source and target addresses

• PLB Master interface

• PLB Slave port used as control interface for reading and writing control and status information

Serial Port

‚

The serial port is compatible with the NS 16570 UART interface.

Features include:

• One 8-pin, one 4-pin, and one 2-pin interfaces are provided

• Selectable internal or external serial clock to allow wide range of baud rates

• Register compatibility with 16750 register set

• Complete status reporting capability

• Fully programmable serial-interface characteristics

IIC Bus Interface

Features include:

• Two IIC interfaces provided

‚

2

• Support for Philips Semiconductors I C Specification, dated 1995

• Operation at 100kHz or 400kHz

• 8-bit data

• 10- or 7-bit address

• Slave transmitter and receiver

• Master transmitter and receiver

• Multiple bus masters

• Supports fixed V IIC interface

DD

• Two independent 4 x 1 byte data buffers

• Twelve memory-mapped, fully programmable configuration registers

• One programmable interrupt request signal

• Full management of all IIC bus protocols

• Programmable error recovery

• Port 0 supports serial Bootstrap ROM with default override parameters at initialization

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PowerPC 440SPe Embedded Processor

General Purpose Timers (GPT)

Preliminary Data Sheet

Provides a time base counter and system timers additional to those defined in the processor core.

• 32-bit time base counter driven by the OPB bus clock

• Seven 32-bit compare timers

General Purpose IO (GPIO) Controller

• Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB

bus master accesses.

• The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO

capabilities acts as a GPIO or is used for another purpose.

• Each GPIO output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain).

Universal Interrupt Controller (UIC)

Four cascaded Universal Interrupt Controllers (UIC) process internal on-chip and external processor interrupts.

Note: Processor specific interrupts (for example, page faults) do not use UIC resources.

Features include:

• 16 external interrupts

• 101 internal interrupts

• Edge-triggered or level-sensitive

• Positive- or negative-active

• Non-critical or critical interrupt to the on-chip processor core

• Programmable interrupt priority ordering

• Programmable critical interrupt vector for faster vector processing

JTAG

Features include:

• IEEE 1149.1 Test Access Port

• IBM RISCWatch Debugger support

• JTAG Boundary Scan Description Language (BSDL)

AMCC Proprietary

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Figure 3. 27mm, 675-Ball FC-PBGA Core Package

Top View

A1 Corner

1

24

A

®

PPC440SPe

Part Number

xpBfffC

AAAAAAAA

Lot Number

AD

Note: All dimensions are in mm.

Bottom View

27.0 ± 0.2

Lid

AF

AD

AB

Y

AE

AC

AA

W

U

1.00 TYP

V

T

R

27.0 ± 0.2

P

N

M

K

H

F

L

J

G

E

D

B

C

A

0.5 MIN

3.22 MAX

01 03 05 07 09 11 13 15 17 19 21 23 25

02 04 06 08 10 12 14 16 18 20 22 24 26

0.6 ± 0.1 SOLDERBALL x 675

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Signal Lists

This section contains two tables that list external signals.

Table 3 lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal

appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate

signal(s) in brackets.

In Table 3, multiplexed pins that have no internal signal connected after reset are marked High Z.

Multiplexed signals appear alphabetically multiple times in the list—once for each signal name on the ball. The

page number listed gives the page in “Signal Functional Description” on page 50 where the signals in the indicated

interface group begin.

Table 4 on page 42 lists all the external signals in order by ball (pin) number.

Signal List—Alphabetic Order

Table 3. Signals Listed Alphabetically (Sheet 1 of 25)

Signal Name

Ball

AE22

AD21

AE21

AD20

Y18

Interface Group

Page

BA0

BA1

BA2

BankSel0

BankSel1

BankSel2

BankSel3

CAS

Y19

DDR SDRAM

52

W17

AB22

Y21

ClkEn0

ClkEn1

ClkEn2

ClkEn3

DM0

AA22

AE25

AF25

AD25

V20

DM1

DM2

V25

DM3

T25

DM4

J26

DDR SDRAM

52

DM5

G22

DM6

F24

DM7

C23

DM8

M19

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 2 of 25)

Signal Name

Ball

AA23

AA24

U21

T19

W23

W24

P24

P25

M22

L22

Interface Group

Page

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

ECC0

ECC1

ECC2

ECC3

ECC4

ECC5

ECC6

ECC7

G25

H25

E22

F22

B25

C25

P21

R21

R19

R20

M20

P18

P19

N19

N21

N18

DDR SDRAM

52

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 3 of 25)

Signal Name

Ball

H05

D03

J08

Interface Group

Page

EMCCD

EMCCrS

EMCGTxClk

EMCMDClk

EMCMDIO

EMCRefClk

EMCRxClk

EMCRxD0

EMCRxD1

EMCRxD2

EMCRxD3

EMCRxD4

EMCRxD5

EMCRxD6

EMCRxD7

EMCRxDV

EMCRxErr

EMCTxClk

EMCTxD0

EMCTxD1

EMCTxD2

EMCTxD3

EMCTxD4

EMCTxD5

EMCTxD6

EMCTxD7

EMCTxEn

EMCTxErr

ExtReset

F03

B02

H07

B01

L06

J02

G03

H02

H03

L04

M07

F05

J06

Ethernet

53

F04

C02

C03

G06

J07

A05

E03

C05

E01

B10

C01

D02

B11

A04

A10

A17

A23

D01

System

Power

55

56

GND

AMCC Proprietary

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 4 of 25)

Signal Name

Ball

D07

D13

D14

D20

D26

G04

G10

G17

G23

J09

J12

J15

J18

K01

K07

K10

K12

K15

K17

K20

K26

L11

L13

L14

L16

Interface Group

Page

GND

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 5 of 25)

Signal Name

Ball

M09

M10

M12

M15

M17

M18

N04

N11

N13

N14

N16

N23

P04

P11

P13

P14

P16

P23

R09

R10

R12

R15

R17

R18

T11

T13

T14

T16

U01

U07

Interface Group

Page

GND

Power

56

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 6 of 25)

Signal Name

Ball

U12

U15

U17

U20

U26

V09

Interface Group

Page

GND

V12

GND

V15

GND

V18

GND

Y04

GND

Y10

GND

Y17

Power

56

GND

Y23

GND

AC01

AC07

AC13

AC14

AC20

AC26

AF04

AF10

AF17

AF23

L01

GND

[GPIO00] [TRCCLK] High Z

[GPIO01] [TRCBS0] High Z

[GPIO02] [TRCBS1] High Z

[GPIO03] [TRCBS2] High Z

[GPIO04] [TRCES0] High Z

[GPIO05] [TRCES1] High Z

[GPIO06] [TRCES2] High Z

[GPIO07] [TRCES3] High Z

[GPIO08] [TECES4] High Z

[GPIO09] [TRCTS0] High Z

[GPIO10] [TRCTS1] High Z

H01

F01

L02

GPIO Peripherals

K03

G02

M05

F02

55

Note: Trace can be enabled at reset by setting

SDR0_SDSTP1[DBG] (bit 27) to 1 in the serial

bootstrap ROM.

J03

H04

J05

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Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 7 of 25)

Signal Name

[GPIO11] [TRCTS2] High Z

[GPIO12] [TRCTS3] High Z

[GPIO13] [TRCTS4] High Z

[GPIO14] [TRCTS5] High Z

[GPIO15] [TRCTS6] High Z

[GPIO16] IRQ0

Ball

G05

L05

J04

Interface Group

Page

K06

H06

L08

M06

M08

E02

E04

H09

L07

F06

H08

A02

E26

E24

C22

L24

K25

K22

N22

AD17

H17

J16

[GPIO17] IRQ1

[GPIO18] IRQ2

[GPIO19] IRQ3

[GPIO20] IRQ4

[GPIO21] IRQ5

GPIO Peripherals

55

[GPIO22] IRQ6

[GPIO23] IRQ7

[GPIO24] IRQ8

[GPIO25] IRQ9

[GPIO26] IRQ10

[GPIO27] IRQ11

[GPIO28] IRQ12

[GPIO29] IRQ13

[GPIO30] IRQ14

[GPIO31] IRQ15

Halt

System

55

54

HISRRst

IIC0SClk

IIC0SDA

IIC Peripheral

IIC1SClk

H18

H15

IIC1SDA

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Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 8 of 25)

Signal Name

IRQ0 [GPIO16]

IRQ1 [GPIO17]

IRQ2 [GPIO18]

IRQ3 [GPIO19]

IRQ4 [GPIO20]

IRQ5 [GPIO21]

IRQ6 [GPIO22]

IRQ7 [GPIO23]

IRQ8 [GPIO24]

IRQ9 [GPIO25]

IRQ10 [GPIO26]

IRQ11 [GPIO27]

IRQ12 [GPIO28]

IRQ13 [GPIO29]

IRQ14 [GPIO30]

IRQ15 [GPIO31]

MemAddr00

Ball

L08

Interface Group

Page

M06

M08

E02

E04

H09

L07

F06

Interrupts

55

H08

A02

E26

E24

C22

L24

K25

K22

AF22

AF19

AD22

T24

MemAddr01

MemAddr02

MemAddr03

MemAddr04

AF18

AB24

AF21

AE18

R25

MemAddr05

MemAddr06

MemAddr07

DDR SDRAM

52

MemAddr08

MemAddr09

AE20

AD19

AB26

R23

MemAddr10

MemAddr11

MemAddr12

MemAddr13

AB17

AE19

MemAddr14

24

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 9 of 25)

Signal Name

MemClkOut0

MemClkOut1

MemClkOut2

MemClkOut3

MemClkOut4

MemClkOut5

MemData00

MemData01

MemData02

MemData03

MemData04

MemData05

MemData06

MemData07

MemData08

MemData09

MemData10

MemData11

MemData12

MemData13

MemData14

MemData15

MemData16

MemData17

MemData18

MemData19

Ball

AA21

AA20

AB21

AC21

AB19

AC19

AA19

AB20

AA18

AB18

AC18

AD18

AC25

AA26

AC24

AA25

AD24

AD23

AB25

AB23

U19

Interface Group

Page

DDR SDRAM

52

T21

V19

T20

V21

V22

T18

W22

U24

W25

V23

V24

AMCC Proprietary

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Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 10 of 25)

Signal Name

Ball

Interface Group

Page

MemData20

MemData21

MemData22

MemData23

MemData24

MemData25

MemData26

MemData27

MemData28

MemData29

MemData30

MemData31

MemData32

MemData33

MemData34

MemData35

MemData36

MemData37

MemData38

MemData39

MemData40

MemData41

MemData42

MemData43

MemData44

MemData45

MemData46

MemData47

MemData48

Y24

V26

Y25

W26

T22

R24

T23

R22

T26

N25

R26

N24

M26

K24

L26

L23

L25

J25

DDR SDRAM

52

M21

M24

J23

H26

H23

G24

H24

H22

J24

J22

F26

26

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Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 11 of 25)

Signal Name

Ball

Interface Group

Page

MemData49

MemData50

MemData51

MemData52

MemData53

MemData54

MemData55

MemData56

MemData57

MemData58

MemData59

MemData60

MemData61

MemData62

MemData63

MemDCFdbkD

MemDCFdbkR

MemODT0

MemODT1

MemODT2

MemODT3

MemVRef0

MemVRef1

No ball

F23

F25

E23

E25

D25

D22

D24

C24

C26

B24

A24

B26

B23

A25

B22

AE24

AF24

W21

Y22

W20

W19

W18

V16

A01

DDR SDRAM

52

AMCC Proprietary

27

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 12 of 25)

Signal Name

Ball

Interface Group

Page

OV

A07

A13

A14

A20

A26

G01

G07

G13

G14

G20

G26

K11

K13

K14

K16

L10

L17

M13

M14

N01

N07

N10

N12

N15

N17

N20

N26

DD

Power

56

28

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 13 of 25)

Signal Name

Ball

Interface Group

Page

PCIE_PLLGNDA

PCIE_PLLGNDB

PCIE_PLLVDD2

PCIE_PLLVDDA

PCIE_PLLVDDB

PCIE_REFCLK

PCIE0_RX0

PCIE0_RX1

PCIE0_RX2

PCIE0_RX3

PCIE0_RX4

PCIE0_RX5

PCIE0_RX6

PCIE0_RX7

PCIE0_TX0

PCIE0_TX1

PCIE0_TX2

PCIE0_TX3

P02

N02

P09

Power

56

P03

N03

P05

P06

V11

W11

AB11

AC11

W12

Y12

AD12

AD13

AF15

AF16

AE16

AD15

V14

PCI-Express 0:2

50

W14

W15

W16

Y11

AA11

AF11

AE11

AB12

AA12

AE13

AF12

AMCC Proprietary

29

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 14 of 25)

Signal Name

Ball

Interface Group

Page

PCIE0_TX4

PCIE0_TX5

PCIE0_TX6

PCIE0_TX7

PCIE0AV25

PCIE0AVREG

PCIE1_RX0

PCIE1_RX1

PCIE1_RX2

PCIE1_RX3

PCIE1_TX0

PCIE1_TX1

PCIE1_TX2

PCIE1_TX3

PCIE1AV25

PCIE1AVREG

AE14

AD14

AB16

AC16

Y15

AA15

Y16

AA16

V13

W13

E20

E21

B21

C20

C19

D19

A19

B19

C21

D21

A21

B20

C18

D18

A18

B18

E19

E18

PCI-Express 0:2

50

30

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Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 15 of 25)

Signal Name

Ball

Interface Group

Page

PCIE2_RX0

PCIE2_RX1

PCIE2_RX2

PCIE2_RX3

PCIE2_TX0

PCIE2_TX1

PCIE2_TX2

PCIE2_TX3

PCIE2AV25

PCIE2AVREG

PCIECalRN

PCIECalRP

PCIEPLLTSTON

J21

K21

J19

K19

F20

F21

F18

F19

L21

L20

J20

H20

G21

H21

G19

H19

L18

L19

T08

R08

J01

PCI-Express 0:2

50

AMCC Proprietary

31

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 16 of 25)

Signal Name

Ball

Interface Group

Page

PCIX0Ack64

PCIX0AD0

AD02

AB04

AA05

AB02

AA03

W05

V06

PCIX0AD1

PCIX0AD10

PCIX0AD11

PCIX0AD12

PCIX0AD13

PCIX0AD14

PCIX0AD15

PCIX0AD16

PCIX0AD17

PCIX0AD18

PCIX0AD19

PCIX0AD2

AA02

AA01

W03

W04

V05

V04

Y06

PCI-X0

50

PCIX0AD20

PCIX0AD21

PCIX0AD22

PCIX0AD23

PCIX0AD24

PCIX0AD25

PCIX0AD26

PCIX0AD27

PCIX0AD28

PCIX0AD29

PCIX0AD3

V03

V02

V01

U06

T07

T06

T05

T04

T02

T01

V08

PCIX0AD30

PCIX0AD31

PCIX0AD32

R07

R06

AD10

32

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 17 of 25)

Signal Name

Ball

Interface Group

Page

PCIX0AD33

PCIX0AD34

PCIX0AD35

PCIX0AD36

PCIX0AD37

PCIX0AD38

PCIX0AD39

PCIX0AD4

AA10

W10

AF09

AF08

AD09

AF06

AD08

W07

PCIX0AD40

PCIX0AD41

PCIX0AD42

PCIX0AD43

PCIX0AD44

PCIX0AD45

PCIX0AD46

PCIX0AD47

PCIX0AD48

PCIX0AD49

PCIX0AD5

AC09

AE06

AD07

AC08

AB09

AE05

AD06

AB08

AA09

Y09

PCI-X0

50

AC02

AF03

AE04

AA08

W08

PCIX0AD50

PCIX0AD51

PCIX0AD52

PCIX0AD53

PCIX0AD54

PCIX0AD55

PCIX0AD56

PCIX0AD57

PCIX0AD58

PCIX0AD59

PCIX0AD6

AB07

AF02

AE03

AD04

AC05

AE07

AA04

W09

PCIX0AD60

AMCC Proprietary

33

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 18 of 25)

Signal Name

Ball

Interface Group

Page

PCIX0AD61

PCIX0AD62

PCIX0AD63

PCIX0AD7

PCIX0AD8

PCIX0AD9

PCIX0BE0

PCIX0BE1

PCIX0BE2

PCIX0BE3

PCIX0BE4

PCIX0BE5

PCIX0BE6

PCIX0BE7

PCIX0CalG0

PCIX0CalR0

PCIX0Cap

PCIX0Clk

U08

AA07

AE02

Y05

W06

V07

Y03

Y02

W02

U03

AB05

AA06

AC06

AB06

AE09

AE08

M03

N05

PCI-X0

50

PCIX0DevSel

PCIX0ECC2

PCIX0ECC3

PCIX0ECC4

PCIX0ECC5

PCIX0Frame

PCIX0Gnt0

PCIX0Gnt1

PCIX0Gnt2

PCIX0Gnt3

PCIX0IDSel

N08

R05

R03

R01

P08

N06

T03

E10

M04

R04

U05

34

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 19 of 25)

Signal Name

Ball

Interface Group

Page

PCIX0INTA

PCIX0IRDY

PCIX0M66En

PCIX0Par

U02

AB01

A09

W01

AD03

N09

AE01

AD01

R02

K02

PCIX0Par64

PCIX0PErr

PCIX0PLLG

PCIX0PLLV

PCIX0Req0

PCIX0Req1

PCIX0Req2

PCIX0Req3

PCIX0Req64

PCIX0Reset

PCIX0Serr

PCIX0Stop

PCIX0TRDY

PCIX0VC

PCI-X0

50

K05

M02

AC03

L03

AF05

AD05

AB03

M01

Y08

PCIX0VRef0

PCIX0VRef1

PerAddr0

T09

E13

PerAddr1

E14

PerAddr10

PerAddr11

PerAddr12

PerAddr13

PerAddr14

PerAddr15

B16

E15

External Slave Peripheral (EBC)

54

F11

D11

C10

B09

AMCC Proprietary

35

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 20 of 25)

Signal Name

Ball

Interface Group

Page

PerAddr16

PerAddr17

PerAddr18

PerAddr19

PerAddr2

PerAddr20

PerAddr21

PerAddr22

PerAddr23

PerAddr24

PerAddr25

PerAddr26

PerAddr3

PerAddr4

PerAddr5

PerAddr6

PerAddr7

PerAddr8

PerAddr9

PerBE0

C09

A08

B07

E11

B15

E09

C08

A06

D08

A22

E17

B17

D15

H16

H14

J14

External Slave Peripheral (EBC)

54

J13

A15

F14

C07

B04

D16

C17

C15

C11

G12

G08

H10

B05

H11

C06

PerBE1

PerBLast

PerClk

PerCS0

PerCS1

PerCS2

PerData00

PerData01

PerData02

PerData03

PerData04

36

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 21 of 25)

Signal Name

Ball

Interface Group

Page

PerData05

PerData06

PerData07

PerData08

PerData09

PerData10

PerData11

PerData12

PerData13

PerData14

PerData15

PerErr

J11

E08

F07

F09

E06

D05

C04

F08

B03

E07

D06

G15

E05

B06

A03

F15

E16

A16

U10

P01

P07

P10

P12

R13

T10

U11

U13

Y01

Y07

Y13

External Slave Peripheral (EBC)

54

PerOE

PerPar0

PerPar1

PerR/W

PerReady

PerWE

PSRO1

Miscellaneous

57

PxVDD

Power

56

PxVDD

AMCC Proprietary

37

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 22 of 25)

Signal Name

Ball

Interface Group

Page

56

PxVDD

AF01

AF07

AF13

AE23

U25

PxVDD

Power

PxVDD

RAS

DDR SDRAM

52

SCANOUT00

SCANOUT07

SCANOUT08

SCANOUT14

SCANOUT15

SCANOUT16

SCANOUT17

SCANOUT18

SCANOUT19

SCANOUT20

SCANOUT21

SCANOUT25

SVDD

U22

P22

AB10

AE10

AD11

AC12

AE12

AB13

AB14

AE15

M23

P15

Tests

56

SVDD

P17

SVDD

P20

SVDD

P26

SVDD

R14

SVDD

T17

SVDD

U14

Power

56

SVDD

U16

SVDD

Y14

SVDD

Y20

SVDD

Y26

SVDD

AF14

AF20

AF26

SVDD

38

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 23 of 25)

Signal Name

Ball

Interface Group

Page

SYS2PLLG

SYS2PLLV

SYSClk

AD26

AE26

C16

M25

A11

SYSErr

Power

56

SysPartSel

SYSPLLG

SYSPLLV

SysReset

TCK

B14

B13

L09

System

JTAG

55

56

AA17

AB15

AD16

E12

AA13

AA14

K08

AC15

L01

TDI

TDO

TESTEN

THERMALDA

THERMALDB

TMR_CLK

TMS

Miscellaneous

57

System

JTAG

55

56

[TRCCLK] [GPIO00] High Z

[TRCBS0] [GPIO01] High Z

[TRCBS1] [GPIO02] High Z

[TRCBS2] [GPIO03] High Z

[TRCES0] [GPIO04] High Z

[TRCES1] [GPIO05] High Z

[TRCES2] [GPIO06] High Z

[TRCES3] [GPIO07] High Z

[TRCES4] [GPIO08] High Z

[TRCTS0] [GPIO09] High Z

[TRCTS1] [GPIO10] High Z

[TRCTS2] [GPIO11] High Z

[TRCTS3] [GPIO12] High Z

[TRCTS4] [GPIO13] High Z

[TRCTS5] [GPIO14] High Z

[TRCTS6] [GPIO15] High Z

TRST

H01

F01

L02

K03

G02

M05

F02

Trace

56

Note: Trace can be enabled at reset by setting

SDR0_SDSTP1[DBG] (bit 27) to 1 in the serial

bootstrap ROM.

J03

H04

J05

G05

L05

J04

K06

H06

AE17

JTAG

56

AMCC Proprietary

39

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 24 of 25)

Signal Name

Ball

Interface Group

Page

UARTSerClk

UART0_CTS

UART0_DCD

UART0_DSR

UART0_DTR

UART0_RI

H12

B08

H13

C12

C13

C14

G09

D12

D09

F10

G11

A12

B12

F13

F12

UART0_RTS

UART0_Rx

UART Peripheral

55

UART0_Tx

UART1_DSR/CTS

UART1_DTR/RTS

UART1_Rx

UART1_Tx

UART2_Rx

UART2_Tx

40

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 25 of 25)

Signal Name

Ball

Interface Group

Page

VDD

WE

D04

D10

D17

D23

J10

J17

K04

K09

K18

K23

L12

L15

M11

M16

R11

R16

T12

Power

56

T15

U04

U09

U18

U23

V10

V17

AC04

AC10

AC17

AC23

AC22

DDR SDRAM

52

AMCC Proprietary

41

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Signal List—Ball Assignment Order

In the following table, only the primary (default) signal name is shown for each pin.

Multiplexed pins are marked with an asterisk (*). To determine the other signals that share a pin, look up the

primary signal name in Table 3 on page 17.

Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)

Ball

A01

A02

A03

A04

A05

A06

Signal name

Ball

B01

B02

B03

B04

B05

B06

Signal name

Ball

C01

C02

C03

C04

C05

C06

Signal name

EMCTxEn

Ball

D01

D02

D03

D04

D05

D06

Signal name

GND

No ball

EMCRxClk

EMCMDIO

PerData13

PerBE1

EMCTxClk

EMCTxD0

PerData11

EMCTxD5

PerData04

EMCTxErr

EMCCrS

VDD

IRQ9*

PerPar1

GND

EMCTxD3

PerAddr22

PerData02

PerPar0

PerData10

PerData15

OV

DD

A07

B07

PerAddr18

C07

PerBE0

D07

GND

A08

A09

A10

A11

A12

PerAddr17

PCIX0M66En

GND

B08

B09

B10

B11

B12

UART0_CTS

PerAddr15

EMCTxD7

ExtReset

C08

C09

C10

C11

C12

PerAddr21

PerAddr16

PerAddr14

PerCS1

D08

D09

D10

D11

D12

PerAddr23

UART0_Tx

VDD

SysPartSel

UART1_Rx

PerAddr13

UART0_Rx

UART1_Tx

UART0_DSR

OV

DD

A13

A14

B13

B14

SYSPLLV

SYSPLLG

C13

C14

UART0_DTR

UART0_RI

D13

D14

GND

OV

DD

A15

A16

A17

A18

A19

PerAddr8

PerWE

B15

B16

B17

B18

B19

PerAddr2

C15

C16

C17

C18

C19

PerCS0

D15

D16

D17

D18

D19

PerAddr3

PerBLast

VDD

PerAddr10

PerAddr26

PCIE1_TX3

PCIE1_RX3

SYSCLK

PerClk

GND

PCIE1_TX3

PCIE1_RX3

PCIE1_TX2

PCIE1_RX2

PCIE1_TX2

PCIE1_RX2

OV

DD

A20

B20

PCIE1_TX1

C20

PCIE1_RX1

D20

GND

A21

A22

A23

A24

A25

PCIE1_TX1

PerAddr24

GND

B21

B22

B23

B24

B25

PCIE1_RX1

MemData63

MemData61

MemData58

DQS7

C21

C22

C23

C24

C25

PCIE1_TX0

GPIO28_IRQ12

DM7

D21

D22

D23

D24

D25

PCIE1_TX0

MemData54

VDD

MemData59

MemData62

MemData56

DQS7

MemData55

MemData53

OV

DD

A26

B26

MemData60

C26

MemData57

D26

GND

42

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)

Ball

Signal name

Ball

Signal name

Ball

Signal name

Ball

Signal name

TRCBS0*

OV

E01

EMCTxD6

F01

G01

H01

TRCBS1*

DD

E02

E03

E04

E05

E06

GPIO19_IRQ3

EMCTxD4

IRQ4*

F02

F03

F04

F05

F06

G02

G03

G04

G05

G06

H02

H03

H04

H05

H06

EMCRxD3

EMCRxD4

TRCTS0*

EMCCD

TRCES3*

EMCMDClk

EMCRxErr

TRCES1*

EMCRxD2

GND

PerOE

EMCRxD7

IRQ7*

TRCTS2*

EMCTxD1

PerData09

TRCTS6*

EMCRefClk

IRQ8*

OV

DD

E07

E08

PerData14

PerData06

F07

F08

PerData07

PerData12

G07

G08

H07

H08

PerData00

E09

E10

E11

E12

PerAddr20

PCIX0Gnt1

PerAddr19

TESTEN

F09

F10

F11

F12

PerData08

G09

G10

G11

G12

UART0_RTS

GND

H09

H10

H11

H12

IRQ5*

UART1_DSR/CTS

PerAddr12

PerData01

PerData03

UARTSerClk

UART1_DTR/RTS

PerCS2

UART2_Tx

OV

DD

E13

E14

PerAddr0

PerAddr1

F13

F14

UART2_Rx

PerAddr9

G13

G14

H13

H14

UART0_DCD

PerAddr5

OV

DD

E15

E16

E17

E18

E19

PerAddr11

PerReady

F15

F16

F17

F18

F19

PerR/W

G15

G16

G17

G18

G19

PerErr

H15

H16

H17

H18

H19

IIC1SDA

PerAddr4

IIC0SClk

IIC1SClk

PCIE2_TX3

Reserved

PCIE2_RX3

Reserved

GND

PerAddr25

PCIE1AVREG

PCIE1AV25

Reserved

PCIE2_TX3

OV

DD

E20

PCIE1_RX0

F20

PCIE2_RX2

G20

H20

PCIE2_TX1

E21

E22

E23

E24

E25

PCIE1_RX0

DQS6

F21

F22

F23

F24

F25

PCIE2_RX2

DQS6

G21

G22

G23

G24

G25

PCIE2_TX2

DM5

H21

H22

H23

H24

H25

PCIE2_TX2

MemData45

MemData42

MemData44

DQS5

MemData51

MemData49

DM6

GND

MemData43

DQS5

IRQ11*

MemData52

IRQ10*

MemData50

OV

DD

E26

F26

MemData48

G26

H26

MemData41

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7)

Ball

J01

J02

J03

J04

J05

J06

J07

J08

J09

J10

Signal name

PCIEPLLTSTON

EMCRxD1

Ball

K01

K02

K03

K04

K05

K06

K07

K08

K09

K10

Signal name

Ball

L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

Signal name

TRCCLK*

Ball

Signal name

GND

M01 PCIX0VC

M02 PCIX0Req3

M03 PCIX0Cap

M04 PCIX0Gnt2

PCIX0Req1

TRCES0*

VDD

TRCBS2*

PCIX0Reset

EMCRxD5

TRCTS3*

EMCRxD0

IRQ6*

TRCES4*

TRCTS4*

TRCTS1*

EMCRxDV

EMCTxD2

EMCGTxClk

GND

PCIX0Req2

M05

M06

TRCES2*

IRQ1*

TRCTS5*

GND

M07 EMCRxD6

M08

TMR_CLK

VDD

IRQ0*

IRQ2*

SysReset

M09 GND

M10 GND

OV

DD

VDD

GND

OV

DD

J11

J12

J13

PerData05

GND

K11

K12

K13

L11

L12

L13

GND

VDD

GND

M11 VDD

M12 GND

GND

OV

DD

OV

PerAddr7

M13

M14

DD

OV

DD

J14

J15

J16

PerAddr6

GND

K14

K15

K16

L14

L15

L16

GND

VDD

GND

M15 GND

M16 VDD

OV

DD

IIC0SDA

OV

DD

J17

VDD

K17

GND

L17

M17 GND

J18

J19

J20

J21

J22

J23

J24

GND

K18

K19

K20

K21

K22

K23

K24

VDD

L18

L19

L20

L21

L22

L23

L24

PCIE2AV25

PCIE2AVREG

PCIE2_TX0

DQS4

M18 GND

PCIE2_RX1

PCIE2_TX1

PCIE2_RX0

MemData47

MemData40

MemData46

PCIE2_RX1

GND

M19 DM8

M20 ECC2

PCIE2_RX0

M21 MemData38

M22 DQS4

IRQ15*

VDD

MemData35

M23 SCANOUT25

M24 MemData39

MemData33

IRQ13*

J25

J26

MemData37

DM4

K25

K26

L25

L26

MemData36

MemData34

M25 SYSERR

IRQ14*

GND

M26 MemData32

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7)

Ball

Signal name

Ball

Signal name

Ball

Signal name

PCIX0ECC4

Ball

Signal name

PCIX0AD29

OV

PxV

DD

N01

P01

R01

T01

DD

N02

N03

N04

N05

N06

PCIE_PLLGNDB

PCIE_PLLVDDB

GND

P02

P03

P04

P05

P06

PCIE_PLLGNDA

PCIE_PLLVDDA

GND

R02

R03

R04

R05

R06

PCIX0Req0

PCIX0ECC3

PCIX0Gnt3

PCIX0ECC2

PCIX0AD31

T02

T03

T04

T05

T06

PCIX0AD28

PCIX0Gnt0

PCIX0AD27

PCIX0AD26

PCIX0AD25

PCIX0Clk

PCIE_REFCLK

PCIX0Frame

OV

DD

PxV

DD

N07

P07

R07

PCIX0AD30

T07

PCIX0AD24

N08

N09

PCIX0DevSel

PCIX0PErr

P08

P09

PCIX0ECC5

R08

R09

PCIECalRP

GND

T08

T09

PCIECalRN

PCIX0VRef1

PCIE_PLLVDD2

OV

DD

PxV

DD

PxV

DD

N10

N11

N12

P10

P11

P12

R10

R11

R12

GND

VDD

GND

T10

T11

T12

GND

VDD

OV

DD

PxV

DD

PxV

DD

N13

N14

GND

P13

P14

GND

R13

R14

T13

T14

GND

SV

DD

OV

DD

SV

DD

N15

N16

N17

P15

P16

P17

R15

R16

R17

GND

VDD

GND

T15

T16

T17

VDD

GND

OV

DD

SV

DD

SV

DD

N18

N19

ECC7

ECC5

P18

P19

ECC3

ECC4

R18

R19

GND

T18

T19

MemData14

DQS1

ECC0

OV

DD

SV

DD

N20

P20

R20

ECC1

T20

MemData11

N21

N22

N23

N24

N25

ECC6

P21

P22

P23

P24

P25

DQS8

R21

R22

R23

R24

R25

DQS8

T21

T22

T23

T24

T25

MemData09

MemData24

MemData26

MemAddr03

DM3

Halt

SCANOUT08

GND

MemData27

MemAddr12

MemData25

MemAddr08

GND

MemData31

MemData29

DQS3

OV

DD

SV

DD

N26

P26

R26

MemData30

T26

MemData28

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7)

Ball

Signal name

Ball

Signal name

Ball

Signal name

Ball

Signal name

PxV

U01

GND

V01

PCIX0AD22

W01 PCIX0Par

Y01

DD

U02

U03

U04

U05

U06

PCIX0INTA

PCIX0BE3

VDD

V02

V03

V04

V05

V06

PCIX0AD21

PCIX0AD20

PCIX0AD19

PCIX0AD18

PCIX0AD13

W02 PCIX0BE2

W03 PCIX0AD16

W04 PCIX0AD17

W05 PCIX0AD12

W06 PCIX0AD8

Y02

Y03

Y04

Y05

Y06

PCIX0BE1

PCIX0BE0

GND

PCIX0IDSel

PCIX0AD23

PCIX0AD7

PCIX0AD2

PxV

DD

U07

GND

V07

PCIX0AD9

W07 PCIX0AD4

Y07

U08

U09

U10

PCIX0AD61

VDD

V08

V09

V10

PCIX0AD3

GND

W08 PCIX0AD53

W09 PCIX0AD60

W10 PCIX0AD34

Y08

Y09

Y10

PCIX0VRef0

PCIX0AD49

GND

PSRO1

VDD

PxV

DD

U11

U12

U13

V11

V12

V13

PCIE0_RX0

GND

W11 PCIE0_RX0

W12 PCIE0_RX2

W13 PCIE0AVREG

Y11

Y12

Y13

PCIE0_TX0

PCIE0_RX2

GND

PxV

DD

PxV

DD

PCIE0AV25

SV

DD

SV

DD

U14

U15

U16

V14

V15

V16

PCIE0_RX6

GND

W14 PCIE0_RX6

W15 PCIE0_RX7

W16 PCIE0_RX7

Y14

Y15

Y16

GND

PCIE0_TX6

PCIE0_TX7

SV

DD

MemVRef1

U17

U18

U19

GND

V17

V18

V19

VDD

W17 BankSel3

W18 MemVRef0

W19 MemODT3

Y17

Y18

Y19

GND

VDD

GND

BankSel1

BankSel2

MemData08

MemData10

SV

DD

U20

GND

V20

DM1

W20 MemODT2

Y20

U21

U22

U23

U24

U25

DQS1

V21

V22

V23

V24

V25

MemData12

MemData13

MemData18

MemData19

DM2

W21 MemODT0

W22 MemData15

W23 DQS2

Y21

Y22

Y23

Y24

Y25

ClkEn0

SCANOUT07

VDD

MemODT1

GND

MemData16

SCANOUT00

W24 DQS2

MemData20

MemData22

W25 MemData17

SV

DD

U26

GND

V26

MemData21

W26 MemData23

Y26

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7)

Ball

Signal name

Ball

Signal name

Ball

Signal name

Ball

Signal name

AA01 PCIX0AD15

AA02 PCIX0AD14

AA03 PCIX0AD11

AA04 PCIX0AD6

AA05 PCIX0AD1

AA06 PCIX0BE5

AA07 PCIX0AD62

AA08 PCIX0AD52

AA09 PCIX0AD48

AA10 PCIX0AD33

AA11 PCIE0_TX0

AA12 PCIE0_TX2

AA13 THERMALDA

AA14 THERMALDB

AA15 PCIE0_TX6

AA16 PCIE0_TX7

AA17 TCK

AB01 PCIX0IRDY

AB02 PCIX0AD10

AB03 PCIX0TRDY

AB04 PCIX0AD0

AB05 PCIX0BE4

AB06 PCIX0BE7

AB07 PCIX0AD54

AB08 PCIX0AD47

AB09 PCIX0AD44

AB10 SCANOUT14

AB11 PCIE0_RX1

AB12 PCIE0_TX2

AB13 SCANOUT19

AB14 SCANOUT20

AB15 TDI

AC01 GND

AD01 PCIX0PLLV

AD02 PCIX0Ack64

AD03 PCIX0Par64

AD04 PCIX0AD57

AD05 PCIX0Stop

AD06 PCIX0AD46

AD07 PCIX0AD42

AD08 PCIX0AD39

AD09 PCIX0AD37

AD10 PCIX0AD32

AD11 SCANOUT16

AD12 PCIE0_RX3

AD13 PCIE0_RX3

AD14 PCIE0_TX4

AD15 PCIE0_RX5

AD16 TDO

AC02 PCIX0AD5

AC03 PCIX0Req64

AC04 VDD

AC05 PCIX0AD58

AC06 PCIX0BE6

AC07 GND

AC08 PCIX0AD43

AC09 PCIX0AD40

AC10 VDD

AC11 PCIE0_RX1

AC12 SCANOUT17

AC13 GND

AC14 GND

AC15 TMS

AB16 PCIE0_TX5

AB17 MemAddr13

AB18 MemClkOut4

AB19 MemClkOut2

AB20 MemClkOut3

AB21 MemClkOut1

AB22 CAS

AC16 PCIE0_TX5

AC17 VDD

AD17 HISRRst

AA18 MemClkOut4

AA19 MemClkOut3

AA20 MemClkOut0

AA21 MemClkOut0

AA22 ClkEn1

AC18 MemClkOut5

AC19 MemClkOut2

AC20 GND

AD18 MemClkOut5

AD19 MemAddr10

AD20 BankSel0

AD21 BA1

AC21 MemClkOut1

AC22 WE

AD22 MemAddr02

AD23 MemData05

AD24 MemData04

AD25 DM0

AA23 DQS0

AB23 MemData07

AB24 MemAddr05

AB25 MemData06

AB26 MemAddr11

AC23 VDD

AA24 DQS0

AC24 MemData02

AC25 MemData00

AC26 GND

AA25 MemData03

AA26 MemData01

AD26 SYS2PLLG

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7)

Ball

Signal name

Ball

Signal name

Ball

Signal name

Ball

Signal name

PxV

AE01 PCIX0PLLG

AF01

DD

AE02 PCIX0AD63

AE03 PCIX0AD56

AE04 PCIX0AD51

AE05 PCIX0AD45

AE06 PCIX0AD41

AF02 PCIX0AD55

AF03 PCIX0AD50

AF04 GND

AF05 PCIX0Serr

AF06 PCIX0AD38

PxV

AE07 PCIX0AD59

AF07

DD

AE08 PCIX0CalR0

AE09 PCIX0CalG0

AE10 SCANOUT15

AE11 PCIE0_TX1

AE12 SCANOUT18

AF08 PCIX0AD36

AF09 PCIX0AD35

AF10 GND

AF11 PCIE0_TX1

AF12 PCIE0_TX3

PxV

SV

AE13 PCIE0_TX3

AE14 PCIE0_TX4

AF13

AF14

DD

AE15 SCANOUT21

AE16 PCIE0_RX5

AE17 TRST

AF15 PCIE0_RX4

AF16 PCIE0_RX4

AF17 GND

AE18 MemAddr07

AE19 MemAddr14

AF18 MemAddr04

AF19 MemAddr01

SV

DD

AE20 MemAddr09

AF20

AE21 BA2

AF21 MemAddr06

AF22 MemAddr00

AF23 GND

AE22 BA0

AE23 RAS

AE24 MemDCFdbkD

AE25 ClkEn2

AF24 MemDCFdbkR

AF25 ClkEn3

SV

DD

AE26 SYS2PLLV

AF26

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PowerPC 440SPe Embedded Processor

Signal Description

Preliminary Data Sheet

The PPC440SPe embedded controller is packaged in a 27mm Flip-Chip Plastic Ball Grid Array (FC-PBGA). The

following tables describe the package level pinout.

Table 5. Pin Summary

Group

No. of Pins

Total Signal Pins

AxV_DD(1.5V)

495

3

AxV_DD(2.5V HSS)

6

AxGND

5

OV_DD(3.3V I/Os)

23

14

28

83

PxV_DD(3.3/1.5V PCI)

SV_DD(2.5/1.8V SDRAM)

V

_DD(1.5V logic)

GND

Total Power Pins

Reserved

4

Total Pins

675

In the table “Signal Functional Description” on page 50, each I/O signal is listed along with a short description of its

function. Active-low signals (for example, RAS) are marked with an overline. See “Signals Listed Alphabetically” on

page 17 for the pin (ball) number to which each signal is assigned.

Multiplexed Signals

Some signals are multiplexed on the same pin so that the pin can be used for different functions. The signal names

shown in Table 6 on page 50 are not accompanied by signal names that might be multiplexed on the same pin. It is

expected that in any single application a particular pin will always be programmed to serve the same function. The

flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.

Strapping Pins

One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only

during reset and are used for other functions during normal operation (see “Strapping” on page 77). Note that

these are not multiplexed pins since the function of the pins is not programmable.

Multipurpose Signals

In addition to multiplexing, some pins are also multi-purpose. For example, the PCIX0Ack can function instead as

PCIX0ECC1 depending on the PCI interface mode of operation.

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Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 6. Signal Functional Description (Sheet 1 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PCI-Express 0:2 Interfaces

PCI Express Reference Clock: 100 MHz differential

clock pair. Input type is controlled by bit 3 of the

PESDR0_PLLLCT1[MCENT] register.

PCIE_REFCLK

I

Diff PECL

0

1

2.5V CMOS or LVDS

2.5V LVPECL (recommended)

PCIE0Tx[7:0]

PCIE1:2Tx[3:0]

PCI Express Serial Data Transmit differential signals

LSB is 0.

O

Diff PECL

X8 Mode: All PCIE0Tx[7:0]/PCIE0Tx[7:0] are used.

X4 Mode: Only PCIE0Tx[3:0]/PCIE0Tx[3:0] are used.

PCIE0Rx[7:0]

PCIE1:2Rx[3:0]

PCI Express Serial Data Receive differential signals

LSB is 0.

I

X8 Mode: All PCIE0Rx[7:0]/PCIE0Rx[7:0] are used.

X4 Mode: Only PCIE0Rx[3:0]/PCIE0Rx[3:0] are used

PCI Express Analog Observation point for internal

voltage regulator

PCIE0:2AVREG

O

PCIECalRP

PCIECalRN

Positive and negative inputs for a 1 Kohm ±1% PCI

Express External calibration resistor

I

PCIEPLLTSTON

Enable PCI Express PLL test modes.

PCI-X0 Interfaces

Ack64 or ECC1.

Normally used as Ack64 indicating that the target can

transfer data using 64 bits.

3.3V PCI or

PCIX0Ack64/PCIX0ECC1

I/O

4

1.5V PCI for

mode 2

or

Used as ECC1 for PCIX mode 2.

3.3V PCI or

PCIX0AD63:00

PCIX0BE7:0

Address/Data bus (bidirectional) for PCI-X0

PCI-X Byte Enables for PCI-X0

I/O

I

1.5V PCI for

mode 2

3.3V PCI or

1.5V PCI for

mode 2

Balls G and R for a 114 Ohm External calibration

resistor. Used to control PCI-X I/O Impedance at 57

Ohm.

PCIX0CalG0

PCIX0CalR0

NA

Capable of PCI-X operation.

This analog input is sampled to configure PCI and

determine the state of the PCIX0VC output signal:

0.00V

(0.0V) = Conventional PCI & PCIX0VC = 0

DD

PCIX0Cap

I

0.49V

(1.0V) = PCI-X DDR 266 Mode 2 &

PCIX0VC = 1

DD

0.75V

1.00V

(2.5V) = PCI-X 66 & PCIX0VC = 0

DD

(3.3V) = PCI-X 133 & PCIX0VC = 0

50

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Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 6. Signal Functional Description (Sheet 2 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

Input PCI & PCI-X Clock.

I/O

Type

Notes

Note:If the PCI-X interface is not being used, drive this

pin with a 3.3V clock signal at a frequency

between 1 and 66MHz

PCIX0Clk

I

3.3V PCI

Indicates the driving device has decoded its address as

the target of the current access.

PCIX0DevSel

PCIX0ECC5:2

PCIX0Frame

I/O

3.3V PCI

4

ECC check bits 5–2. All ECC bits are valid only for PCIX

DDR mode 2.

3.3V PCI or

Note:See PCIXPar for ECC0.

See PCIXAck64 for ECC1.

See PCIXReq64 for ECC6.

See PCIXPar64 for ECC7.

1.5V PCI for

mode 2

Driven by the current master to indicate beginning and

duration of an access.

3.3V PCI

4

Indicates that the specified agent is granted access to

the PCI-X bus. When Arbitration is internal to the

PPC440SPe, all GRANTS Gnt0:3 are outputs. When

arbitration is external, only Gnt 0 is used as an Input.

PCIX0Gnt0

I/O

O

PCIX0Gnt1:3

Used as a chip select during configuration read and

write transactions. If the PCI-X is a Host, during

Configuration the ISDSEL is an Output that duplicates

the AD17. The ISDSEL is always 3.3V even in Mode 2

DDR

PCIX0IDSel

I/O

3.3V PCI

5

4

PCIX0INTA

PCIX0IRDY

Level sensitive PCI interrupt.

O

3.3V PCI

Indicates initiating agent’s ability to complete the current

data phase of the transaction.

I/O

3.3V PCI or

PCIX0M66En

Capable of 66MHz operation.

I

1.5V PCI for

mode 2

Even parity indicator or ECC0.

3.3V PCI or

Normally used to indicate even parity across

PCIAD31:00 and BE3:0.

PCIX0Par/PCIX0ECC0

I/O

1.5V PCI for

mode 2

Used as ECC0 for PCIX0 mode 2.

Even parity indicator or ECC7.

Normally used to indicate even parity across

PCIXAD63:32 and BE7:4 for PCIX0

3.3V PCI or

PCIX0Par64/PCIX0ECC7

PCIX0PErr

I/O

1.5V PCI for

mode 2

or

Used as ECC7 for PCIX0 mode 2.

Reports data parity errors during all PCI transactions

except a Special Cycle.

3.3V PCI

4

An indication to the PCI-X arbiter that the specified

agent wishes to use the bus.

PCIX0Req0

I/O

I

When Arbitration is internal to the PPC440SPe, all

REQS Req0:3 are Inputs. When arbitration is external,

only Req 0 is used as an output.

PCIX0Req1:3

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Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 6. Signal Functional Description (Sheet 3 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

Request 64-bit transfer or ECC6.

3.3V PCI or

Normally used by the current bus master to indicate a

64-bit transfer.

PCIX0Req64/PCIX0ECC6

I/O

4

1.5V PCI for

mode 2

Used as ECC6 for PCIX0 mode 2.

PCIX0Reset

PCIX0SErr

Sets PCI device registers and logic to a consistent state.

O

3.3V PCI

Reports address parity errors, data parity errors on the

Special Cycle command, or other catastrophic system

errors.

I/O

4

Indicates the current target is requesting the master to

stop the current transaction.

PCIX0Stop

I/O

3.3V PCI

4

Indicates the target agent’s ability to complete the

current data phase of the transaction.

PCIX0TRDY

Voltage control output. Used to control the voltage

regulator supplying the PCI I/O voltage. See PCIX0Cap

signal.

PCIX0VC

O

I

3.3(1.5)V PCI

VPCIXDDR

0 = 3.3V (PCI I/O)

1 =1.5V (PCI-X DDR)

Voltage reference input for PCI-X mode 2/DDR (1.5V)

I/O. Not used for PCI or PCI-X mode 1.

PCIX0VRef0:1

DDR SDRAM Interface

BA0:2

5

2.5(1.8)V

DDR SDRAM

Bank Address supporting up to 8 internal banks.

Selects up to four external DDR SDRAM banks.

Column Address Strobe.

O

2.5(1.8)V

DDR SDRAM

BankSel0:3

CAS

2.5(1.8)V

DDR SDRAM

2.5(1.8)V

DDR SDRAM

ClkEn0:3

DM0:8

Clock Enable. One for each external bank.

Memory write data byte lane masks. MEMDM8 is the

byte lane mask for the ECC byte lane.

2.5(1.8)V

DDR SDRAM

2.5(1.8)V

DDR SDRAM

DIFF

DQS0:8

Byte lane data strobe. DQS8 is the data strobe for the

ECC byte lane. These signals are differential pairs.

I/O

2.5(1.8)V

DDR SDRAM

ECC0:7

ECC check bits 0:7.

I/O

O

Memory address bus.

2.5(1.8)V

DDR SDRAM

MemAddr14:00

Note:MemAddr14 is the most significant bit (msb).

Subsystem clocks. The Clock signal (differential pair) is

duplicated six times to support high loading:

2.5(1.8)V

DDR SDRAM

DIFF

MemClkOut0:5

Six clocks can be used for two unbuffered DIMMS.

O

Each individual clock signal can be enabled by

programming the SDR0_DDRCLKSET register.

Memory data bus.

2.5(1.8)V

DDR SDRAM

MemData63:00

52

I/O

Note:MemData63 is the most significant bit (msb).

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 6. Signal Functional Description (Sheet 4 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

MemDCFdbkD

Description

I/O

Type

Notes

2.5(1.8)V

DDR SDRAM

Feedback driver, for I/O timing measurements.

O

Feedback receiver. Connect externally to

MemDCFdbkD.

2.5(1.8)V

DDR SDRAM

MemDCFdbkR

MemODT0:3

I

2.5(1.8)V

DDR SDRAM

Memory on-die termination control

O

2.5(1.8)V

DDR SDRAM

Volt Ref Rcv

Memory reference voltage (SV

) input.

MemVRef0

MemVRef1

I

REF

2.5(1.8)V

DDR SDRAM

Volt Ref Sup

Memory reference voltage (SV

) supplemental input.

REF

2.5(1.8)V

DDR SDRAM

RAS

WE

Row Address Strobe.

Write Enable.

O

2.5(1.8)V

DDR SDRAM

Ethernet Interface

EMCCD

Collision detection.

Carrier sense.

I

3.3V LVTTL

EMCCrS

EMCMDClk

Management data clock.

O

Transfer command and status information between MII

and PHY.

EMCMDIO

I/O

3.3V LVTTL

EMCRxD0:7

EMCRxDV

EMCRxErr

EMCRxClk

EMCRefClk

EMCTxClk

EMCGTxClk

EMCTxD0:7

EMCTxEn

Receive data.

I

3.3V LVTTL

Receive data valid.

Receive error.

I

Receive clock.

I

Reference clock.Typical use: GMII Gigabit interface

Transmit clock for 10/100 Mb/s.

Ethernet gigabit transmit clock. 125MHz to PHY

Transmit data.

I

O

Transmit data enabled.

Transmit error.

EMCTxErr

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 6. Signal Functional Description (Sheet 5 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

External Slave Peripheral Interface - EBC

Peripheral address bus.

PerAddr00:26

O

3.3V LVTTL

1

Note:PerAddr00 is the most significant bit (msb).

PerBE0:1

PerBLast

PerCS0:2

External peripheral data bus byte enable.

O

3.3V LVTTL

Used by the peripheral controller to indicates the last

transfer of a memory access.

External peripheral device select.

Peripheral data bus.

PerData00:15

PerOE

I/O

O

3.3V LVTTL

1

Note:PerData0 is the most significant bit (msb).

Used by peripheral controller or DMA controller

depending upon the type of transfer involved. When the

PPC440SPe is the bus master, it enables the selected

device to drive the bus.

PerPar0:1

PerReady

External peripheral data bus byte parity.

I/O

I

3.3V LVTTL

1

Used by a peripheral slave to indicate it is ready to

transfer data.

The peripheral controller set this signal to High for a

Read from external memory, and to Low for a Write.

PerR/W

O

3.3V LVTTL

PerWE

PerClk

Write Enable.

O

3.3V LVTTL

Peripheral clock used by synchronous peripheral slaves.

External error used as an input to record external slave

peripheral errors.

PerErr

I

3.3V LVTTL

1, 5

IIC Peripheral Interface

IIC0SClk

IIC0 Serial Clock.

IIC0 Serial Data.

IIC1 Serial Clock.

IIC1 Serial Data.

I/O

3.3V IIC

1, 2

IIC0SDA

IIC1SClk

IIC1SDA

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Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 6. Signal Functional Description (Sheet 6 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

UART Peripheral Interface

Serial clock input that provides an alternative to the

internally generated serial clock. Used in cases where

the allowable internally generated clock rates are not

satisfactory.

UARTSerClk

I

3.3V LVTTL

1, 4

UART0_Rx

UART0 Receive data.

I

O

I

3.3V LVTTL

1, 4

UART0_Tx

UART0 Transmit data.

4

UART0_DCD

UART0_DSR

UART0_CTS

UART0_DTR

UART0_RTS

UART0 Data Carrier Detect.

UART0 Data Set Ready.

UART0 Clear To Send.

UART0 Data Terminal Ready.

UART0 Request To Send.

6

I

6

I

1, 4, 6

O

4

3.3V LVTTL

w/pull-up

UART0_RI

UART0 Ring Indicator.

I

1, 4

UART1_Rx

UART1_Tx

UART1 Receive data.

UART1 Transmit data.

I

3.3V LVTTL

1, 4

O

UART1 Data Set Ready or Clear To Send. The choice is

determined by a DCR register bit setting.

UART1_DSR/CTS

UART1_DTR/RTS

I

3.3V LVTTL

1, 4

UART1 Request To Send or Data Terminal Ready. The

choice is determined by a DCR register bit setting.

O

UART2_Rx

UART2 Receive data.

UART2 Transmit data.

I

3.3V LVTTL

1, 4

UART2_Tx

O

Interrupts Interface

External interrupt Requests 0 through 15.

These pins are multiplexed with GPIO16:31

IRQ0:15

I

3.3V LVTTL

1, 5

1, 4

System Interface

Halt

Halt from external debugger.

I

3.3V LVTTL

General purpose I/O 0 through 31.

GPIO00:31

I/O

The GPIOs are multiplexed with IRQs, and Trace signal

IO. Setting is done with the DCR register bits.

SysClk

Main system clock input.

Set to 1 when a machine check is generated.

Not used.

I

O

I

3.3V LVTTL

NA

SysErr

SysPartSel

3

Main system reset. External logic can drive this pin low

(minimum of 16 cycles) to initiate a system reset. A reset

of the PPC440SPe can also be initiated by software.

SysReset

ExtReset

I

3.3V LVTTL

1, 2

External Reset. During the PPC440SPe’s reset phase

this signal is at down level.

O

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 6. Signal Functional Description (Sheet 7 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

1, 2

3

Hardware initiated system reset with an initial SDRAM

self-refresh phase to save data in Memory.

HISRRst

I

3.3V LVTTL

TESTEN

Test Enable.

I

3.3V LVTTL

TMR_CLK

Processor timer external input clock.

JTAG Interface

TCK

Test Clock.

I

3.3V LVTTL

1

4

3.3V LVTTL

w/pull-down

TDI

Test Data In.

TDO

TMS

Test Data Out.

Test Mode Select.

O

I

3.3V LVTTL

with pull-up

1

5

Test Reset. During chip power-up, this signal must be

low from the start of VDD ramp-up until at least 16

SysClk cycles after VDD is stable in order to initialize the

JTAG controller.

3.3V LVTTL

with pull-up

TRST

I

Trace Interface

TrcClk

Trace data capture clock, runs at 1/4 the frequency of

the processor.

O

3.3V LVTTL

TRCBS0:2

TrcES0:4

Trace branch execution status.

Trace Execution Status is presented every fourth

processor clock cycle.

Additional information on trace execution and branch

status.

TrcTS0:6

O

3.3V LVTTL

Tests

Test scan out

SCANOUT[00][07:08] [14:21] [25]

n/a

Manufacturing test signals: No need for termination

Power

PCIE0:2AV25

2.5V supply voltage for the serial link of the PCI Express

I

2.5V supply voltage for the PCI Express Reference

clock Input receiver in front of the PLL

PCIE_PLLVDD2

PCIE_PLLVDDA

PCIE_PLLVDDB

Analog 2.5V filtered supply voltage A for the PLL of the

PCI Express

I

Analog 2.5V filtered supply voltage B for the PLL of the

PCI Express

PCIE_PLLGNDA

PCIE_PLLGNDB

PCIX0PLLG

GNDA for the PLL of the PCI Express

GNDB for the PLL of the PCI Express

Ground for the PCI-X0 PLL

I

n/a

Analog 1.5V Filtered Supply voltages input for PCI-X0

A separate filter for all analog voltages is recommended.

PCIX0PLLV

I

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 6. Signal Functional Description (Sheet 8 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

Ground for the SYS_PLL

I/O

Type

Notes

SYSPLLG

n/a

Analog 1.5V Filtered Supply voltages input for the

SYS_PLL

SYSPLLV

I

n/a

I

n/a

A separate filter for all analog voltages is recommended.

SYS2PLLG

SYS2PLLV

GND

Ground for the DDR_PLL (SDRAM)

Analog 1.5V Filtered Supply voltages input for the

DDR_PLL (SDRAM)

A separate filter for all analog voltages is recommended.

Logic and I/O voltage ground.

n/a

OV

DD

3.3V I/O supply (except DDR SDRAM and PCI-X).

PCI-X I/O voltage supply.

3.3 V for PCI and PCI-X

PxV

DD

n/a

1.5 V for PCI-X 266 DDR Mode 2

DDR SDRAM I/O voltage supply.

2.5V for DDR1 SDRAM

SV

DD

n/a

1.8V for DDR2 SDRAM

V

1.5V Logic voltage supply.

DD

Miscellaneous

PSRO1

Performance Screen Ring Oscillator.

n/a

5

THERMALDA

THERMALDB

On chip Diode for thermal monitoring.

I

P diffusion on Pad A (In), and N on pad B (out)

O

Do not connect voltage, ground, or any signals to these

pins.

Reserved

n/a

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Device Characteristics

Table 7. Absolute Maximum Ratings

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause

permanent damage to the device. None of the performance specification contained in this document are guaranteed when

operating at these maximum ratings.

Characteristic

Supply Voltage (Internal logic)

Supply Voltage (I/O interface, except DDR SDRAM)

Supply Voltage (PCI-X I/O)

Symbol

Value

0 to +1.6

0 to +3.6

0 to +1.6

0 to +2.7

0 to +1.95

0 to +3.6

-55 to +150

-40 to +120

Unit

V

Notes

V_DD

OV_DD

PxV_DD

AxV_DD

APxV_DD

SV_DD

V_IN

V

Supply Voltage (PCI-X DDR I/O)

Supply Voltages (System PLLs)

Supply Voltages (PCI-X PLLs)

Supply Voltage (DDR SDRAM logic)

Supply Voltage (DDR2 SDRAM logic)

Input Voltage (3.3V LVTTL receivers)

Storage temperature range

V

1

V

T_STG

°C

T_C

Case temperature under bias

Notes:

2

1. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the

PPC440SPe. A separate filter, as shown below, is recommended for each voltage:

AxV , APxV

DD

PCIE_PLLVDDA & B

PCI Express

V

DD

L

L – SMT ferrite bead chip, Murata BLM31A700S

Murata BLM15AG102SN1

C

C – 0.1μF ceramic

C – 1μF ceramic

2. This value is not a specification of the operational temperature range, it is a stress rating only.

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Preliminary Data Sheet

Table 8. Package Thermal Specifications

Thermal resistance values for the PPC440SPe package in a convection environment are as follows:

Airflow ft/min (m/sec)

Parameter

Symbol

Unit

Notes

0 (0)

100 (0.51)

200 (1.02)

θ

Junction-to-case thermal resistance

0.8

°C/W

1

2

JC

θ

Case-to-ambient thermal resistance (w/o heat sink)

15.5

13.1

11.9

CA

Range

Minimum

Maximum

θ

Junction-to-ball (typical)

6.5

°C/W

3

JB

Notes:

1. Case temperature, T , is measured at top center of case surface with device soldered to circuit board. For this part the junction

C

temperature and the case temperature are essentially identical.

2. The case-to-ambient thermal resistance is measured in a JEDEC JESD51-6 standard environment; and may not accurately

predict thermal performance in production equipment environments. The operational case temperature must be maintained.

^{3. 6.5 °C/W is the theoretical}θ using an infinite heat sink. The larger number applies to the module mounted on a 1.8mm thick,

JB

2P card using 1oz. copper power planes, with an effective heat transfer area of 75mm².

Table 9. Recommended DC Operating Conditions (Sheet 1 of 3)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Logic Supply Voltage

Symbol

Minimum

+1.425

+3.0

Typical

+1.5

Maximum

+1.575

+3.6

Unit

V

Notes

V_DD

4

OV_DD

I/O Supply Voltage

+3.3

V

PCI & PCI-X I/O Supply Voltage

PCI-X DDR mode 2

+3.0

+3.3

+1.5

+3.6

PxV_DD

V

4

3

+1.425

+1.575

Voltage Reference Input for PCI-X DDR Mode 2

PCIX0VRef0:1

SV_DD

+1.425

+1.5

+1.575

DDR1 SDRAM Supply Voltage (DDR400)

DDR2 SDRAM

+2.3

+1.7

+2.5 (2.6)

+1.8

+2.7

+1.9

AxV_DD

APExV_DD

APxV_DD

SV_REF

Analog System and DDR PLL Supply Voltages

Analog PCI Express PLL Supply voltage

Analog PCI-X PLL Supply Voltages

DDR1 SDRAM Reference Voltage

+1.4

+ 1.65

+1.5

+2.5

+1.6

+2.75

V

+1.4

+1.5

+1.6

3

+1.15

+1.25

+1.35

SV_REF

0.49 x SV_DD

0.50 x SV_DD

0.51 x SV_DD

DDR2 SDRAM Reference Voltage

AMCC Proprietary

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 9. Recommended DC Operating Conditions (Sheet 2 of 3)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

V

Notes

SV_REF+0.18

SV_DD+0.3

Input Logic High (2.5V DDR SDRAM)

Input Logic High (1.8V DDR2 SDRAM)

2

SV_REF+0.125

SV_DD+0.3

OV_DD+0.5

V

Input Logic High (2.5V CMOS, 3.3V tolerant

receiver)

1.7

V

V_IH

0.5OV_DD

Input Logic High (3.3V PCI-X)

V

1

Input Logic High (1.5V PCI-X DDR)

Input Logic High (3.3V LVTTL)

Input Logic Low (2.5V DDR SDRAM)

-

+2.0

-0.3

+3.6

SV_REF-0.18

SV_REF-0.125

Input Logic Low (1.8V DDR2 SDRAM)

-0.3

V

Input Logic Low (2.5V CMOS, 3.3V tolerant

receiver)

0.7

V_IL

0.35OV_DD

Input Logic Low (3.3V PCI-X)

-0.5

V

1

Input Logic Low (1.5V PCI-X DDR)

Input Logic Low (3.3V LVTTL)

-

0

-

+0.8

SV_DD

Output Logic High (2.5V DDR SDRAM)

+1.95

SV_DD-0.45

SV_DD

Output Logic High (1.8V DDR2 SDRAM)

V

Output Logic High (2.5V CMOS, 3.3V tolerant

receiver)

2.0

V_OH

0.9OV_DD

OV_DD

Output Logic High (3.3V PCI-X)

V

1

Output Logic High (1.5V PCI-X DDR)

Output Logic High (3.3V LVTTL)

-

+2.4

0

-

OV_DD

Output Logic Low (2.5V DDR SDRAM)

Output Logic Low (1.8V DDR2 SDRAM)

0.45

0

Output Logic Low (2.5V CMOS, 3.3V tolerant

receiver)

0.4

V

V_OL

0.1OV_DD

Output Logic Low (3.3V PCI-X)

Output Logic Low (1.5V PCI-X DDR)

Output Logic Low (3.3V LVTTL)

V

1

-

0

+0.4

Input Leakage Current (with no internal pull-up

or pull-down)

I_IL1

I_IL2

I_IL3

0

1

μA

Input Leakage Current (with internal pull-down)

Input Leakage Current (with internal pull-up)

0 (LPDL)

200 (MPUL)

0 (MPUL)

μA

5

-150 (LPDL)

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 9. Recommended DC Operating Conditions (Sheet 3 of 3)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

V

Notes

V

Input Max Allowable Overshoot (3.3V LVTTL)

Input Max Allowable Undershoot (3.3V LVTTL)

Output Max Allowable Overshoot (3.3V LVTTL)

+3.9

IMAO

V_IMAU

-0.6

V

+3.9

+95

V

OMAO

V_OMAU3

T_C

Output Max Allowable Undershoot (3.3V LVTTL)

-0.6

0

V

Case Temperature

°C

6

Notes:

1. PCI-X drivers meet PCI-X specifications.

2. SV_REF= SV_DD/2

3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the

PPC440SPe. See “Absolute Maximum Ratings” on page 58.

4. During chip power-up, OV

should begin to ramp before VDD. External voltage should not be applied to the chip I/O pins before

DD

is applied to the chip. A power-down cycle should complete (OV

OV

and VDD should both be below 0.4V) before a new power

DD

up cycle is started.

5. LPDL is least positive down level; MPUL is most positive up level.

6. Case temperature, T_C, is measured at top center of case surface with device soldered to circuit board.

Table 10. Input Capacitance

Parameter

Group 1 (2.5V SSTL I/O)

Symbol

Maximum

Unit

Notes

C

5.7

pF

IN1

C

Group 2 (3.3V LVTTL I/O)

Group 3 (PCI-X I/O)

6.8

5.1

6.7

2.6

pF

IN2

C

IN3

C

Group 4 (Receivers)

IN4

C

Group 5 (3.3V tolerant CMOS I/O)

IN5

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PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Table 11. DC Power Supply Loads

Parameter

Symbol

Minimum

Typical

Maximum

3000

30

Unit

mA

Notes

V

_DD(1.5V) active operating current

I_DD

2

OV_DD(3.3V) active operating current

PxV_DD(3.3V) active operating current

PxV_DD(1.5V) active operating current

SV_DD(2.5V) active operating current

SV_DD(1.8V) active operating current

I_ODD

I_PDD

I_SDD

I_ADD

I_APDD

-

1200

285

2

580

2

AxV

DD

(1.5V) input current

33

mA

1, 2

APxV

DD

Notes:

1. See “Absolute Maximum Ratings” on page 58 for filter recommendations.

2. Valid only for CPU/PLB/OPB = 533.33/133.33/66.66 MHz.

Clock Test Conditions

Output

Clock timing and switching characteristics are specified in accordance with operating

conditions shown in the table “Recommended DC Operating Conditions.” AC

C

10pF

specifications are characterized with V = 1.5V, T = +95°C and a 10pF test load as

DD

C

shown in the figure to the right.

Table 12. Clocking Specifications

Symbol

SysClk Input

F_C

Parameter

Min

Max

Units

Frequency

Period

33.33

83.33

30

MHz

ns

T_C

12

T

Edge stability (cycle-to-cycle jitter)

–

±0.15

ns

CS

T_CH

T_CL

High time

Low time

40% of nominal period

60% of nominal period

ns

Note:Input slew rate ≥ 1V/ns

PLL VCO

F_C

T_C

Frequency

Period

600

1333.33

1.66

MHz

ns

0.75

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Preliminary Data Sheet

Table 12. Clocking Specifications

Symbol

Parameter

Min

Max

Units

Processor Clock (CPU Clock)

F_C

T_C

Frequency

Period

400

1.5

666.66

2.5

MHz

ns

MemClkOut

F_C

Frequency

Period

200

333.33

MHz

ns

T_C

3

5

T_CH

High time

45% of nominal period

55% of nominal period

ns

OPB Clock and PerClk

F_C

T_C

Frequency

Period

–

83.33

–

MHz

ns

12

MAL Clock

F_C

Frequency

Period

45

12

83.33

22.2

MHz

ns

T_C

Figure 4. Clock Timing Waveform

T

CL

CH

T

C

Spread Spectrum Clocking

Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440SPe. This controller

uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to

as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the

SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the

PPC440SPe the following conditions must be met:

• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the

PPC440SPe with one or more internal clocks at their maximum supported frequency, the SSCG can only lower

the frequency.

• The maximum frequency deviation cannot exceed -1%, and the modulation frequency cannot exceed 40kHz.

In some cases, on-board PPC440SPe peripherals impose more stringent requirements.

• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the

modulation.

• Use the DDR SDRAM MemClkOut since it also tracks the modulation.

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Preliminary Data Sheet

• For PCI-X and PCI 66 the maximum spread spectrum is -1% modulated between 30kHz and 33kHz.

• For PCI Express, the maximum spread spectrum is -0.5%, modulated between 30kHz and 33kHz. The ports

on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at

all times. This is specified to allow bit rate clock sources with a +/- 300 ppm tolerance.

Notes:

1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of

approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that

the connected device is running at precise baud rates.

2. Ethernet operation is unaffected.

3. IIC operation is unaffected.

Important: It is up to the system designer to ensure that any SSCG used with the PPC440SPe meets the above

requirements and does not adversely affect other aspects of the system.

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Preliminary Data Sheet

I/O Specifications

Table 13. Peripheral Interface Clock Timings

Parameter

PCIX0Clk input frequency (asynchronous mode)

PCIX0Clk period (asynchronous mode)

PCIX0Clk input high time

PCIX0Clk input low time

Min

Max

Units

MHz

ns

Notes

–

133.33

2

7.5

–

40% of nominal period

60% of nominal period

ns

40% of nominal period

60% of nominal period

ns

EMCMDClk output frequency

EMCMDClk period

–

2.5

MHz

ns

400

–

EMCMDClk output high time

EMCMDClk output low time

EMCTxClk input frequency

EMCTxClk period

160

–

ns

160

–

ns

2.5

25

MHz

ns

40

400

EMCTxClk input high time

EMCTxClk input low time

EMCRxClk input frequency

EMCRxClk period

35% of nominal period

–

ns

35% of nominal period

–

ns

2.5

25

MHz

ns

40

400

EMCRxClk input high time

EMCRxClk input low time

PerClk output frequency (for sync. slaves)

PerClk period

35% of nominal period

–

ns

–

ns

83.33

–

MHz

ns

12

PerClk output high time

50% of nominal period

33% of nominal period

66% of nominal period

50% of nominal period

ns

PerClk output low time

ns

1000/(2T

¹+2ns)

UARTSerClk input frequency

UARTSerClk period

–

MHz

ns

1

OPB

2T

T

+2

–

OPB

+1

UARTSerClk input high time

UARTSerClk input low time

ns

OPB

T

+1

–

ns

OPB

TmrClk input frequency

TmrClk period

–

100

–

MHz

ns

10

TmrClk input high time

TmrClk input low time

Notes:

40% of nominal period

60% of nominal period

ns

1. T

OPB

is the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of

the PLB clock. The maximum OPB clock frequency is 83.33 MHz. Refer to the Clocking chapter of the PPC440SPe

Embedded Processor User’s Manual for details.

2. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk frequency is 66.66MHz.

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Input/Output Timing

Preliminary Data Sheet

These timing diagrams illustrate the relationship of the timing parameters defined in the I/O Specification tables

that follow.

Figure 5. Input Setup and Hold Waveform

Clock

T

min

IS

T

min

IH

Inputs

Valid

Figure 6. Output Delay and Hold Timing Waveform

Clock

max

T

OV

max

T

OV

max

T

OV

T

min

OH

T

min

OH

T

min

OH

Outputs

High (Drive)

Float (High-Z)

Valid

Low (Drive)

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Preliminary Data Sheet

Table 14. I/O Specifications—All Speeds (Sheet 1 of 2)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz

and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time

requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.

3. These are DDR signals that can change on both the positive and negative clock transitions.

Input (ns)

Output (ns)

Hold Time

(T max) (T min)

OV

Output Current (mA)

I/O H I/O L

(minimum) (minimum)

Signal

Clock

Notes

Setup Time Hold Time Valid Delay

(T min)

IS

IH

OH

PCI-X Interface

PCIX0Ack64

PCIX0AD63:00

PCIX0BE7:0

PCIX0CalG0:1

PCIX0CalR0:1

PCIX0Cap

Note 2 (2)

dc

0.5(0)

dc

3.5(6)

n/a

0.7 (Note 2)

n/a

0.5

n/a

0.5

n/a

0.5

n/a

0.5

1.5

n/a

1.5

n/a

1.5

n/a

1.5

PCIX0Clk

2

n/a

async

2

Note 2 (2)

n/a

0.5(0)

n/a

3.5(6)

n/a

0.7 (Note 2)

n/a

PCIX0Clk

2

PCIX0DevSel

PCIX0ECC5:2

PCIX0Frame

PCIX0Gnt0

PCIX0Gnt1

PCIX0Gnt2:3

PCIX0IDSel

PCIX0INTA

PCIX0IRDY

PCIX0M66En

PCIXPar

2

n/a

2

n/a

2

Note 2 (2)

n/a

0.5(0)

n/a

2

3.5(6)

n/a

0.7 (Note 2)

n/a

2

PCIXPar64

PCIX0PErr

2

n/a

2

PCIX0Req0

PCIX0Req1:3

PCIX0Req64

PCIX0Reset

PCIX0SErr

n/a

2

n/a

2

Note 2 (2)

0.5(0)

3.5(6)

0.7 (Note 2)

2

PCIX0Stop

PCIX0TRDY

PCIX0VC

2

Ethernet Interface

EMCCD

-

na

-

na

-

19.1

8.7

1, async

EMCCrS

EMCMDClk

EMCMDIO

na

-

na

-

EMCMDClk

EMCRxClk

EMCRxD0:7

EMCRxDV

4

1

na

15

na

2

4

1

EMCRxErr

-

EMCRxClk

-

1, async

EMCRefClk

EMCTxClk

-

na

1, async

EMCGTxClk

EMCTxD0:7

EMCTxClk

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Preliminary Data Sheet

Table 14. I/O Specifications—All Speeds (Sheet 2 of 2)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz

and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time

requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.

3. These are DDR signals that can change on both the positive and negative clock transitions.

Input (ns)

Output (ns)

Hold Time

(T min)

Output Current (mA)

I/O H I/O L

(minimum) (minimum)

Signal

Clock

Notes

Setup Time Hold Time Valid Delay

(T min)

(T

max)

15

IS

IH

OV

OH

EMCTxEn

EMCTxErr

na

2

19.1

8.7

EMCTxClk

15

2

Internal Peripheral Interface

IIC0SClk

n/a

-

n/a

-

n/a

-

n/a

-

15.3

19.1

-

10.2

8.7

-

IIC0SDA

IIC0SClk

IIC1SClk

n/a

-

n/a

-

n/a

-

n/a

-

IIC1SDA

UARTSerClk

UART0_Rx

UART0_Tx

UART0_DCD

UART0_DSR

UART0_CTS

UART0_DTR

UART0_RI

UART0_RTS

UART1_Rx

UART1_Tx

UART1_DSR/CTS

UART1_DTR/RTS

UART2_Rx

UART2_Tx

Interrupts Interface

IRQ0:15

n/a

-

n/a

-

n/a

-

n/a

-

UARTSerClk

async

n/a

-

n/a

-

19.1

-

8.7

-

n/a

-

async

-

async

n/a

-

n/a

-

async

n/a

async

n/a

19.1

8.7

async

n/a

-

n/a

-

UARTSerClk

async

n/a

-

n/a

-

n/a

-

n/a

-

async

n/a

-

n/a

-

UARTSerClk

n/a

-

n/a

async

JTAG Interface

TDI

-

na

-

na

-

na

8.7

na

async

TMS

TDO

na

-

na

-

19.1

na

TCK

na

TRST

-

na

System Interface

Halt

-

n/a

-

n/a

-

n/a

19.1

n/a

8.7

n/a

8.7

n/a

8.7

n/a

async

na

GPIO00:31

SysClk

-

n/a

-

n/a

-

SysErr

n/a

19.1

n/a

async

na

SysReset

HISRRst

-

19.1

n/a

TESTEN

n/a

TmrClk

n/a

Trace Interface

TrcClk

n/a

-

19.1

8.7

TRCBS0:2

TrcES0:4

-

TrcTS0:6

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Preliminary Data Sheet

Table 15. I/O Specifications—667MHz

Notes:

1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.

Input (ns)

Output (ns)

Hold Time

(T max) (T min)

OV

Output Current (mA)

I/O H I/O L

(minimum) (minimum)

Signal

Clock

Notes

Setup Time Hold Time Valid Delay

(T min)

IS

(T min)

IH

OH

External Slave Peripheral Interface

PerAddr00:26

PerBE0:1

PerBLast

PerCS0:2

PerData0:15

PerOE

n/a

-

1

-

6.2

0

19.1

27.7

19.1

8.7

12.8

8.7

PerClk

na

-

n/a

1.2

n/a

1.7

3.6

n/a

1.2

1

5.7

5.9

6

n/a

0

n/a

1

0

n/a

1

5.8

5.7

n/a

5.7

n/a

0

PerPar0:1

PerReady

PerR/W

n/a

0

1

PerWE

n/a

ExtReset

PerClk

n/a

PerClk

PLB clk

PerClk

PerErr

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DDR SDRAM I/O Specifications

Preliminary Data Sheet

The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from

the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the

same frequency as the PLB clock signal and is in phase with the PLB clock signal.

Note: MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR

programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific

application and requires a thorough understanding of the memory system in general (refer to the DDR

SDRAM controller chapter in the PPC440SPe Embedded Processor User’s Manual).

In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and

MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90°. Advancing MemClkOut0 by 90°

creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to

MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.

The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths.

It is not to be used as a circuit design recommendation. Values are calculated over best case and worst case

processes with speed, temperature, and voltage as follows:

Best Case = Fast process, 0°C, +1.6V

Worst Case = Slow process, +95°C, +1.4V

Note: In all the following DDR tables and timing diagrams, minimum values are measured under best case

conditions and maximum values are measured under worst case conditions.

The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.

Figure 7. DDR SDRAM Signal Termination

MemClkOut0

10pF

120Ω

10pF

MemClkOut0

PPC440SPe

V

= SV /2

DD

TT

50Ω

Addr/Ctrl/Data/DQS

30pF

Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.

It is not a recommended physical circuit design for this interface. An actual interface design will depend on many

factors, including the type of memory used and the board layout.

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Preliminary Data Sheet

Table 16. DDR SDRAM Output Driver Specifications

Output Current (mA)

Signal Path

I/O H (maximum)

I/O L (minimum)

Write Data

MemData00:07

MemData08:15

MemData16:23

MemData24:31

MemData32:39

MemData40:47

MemData48:55

MemData56:63

ECC0:7

15.2

DM0:8

MemClkOut0

MemAddr00:12

BA0:1

RAS

CAS

WE

BankSel0:3

ClkEn0:3

DQS0:8

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DDR SDRAM Write Operation

Preliminary Data Sheet

The following timing chart shows the relationship between the signals involved in a DDR write operation.

Figure 8. DDR SDRAM Write Cycle Timing

PLB Clk

MemClkOut

T

DS

T

HA

SA

Addr/Cmd

DQS

T

SD

T

SD

MemData

T

HD

T

HD

T

= Setup time for address and command signals to MemClkOut

SA

HA

SD

HD

DS

= Hold time for address and command signals from MemClkOut

= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)

= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)

= Delay from rising/falling edge of clock to the rising/falling edge of DQS

DDR SDRAM Read and Write I/O Timing—T and T

SA

HA

Note 1: Clock speed is 333 MHz. T and T are referenced to MemClkOut.

SA

HA

Note 2: Memory clock signal is shifted by 90° from the internal clock.

Table 17. DDR SDRAM Read and Write I/O Timing—T and T

SA

HA

T

(ns)

T

(ns)

HA

SA

Signal Name

Minimum

1.32

Minimum

1.2

MemAddr00:12

BA0:1

1.15

1.49

BankSel0:3

ClkEn0:3

CAS

1.12

1.52

1.29

1.45

1.24

1.14

RAS

1.29

1.48

WE

1.35

1.43

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Preliminary Data Sheet

DDR SDRAM Clock to Write DQS Timing—T

DS

Note 1: All of the DQS signals are referenced to MemClkOut.

Note 2: Clock speed is 333 MHz.

Note 3: The TDS values in the table include 1.5 × 3ns cycle at 333 MHz (3 ns × 1.5 = 4.5 ns).

Note 4: To obtain adjusted values for lower clock frequencies, subtract 4 ns from the values in the following table

and add × 1.5 of the cycle time for the lower clock frequency (T - 4.5 + 1.5 T

).

DS

CYC

Table 18. DDR SDRAM Clock to Write DQS Timing—T

DS

T

(ns)

DS

Signal Name

Minimum

4.76

Maximum

5.07

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

4.78

5.09

4.78

5.10

4.76

5.07

4.79

5.11

4.80

5.13

4.81

5.11

4.79

5.11

4.77

5.07

DDR SDRAM Write Data to DQS Timing—T

T

SD and HD

Note 1: T and T are measured under worst-case conditions.

SD

HD

Note 2: Clock speed for the values in the following table is 333 MHz.

Table 19. DDR SDRAM Write Data to DQS Timing—T and T

SD

HD

T_HD(ns)

T_SD(ns)

Signal Name

Reference Signal

DQS0

MemData00:07, DM0

MemData08:15, DM1

MemData16:23, DM2

MemData24:31, DM3

MemData32:39, DM4

MemData40:47, DM5

MemData48:55, DM6

MemData56:63, DM7

ECC0:7, DM8

0.58

0.62

0.63

0.68

0.67

0.62

0.65

0.63

0.64

0.55

0.60

0.57

0.54

0.52

0.61

0.55

0.61

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

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DDR SDRAM Read Operation

Preliminary Data Sheet

The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS

signal. The Data must be centered to these edges for correct operation.

The PPC440SPe can delay with very fine granularity the DQS through the programming of the

MCIF0_RODC[RQFD] register field.

DDR SDRAM MemClkOut0 and Read Clock Delay

In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data

path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency.

The data are stored in the 8 Flip Flops of the Stage 1, such that it can be transferred later within a 8X period.

Figure 9. DDR SDRAM Read Data Path

FF: Flip-Flop

DDR 1X Clock

Ext FeedBack

Signals

Driver

MemDCFdbkD

FeedBack

Signal Gen

Coarse Delay

MCIF0_RFDC[RFFD]

Fine Delay

Read Start

Read Latency adjust circuit

CAS Lat Delay

DDR 1X Clock

Rec

Stage 2 Store

Oversampling

Fine Delay

MemDCFdbkR

DQS aligned

FBK signal

Cycles

Delay

+1

MCIF0_RFDC[RFOS]

Feedback

Data Capture

Window

T1 T2 T3 T4

MCIF0_RDCC[RDSS]

adjust

Oversampling

Clock

0

1

Q2_Ovs

7

Package

pins

Mux

0

2

4

6

FF

Compare

FF

Q2

PLB bus

[0:63]

D

Read FIFO

Upper

(x64)

C

Mux

DQS Rising

Edge Sync

DQ

Data

(x64)

Stage 2

Stage 3

Stage 1

Lower

FF

1

3

5

Q3

PLB bus

[64:127]

FF

D

(x64)

7

C

Programmed

Read DQS

Delay

DQS Falling

Edge Sync

DQS

(Diff)

DDR 1X Clock

PLB 1X Clock

MCIF0_RQDC[RQFD]

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Preliminary Data Sheet

Table 20. DDR SDRAM I/O Read Timing—T and T

SD

HD

Notes:

1. T

and T

are measured under worst case conditions.

SD

HD

2. Clock speed for the values in the table is 333.33MHz.

3. The time values in the table include 1/4 of a cycle at 166MHz (3ns x 0.25 = 0.75 ns).

4. To obtain adjusted T and T values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4

SD

HD

of the cycle time for the lower clock frequency (e.g., T

- 0.75 + 0.25T

).

SD

CYC

Read Data vs DQS Set up

(ns)

Read Data vs DQS Hold

(ns)

Signal Names

MemData00:07

Reference Signal

T

SD

0.00

HD

1.00

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

MemData08:15

MemData16:23

MemData24:31

MemData32:39

MemData40:47

MemData48:55

MemData56:63

ECC0:7

0.00

1.00

In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a

slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal

routing. It is recommended that the signal length for all of the eight DQS signals be matched.

Figure 10. DDR SDRAM Memory Data and DQS

DQS

T

SD

MemData

T

HD

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Preliminary Data Sheet

The following example shows the timing relationship between SDRAM DDR Data at the input pin and the store of

the Data in stage 1.

Figure 11. DDR SDRAM Read Cycle Timing—Example

Oversampling Guard Band

DDR 1X Clock

DDR 2X Clock

Memclk (Diff.)

DQS at

MemCntl Pin

Data at Pin

D0

D1

D2

D3

D4

T2

D5

D6

D7

D8

D9

Store 1st Data in Stage 2

T3

Feedback

Output

1X DDR Clk cycle

T1

T4

Delayed DQS

Data Out Stage 1 (0)

Data Out Stage 1 (1)

Data out Stage 1 (2)

Valid

High

Low

D0

D1

D2

D3

Data Out Stage 2

PLB 1X Clock

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Initialization

Preliminary Data Sheet

The PPC440SPe provides the option for setting initial parameters based on default values or by reading them from

a serial “bootstrap” ROM attached to the IIC0 bus. These options are defined by strapping on three external pins

(see “Strapping” below).

Strapping

While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default

initial conditions prior to PPC440SPe start-up. The actual capture instant is the nearest SysClk edge before the

deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)

resistors to select the desired default conditions. They are used for strap functions only during reset. Following

reset they are used for normal functions.

The following table lists the strapping pins along with their functions and strapping options:

Table 21. Strapping Pin Assignments

Pin Strapping

Bit 1

Bit2

Function

Option

Bit 0

H13

(UART0_DCD)

C12

(UART0_DSR)

B08

(UART0_CTS)

Serial Bootstrap ROM is disabled (Bit 0 off).

Refer to the IIC Bootstrap Controller chapter in the

PPC440SPe Embedded Processor User’s Manual

for details.

Boot from EBC

Boot from PCI

0x54

0

1

0

1

0

Serial Bootstrap ROM is enabled (Bit 0 on).

The options being selected are the IIC0 slave

address that responds with strapping data and

reading 128 bits from the Bootstrap ROM.

0

1

0x50

0x54

0x50

1

0

1

Serial Bootstrap ROM is enabled (Bit 0 on).

The options being selected are the IIC0 slave

address that responds with strapping data and

reading 256 bits from the Bootstrap ROM.

Serial Bootstrap ROM

During reset, if the serial device is enabled, initial conditions can be read from a ROM connected to the IIC0 port. In

this case, at the de-assertion of SysReset, the PPC440SPe sequentially reads up to 32 bytes from the ROM device

on the IIC0 port and sets the SDR0_SDSTP0 - SDR0_SDSTP7 registers accordingly.

The initialization settings and their default values are covered in detail in the PPC440SPe Embedded Processor

User’s Manual.

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Document Revision History

Preliminary Data Sheet

Revision

1.23

Date

Description

Sept 21, 2006

Sept 12, 2006

Updated Recommended DC Operating Conditions table.

1.22

Updated Processor Clock values in Clocking Specifications table.

Updated Recommended DC Op Conditions and Signal Functional Description tables for PCI-X

DDR mode 2.

1.21

1.20

June 27, 2006

June 14, 2006

Updated signal lists. Corrected reference to PCIX0Cap in Signal Functional Description table.

Added reference to Note 6 for UART0_CTS register in Signal Functional Description table.

Fixed doc issue for PEROE signal in Signal Functional Description table. Fixed doc issue for

UARTSerClk signal throughout document. Fixed doc issue for PSRO1 signal in Signal Functional

Description table. Updated Clocking Specifications table and Serial Bootstrap ROM paragraph.

1.19

1.18

May 23, 2006

May 1, 2006

Updated ordering and PVR information, and core package graphic in Figure 3. Added RAID

acceleration section to Features, Description, and functional details sections.

1.17

1.16

April 6, 2006

Additional update to ordering and PVR information. GJG

March 8, 2006

Updated ordering and PVR information, part number list, and package diagram. GJG

Removed DMA statement from Serial Port feature statement. Removed reference to notes from

PERBLAST entry in signal functional description table. GJG

1.15

1.14

1.13

1.12

1.11

March 7, 2006

March 6, 2006

Updated description of On-Chip SRAM/L2 Cache in Introduction. GJG

Updated Signal Function Description table per JB, updated mailing address and copyright date in

disclaimer. GJG

January 9, 2006

November 15, 2005

October 26, 2005

Clarified information about DDR SDRAM I/O specifications. GJG

Corrected upper limit of allowable case temperature, documented reserved signal pins, added

bookmarks for signal lists. GJG

Restored multiplexed signal information to the “Signals Listed Alphabetically” table. Applied

corrections to the table from GB. GJG

1.10

October 17, 2005

1.09

1.08

1.07

1.06

July 12, 2005

May 23, 2005

May 20, 2005

Mar 10, 2005

Updated leakage current info, case temp range, DDR SDRAM Signal Termination graphic. GJG

Update Write timing diagrams. GJG

Updated system memory address map. Corrected functional block diagram. GJG

Removed text for unsupported COLA component. GJG

Removed references to unsupported COLA serial interface. Reformatted LOF, LOT to comply with

AMCC style. GJG

1.05

1.04

1.03

Feb 15, 2005

Dec 21, 2004

Dec 20, 2004

Update max case temp in Recommended DC Op Conditions table to match Ordering and PVR

Information table. GJG

Update Ordering and PVR info, PCI Express features info, DDR SDRAM read data path and read

cycle timing example, memory map. GJG

1.02

1.01

0.5

Sept 21, 2004

Sept 13, 2004

Sept 10, 2004

Aug 02, 2004

July 18, 2004

June 25, 2004

June 18, 2004

PCI-Express Rx Tx pin assignment changes. GJG

Converted to AMCC format, corrected tables, graphics as needed. GJG

Renamed 440SPe, added Mux table, VDDA 2.5V (IN PROGRESS)

Miscellaneous technical additions, PN and corrections from Support.

Correct TOC, LOF, LOT, broken cross-references.

Add alphabetic list, update Sys Mem address map.

Create initial data sheet.

0.4

0.3

0.2

0.1

78

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

AMCC Proprietary

79

Revision 1.23 - Sept 21, 2006

PowerPC 440SPe Embedded Processor

Preliminary Data Sheet

Applied Micro Circuits Corporation

215 Moffett Park Dr., Sunnyvale, CA 94089

Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885

http://www.amcc.com

AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war-

rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available

datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.

AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia-

bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under

its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower

grade.

AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE

SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL

APPLICATIONS.

80

AMCC Proprietary


型号：	PPC440SPE-RNB533C
厂家：	APPLIED MICRO CIRCUITS CORPORATION
描述：	PowerPC 440SPe Embedded Processor 440SPe的PowerPC嵌入式处理器 PC
文件：	总80页 (文件大小：1204K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PPC440SPE-RNB533C [AMCC]

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