PPC460EX-NTB1000T [AMCC]
RISC Microprocessor, 1000MHz, CMOS, PBGA728, 35 X 35 MM, PLASTIC, MS-034, TEEBGA-728;![PPC460EX-NTB1000T](http://pdffile.icpdf.com/pdf2/p00293/img/icpdf/PPC460EX-SUA_1775856_icpdf.jpg)
型号: | PPC460EX-NTB1000T |
厂家: | ![]() |
描述: | RISC Microprocessor, 1000MHz, CMOS, PBGA728, 35 X 35 MM, PLASTIC, MS-034, TEEBGA-728 |
文件: | 总106页 (文件大小:1089K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Part Number 460EX
Revision 1.19 – June 17, 2009
Preliminary Data Sheet
460EX
PowerPC 460EX Embedded Processor
Features
• PowerPC® 440 processor operating between
600MHz and 1.000GHz with 32KB I-cache and D-
cache and 256KB L2/SRAM with parity checking
• Two Ethernet 10/100/1000Mbps half- or full-
duplex interfaces. Operational modes supported
are MII, GMII, RGMII, and SGMII with QoS,
Jumbo frames, interrupt coalescing, and TCP/IP
acceleration
• On-chip memory (64KB)
• Floating Point Unit
• Up to four serial (UART) ports (16750 compatible)
• USB 2.0 Host/Device OTG and Host interface
• Processor Local Bus (PLB) with 128-bit width
• Double Data Rate 2/1 (DDR2/1) Synchronous
DRAM (SDRAM) interface
• Two IIC interfaces (one with boot parameter read
capability)
• One four-channel DMA (Direct Memory Access)
for internal and external peripherals
• NAND Flash interface
• SPI interface
• One single-channel, high-performance DMA for
internal use
• SATA controller
• General Purpose I/O (GPIO) interface
• JTAG interface for board level testing
• External 32-bit peripheral bus (EBC) for up to six
devices. Up to 100MHz
• Programmable Interrupt Controller (UIC) with up
to 16 external interrupts
• Boot from PCI memory, NOR Flash on the
external peripheral bus, or NAND Flash on the
NAND Flash interface
• Programmable General Purpose Timers (GPTs)
• Optional security feature with KASUMI
• Two PCI Express 1.1 interfaces—one 4-lane and
one 1-lane
• Available in RoHS compliant, lead-free package
• PCI V2.3 interface. Thirty-two bits at up to 66MHz
Description
Designed specifically to address high-end embedded
applications, the PowerPC 460EX (PPC460EX)
provides a high-performance, low-power solution that
interfaces to a wide range of peripherals and
Technology: CMOS Cu-08, 90nm.
Package: 35mm, 728-ball thermally and electrically
enhanced plastic ball grid array (TE-EPBGA). RoHS
compliant package available.
incorporates on-chip power management features.
Typical power: Less than 5W at 1GHz with DDR2.
This chip contains a high-performance RISC
processor, on-chip memory, a floating point unit, a
DDR2/1 SDRAM controller, PCI and PCI Express bus
interfaces, control for external ROM and peripherals,
DMA with scatter/gather support, Ethernet ports, serial
ports, IIC interfaces, SPI interface, USB ports, NAND
Flash interface, SATA interface, an optional security
feature with KASUMI, and general purpose I/O.
Supply voltages required: 3.3V, 2.5V (DDR1,
Ethernet), 1.8V (DDR2), 1.2V.
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Contents
Preliminary Data Sheet
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PPC460EX Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PowerPC 440 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
L2 Cache/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Security Function (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PCI Express Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDR2/1 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DMA 4-Channel Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I2O/DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Ports (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
IIC Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Peripheral Controller (SPI/SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Universal Serial Bus 2.0 (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Assembly Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DDR2/1 SDRAM Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
PCI Express Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Serial ATA (SATA) Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PCI-E and SATA Reference Clock AC Coupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Revision Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Figures
Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. PPC460EX Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. 35mm, 728-Ball TE-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 6. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 7. Setup and Hold Timing Waveforms for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 8. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 9. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 10. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 11. LVDS PCIe or SATA Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 12. LVPECL PCIe or SATA Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 13. CML PCIe or SATA Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 14. HCSL PCIe or SATA Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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460EX – PPC460EX Embedded Processor
Tables
Preliminary Data Sheet
Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Recommended Reflow Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. JEDEC Moisture Sensitivity Level and Ball Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 7. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 8. Non-Functional Ball Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 9. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 10. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 11. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 12. 3.3V, 2.5V, and LVDS I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 13. Typical DC Power Supply Requirements Using DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 14. Typical DC Power Supply Requirements Using DDR1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 16. Maxiumum DC Power Supply Requirements Using DDR1 Memory . . . . . . . . . . . . . . . . . . . . . . 78
Table 15. Maxiumum DC Power Supply Requirements Using DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . 78
Table 17. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 18. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 19. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 20. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 21. RGMII I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 22. AC I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 23. DDR I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 24. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 25. DDR SDRAM Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 26. I/O Timing—DDR SDRAM TDS for 200 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 27. I/O Timing—DDR SDRAM TSA, and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 28. I/O Timing—DDR SDRAM Write Timing TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 29. I/O Timing—DDR SDRAM Read Timing TSD and THD for 200MHz . . . . . . . . . . . . . . . . . . . . . . 96
Table 30. PCI Express Transmitter Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 31. PCI Express Receiver Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 32. PCI Express Reference Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 33. SATA Transmitter Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 34. SATA Receiver Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 35. SATA Reference Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 36. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Ordering and PVR Information
For information on the availability of the following parts, contact your local AMCC sales office. For additional
information on the part number structure see Figure 1.
Order Part Number
Revision
Level
Product Name
Package
PVR Value
JTAG ID
(see Notes)
PPC460EX
PPC460EX
PPC460EX-opAfff(f)T
PPC460EX-opBfff(f)T
35mm 728-ball TE-EPBGA
35mm 728-ball TE-EPBGA
A
B
0x130218A2
0x130218A4
0x144101E1
0x144101E1
Notes: Characters following the dash (-):
1. o = Security option: S = security feature present, N = no security
2. p = Package type: U = lead-free (RoHS compliant), T = contains lead.
3. A = Chip revision level A, B = Chip revision level B
4. fff(f) = Processor frequency: fff = 600 = 600MHz, fff = 800 = 800MHz, ffff = 1000 = 1GHz
5. T = Case temperature range of −40°C to +85°C.
Each part number contains a revision code. This is the die mask revision number and is included in the part
number for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain
information that uniquely identifies the part. Refer to the PowerPC 460EX/EXr/GT Embedded Processor User’s
Manual for details on accessing these registers.
Figure 1. Order Part Number Key
PPC460EX-SUB1000T
AMCC Part Number
Security Feature
Case Temperature Range
Processor Frequency
Package
Revision Level
Note: The example P/N above contains the security feature, is lead-free, is capable of running at 1GHz, and is shipped
in a tray (tape-and-reel packaging is not available).
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Block Diagram
Figure 2. PPC460EX Functional Block Diagram
16
External
Interrupts
Clock
Control
Reset
Power
Mgmt
DCRs
Timers
MMU
External
Bus
Controller
NAND
Flash
Controller
IIC(x2)
BSC
UART
x4
GPIO GPT
SPI
UIC
PPC440
DCR Bus
Processor
On-chip Peripheral Bus (OPB)–32 bits, 100MHz
Arb
FPU
JTAG
Trace
Security
Engine
w/KASUMI
DMA
Cntl
(4-Ch)
OPB
Bridge
SRAM
Cntl
OCM
64KB
HSDMA
Cntl
TRNG/
PKA
32KB
I-Cache
32KB
D-Cache
S2
S7
S1
S3
S4
S5
Low Latency (LL) Segment
256KB L2 Cache
S0
S6
M0
M5
M1
M4
M6
M7
M8 M9
Arb
Processor Local Bus (PLB)–128 bits, 200MHz
M3
M2
M11
PLB-to-AHB
M10
High Bandwidth (HB) Segment
S2
S1
MAL w/
Int. Coalescing
Bridge
S4
S3
S0
M1 S1
AHB Bus–32 bits, 200MHz
Arb
Memory
Queue
PCI-Express
S6
TAH/QoS
PCI
33/66 MHz
USB 2.0 USB 2.0
DMA
Cntl
M1
PCI-E0
(x1)
Int
PCI-E1
(x4)
10/100/1000
x2
OTG
Cntl
Host
Cntl
DDR 1 and 2
SDRAM Cntrlr
Hand
32-bit
Ethernet
RGMII
Bridge Bridge
ZMII
ICM
1 lane
4 lanes
64 + 8
HSS x1
HSS x1/x4
ULPI SDR
SATA
SGMII
Interface
x2
Sn = Slave n
Mn = Master n
The PPC460EX is a system on a chip (SOC).
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Address Maps
The PPC460EX incorporates two address maps. The first is a fixed processor System Memory Address Map. This
address map defines the possible contents of various address regions which the processor can access. The
second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC460EX processor through the use of mtdcr and mfdcr instructions.
Table 1. System Memory Address Map (Part 1 of 3)
Function
Sub Function
DDR SDRAM
Start Address
End Address
Size
16GB
256KB
64KB
704KB
64KB
256B
256B
256B
63.25KB
64KB
384KB
512KB
~3GB
256KB
64KB
1KB
0000 0000 0000 0000
0000 0004 0000 0000
0000 0004 0004 0000
0000 0004 0005 0000
0000 0004 0010 0000
0000 0004 0010 0000
0000 0004 0010 0100
0000 0004 0010 0200
0000 0004 0010 0300
0000 0004 0011 0000
0000 0004 0012 0000
0000 0004 0018 0000
0000 0004 0020 0000
0000 0004 BFF8 0000
0000 0004 BFFC 0000
0000 0004 BFFD 0000
0000 0004 BFFD 0400
0000 0004 BFFD 0800
0000 0004 BFFD 0C00
0000 0004 BFFD 1000
0000 0004 BFFD 1800
0000 0004 BFFD 2000
0000 0004 BFFD 2400
0000 0003 FFFF FFFF
0000 0004 0003 FFFF
0000 0004 0004 FFFF
0000 0004 000F FFFF
0000 0004 0010 FFFF
0000 0004 0010 00FF
0000 0004 0010 01FF
0000 0004 0010 02FF
0000 0004 0010 FFFF
0000 0004 0011 FFFF
0000 0004 0017 FFFF
0000 0004 001F FFFF
0000 0004 BFF7 FFFF
0000 0004 BFFB FFFF
0000 0004 BFFC FFFF
0000 0004 BFFD 03FF
0000 0004 BFFD 07FF
0000 0004 BFFD 0BFF
0000 0004 BFFD 0FFF
0000 0004 BFFD 17FF
0000 0004 BFFD 1FFF
0000 0004 BFFD 23FF
0000 0004 BFFF FFFF
SRAM (L2 Cache)
On-Chip Memory (OCM)
Reserved
1
Local Memory (LL)
I2O/DMA
I2O Registers
Reserved
HSDMA Registers
Reserved
1
Internal PLB Interfaces (LL)
PKA & TRNG (EIPPKP)
Reserved
Security Function (EIP94)
Reserved
USB 2.0 OTG
Reserved
USB 2.0 Host (OHCI)
USB 2.0 Host (EHCI)
AHBDMA for SATA
Reserved
1KB
1KB
Internal AHB Peripherals (LL)
1KB
SATA
2KB
Reserved
2KB
AHB Arbiter
1KB
Reserved
183KB
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 1. System Memory Address Map (Part 2 of 3)
Function
Sub Function
EBC Memory except Bank 0
Reserved
Start Address
End Address
Size
640MB
118MB
512B
256B
8B
6
0000 0004 C000 0000
0000 0004 E800 0000
0000 0004 EF60 0000
0000 0004 EF60 0200
0000 0004 EF60 0300
0000 0004 EF60 0308
0000 0004 EF60 0400
0000 0004 EF60 0408
0000 0004 EF60 0500
0000 0004 EF60 0508
0000 0004 EF60 0600
0000 0004 EF60 0608
0000 0004 EF60 0700
0000 0004 EF60 0720
0000 0004 EF60 0800
0000 0004 EF60 0820
0000 0004 EF60 0900
0000 0004 EF60 0910
0000 0004 EF60 0A00
0000 0004 EF60 0A40
0000 0004 EF60 0B00
0000 0004 EF60 0B80
0000 0004 EF60 0C00
0000 0004 EF60 0C80
0000 0004 EF60 0D00
0000 0004 EF60 0D10
0000 0004 EF60 0E00
0000 0004 EF60 0F00
0000 0004 EF60 1000
0000 0004 EF60 1300
0000 0004 EF60 1400
0000 0004 EF60 1500
0000 0004 EF60 1510
0000 0004 FF00 0000
0000 0005 0000 0000
0000 0008 0000 0000
0000 0004 E7FF FFFF
0000 0004 EF5F FFFF
0000 0004 EF60 01FF
0000 0004 EF60 02FF
0000 0004 EF60 0307
0000 0004 EF60 03FF
0000 0004 EF60 0407
0000 0004 EF60 04FF
0000 0004 EF60 0507
0000 0004 EF60 05FF
0000 0004 EF60 0607
0000 0004 EF60 06FF
0000 0004 EF60 071F
0000 0004 EF60 07FF
0000 0004 EF60 081F
0000 0004 EF60 08FF
0000 0004 EF60 090F
0000 0004 EF60 09FF
0000 0004 EF60 0A3F
0000 0004 EF60 0AFF
0000 0004 EF60 0B7F
0000 0004 EF60 0BFF
0000 0004 EF60 0C7F
0000 0004 EF60 0CFF
0000 0004 EF60 0D0F
0000 0004 EF60 0DFF
0000 0004 EF60 0EFF
0000 0004 EF60 0FFF
0000 0004 EF60 12FF
0000 0004 EF60 13FF
0000 0004 EF60 14FF
0000 0004 EF60 150F
0000 0004 FEFF FFFF
0000 0004 FFFF FFFF
0000 0007 FFFF FFFF
0000 000B FFFF FFFF
General Purpose Timer
Reserved
UART0
Reserved
248B
8B
UART1
Reserved
248B
8B
UART2
Reserved
248B
8B
UART3
Reserved
248B
32B
IIC0
Reserved
224B
32B
IIC1
Reserved
224B
16B
Internal OPB Peripherals (LL)
SPI
Reserved
240B
64B
OPB Arbiter
Reserved
192B
128B
128B
128B
128B
16B
GPIO0 Controller
Reserved
GPIO1 Controller
Reserved
Ethernet PHY ZMII
Reserved
240B
256B
256B
768B
256B
256B
16B
EMAC0 Controller
EMAC1 Controller
Reserved
TAHOE0 Accelerator
TAHOE1 Accelerator
RGMII0 Controller
Reserved
~250MB
16MB
12GB
16GB
2, 3
Boot ROM
EBC Memory Bank 0
Reserved
Internal PLB Interfaces (LL)
Local Memory Alias (HB)
Aliased DDR SDRAM
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 1. System Memory Address Map (Part 3 of 3)
Function
Sub Function
PCI Express Memory
Start Address
End Address
Size
128MB
64KB
0000 000C 0000 0000
0000 000C 0800 0000
0000 000C 0801 0000
0000 000C 0880 0000
0000 000C 0C00 0000
0000 000C 0EC0 0000
0000 000C 0EC0 0008
0000 000C 0EC8 0000
0000 000C 0EC8 1200
0000 000C 0ED0 0000
0000 000C 0ED0 0004
0000 000C 1000 0000
0000 000C 1000 0100
0000 000C FF00 0000
0000 000D 0000 0000
0000 0010 0000 0000
0400 0000 0000 0000
1000 0000 0000 0000
2000 0000 0000 0000
0000 000C 07FF FFFF
0000 000C 0800 FFFF
0000 000C 087F FFFF
0000 000C 0BFF FFFF
0000 000C 0EBF FFFF
0000 000C 0EC0 0007
0000 000C 0EC7 FFFF
0000 000C 0EC8 11FF
0000 000C 0ECF FFFF
0000 000C 0ED0 0003
0000 000C 0FFF FFFF
0000 000C 1000 00FF
0000 000C FEFF FFFF
0000 000C FFFF FFFF
0000 000F FFFF FFFF
03FF FFFF FFFF FFFF
0FFF FFFF FFFF FFFF
1FFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF
PCI I/O
PC Express Memory
PCI Extra I/O
~8MB
~56MB
~44MB
8B
PCI Express Memory
PCI Configuration Registers
Reserved
~512KB
4.75KB
~512KB
4B
PCI/PCIE Space (HB)
PCI Local Registers
Reserved
PCI Special Cycle
Reserved
~19MB
256B
PCI Express Interrupt Handler
PCI, PCI Express Memory
PCI Boot ROM (PCI Memory)
PCI, PCI Express Memory
~3.8MB
16MB
12GB
4
Reserved
5
Reserved
XOR Space (HB)
PCI/PCIE Space (HB)
Notes:
XOR
PCI, PCI Express Memory
1. DDR SDRAM, SRAM (L2 Cache) and On-Chip Memory (OCM) can be located anywhere in the Local Memory area of the memory
map.
2. The Boot ROM area of the memory map are intended for use by ROM or Flash-type devices. While locating volatile DDR SDRAM and
SRAM in this region is supported, use of these regions for this purpose is not recommended.
3. When the optional boot from PCI Memory is selected, the PCI Boot ROM address space begins at 0000 000C FF00 0000 (16 MB).
4. Never decoded.
5. Unpredictable results on Read and Write operations.
6. Accessed by means of EBC Peripheral Bank Configuration Registers.
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 2. DCR Address Map
Function
Base Address
Start Address
End Address
Size
1
1
Total DCR Address Space
000
3FF
1KW (4KB)
By function:
Reserved
000
00C
00E
010
012
014
020
030
040
050
060
080
090
0A0
0B0
0C0
0D0
0E0
0F0
100
120
140
160
168
180
200
240
00B
00D
00F
011
013
01F
02F
03F
04F
05F
07F
08F
09F
0AF
0BF
0CF
0DF
0EF
0FF
11F
13F
15F
167
17F
1FF
23F
3FF
12W
2W
Clocking Power On Reset (CPR)
System DCRs (SDR)
Memory Controller
External Bus Controller (EBC)
Reserved
00 0000 110x
00 0000 111x
00 0001 000x
00 0001 001x
2W
2W
2W
12W
16W
16W
16W
16W
32W
16W
16W
16W
16W
16W
16W
16W
16W
32W
32W
32W
8W
L2 Cache as SRAM
L2 Controller
00 0010 xxxx
00 0011 xxxx
00 010x xxxx
Memory Queue
Reserved
I2O/DMA Controller
PLB Arbiter
00 011x xxxx
00 1000 xxxx
00 1001 xxxx
00 1010 xxxx
00 1011 xxxx
00 1100 xxxx
00 1101 xxxx
00 1110 xxxx
00 1111 xxxx
01 000x xxxx
01 001x xxxx
PLB-to-OPB Bridge
PLB-to-AHB Bridge
On-Chip Memory (OCM)
Universal Interrupt Controller 0
Universal Interrupt Controller 1
Universal Interrupt Controller 2
Universal Interrupt Controller 3
PCI Express 0
PCI Express 1
Reserved
Power Management
Reserved
01 011x xxxx
24W
128W
64W
448W
Ethernet MAL
01 1xxx xxxx
10 00xx xxxx
DMA Controller
Reserved
Notes:
1. DCR addresses are 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One
kiloword (1024W) equals 4KB (4096 B).
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
PPC460EX Features
The following sections provide information on the features of the chip.
PowerPC 440 Processor
The PowerPC 440 processor (in 90nm technology) is designed for high-end applications: RAID controllers, SAN,
iSCSI, routers, switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture
and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
• Up to 1.000GHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
– UTLB Word Wide parity on data and tag address parity with exception force
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• Three execution pipelines
• Dynamic branch prediction
• Memory management unit
– 64-entry, full associative, unified TLB with optional parity
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
• Debug facilities
– Multiple instruction and data range breakpoints
– Data value compare
– Single step, branch, and trap events
– Non-invasive real-time trace interface
• 24 DSP instructions
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
– 16 x 16 -> 32-bit MAC
Floating Point Unit (FPU)
The chip has a built-in super scalar FPU that supports both single- and double-precision operations, and offers
single cycle through put on most instructions.
Features include:
• Five stages with 2 MFlops/MHz
• Hardware support for IEEE 754
• Single- and double-precision
• Single-cycle throughput on most instructions
• Thirty-two 64-bit floating point registers
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
L2 Cache/SRAM
The PPC460EX also provides a 256KB L2 cache between the Processor Local Bus and the processor’s D- and
I-caches. This memory unit can be alternatively programmed to function as 256KB of SRAM.
Features include:
• Four banks of 64KB each
• Memory cycles supported:
– Single beat read and write, 1 to 16 bytes
– Quadword Read and Write burst for 12-bit master
– Guarded memory accesses on 4KB boundaries
• Sustainable 3.2GB/s peak bandwidth at 200MHz
• Use as an L2 cache improves processor performance and reduces the PLB load
– Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) Processor Local
Bus (PLB) or by software
– Data Array and Tag Array parity
– Unified data and instruction cache
– Four-way set associative
– 36-bit addressing
– Full LRU replacement algorithm
– Write through, look aside
On-Chip Memory (OCM)
The PPC460EX provides 64KB of on-chip memory.
Features include:
• Up to 128-bit bus width
• 128-bit slave attachment, addressable by any PLB master
• Transfers by PLB slave cycles:
– Single-beat read and write (1 to 8 bytes for 64-bit masters, 1 to 16 bytes for 128-bit masters)
– 4- and 8-word line reads and writes
– Double word read and write bursts for 64-bit masters
– Quadword read and write bursts for 128-bit masters
– Slave-terminated double word and quadword fixed length bursts
– Master-terminated variable length bursts
• Guarded memory access on 4KB boundaries
• Data parity checking
• Data transfers at PLB bus speeds
• Power management
• Use as storage area for DMA descriptors and packet data for processing by Ethernet and Security Function.
Internal Buses
The PowerPC 460EX features four standard internal buses: one Processor Local Bus (PLB), one On-chip
Peripheral Bus (OPB), the Advanced High-performance Bus (AHB), and the Device Control Register bus (DCR).
The high performance, high bandwidth functions such as the PowerPC 440 processor, the DDR SDRAM memory
controller, PCI Express, PCI, and the AHB bridge, connect to the PLB. The OPB hosts lower data rate peripherals.
The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the
processor and the other on-chip cores.
The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments
identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU
and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB
segment allows PLB masters DMA, PCI and PCI Express to exchange large blocks of data with SDRAM, PCI and
PCI Express without interfering with the low latency PLB masters.
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Features include:
• PLB4 (128-bit)
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 64-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte-enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
– 200MHz, maximum 12.8GB/s (simultaneous read and write)
– Processor:bus clock ratios of N:1
• AHB
– 32-bit data path
– 32-bit address
– Synchronous to the PLB
– Up to 200MHz, maximum 800MB/s
• OPB
– 32-bit data path with dynamic sizing for 32-, 16-, and 8-bit width
– 32-bit address
– 100MHz
• DCR
– 32-bit data path
– 10-bit address
Security Function (Optional)
The built-in security function is a cryptographic engine attached to the PLB with built-in DMA and interrupt
controllers.
Features include:
• Federal Information Processing Standard (FIPS) 140-2 design
• Support for an unlimited number of Security Associations (SA)
• Different SA formats for each supported protocol (IPsec/SSL/TLS/sRTP)
• Internet Protocol Security (IPSec) features
– Full packet transforms, Encapsulated Security Payload (ESP) and Authentication Header (AH)
– Complete header and trailer processing (IPv4 and IPv6)
– Multi-mode automatic padding
– "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
– Extended Sequence Number (ESN) processing for ESP and AH
• Secure Socket Layer (SSL) and Transport Layer Security (TLS) features and Datagram Transport Layer
Security (DTLS) features
– Packet transforms
– One-pass hash-then-encrypt for SSL and TLS packet transforms for inbound packet using Stream Cipher
• Secure Real-Time Protocol (sRTP) features
– Packet transforms
– Roll Over Counter (ROC) removal and TAG insertion
– Variable bypass offset of header length per packet
• Media Access Control Security (MACSec) features
– MSDU (User data) encryption 0, 30, or 50 bytes offset
– Header insertion and removal
– SecTAG header with or without Secure Channel Identifier (SCI) field
– 128-bit key, 96-bit IV (nonce) and 128-bit ICV
– IV from SA record or from input buffer (as part of SecTAG)
– ICV generation and validation
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
• SGT features:
– GCM-AES with 128-bit key, 96-bit IV (nonce) and 128-bit ICV
– SecTAG header with or without Secure Channel Identifier (SCI) field
– Replay protection "Strict order Mode" and "Out of Order Mode"
– Header insertion and removal
– ICV generation and validation
• IPsec/SSL security acceleration engine
• DES, 3DES, AES, ARC-4 encryption (no support for hashing of zero length messages)
• MD-5, SHA-1, and SHA-2 (224-, 256-, 384-, and 512-bit) hashing, HMAC encrypt-hash and hash-decrypt
• Public key acceleration (PKA) for RSA, DSA and Diffie-Hellman
• True (TRNG) or pseudo (PRNG) random number generators
– Non-deterministic true random numbers
– Pseudo random numbers with lengths of 8 or 16 bytes
– ANSI X9.17 Annex C compliant using a DES algorithm
• Interrupt controller
– Fifteen programmable, maskable interrupts
– Initiate commands by means of an input interrupt
– Sixteen programmable interrupts indicating completion of certain operations
– All interrupts mapped to one level- or edge-sensitive programmable interrupt output
• DMA controller
– Autonomous, 4-channel
– 1024 words (32 bits/word) per DMA transfer
– Scatter/gather capability with byte aligned addressing
PCI Controller
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is
designed to Version 2.3 of the PCI Specification and supports 32- bit PCI devices.
Reference Specifications:
• PCI Specification Version 2.3
• PCI Bus Power Management Interface Specification Version 1.1
Features include:
• Frequency to 66MHz
• 32-bit bus
• PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to four external devices, that can be disabled for use with an
external arbiter
• Support for inbound and outbound Message Signaled Interrupts (MSI)
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI bus memory
• Error tracking/status
• Supports initiation of transfers of the following types:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
• Vital Product Data (VPD) support
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
PCI Express Controller
There are two independent PCI Express interfaces compliant with PCI Express base specification 1.1. One
interface can be configured as one to four lanes while the other functions as one-lane only. Both can be Root or
Endpoint Ports. The single lane interface shares a High-Speed SERDES with the Serial ATA (SATA) interface.
Features include:
• Two independent PCI Express interfaces
– One 4 lanes
– One 1 lane
– 2.5 GB/sec full duplex per lane
• Compliant with PCI Express base specification 1.1
• Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)
– Applications compliant with MSI rules are limited to one Endpoint port per PPC460EX
• Power Management
• Supports one virtual channel (VC0) no Traffic Class (TC) filtering
• Maximum Payload block size 512 Bytes
• Supports up to 512 Bytes maximum Read request size
• Requests supported:
– up to 4 (x4) or 2 (x1) posted outbound Write requests (memory and messages)
– up to 4 (x4) or 2 (x1) posted inbound Write requests
– up to 4 (x4) or 2 (x1) outbound Read requests outstanding on PCI Express
– up to 4 (x4) or 2 (x1) inbound Read requests outstanding on PCI Express
– Outbound I/O request as a PCI Express Root Port
– Inbound I/O request as a PCI Express Endpoint
• Buffering in each PCI Express port for the following transaction types:
– 2KB Replay buffer: up to 4 in flight transactions
– 2KB (x4) or 1KB (x1) for Outbound posted Writes
– 2KB (x4) or 1KB (x1) for Outbound Reads completion
– 2KB (x4) or 1KB (x1) for Inbound posted Writes
– 2KB (x4) or 1KB (x1) for Inbound Reads completion
• Parity checking on each buffer
• Programmable Outbound Memory (POM) regions: 3 memory, 1 I/O, 1 message, 1 configuration, 1 internal
register
• Programmable Inbound Memory (PIM) regions: 4 memory, 1 I/O, 1 expansion ROM
• INTx Interrupts support (legacy PCI):
– Up to four INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC
– A/B/C/D INTx types generation for Endpoints
• MSI - Message Signaled Interrupts
– MSI generation for Endpoint
– MSI termination for Root Ports
– MSI_X termination for Root Ports
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
DDR2/1 SDRAM Memory Controller
The Double Data Rate 2/1 (DDR2/1) SDRAM memory controller supports industry standard 184-pin DIMMs, SO-
DIMMs, and other discrete devices. Global memory timings, address and bank sizes, and memory addressing
modes are programmable. This controller interfaces to the PLB through a Memory Queue (MQ) function that
includes six high-speed 1KB FIFO buffers.
The correct I/O supply voltage must be provided for the two types of DDR devices: DDR1 devices require +2.5V
and DDR2 devices require +1.8V.
Features include:
• Registered and non-registered industry standard DIMMs
• DDR2 333/400 support
• 64- and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)
• 3.2GB/s peak bandwidth for the 64-bit interface
• 1.6GB/s peak bandwidth for the 32-bit interface
• Four chip (bank) select signals supporting four external banks
• CAS latencies of 2, 3, 4, 5, 6, and 7
• Page mode accesses (up to 32 open pages) with configurable paging policy
• Look-ahead request queue with programmable depth of four commands
• Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current
bank)
• Up to 8GB in four external banks
• Up to two MemClkOut signals
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Sync DRAM configuration by means of mode register and extended mode register set commands
• Power management (self-refresh, suspend, sleep)
• Low Latency and High Bandwidth PLB ports
• Selectable PLB read response (immediate or deferred)
• Programmable Low Latency and High Bandwidth arbitration schemes
• High Bandwidth port has four 1KB read buffers and two 1KB write buffers
• Low Latency port has four 128B read buffers and two 128B write buffers
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
External Peripheral Bus Controller (EBC)
The External Bus Controller (EBC) transfers data between the PLB and external memory or peripheral devices
attached to the external peripheral bus. The EBC allows for direct attachment of memory devices such as ROM
and SRAM, DMA device-paced memory devices, and DMA peripheral devices.
Features include:
• Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 100MHz operation
• Burst and non-burst devices
• 32-bit byte-addressable data bus
• Data parity
• 27-bit address
• Peripheral Device pacing with external Ready
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to eight Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping
• External DMA Slave Support
Ethernet Controller
Two 10/100/1000 Ethernet ports are supported.
Features include:
• Compliant with ANSI/IEEE Standard 802.3 and IEEE 802.3u supplement
• Compliant with IEEE Standard 802.3z (Gigabit Ethernet)
• Two 10/100/1000 interfaces running in full- and half-duplex modes providing:
– One Gigabit Media Independent Interface (GMII)
– One Media Independent Interface (MII)
– Two Reduced Gigabit MII (RGMII)
– Two Serial GMIIs (SGMII)
• Quality of Service (QoS) support
– Support of IEEE 802.1p priority queueing for up to 8 priorities
– Recognizes TCI field in VLAN-tagged frames where the priority field is coded
• Jumbo frame support (9018 bytes)
– Support for Ethernet II formatted frames (RFC894)
– Support for IEEE formatted frames (RFC1042)
– Handles VLAN-tagged frames (IEEE 802.2ac)
• TCP/IP Acceleration Hardware (TAH) support
• Off loads Gigabit Ethernet protocol processing from the CPU
• Checksum verification for TCP/UDP/IP headers in the receive path
• Checksum generation for TCP/UDP/IP headers in the transmit path
• TCP segmentation support in the transmit path
• IPv4 and IPv6 support
• IPv6 header extension support
• Wake On LAN handling
• 256-bit hash table to filter multicast frames
• DMA capability
• Interrupt coalescence
AMCC Proprietary
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
DMA 4-Channel Controller
The 4-channel DMA controller provides a DMA interface between the PLB memories and internal and external
peripheral devices.
Features include:
• Supports the following transfers:
– Memory-to-memory
– Buffered peripheral to memory
– Buffered memory to peripheral
• Scatter/Gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 64-bit addressing
• 128 byte FIFO buffer
• Address increment or decrement
• Support for:
– Internal and external peripherals
– Memory mapped peripherals
– Peripherals running on slower frequency buses
I2O/DMA Controller
The I2O/DMA controller provides one High Speed DMA (HSDMA) interface to the PLB and support for I2O
messaging. The HSDMA provides single-channel direct memory access support to ease the CPU burden. I2O
manages Message Frame Address (MFA) FIFOs or queues in memory in response to I2O register reads and
writes and transfers message frames.
DMA features include:
• Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)
• Separate 512-byte buffering for transmit and receive
– 1.4GB throughput (local read)
– 1.0GB throughput (remote read)
• Simultaneous fill and drain (PLB read/write pipelining)
• Any source PLB address to any destination address
• No memory alignment restrictions on source or destination
• 32-byte command descriptor block
• Maximum transfer size of 16MB
• 64-bit addressing
• Prefetch indicators for PCI buffer management
• Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
I2O features include:
• I2O pull- and push-messaging methods
• Dynamic message frame size
• Programmable FIFO size (4096 64-bit MFAs maximum)
• 64- and 32-bit MFA sizes
• Three interrupt gathering methods
• Registered MFA prefetch and posting
• 32-bit inbound and outbound doorbell registers
• Four 32-bit scratch pad registers
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Serial Ports (UART)
The Universal Asynchronous Receiver/Transmitter (UART) interface provides one 8-signal port, or two 4-signal
ports, or four 2-signal ports. The UART performs serial-to-parallel conversion on data received from a peripheral
device or a modem, and parallel-to-serial conversion on data received from the processor.
Features include:
• Up to four ports in the following combinations:
– One 8-pin (UART0)
– Two 4-pin (UART0 and UART1)
– Four 2-pin (UART0, UART1, UART2, and UART3)
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with 16750 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using the 4-channel internal DMA function
• 64-byte FIFOs for buffering transmit and receive data
IIC Bus Controller
The Inter-Integrated Circuit (IIC) interface provides a Philips® I2C™ compatible interface operating up to 400 kHz
either as a master, a slave, or both, with a Bootstrap Controller (BSC) included. During chip reset, the Bootstrap
Controller can read configuration data from an IIC-compatible memory device (for example, EEPROM). This data
can be used to replace the default configuration settings provided by the chip.
Features include:
• Two IIC interfaces
• Support for Philips Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed VDD IIC interface
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
• Port 0 includes an integrated BSC that supports a serial Bootstrap ROM with default override parameters at
initialization
AMCC Proprietary
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Serial Peripheral Controller (SPI/SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,
character-oriented (byte) port that allows the exchange of data with other serial devices. The SPI is a master on the
serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features include:
• Three-wire serial port interface
• Full-duplex synchronous operation
• SPI bus master
• OPB bus slave
• Programmable clock rate divider
• Clock inversion
• Reverse data
• Local data loop back for test
Universal Serial Bus 2.0 (USB)
Two USB 2.0 interfaces provide both Device and Host support. These interfaces are provided as one USB 2.0 On-
The-Go (OTG) controller (Host and Device) and one USB 2.0 Host controller. Both controllers provide support to
an external PHY device through separate ULPI SDR interfaces.
Features include:
• USB 2.0 Host
– Fully compliant to the following specifications:
• Universal Serial Bus Specification, Revision 2.0
• Enhanced Host Controller Interface (EHCI) Specification for USB, Revision 1.0
• Open Host Controller Interface (OHCI) Specification for USB, Revision 1.0a
– One EHCI high speed (480Mbps) Host interface
– One OHCI full/low speed (12Mbps/1.5Mbps) Host interface
– Maximum packet sizes of 1024B for isochronous transfers and 512B for bulk transfers
– Isochronous traffic can have three packets per microframe (196.6 Mbps throughput)
– Data and descriptor prefetch to optimize performance and off load CPU
– 4 KB buffer
• USB 2.0 OTG
– Fully compliant to the following specifications
• Universal Serial Bus Specification, Revision 2.0
• On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a
– Configurable as a Host-only or Device-only controller
– Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transfers
– Maximum packet sizes of 1024B for isochronous transfers and 512B for bulk transfers
– Isochronous traffic can have three packets per microframe (196.6 Mbps throughput)
– Integrated DMA support to optimize performance and off load CPU
– Device support provides six Endpoints (3 IN, 3 OUT)
– 8192-byte FIFO by Endpoint (supports high-bandwidth isochronous transfers, double buffering of 1024-
byte packets)
– FIFOs are not shared between IN and OUT Endpoints
– Two USB 2.0 device Endpoints have DMA dedicated channels
– 16KB buffer
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Serial ATA (SATA)
The Serial Advanced Technology Attachment (ATA) interface provides an interface to physical storage devices. It
shares the High-Speed SERDES with the PCI-Express interface with 1-Lane.
Features include:
• Compliant with Serial ATA Revision 2.5 Specification
• Supports SATA 1.5Gbps Generation 1 and 3Gbps Generation 2 speeds
• Supports device hot-plugging
• Supports power management
• Supports BIST loopback modes
• Dedicated DMA controller support to optimize performance and off load CPU
• Separate 512B transmit and receive buffers
NAND Flash Controller
The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND
Flash devices. It provides both direct command, address, and data access to the external device as well as a
memory-mapped linear region that generates data accesses. NAND Flash data is transferred on the peripheral
data bus.
Features include:
• One to four banks supported on EBC
• Direct interface to:
– Discrete NAND Flash devices (up to four devices)
– SmartMedia Card socket (22-pins)
• Device sizes of 4MB and larger supported for read/write access
• (512 + 16)-B or (2K + 64)-B page sizes supported
• Boot from NAND supported with execution of up to 4KB of boot code out of block 0
• ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED):
– ECC generation assist software with ECC checking of SLC NAND
– No ECC checking supported when booting directly from block 0
• Chip select pins are multiplexed with EBC
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor.
Features include:
• Time Base Counter (32 bits) driven by the OPB bus clock
• Seven 32-bit compare timers
General Purpose IO (GPIO) Controller
Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB bus
master accesses.
Features include:
• Sixty-four GPIOs multiplexed with other functions. DCRs control whether a GPIO pin acts as a GPIO or is used
for another purpose.
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
tri-stated if output bit is 1).
AMCC Proprietary
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Universal Interrupt Controller (UIC)
Universal Interrupt Controllers (UICs) provide control, status, and communications necessary between the external
and internal sources of interrupts and the on-chip PowerPC processor.
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.
Features include:
• Sixteen external interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to the on-chip processor
• Programmable interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
JTAG
Features include:
• IEEE 1149.1 Test Access Port
• JTAG Boundary Scan Description Language (BSDL)
• IBM RISCWatch support
Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with
this port.
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Package Diagram
Figure 3. 35mm, 728-Ball TE-PBGA Package
Top View
Logo View
Part
Number
®
24
30
TYP TYP
PPC460EX e1
PPC460EX-nprfff(f)T
ccccccc
Heat Slug
1YWWBZZZZZ MMDDQL
Side View
2.65 max
Mold
Compound
Lot Number (ZZZZZ)
PCB
Substrate
Gold Gate Release
Corresponds to
A01 Ball Location
Bottom View
0.4 - 0.6
35.0
33.0
AP
AM
AK
AH
AN
AL
AJ
1.0
AG
AF
AD
AB
Y
AE
AC
AA
W
U
Thermal Balls
Notes: 1. All dimensions are in mm.
2. Package is available with lead or
lead-free (RoHS compliant).
3. Package conforms to JEDEC MS-034.
4. Optional solder ball diameter is
V
T
R
0.63 +0.07/−0.13.
P
N
7.0
M
K
L
J
H
G
F
E
D
C
B
A
19 21 23
27 29 31 33
01 03 05 07 09 11 13 15 17
08 10
25
22 26 28
24
06
12 14
30
34
32
04
16 18
02
20
728 x 0.60 0.10 Solder Ball
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460EX – PPC460EX Embedded Processor
Assembly Recommendations
Preliminary Data Sheet
Assembly recommendations from JEDEC standard J-STD-020 should be used unless recommended differently in
the following table.
Table 3. Recommended Reflow Soldering Profile
Sn-Pb Eutectic Assembly
(PPC460EX-STxfff)
Pb Free Reflow Assembly
(PPC460EX-SUxfff)
Profile Feature
Average ramp-up rate
Preheat:
3°C/second max
3°C/second max
•
•
•
Temperature Min
Temperature Max
Time (min to max)
100°C
150°C
150°C
200°C
60–120 seconds
60–120 seconds
Time Maintained Above:
•
•
Temperature
Time
183°C
60–150 seconds
217°C
60–150 seconds
Peak Temperature
225°C
260°C
Time within 5°C of Actual Peak Temperature
Ramp-down Rate
20 seconds max
6°C/second max
6 minutes max
30 seconds max
6°C/second max
8 minutes max
Time 25°C to Peak Temperature
Table 4. JEDEC Moisture Sensitivity Level and Ball Composition
Sn-Pb (PPC460EX-STxfff)
Pb Free (PPC460EX-SUxfff)
MSL Level
3
3
Solder Ball Metallurgy
63Sn/37Pb
Sn/4Ag/05Cu
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Signal Lists
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the
signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate
signals in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each signal name
on the ball. The page number listed gives the page in Table 9 on page 64 where the signals in the indicated
interface group begin. In cases where signals in the same interface group (for example, Ethernet) have different
names to distinguish variations in the mode of operation, the names are separated by a comma with the primary
mode name appearing first. In cases where the signals have the same function but are associated with different
ports (for example, UART), the signals are separated by a slash (/). These signals are listed only once, and appear
alphabetically by the primary mode or primary port name.
Alphabetical Signal List
Table 5. Signals Listed Alphabetically (Part 1 of 26)
Signal Name
Ball
L01
Interface Group
Page
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
L02
M04
M06
P03
P04
P06
R01
R02
R06
U01
U04
U05
Y01
Y03
Y05
AA04
Power
73
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 2 of 26)
Signal Name
Ball
L03
Interface Group
Page
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
L06
M03
M05
N03
N06
P05
T03
U02
Power
73
U03
U06
V03
V06
W03
W06
Y02
Y04
AB04
AN32
AP31
AM31
AL28
AP29
AM29
AN29
AL29
AE29
AF34
AE33
AE31
C31
BA0
BA1
DDR2/1 SDRAM
66
BA2
BankSel0
BankSel1
DDR2/1 SDRAM
DDR2/1 SDRAM
DDR2/1 SDRAM
66
66
66
BankSel2
BankSel3
CAS
ClkEn0
ClkEn1
ClkEn2
ClkEn3
[DMAAck0]GPIO47[PerAddr06][IRQ14]
[DMAAck1]GPIO44[PerCS4][IRQ11]
[DMAAck2]GPIO31[PerPar1][IRQ8]
[DMAAck3]GPIO36[UART0CTS][UART3Rx]
[DMAReq0]GPIO46[PerAddr05][IRQ13]
[DMAReq1]GPIO43[PerCS3][NFCE3][IRQ10]
[DMAReq2]GPIO30[PerPar0][IRQ7]
[DMAReq3]GPIO33[PerPar3][IRQ4]
E21
A16
E31
DMA
69
B32
A22
A20
F13
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 3 of 26)
Signal Name
Ball
P31
Interface Group
Page
DM0
DM1
U30
DM2
V30
DM3
AB34
AM25
AP23
AN20
AM17
AD34
P33
DM4
DDR2/1 SDRAM
66
DM5
DM6
DM7
DM8
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DQS8
DQS8
P32
U32
U31
W31
W32
AA30
AA31
AP25
AN25
AN22
AM22
AM19
AL19
AK17
AL17
AD32
AD33
Y14
DDR2/1 SDRAM
66
E1OV
E1OV
E1OV
E1OV
E1OV
E1OV
E1OV
E1OV
E1OV
E1OV
E2OV
E2OV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
AA15
AD06
AF02
AG05
AJ11
AK02
AK08
AN05
AN09
AK13
AN16
Power
73
Power
73
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 4 of 26)
Signal Name
Ball
AP12
Interface Group
Page
EAGND
Power
73
EAVDD
AP11
AC31
AC30
AE32
AE34
AC34
AC32
AD31
AD30
D30
ECC0
ECC1
ECC2
ECC3
DDR2/1 SDRAM
66
ECC4
ECC5
ECC6
ECC7
[EOT0/TC0]GPIO48[PerAddr07][IRQ15]
[EOT1/TC1]GPIO45[PerCS5][IRQ12]
[EOT2/TC2]GPIO32[PerPar2][IRQ9]
[EOT3/TC3]GPIO37[UART0RTS][UART3Tx]
ExtReset
D21
DMA
69
A14
D33
F22
External Peripheral
System
69
72
FSOURCE0
E17
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 5 of 26)
Signal Name
GMC0CD, GMC1RxClk
GMC0CrS, GMC1TxClk
GMC0GTxClk, GMC0TxClk
GMC0RxClk, GMC0RxClk
GMC0RxD0, GMC0RxD0
GMC0RxD1, GMC0RxD1
GMC0RxD2, GMC0RxD2
GMC0RxD3, GMC0RxD3
GMC0RxD4, GMC1RxD0
GMC0RxD5, GMC1RxD1
GMC0RxD6, GMC1RxD2
GMC0RxD7, GMC1RxD3
GMC0RxDV, GMC0RxCtl
GMC0RxEr, GMC1RxCtl
GMC0TxClk
Ball
AP05
Interface Group
Page
AL07
AN06
AM07
AL09
AK09
AP08
AJ09
AN08
AL08
AM08
AP07
AL06
AJ10
AN04
AM02
AK04
AL02
AL01
AK03
AM01
AH05
AL03
AM05
AJ08
AJ03
AK01
AP09
Ethernet 0
67
GMC0TxD0, GMC0TxD0
GMC0TxD1, GMC0TxD1
GMC0TxD2, GMC0TxD2
GMC0TxD3, GMC0TxD3
GMC0TxD4, GMC1TxD0
GMC0TxD5, GMC1TxD1
GMC0TxD6, GMC1TxD2
GMC0TxD7, GMC1TxD3
GMC0TxEn, GMC0TxCtl
GMC0TxEr, GMC1TxCtl
GMCMDClk
GMCMDIO
Ethernet 0
67
GMCRefClk
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 6 of 26)
Signal Name
Ball
A01
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A02
A03
A33
A34
B01
B02
B03
B07
B12
B23
B28
B33
B34
C01
C02
C03
C16
C32
D04
D31
E05
E10
E23
E25
E28
E30
F06
F16
F19
F29
F30
F31
F32
Power
73
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 7 of 26)
Signal Name
Ball
G02
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
G31
G33
H01
J01
J03
J30
J32
K02
K05
K06
K30
M30
M33
P14
P16
P19
P21
R15
R16
R19
R20
T14
T15
T16
T17
T18
T19
T20
T21
T30
U16
U17
U18
U19
Power
73
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 8 of 26)
Signal Name
Ball
V16
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V17
V18
V19
W14
W15
W16
W17
W18
W19
W20
W21
W29
Y15
Y16
Y19
Y20
AA14
AA16
AA19
AA21
AC01
AC03
AC04
AC05
AC33
AD01
AE03
AE05
AE30
AF05
AF29
AF30
AG29
AH02
AH33
Power
73
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 9 of 26)
Signal Name
Ball
AJ06
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AJ13
AJ16
AJ23
AJ25
AJ26
AJ27
AJ29
AJ30
AJ31
AK05
AK06
AK07
AK10
AK14
AK19
AK24
AK25
AK28
AK29
AK30
AL04
AL05
AL22
AL25
AL30
AL31
AL32
AL33
AL34
AM03
AM04
AM06
AM10
AM30
AM32
Power
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 10 of 26)
Signal Name
Ball
AN01
AN02
AN03
AN07
AN12
AN23
AN28
AN31
AN33
AN34
AP01
AP02
AP03
AP04
AP06
AP16
AP17
AP33
AP34
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
73
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AMCC Proprietary
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 11 of 26)
Signal Name
GPIO00[USB2HD0]
GPIO01[USB2HD1]
GPIO02[USB2HD2]
GPIO03[USB2HD3]
GPIO04[USB2HD4]
GPIO05[USB2HD5]
GPIO06[USB2HD6]
GPIO07[USB2HD7]
GPIO08[USB2DD0]
GPIO09[USB2DD1]
GPIO10[USB2DD2]
GPIO11[USB2DD3]
GPIO12[USB2DD4]
GPIO13[USB2DD5]
GPIO14[USB2DD6]
GPIO15[USB2DD7]
GPIO16[USB2HStop]
GPIO17[USB2HNext]
GPIO18[USB2HDir]
GPIO19[USB2DStop]
GPIO20[USB2DNext]
GPIO21[USB2DDir]
GPIO22[NFRdyBusy]
GPIO23[NFREn]
Ball
AG01
AD05
AE04
AF01
AE02
AE01
AB05
AD03
AH04
AJ05
AG06
AJ02
AJ04
AH03
AJ01
AH01
AF04
AG02
AG04
AF03
AG03
AD04
C24
Interface Group
Page
System
72
B24
GPIO24[NFWEn]
A24
GPIO25[NFCLE]
F26
GPIO26[NFALE]
A25
GPIO27[IRQ0]
D12
GPIO28[IRQ1]
E12
GPIO29[IRQ2]
F12
GPIO30[PerPar0][DMAReq2][IRQ7]
GPIO31[PerPar1][DMAAck2][IRQ8]
A20
A16
AMCC Proprietary
35
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 12 of 26)
Signal Name
GPIO32[PerPar2][EOT2/TC2][IRQ9]
GPIO33[PerPar3][DMAReq3][IRQ4]
GPIO34[UART0DCD][UART1CTS][UART2Tx]
GPIO35[UART0DSR][UART1RTS][UART2Rx]
GPIO36[UART0CTS][DMAAck3][UART3Rx]
GPIO37[UART0RTS][EOT3/TC3][UART3Tx]
GPIO38[UART0DTR][UART1Tx][IRQ5]
GPIO39[UART0RI][UART1Rx][IRQ6]
GPIO40[IRQ3]
Ball
A14
Interface Group
Page
F13
E34
E32
E31
D33
D32
D34
C12
B22
D25
A22
E21
D21
B32
C31
D30
H33
J34
GPIO41[PerCS1][NFCE1]
GPIO42[PerCS2][NFCE2]
GPIO43[PerCS3][NFCE3][DMAReq1][IRQ10]
GPIO44[PerCS4][DMAAck1][IRQ11]
GPIO45[PerCS5][EOT1/TC1][IRQ12]
GPIO46[PerAddr05][DMAReq0][IRQ13]
GPIO47[PerAddr06][DMAAck0][IRQ14]
GPIO48[PerAddr07][EOT0/TC0][IRQ15]
GPIO49[TrcBS0]
System
72
GPIO50[TrcBS1]
GPIO51[TrcBS2]
H34
L30
L31
K33
L32
K34
L33
N29
M31
L34
M32
M34
N31
H32
B11
J31
GPIO52[TrcES0]
GPIO53[TrcES1]
GPIO54[TrcES2]
GPIO55[TrcES3]
GPIO56[TrcES4]
GPIO57[TrcTS0]
GPIO58[TrcTS1]
GPIO59[TrcTS2]
GPIO60[TrcTS3]
GPIO61[TrcTS4]
GPIO62[TrcTS5]
GPIO63[TrcTS6]
Halt
System
72
66
HISRRst
DDR2/1 SDRAM
IIC0SClk
IIC0SData
H31
K31
G34
IIC Peripheral
70
[IIC1SClk]SPIClkOut
[IIC1SData]SPIDO
36
AMCC Proprietary
Downloaded from DatasheetLib.com - datasheet search engine
Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 13 of 26)
Signal Name
Ball
D12
Interface Group
Page
[IRQ0]GPIO27
[IRQ1]GPIO28
E12
[IRQ2]GPIO29
F12
[IRQ3]GPIO40
C12
[IRQ4]GPIO33[PerPar3][DMAReq3]
[IRQ5]GPIO38[UART0DTR][UART1Tx]
[IRQ6]GPIO39[UART0RI][UART1Rx]
[IRQ7]GPIO30[PerPar0][DMAReq2]
[IRQ8]GPIO31[PerPar1][DMAAck2]
[IRQ9]GPIO32[PerPar2][EOT2/TC2]
[IRQ10]GPIO43[PerCS3][NFCE3][DMAReq1]
[IRQ11]GPIO44[PerCS4][DMAAck1]
[IRQ12]GPIO45[PerCS5][EOT1/TC1]
[IRQ13]GPIO46[PerAddr05][DMAReq0]
[IRQ14]GPIO47[PerAddr06][DMAAck0]
[IRQ15]GPIO48[PerAddr07][EOT0/TC0]
MemAddr00
F13
D32
D34
A20
Interrupt
71
A16
A14
A22
E21
D21
B32
C31
D30
AK34
AJ33
AJ32
AJ34
AH30
AH31
AH32
AG31
AH34
AG32
AG33
AF31
AG34
AC29
AF32
AP27
AN27
AK31
AK32
MemAddr01
MemAddr02
MemAddr03
MemAddr04
MemAddr05
MemAddr06
MemAddr07
DDR2/1 SDRAM
66
MemAddr08
MemAddr09
MemAddr10
MemAddr11
MemAddr12
MemAddr13
MemAddr14
MemClkOut0
MemClkOut0
DDR2/1 SDRAM
66
MemClkOut1
MemClkOut1
AMCC Proprietary
37
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 14 of 26)
Signal Name
MemData00
MemData01
MemData02
MemData03
MemData04
MemData05
MemData06
MemData07
MemData08
MemData09
MemData10
MemData11
MemData12
MemData13
MemData14
MemData15
MemData16
MemData17
MemData18
MemData19
MemData20
MemData21
MemData22
MemData23
MemData24
MemData25
MemData26
MemData27
MemData28
MemData29
MemData30
MemData31
Ball
P30
Interface Group
Page
N34
R32
R30
N33
N32
P34
R31
R34
T34
V34
T32
R33
T31
U33
U34
V32
V31
Y32
W30
V33
W34
Y34
Y33
AA33
AA32
AB31
Y30
AA34
Y31
AB33
AB32
DDR2/1 SDRAM
66
38
AMCC Proprietary
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 15 of 26)
Signal Name
MemData32
MemData33
MemData34
MemData35
MemData36
MemData37
MemData38
MemData39
MemData40
MemData41
MemData42
MemData43
MemData44
MemData45
MemData46
MemData47
MemData48
MemData49
MemData50
MemData51
MemData52
MemData53
MemData54
MemData55
MemData56
MemData57
MemData58
MemData59
MemData60
MemData61
MemData62
MemData63
MemDCFdbkD
MemDCFdbkR
MemODT0
Ball
AM26
AP26
AK21
AN24
AL26
AK26
AL24
AM24
AL23
AM23
AM21
AN21
AK23
AP24
AP22
AL21
AL20
AM20
AL18
AM18
AK20
AP21
AP20
AP19
AP18
AN17
AL16
AP15
AK18
AN18
AM16
AK16
AM33
AM34
AP28
AM27
AM28
AL27
Interface Group
Page
DDR2/1 SDRAM
66
DDR2/1 SDRAM
DDR2/1 SDRAM
66
66
MemODT1
MemODT2
MemODT3
AMCC Proprietary
39
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 16 of 26)
Signal Name
Ball
AJ19
Interface Group
Page
MemVRef1A
MemVRef1B
AB29
AJ22
T29
A25
E24
B22
D25
A22
F26
C24
B24
A24
B05
B09
B16
B19
B26
B30
E02
E08
E13
E22
E27
E33
F11
F24
H05
H30
J02
DDR2/1 SDRAM
66
MemVRef2A
MemVRef2B
[NFALE]GPIO26
[NFCE0]PerCS0
[NFCE1]GPIO41[PerCS1
[NFCE2]GPIO42[PerCS2]
[NFCE3]GPIO43[PerCS3][DMAReq1][IRQ10]
[NFCLE]GPIO25
NAND Flash
71
[NFRdyBusy]GPIO22
[NFREn]GPIO23
[NFWEn]GPIO24
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Power
73
J33
L29
P15
P20
R14
R21
T06
AA05
PAV
PAV
DD
DD
Power
73
40
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AMCC Proprietary
Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 17 of 26)
Signal Name
Ball
D11
Interface Group
Page
PCI0AD00
PCI0AD01
E11
B10
A10
C10
F10
D10
A09
D09
A08
F09
B08
C08
D08
A07
F08
A05
A04
D05
B04
D02
F04
E03
D03
E01
E04
G05
G04
F02
H06
F01
F05
C09
C07
C05
F03
K01
A06
E06
PCI0AD02
PCI0AD03
PCI0AD04
PCI0AD05
PCI0AD06
PCI0AD07
PCI0AD08
PCI0AD09
PCI0AD10
PCI0AD11
PCI0AD12
PCI0AD13
PCI0AD14
PCI0AD15
PCI
64
PCI0AD16
PCI0AD17
PCI0AD18
PCI0AD19
PCI0AD20
PCI0AD21
PCI0AD22
PCI0AD23
PCI0AD24
PCI0AD25
PCI0AD26
PCI0AD27
PCI0AD28
PCI0AD29
PCI0AD30
PCI0AD31
PCI0C/BE0
PCI0C/BE1
PCI0C/BE2
PCI0C/BE3
PCI0Clk
PCI
PCI
64
64
PCI0DevSel
PCI0Frame
AMCC Proprietary
41
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 18 of 26)
Signal Name
Ball
G03
Interface Group
Page
PCI0Gnt0/Req
PCI0Gnt1
H04
G01
H03
D01
J04
PCI
64
PCI0Gnt2
PCI0Gnt3
PCI0IDSel
PCI0Int
PCI0IRdy
C04
E09
PCI
64
PCI0M66En
PCI0Par
D07
B06
PCI0PErr
PCI0Req0/Gnt
J06
PCI0Req1
H02
K04
PCI
PCI
64
64
PCI0Req2
PCI0Req3
J05
PCI0Reset
K03
PCI0SErr
E07
PCI0Stop
C06
D06
AA01
AB02
AB01
AA02
AA03
W04
W05
W02
W01
PCI0TRdy
PCIE0AVReg[SATA0AVReg]
PCIE0CalRN[SATA0CalRN]
PCIE0CalRP[SATA0CalRP]
PCIE0RefClk[SATA0RefClk]
PCIE0RefClk[SATA0RefClk]
PCIE0Rx0[SATA0Rx0]
PCIE0Rx0[SATA0Rx0]
PCIE0Tx0[SATA0Tx0]
PCIE0Tx0[SATA0Tx0]
PCI Express 0
64
42
AMCC Proprietary
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 19 of 26)
Signal Name
Ball
R05
Interface Group
Page
PCIE1AVReg
PCIE1CalRN
PCIE1CalRP
PCIE1RefClk
PCIE1RefClk
PCIE1Rx0
PCIE1Rx0
PCIE1Rx1
PCIE1Rx1
PCIE1Rx2
PCIE1Rx2
PCIE1Rx3
PCIE1Rx3
PCIE1Tx0
PCIE1Tx0
PCIE1Tx1
PCIE1Tx1
PCIE1Tx2
PCIE1Tx2
PCIE1Tx3
PCIE1Tx3
P01
P02
R04
R03
L05
L04
N05
N04
T04
T05
V05
V04
M02
M01
N02
N01
T02
T01
V02
V01
PCI Express 1
65
AMCC Proprietary
43
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 20 of 26)
Signal Name
Ball
B32
Interface Group
Page
[PerAddr05]GPIO46[DMAReq0][IRQ13]
[PerAddr06]GPIO47[DMAAck0][IRQ14]
C31
D30
A32
E29
C30
B31
A30
A31
D29
C29
A29
D28
C28
B29
C27
A28
D26
F27
B27
D27
A27
C26
A26
C25
B25
D24
F25
F23
E24
B22
D25
A22
E21
D21
[PerAddr07]GPIO48[EOT0/TC0][IRQ15]
PerAddr08
PerAddr09
PerAddr10
PerAddr11
PerAddr12
PerAddr13
PerAddr14
PerAddr15
PerAddr16
PerAddr17
PerAddr18
External Peripheral
69
PerAddr19
PerAddr20
PerAddr21
PerAddr22
PerAddr23
PerAddr24
PerAddr25
PerAddr26
PerAddr27
PerAddr28
PerAddr29
PerAddr30
PerAddr31
PerBLast
External Peripheral
External Peripheral
69
69
PerClk
PerCS0[NFCE0]
[PerCS1]GPIO41[NFCE1]
[PerCS2]GPIO42[NFCE2]
[PerCS3]GPIO43[NFCE3][DMAReq1][IRQ10]
[PerCS4]GPIO44[DMAAck1][IRQ11]
[PerCS5]GPIO45[EOT1/TC1][IRQ12]
External Peripheral
69
44
AMCC Proprietary
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 21 of 26)
Signal Name
Ball
C21
Interface Group
Page
PerData00
PerData01
B21
A21
E20
D20
C20
D18
B20
E19
D19
E18
C19
A19
C18
B18
A18
D17
B17
A15
B15
E15
C15
D16
D15
E16
C14
E14
D14
B14
A13
B13
C13
A20
A16
A14
F13
D13
E26
D23
PerData02
PerData03
PerData04
PerData05
PerData06
PerData07
PerData08
PerData09
PerData10
PerData11
PerData12
PerData13
PerData14
PerData15
External Peripheral
69
PerData16
PerData17
PerData18
PerData19
PerData20
PerData21
PerData22
PerData23
PerData24
PerData25
PerData26
PerData27
PerData28
PerData29
PerData30
PerData31
[PerPar0]GPIO30[DMAReq2][IRQ7]
[PerPar1]GPIO31[DMAAck2][IRQ8]
[PerPar2]GPIO32[EOT2/TC2][IRQ9]
[PerPar3]GPIO33[DMAReq3][IRQ4]
PerErr
External Peripheral
69
External Peripheral
External Peripheral
External Peripheral
69
69
69
PerOE
PerR/W
AMCC Proprietary
45
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 22 of 26)
Signal Name
Ball
C17
Interface Group
Page
PerReady
External Peripheral
69
PerWBE0
C23
PerWBE1
A23
External Peripheral
DDR2/1 SDRAM
69
66
PerWBE2
D22
PerWBE3
C22
RAS
AP30
A17
Reserved
Reserved
AL13
AM13
AL12
AM12
AM15
AN15
AP10
AN10
AA01
AB02
AB01
AA02
AA03
W04
Reserved
Reserved
Reserved
Other
73
Reserved
Reserved
Reserved
Reserved
[SATA0AVReg]PCIE0AVReg
[SATA0CalRN]PCIE0CalRN
[SATA0CalRP]PCIE0CalRP
[SATA0RefClk]PCIE0RefClk
[SATA0RefClk]PCIE0RefClk
[SATA0Rx0]PCIE0Rx0
[SATA0Rx0]PCIE0Rx0
[SATA0Tx0]PCIE0Tx0
[SATA0Tx0]PCIE0Tx0
SGMII0RxClk
Serial ATA
68
W05
W02
W01
AK15
AL15
AN14
AP14
AM11
AN11
AL14
AM14
AN13
AP13
AK11
AL11
AJ12
AK12
SGMII0RxClk
SGMII0RxD
Ethernet SGMII 0
68
SGMII0RxD
SGMII0TxD
SGMII0TxD
SGMII1RxClk
SGMII1RxClk
SGMII1RxD
SGMII1RxD
Ethernet SGMII 1
68
SGMII1TxD
SGMII1TxD
SGMIITxClk
SGMIITxClk
46
AMCC Proprietary
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 23 of 26)
Signal Name
Ball
N30
Interface Group
Page
SOV
SOV
SOV
SOV
SOV
SOV
SOV
SOV
SOV
SOV
SOV
SOV
SOV
SOV
SOV
SOV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
T33
W33
Y21
AA20
AB30
AD29
AF33
AG30
AJ24
AK22
AK27
AK33
AN19
AN26
AN30
A11
Power
73
SPAGND
SPAV
Power
73
71
A12
DD
SPIClkOut[IIC1SClk]
SPIDI
K31
K32
Serial Peripheral
SPIDO[IIC1SData]
SysClk
G34
AD02
AB03
AC02
J29
SysErr
System
JTAG
72
72
72
SysReset
TCK
TDI
F34
TDO
F33
TestEn
K29
TherMonA
TherMonB
TmrClk
AM09
AL10
C11
System
System
JTAG
72
72
TMS
G32
[TrcBS0]GPIO49
[TrcBS1]GPIO50
[TrcBS2]GPIO51
H33
J34
Trace
72
H34
AMCC Proprietary
47
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 24 of 26)
Signal Name
Ball
M29
Interface Group
Page
TrcClk
[TrcES0]GPIO52
L30
L31
K33
L32
K34
L33
N29
M31
L34
M32
M34
N31
H29
G30
E31
E34
E32
D32
D34
D33
C34
C33
E34
E32
D34
D32
E32
E34
E31
D33
[TrcES1]GPIO53
Trace
72
[TrcES2]GPIO54
[TrcES3]GPIO55
[TrcES4]GPIO56
[TrcTS0]GPIO57
[TrcTS1]GPIO58
[TrcTS2]GPIO59
[TrcTS3]GPIO60
Trace
72
[TrcTS4]GPIO61
[TrcTS5]GPIO62
[TrcTS6]GPIO63
TRST
JTAG
72
70
UARTSerClk[LeakTest]
UART Peripheral
[UART0CTS]GPIO36[DMAAck3][UART3Rx]
[UART0DCD]GPIO34[UART1CTS][UART2Tx]
[UART0DSR]GPIO35[UART1RTS][UART2Rx]
[UART0DTR]GPIO38[UART1Tx][IRQ5]
[UART0RI]GPIO39[UART1Rx][IRQ6]
[UART0RTS]GPIO37[EOT3/TC3][UART3Tx]
UART0Rx
UART Peripheral
70
UART0Tx
[UART1CTS][UART0DCD]GPIO34[UART2Tx]
[UART1RTS][UART0DSR]GPIO35[UART2Rx]
[UART1Rx][UART0RI]GPIO39[IRQ6]
[UART1Tx][UART0DTR]GPIO38[IRQ5]
[UART2Rx][UART0DSR]GPIO35[UART1RTS]
[UART2Tx][UART0DCD]GPIO34[UART1CTS]
[UART3Rx][UART0CTS]GPIO36[DMAAck3]
[UART3Tx][UART0RTS]GPIO37[EOT3/TC3]
UART Peripheral
70
48
AMCC Proprietary
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 25 of 26)
Signal Name
Ball
AF06
Interface Group
Page
USB2DClk
USB 2.0
70
[USB2DD0]GPIO08
[USB2DD1]GPIO09
[USB2DD2]GPIO10
[USB2DD3]GPIO11
[USB2DD4]GPIO12
[USB2DD5]GPIO13
[USB2DD6]GPIO14
[USB2DD7]GPIO15
[USB2DDir]GPIO21
[USB2DNext]GPIO20
[USB2DStop]GPIO19
USB2HClk
AH04
AJ05
AG06
AJ02
AJ04
AH03
AJ01
AH01
AD04
AG03
AF03
AC06
AE06
AG01
AD05
AE04
AF01
AE02
AE01
AB05
AD03
AG04
AG02
AF04
USB 2.0
70
USB 2.0
70
71
USB 2.0 Host
USB2HClk48
[USB2HD0]GPIO00
[USB2HD1]GPIO01
[USB2HD2]GPIO02
[USB2HD3]GPIO03
[USB2HD4]GPIO04
[USB2HD5]GPIO05
[USB2HD6]GPIO06
[USB2HD7]GPIO07
[USB2HDir]GPIO18
[USB2HNext]GPIO17
[USB2HStop]GPIO16
USB 2.0 Host
71
USB 2.0 Host
71
AMCC Proprietary
49
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 5. Signals Listed Alphabetically (Part 26 of 26)
Signal Name
Ball
F14
Interface Group
Page
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
F15
F17
F18
F20
F21
P17
P18
P29
R17
R18
R29
U14
U15
U20
U21
U29
V14
V15
Power
73
V20
V21
V29
Y06
Y17
Y18
Y29
AA06
AA17
AA18
AA29
AB06
AJ14
AJ15
AJ17
AJ18
AJ20
AJ21
AP32
WE
DDR2/1 SDRAM
66
50
Downloaded from DatasheetLib.com - datasheet search engine
AMCC Proprietary
Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Signals in Ball Assignment Order
In the following table, only the default signal name is shown for each ball. Multiplexed or multifunction signals are
marked with an asterisk (*). To determine what other signals or functions can be programmed to those balls, look
up the default signal name in Table 5 on page 25.
AMCC Proprietary
51
Downloaded from DatasheetLib.com - datasheet search engine
Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 6. Signals Listed by Ball Assignment (Part 1 of 9)
Ball
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
Signal Name
Ball
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
Signal Name
Ball
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
Signal Name
Ball
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
Signal Name
PCI0IDSel
GND
GND
GND
GND
GND
GND
GND
GND
GND
PCI0AD20
PCI0AD23
GND
PCI0AD17
PCI0AD16
PCI0DevSel
PCI0AD14
PCI0AD09
PCI0AD07
PCI0AD03
SPAGND
PCI0AD19
PCI0IRdy
PCI0C/BE2
PCI0Stop
PCI0C/BE1
PCI0AD12
PCI0C/BE0
PCI0AD04
TmrClk
OV
DD
PCI0AD18
PCI0TRdy
PCI0Par
PCI0PErr
GND
PCI0AD11
PCI0AD13
PCI0AD08
PCI0AD06
PCI0AD00
GPIO27 *
PerErr
OV
DD
PCI0AD02
HISRRst
GND
SPAV
GPIO40 *
PerData31
PerData25
PerData21
GND
DD
PerData29
GPIO32 *
PerData18
GPIO31 *
Reserved
PerData15
PerData12
GPIO30 *
PerData02
GPIO43 *
PerWBE1
GPIO24 *
GPIO26 *
PerAddr28
PerAddr26
PerAddr21
PerAddr16
PerAddr12
PerAddr13
PerAddr08
GND
PerData30
PerData28
PerData19
PerData27
PerData23
PerData22
PerData16
PerData06
PerData09
PerData04
GPIO45 *
PerWBE2
PerR/W
OV
DD
PerData17
PerData14
PerReady
PerData13
PerData11
PerData05
PerData00
PerWBE3
PerWBE0
GPIO22 *
PerAddr29
PerAddr27
PerAddr20
PerAddr18
PerAddr15
PerAddr10
GPIO47 *
GND
OV
DD
PerData07
PerData01
GPIO41 *
GND
GPIO23 *
PerAddr30
PerAddr31
GPIO42 *
PerAddr22
PerAddr25
PerAddr17
PerAddr14
GPIO48 *
GND
OV
DD
PerAddr24
GND
PerAddr19
OV
DD
PerAddr11
GPIO46 *
GND
GPIO38 *
GPIO37 *
GPIO39 *
UART0Tx
UART0Rx
GND
GND
52
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AMCC Proprietary
Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 6. Signals Listed by Ball Assignment (Part 2 of 9)
Ball
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
Signal Name
PCI0AD24
OV
Ball
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
Signal Name
Ball
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
Signal Name
PCI0Gnt2
Ball
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
Signal Name
PCI0AD30
GND
PCI0AD28
PCI0C/BE3
PCI0AD21
PCI0AD31
GND
GND
PCI0Req1
PCI0Gnt3
PCI0Gnt1
DD
PCI0AD22
PCI0AD25
GND
PCI0Gnt0/Req
PCI0AD27
PCI0AD26
No ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No ball
UARTSerClk
GND
OV
DD
PCI0Frame
PCI0SErr
PCI0AD29
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
TRST
No ball
OV
DD
PCI0AD15
PCI0AD10
PCI0AD05
PCI0M66En
GND
PCI0AD01
GPIO28 *
OV
DD
GPIO29 *
GPIO33 *
OV
DD
PerData26
PerData20
PerData24
FSOURCE0
PerData10
PerData08
PerData03
GPIO44 *
V
DD
V
DD
GND
V
DD
V
DD
GND
V
DD
V
DD
OV
ExtReset
PerClk
DD
GND
PerCS0
GND
OV
DD
PerBLast
GPIO25 *
PerAddr23
No ball
GND
PerOE
OV
DD
GND
PerAddr09
GND
GND
OV
DD
GPIO36 *
GPIO35 *
GND
IIC0SData
Halt
GND
TMS
OV
DD
TDO
GND
GPIO49 *
GPIO51 *
GPIO34 *
TDI
SPIDO *
AMCC Proprietary
Downloaded from DatasheetLib.com - datasheet search engine
53
Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 6. Signals Listed by Ball Assignment (Part 3 of 9)
Ball
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
Signal Name
Ball
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
Signal Name
Ball
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
Signal Name
AGND
Ball
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
M31
M32
M33
M34
Signal Name
PCIE1Tx0
GND
OV
PCI0Clk
GND
AGND
PCIE1Tx0
DD
GND
PCI0Reset
PCI0Req2
GND
AV
DD
AV
DD
PCI0Int
PCI0Req3
PCI0Req0/Gnt
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
TCK
PCIE1Rx0
PCIE1Rx0
AGND
AV
DD
GND
AV
DD
AGND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
TestEn
GND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
TrcClk
OV
DD
GND
GPIO52 *
GPIO53 *
GPIO55 *
GPIO57 *
GPIO60 *
GND
IIC0SClk
GND
SPIClkOut *
SPIDI *
GPIO54 *
GPIO56 *
GPIO59 *
GPIO61 *
GND
OV
DD
GPIO50 *
GPIO62 *
54
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AMCC Proprietary
Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 6. Signals Listed by Ball Assignment (Part 4 of 9)
Ball
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
N31
N32
N33
N34
Signal Name
Ball
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
Signal Name
Ball
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
Signal Name
AGND
Ball
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
Signal Name
PCIE1Tx2
PCIE1Tx1
PCIE1CalRN
PCIE1Tx1
PCIE1CalRP
AGND
AGND
PCIE1Tx2
AV
DD
PCIE1RefClk
PCIE1RefClk
PCIE1AVReg
AGND
AV
DD
PCIE1Rx1
PCIE1Rx1
AGND
PCIE1Rx2
PCIE1Rx2
AV
DD
AV
DD
AGND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
GND
PAV
DD
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
GPIO58 *
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
GND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
OV
DD
OV
DD
GND
GND
GND
GND
GND
V
V
GND
DD
DD
V
V
GND
DD
DD
GND
GND
GND
GND
OV
DD
GND
GND
OV
DD
GND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
MEMVRef2B
GND
V
V
DD
DD
SOV
DD
MemData00
DM0
MemData03
MemData07
MemData02
MemData12
MemData08
GPIO63 *
MemData13
MemData11
MemData05
MemData04
MemData01
DQS0
DQS0
SOV
DD
MemData06
MemData09
AMCC Proprietary
Downloaded from DatasheetLib.com - datasheet search engine
55
Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 6. Signals Listed by Ball Assignment (Part 5 of 9)
Ball
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
Signal Name
Ball
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
Signal Name
Ball
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
W31
W32
W33
W34
Signal Name
PCIE0Tx0
Ball
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Signal Name
AGND
PCIE1Tx3
AGND
AV
AV
PCIE1Tx3
PCIE0Tx0
AV
DD
DD
AV
DD
AV
DD
AGND
DD
AGND
AGND
PCIE1Rx3
PCIE1Rx3
PCIE0RX0
PCIE0RX0
AV
DD
AGND
AV
DD
AV
DD
AV
DD
V
DD
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
GND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
E1OV
V
V
DD
DD
DD
V
V
GND
GND
GND
DD
DD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DD
GND
V
DD
GND
GND
GND
SOV
V
V
GND
DD
DD
V
V
GND
DD
DD
DD
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
GND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
V
V
V
DD
DD
DD
DM1
DM2
MemData19
DQS2
DQS2
MemData27
MemData29
MemData18
MemData23
MemData22
DQS1
MemData17
MemData16
MemData20
MemData10
DQS1
MemData14
MemData15
SOV
DD
MemData21
56
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AMCC Proprietary
Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 6. Signals Listed by Ball Assignment (Part 6 of 9)
Ball
AA01
AA02
AA03
AA04
AA05
AA06
AA07
AA08
AA09
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
Signal Name
Ball
AB01
AB02
AB03
AB04
AB05
AB06
AB07
AB08
AB09
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
Signal Name
Ball
AC01
AC02
AC03
AC04
AC05
AC06
AC07
AC08
AC09
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
Signal Name
Ball
AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
Signal Name
PCIE0AVReg
PCIE0CalRP
GND
GND
PCIE0RefClk
PCIE0RefClk
AGND
PCIE0CalRN
SysErr
SysReset
GND
SysClk
GPIO07 *
GPIO21 *
GPIO01 *
AV
DD
GND
PAV
DD
GPIO06 *
GND
V
V
USB2HClk
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
MemAddr13
ECC1
E1OV
DD
DD
DD
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
GND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
MemVRef1B
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
E1OV
DD
GND
V
DD
V
DD
GND
SOV
DD
GND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
V
SOV
DD
DD
DQS3
SOV
DD
ECC7
ECC6
DQS8
DQS8
DM8
DQS3
MemData26
MemData31
MemData30
DM3
ECC0
MemData25
MemData24
MemData28
ECC5
GND
ECC4
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 6. Signals Listed by Ball Assignment (Part 7 of 9)
Ball
AE01
AE02
AE03
AE04
AE05
AE06
AE07
AE08
AE09
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
Signal Name
Ball
AF01
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
Signal Name
Ball
Signal Name
GPIO00 *
Ball
AH01
AH02
AH03
AH04
AH05
AH06
AH07
AH08
AH09
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
AH34
Signal Name
GPIO15 *
GPIO05 *
GPIO03 *
AG01
AG02
AG03
AG04
AG05
AG06
AG07
AG08
AG09
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AG31
AG32
AG33
AG34
GPIO04 *
GND
E1OV
DD
GPIO17 *
GPIO20 *
GPIO18 *
GND
GPIO19 *
GPIO16 *
GND
GPIO13 *
GPIO08 *
GMC0TxD6
No ball
GPIO02 *
GND
E1OV
DD
USB2HClk48
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
ClkEn0
GND
USB2DClk
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
GND
GPIO10 *
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
GND
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No ball
GND
SOV
DD
MemAddr04
MemAddr05
MemAddr06
GND
ClkEn3
ECC2
MemAddr11
MemAddr14
MemAddr07
MemAddr09
MemAddr10
MemAddr12
ClkEn2
ECC3
SOV
DD
ClkEn1
MemAddr08
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Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 6. Signals Listed by Ball Assignment (Part 8 of 9)
Ball
AJ01
AJ02
AJ03
AJ04
AJ05
AJ06
AJ07
AJ08
AJ09
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
Signal Name
Ball
AK01
AK02
AK03
AK04
AK05
AK06
AK07
AK08
AK09
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
Signal Name
Ball
AL01
AL02
AL03
AL04
AL05
AL06
AL07
AL08
AL09
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
Signal Name
GMC0TxD3
Ball
Signal Name
GMC0TxD5
GPIO14 *
GMCMDIO *
AM01
AM02
AM03
AM04
AM05
AM06
AM07
AM08
AM09
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AM34
GPIO11 *
GMCMDClk *
GPIO12 *
GPIO09 *
GND
E1OV
DD
GMC0TxD2
GMC0TxD7
GND
GMC0TxD0
GND
GMC0TxD4
GMC0TxD1
GND
GND
GND
GMC0TxEn
GND
GND
GMC0RxDV
GMC0CrS
GMC0RxD5
GMC0RxD0
TherMonB
SGMII1TxD
Reserved
Reserved
SGMII1RxClk
SGMII0RxClk
MemData58
DQS7
No ball
GND
GMC0RxClk
GMC0RxD6
TherMonA
GND
GMC0TxER
GMC0RxD3
GMC0RxER
E1OV
DD
GMC0RxD1
GND
E1OV
DD
SGMII1TxD
SGMIITxClk
SGMII0TxD
Reserved
Reserved
SGMII1RxClk
Reserved
MemData62
DM7
SGMIITxClk
GND
E2OV
GND
DD
V
DD
V
SGMII0RxClk
MemData63
DQS7
DD
GND
V
DD
V
MemData60
GND
MemData50
DQS6
MemData51
DQS6
DD
MemVRef1A
V
MemData52
MemData34
MemData48
MemData47
GND
MemData49
MemData42
DQS5
DD
V
DD
MemVRef2A
GND
SOV
DD
MemData44
GND
MemData40
MemData38
GND
MemData41
MemData39
DM4
SOV
DD
GND
GND
GND
MemData37
MemData36
MemODT3
BankSel0
CAS
MemData32
MemODT1
MemODT2
BankSel2
GND
GND
SOV
DD
No ball
GND
GND
GND
GND
GND
GND
GND
MemClkOut1
MemClkOut1
GND
BA2
MemAddr02
MemAddr01
MemAddr03
GND
GND
SOV
DD
GND
MemDCFdbkD
MemDCFdbkR
MemAddr00
GND
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 6. Signals Listed by Ball Assignment (Part 9 of 9)
Ball
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
Signal Name
Ball
AP01
AP02
AP03
AP04
AP05
AP06
AP07
AP08
AP09
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
Signal Name
Ball
Signal Name
Ball
Signal Name
GND
GND
GND
GND
GND
GND
GND
GMC0TxClk
E1OV
DD
GMC0CD
GND
GMC0GTxClk
GND
GMC0RxD7
GMC0RxD2
GMCRefClk
Reserved
EAVDD
GMC0RxD4
E1OV
DD
Reserved
SGMII0TxD
GND
EAGND
SGMII1RxD
SGMII0RxD
Reserved
SGMII1RxD
SGMII0RxD
MemData59
GND
E2OV
DD
MemData57
MemData61
GND
MemData56
MemData55
MemData54
MemData53
MemData46
DM5
SOV
DM6
DD
MemData43
DQS5
GND
MemData35
DQS4
MemData45
DQS4
SOV
DD
MemData33
MemClkOut0
MemODT0
BankSel1
RAS
MemClkOut0
GND
BankSel3
SOV
DD
GND
BA0
BA1
WE
GND
GND
GND
GND
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Signal Descriptions
The PPC460EX embedded controller is packaged in a 728-ball thermally enhanced plastic ball grid array (TE-
PBGA). The following tables describe the package level pin-out.
Table 7. Pin Summary
Group
No. of Pins
Total Signal Pins
430
V
37
DD
OV
23
16
10
2
DD
SOV
DD
E1OV
DD
E2OV
DD
GND
160
2
PAV
DD
AV
18
17
1
DD
AGND
EAV
DD
EAGND
1
SPAV
1
DD
SPAGND
Total Power Pins
Reserved
1
289
9
Total Pins
728
In the table Table 9 on page 64, each I/O signal is listed along with a short description of its function. Active-low
signals (for example, RAS) are marked with an overline. Please see Table 5 on page 25 for the pin (ball) number to
which each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in the following table are not accompanied by signal names that might share the same pin.
If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in Table 5 on
page 25. It is expected that in any single application a particular pin will always be programmed to serve the same
function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be
possible.
Note: Signals multiplexed with GPIO default to GPIO receivers and float after reset. Initialization software must
configure the GPIO registers for the desired function as described in the GPIO section of the user’s manual. Any of
these signals requiring a particular state prior to running initialization code must be terminated with pull-ups or
pull-downs.
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Multipurpose Signals
In addition to multiplexing, some pins such as those carrying the EOTx/TCx signals are also multipurpose. Control
of which function a multipurpose pin has is determined by direction, register settings, and so on. Both functions are
shown separated by a slash (/).
Multimode Signals
In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin
has multiple signal names assigned to distinguish different modes of operation, all of the names are shown
separated by a comma.
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 102). Note that
these are not multiplexed pins since the function of the pins is not programmable.
Reserved Pins
The balls marked Reserved on this chip are not functional. However, some of the reserved balls cannot be left
unconnected. Connect the balls shown in the following table as indicated:
Table 8. Non-Functional Ball Connections
Ball
Connection
1kΩ to GND
1kΩ to GND
AM15
AN15
Unused Interfaces
The following describes how to terminate the PCI, PCI Express, SATA, and GPIO signals that might not be used.
PCI:
When the PCI bridge is unused, configure the PCI controller to park on the bus by pulling the PCIReq0/GNT signal
low. Parking forces the PLB4 to PCI bridge to actively drive PCI0AD0:31 and PCI0C0:3/BE0:3 greatly reducing the
number of termination resistors required. The remaining PCI control signals must be terminated as follows:
• Disable the internal PCI arbiter. (See the Bootstrap Operation chapter in the user’s manual. Boot Options A-F
automatically disable the PCI Arbiter.)
• PCI0SErr - Pull up through a 3kΩ resistor to +3.3V
• PCI0TRDY - Pull up through a 3kΩ resistor to +3.3V
• PCI0Stop - Pull up through a 3kΩ resistor to +3.3V.
• PCI0Req0/Gnt - Pull down through a 1kΩ resistor to GND.
• PCI0Req1:3 - Individually pull up each signal through 3kΩ resistors to +3.3V.
• PCI0Clk - Requires a clock. The frequency must be between 1MHz and 66MHz.
PCI-E/SATA:
When the PCI Express 0/SATA interface is unused, terminate as follows:
• PCIE0AVReg[SATA0AVReg] - Leave unconnected.
• PCIE0CalRN[SATA0CalRN] - Leave unconnected.
• PCIE0CalRP[SATA0CalRP] - Leave unconnected.
• PCIE0RefClk[SATA0RefClk] - Pull down through a 1kΩ resistor to GND.
• PCIE0RefClk[SATA0RefClk] - Pull down through a 1kΩ resistor to GND.
• PCIE0Rx0[SATA0Rx0] - Pull down through a 1kΩ resistor to GND.
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
• PCIE0Rx0[SATA0Rx0] - Pull down through a 1kΩ resistor to GND.
• PCIE0Tx0[SATA0Tx0] - Leave unconnected.
• PCIE0Tx0[SATA0Tx0] - Leave unconnected.
When the PCI Express 1 interface is unused terminate as follows:
• PCIE1AVReg - Leave unconnected.
• PCIE1CalRN - Leave unconnected.
• PCIE1CalRP - Leave unconnected.
• PCIE1RefClk - Pull-down through a 1kΩ resistor to GND.
• PCIE1RefClk - Pull-down through a 1kΩ resistor to GND.
• PCIE1Rx0:3 - Individually pull-down each signal through a 1kΩ resistor to GND.
• PCIE1Rx0:3 - Individually pull-down each signal through a 1kΩ resistor to GND.
• PCIE1Tx0:3 - Leave unconnected.
• PCIE1Tx0:3 - Leave unconnected.
Signals Multiplexed with GPIO:
By default after reset, signals shared with GPIO pins are configured as GPIO receivers. Termination however, is
not needed if the GPIO during initialization are configured as outputs. To configure as drivers, set and clear the
appropriate bits in the GPIOn_ODR, GPIOn_TCR and GPIOn_OR registers as described in the GPIO chapter of
the user’s manual.
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 9. Signal Functional Description (Part 1 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
PCI Interface
Description
I/O
Type
Notes
PCIAD00:31
Address/Data bus (bidirectional).
I/O
I/O
3.3V PCI
3.3V PCI
PCIC0:3/BE0:3
PCI Command/Byte Enables.
Provides timing to the PCI interface for PCI transactions.
PCI0Clk
I
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
1
4
4
4
4
4
4
4
Note: A clock is required even when the PCI interface is not
used. The frequency must be between 1MHz and 66MHz.
Indicates the driving device has decoded its address as the
target of the current access.
PCI0DevSel
PCI0Frame
PCI0IRdy
PCI0TRdy
PCI0Stop
PCI0PErr
PCI0SErr
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.)
Driven by the current master to indicate beginning and duration
of an access.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.)
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.)
Indicates the target agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.)
Indicates the current target is requesting the master to stop the
current transaction.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.)
Reports data parity errors during all PCI transactions except a
Special Cycle.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.)
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.)
Indicates to the PCI arbiter that the specified agent wishes to use
the bus. When the internal arbiter is enabled, input is Req0.
When internal arbiter is disabled, input is Gnt.
PCI0Req0/Gnt
I
3.3V PCI
2
2
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.)
An indication to the PCI arbiter that the specified agent wishes to
use the bus. Used only when internal PCI arbiter enabled.
PCI0Req1:3
I
3.3V PCI
3.3V PCI
Indicates that the specified agent is granted access to the bus.
When the internal arbiter is enabled, output is Gnt0. When the
internal arbiter is disabled, output is Req.
PCI0Gnt0/Req
O
Indicates that the specified agent is granted access to the bus.
Used only when internal PCI arbiter enabled.
PCI0Gnt1:3
PCI0IDSel
O
I
3.3V PCI
3.3V PCI
Used as a chip select during configuration read and write
transactions.
5
5
PCI0INT
Level sensitive PCI interrupt.
O
I
3.3V PCI
3.3V PCI
3.3V PCI
PCI0M66En
PCI0Par
Capable of 66MHz operation.
Even parity across PCIAD00:31 and PCIC0:3/BE0:3 buses.
I/O
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 9. Signal Functional Description (Part 2 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
PCI0Reset
Description
I/O
Type
Notes
Brings PCI device registers and logic to a consistent state.
O
3.3V PCI
PCI Express Interface (n = 0 and 1)
Reference Clock: 100MHz differential pair.
PCIEnRefClk
PCIEnRefClk
2.5V LVDS
Rcvr w/term
I
Note: AC coupling required. See “PCI-E and SATA Reference
Clock AC Coupling Recommendations” on page 100.
Analog obvservation point for manufacturing test of internal
voltage regulator.
PCIEnAVReg
na
na
Analog
Analog
Note: For normal operation, do not terminate.
PCIEnCalRN
PCIEnCalRP
Connect a 1.37kΩ ± 1% external calibration resistor between
these two pins.
Differential receive signal pairs.
PCIE0 is a single-channel (Rx0 only) interface.
PCIE1 is a four-channel (Rx0:3) interface.
Lane 0 is the LSB.
PCIEnRx0:3
PCIEnRx0:3
2.5V LVDS
Rcvr w/term
I
Differential transmit signal pairs.
PCIE0 is a single-channel (Tx0 only) interface.
PCIE1 is a four-channel (Tx0:3) interface.
Lane 0 is theLSB.
PCIEnTx0:3
PCIEnTx0:3
2.5V LVDS
Drvr w/term
O
Note: AC couple only.
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 9. Signal Functional Description (Part 3 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
Description
I/O
Type
Notes
DDR2/1 SDRAM Interface
2.5V (1.8V)
SSTL2 Dr/Rcv
BA0:2
Bank Address supporting up to eight internal banks.
Selects up to four external DDR SDRAM banks (a.k.a. ranks).
Column Address Strobe.
O
O
O
O
O
2.5V (1.8V)
SSTL2 Dr/Rcv
BankSel0:3
CAS
2.5V (1.8V)
SSTL2 Dr/Rcv
2.5V (1.8V)
SSTL2 Dr/Rcv
ClkEn0:3
Clock Enable.
DM0:7
DM8
Memory write data byte lane masks. DM8 is the byte lane mask
for the ECC byte lane.
2.5V (1.8V)
SSTL2 Dr/Rcv
DQS0:7
DQS0:7
Differential byte lane data strobe.
2.5V (1.8V)
SSTL2 Diff
Dr/Rcv
I/O
DQS8
DQS8
Differential byte lane data strobe for ECC.
2.5V (1.8V)
SSTL2 Dr/Rcv
ECC0:7
ECC check bits 0:7.
I/O
O
Memory address bus.
2.5V (1.8V)
SSTL2 Dr/Rcv
MemAddr00:14
MemData00:63
MemAddr14 is the most significant bit (msb).
Memory data bus (MemData32:63 available for DDR2 only).
MemData00 is the most significant bit (msb).
2.5V (1.8V)
SSTL2 Dr/Rcv
I/O
2.5V (1.8V)
SSTL2 Dr/Rcv
Diff Driver
MemClkOut0:1
MemClkOut0:1
Subsystem clock outputs.
O
2.5V (1.8V)
SSTL2 Dr/Rcv
MemODT0:3
RAS
DDR2 On-die termination enable (not used with DDR1).
Row Address Strobe.
O
O
O
I
2.5V (1.8V)
SSTL2 Dr/Rcv
2.5V (1.8V)
SSTL2 Dr/Rcv
WE
Write Enable.
Volt ref receiver
(1.25V or 0.9V)
MemVRef1A:B
MemVRef2A:B
Memory voltage reference 1, A and B input.
Volt ref driver
(1.25V or 0.9V)
Memory voltage reference 2, A and B input.
Feedback driver for I/O timing measurements.
I
2.5V (1.8V)
SSTL2 Dr/Rcv
Note: Connect directly to MemDCFdbkR. Use the shortest trace
length possible. Do not include series termination or parallel
termination to Vtt.
MemDCFdbkD
O
2.5V (1.8V)
SSTL2 Dr/Rcv
MemDCFdbkR
HISRRst
Feedback receiver. Connect externally to MemDCFdbkD.
SDRAM hardware initiated self-refresh reset control.
I
I
3.3V LVTTL
1, 2
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Preliminary Data Sheet
Table 9. Signal Functional Description (Part 4 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
Description
I/O
Type
Notes
Ethernet 0 Interface
3.3V tolerant
2.5V CMOS
GMCMDClk
GMCMDIO
GMCRefClk
GMII, MII, RGMII: Management data clock.
O
I/O
I
GMII, MII, RGMII: Transfer command and status information
between MII and PHY.
3.3V tolerant
2.5V CMOS
GMII, SGMII, RGMII: 125MHz reference clock for
10/100/1000Mbps.
3.3V tolerant
2.5V CMOS
1, 5
1, 5
GMC0GTxClk,
GMC0TxClk
GMII 0: Transmit clock for 1000Mbps.
RGMII 0: Transmit clock for 1000Mbps.
3.3V tolerant
2.5V CMOS
O
I
3.3V tolerant
2.5V CMOS
GMC0TxClk
GMII/MII 0: Transmit clock for 10/100Mbps.
GMC0TxD1:0,
GMC0TxD1:0
GMII/MII 0: Transmit data.
RGMII 0: Transmit data.
3.3V tolerant
2.5V CMOS
O
O
O
O
O
I
GMC0TxD3:2,
GMC0TxD3:2
GMII/MII 0: Transmit data.
RGMII 0: Transmit data.
3.3V tolerant
2.5V CMOS
GMC0TxD7:4,
GMC1TxD3:0
GMII 0: Transmit data.
RGMII 1: Transmit data.
3.3V tolerant
2.5V CMOS
GMC0TxEn,
GMC0TxCtl
GMII/MII 0: Transmit enable.
RGMII 0: Transmit control.
3.3V tolerant
2.5V CMOS
GMC0TxEr,
GMC1TxCtl
GMII/MII 0: Transmit error.
RGMII 1: Transmit control.
3.3V tolerant
2.5V CMOS
GMC0CD,
GMC1RxClk
GMII/MII 0: Collision detection.
RGMII 1: Receive clock.
3.3V tolerant
2.5V CMOS
1, 5
GMC0CrS,
GMC1GTxClk
GMII/MII 0: Carrier sense.
RGMII 1: Transmit clock for 1000 Mbps.
3.3V tolerant
2.5V CMOS
I/O
I
GMC0RxClk,
GMC0RxClk
GMII/MII 0: Receive clock.
RGMII 0: Receive clock.
3.3V tolerant
2.5V CMOS
1, 5
5
GMC0RxD1:0,
GMC0RxD1:0
GMII/MII 0: Receive data.
RGMII 0: Receive data.
3.3V tolerant
2.5V CMOS
I
GMC0RxD3:2,
GMC0RxD3:2
GMII/MII 0: Receive data.
RGMII 0: Receive data.
3.3V tolerant
2.5V CMOS
I
5
GMC0RxD7:4,
GMC1RxD3:0
GMII/MII 0: Receive data.
RGMII 1: Receive data.
3.3V tolerant
2.5V CMOS
I
5
GMC0RxDV,
GMC0RxCtl
GMII/MII 0: Receive data valid.
RGMII 0: Receive control.
3.3V tolerant
2.5V CMOS
I
5
GMC0RxEr,
GMC1RxCtl
GMII/MII 0: Receive error.
RGMII 1: Receive control.
3.3V tolerant
2.5V CMOS
I
5
AMCC Proprietary
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 9. Signal Functional Description (Part 5 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
Description
I/O
Type
Notes
Ethernet SGMII Gigabit Interface
SGMIITxClk
SGMIITxClk
1.8V LVDS
Drvr w/term
Differential transmit clock: Common 625MHz to PHYs.
O
I
Differential receive clock: 625MHz from PHY. The differential
receiver clock is required for SGMII. Clock recovery from the
differential SGMII0:2RxD signals is not supported.
SGMII0:1RxClk
SGMII0:1RxClk
1.8V LVDS
Rcvr w/term
SGMII0:1RxD
SGMII0:1RxD
1.8V LVDS
Rcvr w/term
Differential receive data.
Differential transmit data.
I
SGMII0:1TxD
SGMII0:1TxD
1.8V LVDS
Drvr w/term
O
SATA Interface
Reference Clock: 100 MHz differential clock pair.
SATA0RefClk
SATA0RefClk
2.5V LVDS
Rcvr w/term
I
Note: AC coupling required. See “PCI-E and SATA Reference
Clock AC Coupling Recommendations” on page 100.
SATA0Rx0
SATA0Rx0
Data Receive differential signals.
2.5V LVDS
Rcvr w/term
I
Note: Must be AC coupled.
SATA0Tx0
SATA0Tx0
Data Transmit differential signals.
2.5V LVDS
Drvr w/term
O
Note: Must be AC coupled.
Analog obvservation point for manufacturing test of internal
voltage regulator.
SATA0AVReg
na
na
Analog
Analog
Note: For normal operation, do not terminate.
SATA0CalRP
SATA0CalRN
Connect a 1.37kΩ ± 1% external calibration resistor between
these two pins.
68
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 9. Signal Functional Description (Part 6 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
DMA Interface
Description
I/O
Type
Notes
External peripheral DMA acknowledge.
DMAAck0:3
DMAReq0:3
O
3.3V LVTTL
Used by the PPC460EX to indicate that data transfers have
occurred.
External peripheral DMA request.
I
3.3V LVTTL
3.3V LVTTL
5
5
Used by slave peripherals to indicate they are prepared to
transfer data.
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
External Peripheral Interface
Peripheral address bus used by the PPC460EX.
PerAddr05:31
I/O
3.3V LVTTL
PerAddr05 is the most significant bit (msb) on this bus.
Peripheral data bus used by the PPC460EX.
PerData00:31
PerPar0:3
I/O
I/O
3.3V LVTTL
3.3V LVTTL
PerData00 is the most significant bit (msb) on this bus.
Peripheral data bus parity used by the PPC460EX.
Last burst transfer.
PerBLast
PerCS0:5
I/O
O
3.3V LVTTL
3.3V LVTTL
Used by either the peripheral controller or DMA controller to
indicates the last transfer of a memory access.
External peripheral device select.
Output enable.
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC460EX is the
bus master, it enables the selected device to drive the bus.
PerOE
O
I
3.3V LVTTL
3.3V LVTTL
Rcvr
PerReady
Used by a peripheral slave to indicate it is ready to transfer data.
1, 2
Read/Write.
Used by the PPC460EX as an output by either the peripheral
controller or DMA controller depending upon the type of transfer
involved. High indicates a read from memory, low indicates a
write to memory.
PerR/W
I/O
3.3V LVTTL
3.3V LVTTL
PerWBE0:3
PerErr
External peripheral data bus byte enables.
I/O
I
External Error. Used as an input to record external slave
peripheral errors.
3.3V LVTTL
Rcvr
1, 5
Peripheral Reset. Used by synchronous peripheral slaves.
ExtReset
PerClk
O
O
3.3V LVTTL
3.3V LVTTL
Note: The state of any external signals or clocks cannot be
guaranteed until the ExtReset signal has been de-asserted.
Peripheral Clock. Used by synchronous peripheral slaves.
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Preliminary Data Sheet
Table 9. Signal Functional Description (Part 7 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
Description
I/O
Type
Notes
UART Peripheral Interface
The UART interface can be configured as follows:
1. One 8-pin, where n = 0
2. Two 4-pin, where n = 0 & 1
3. Four 2-pin, where n = 0 & 1 & 2 & 3
This input provides an alternative to the internally generated
serial clock. It is used in cases where the allowable internally
generated clock rates are not satisfactory.
3.3V LVTTL
w/pull-up
UARTSerClk
I
1
UARTnRx
Receive data.
I
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
UARTnTx
Transmit data.
UARTnDCD
UARTnDSR
UARTnCTS
UARTnDTR
UARTnRTS
UARTnRI
Data Carrier Detect.
Data Set Ready.
Clear To Send.
6
6
6
I
I
Data Terminal Ready.
Request To Send.
Ring Indicator.
O
O
I
IIC Peripheral Interface (n = 0 and 1)
IICnSClk
IIC0 Serial Clock.
IIC0 Serial Data.
I/O
I/O
3.3V LVTTL
3.3V LVTTL
1, 2
2
IICnSData
USB 2.0 OTG (Device or Host) Interface
3.3V tolerant
2.5V CMOS
USB2DD7:0
USB2DDir
Bidirectional Device data bus.
I/O
I
3.3V tolerant
2.5V CMOS
Transfer direction. PHY has data to transfer.
1
1
Next transfer. Input signal from the PHY:
Receiving—ready to accept the next data transfer.
Transmitting—a new byte is ready to send.
3.3V tolerant
2.5V CMOS
USB2DNext
I
Stop transfer. Output signal to the PHY:
Receiving—stop transferring data.
3.3V tolerant
2.5V CMOS
USB2DStop
USB2DClk
O
I
Transmitting—the last byte of data has been sent.
3.3V tolerant
2.5V CMOS
USB 2.0 OTG clock—60MHz.
1, 5
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Preliminary Data Sheet
Table 9. Signal Functional Description (Part 8 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
Description
I/O
Type
Notes
USB 2.0 Host Interface
3.3V tolerant
2.5V CMOS
USB2HD7:0
USB2HDir
Bidirectional Host data bus.
I/O
I
3.3V tolerant
2.5V CMOS
Transfer direction. PHY has data to transfer.
1
Next transfer. Input signal from the PHY:
Receiving—ready to accept the next data transfer.
Transmitting—a new byte is ready to send.
3.3V tolerant
2.5V CMOS
USB2HNext
USB2HStop
I
1, 5
Stop transfer. Output signal to the PHY:
Receiving—stop transferring data.
3.3V tolerant
2.5V CMOS
O
Transmitting—the last byte of data has been sent.
3.3V tolerant
2.5V CMOS
USB2HClk
USB 2.0 Host clock—60MHz.
USB 2.0 Host clock—48MHz.
I
I
1, 5
1, 5
3.3V tolerant
2.5V CMOS
USB2HClk48
NAND Flash Interface
NFALE
Address Latch Enable.
O
O
3.3V LVTTL
3.3V LVTTL
Command Latch Enable.
NFCLE
Latches operational commands into the NAND Flash.
Ready/Busy.
NFRdyBusy
I
3.3V LVTTL
3.3V LVTTL
Indicates status of device during program erase or page read.
This signal is wire-OR connected from all NAND Flash devices.
Read Enable.
NFREn
NFWEn
O
Data is latched on the rising edge.
Write Enable.
O
O
3.3V LVTTL
3.3V LVTTL
Data is latched on the rising edge.
NFCE0:3
Chip enable.
Serial Peripheral Interface
SPIClkOut
Clock output.
Data input.
O
I
3.3V LVTTL
1
2
3.3V LVTTL
w/pull-up
SPIDI
SPIDO
Data output.
O
3.3V LVTTL
Interrupts Interface
IRQ0:15
External interrupt requests 0 through 15.
I
3.3V LVTTL
1, 5
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 9. Signal Functional Description (Part 9 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
JTAG Interface
Description
I/O
Type
Notes
3.3V LVTTL
w/pull-up
TCK
Test Clock.
I
1
3.3V LVTTL
w/pull-up
TDI
Test Data In.
I
O
I
TDO
TMS
Test Data Out.
Test Mode Select.
3.3V LVTTL
3.3V LVTTL
w/pull-up
Test Reset. During chip power-up, this signal must be low from
3.3V LVTTL
w/pull-up
TRST
the start of V ramp-up until at least 32 SysClk cycles after V
I
5
1
DD
DD
is stable in order to initialize the JTAG controller.
System Interface
3.3V tolerant
2.5V CMOS
SysClk
Main system clock input.
I
3.3V tolerant
2.5V CMOS
SysErr
Set to 1 when a machine check is generated.
O
Main system reset. External logic can drive this pin low (minimum
of 32 SysClk cycles) to initiate a system reset. A system reset
can also be initiated by software.
3.3V tolerant
2.5V CMOS
SysReset
I
1, 2
3.3V LVTTL
w/pull-up
TmrClk
Halt
Processor timer external input clock.
Halt from external debugger.
I
I
I
1
1
3.3V LVTTL
w/pull-up
Reserved, Manufacturing Test Signal
FSOURCE0
N/A
Must connect to GND (no pull-down resistor required).
Test enable.
3.3V LVTTL
w/pull-down
TestEn
I
Note: Do not connect for normal operation.
3.3V tolerant
2.5V CMOS
GPIO00:21
GPIO22:63
General purpose I/O.
General purpose I/O.
I/O
I/O
3.3V LVTTL
TherMonA
TherMonB
On-chip thermal monitor (P diffusion).
On-chip thermal monitor (N diffusion).
I
Thermal
monitor
O
Trace Interface
TrcBS0:2
Trace branch execution status.
O
O
3.3V LVTTL
3.3V LVTTL
Trace data capture clock; runs at 1/4 the frequency of the
processor.
TrcClk
Trace Execution Status is presented every fourth processor clock
cycle.
TrcES0:4
TrcTS0:6
O
O
3.3V LVTTL
3.3V LVTTL
Additional information on trace execution and branch status.
72
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Preliminary Data Sheet
Table 9. Signal Functional Description (Part 10 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
or 8.2kΩ for PCI to OV
or equivalent.
DD
DD
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
or equivalent.
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV ) or pull-down (recommended value is 1kΩ to
DD
GND) required
Signal Name
Description
I/O
Type
Notes
Other
To avoid noise pickup problems, some of these balls must be
connected in the board design as shown Table 8 on page 62.
Otherwise, do not connect voltage, ground, or any signals to
these pins.
Reserved
na
na
Power
V
+1.25V—Logic voltage.
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
DD
OV
+3.3V—I/O voltage (except DDR SDRAM, Ethernet, and USB).
+1.8V (DDR2) or +2.5V (DDR1)—I/O voltage for DDR SDRAM.
+2.5V—I/O voltage for Ethernet (except SGMII) and USB.
+1.8V—I/O Ethernet (SGMII).
DD
SOV
DD
E1OV
E2OV
GND
DD
DD
Ground for logic and I/O voltages.
AV
+1.25V—PCI-Express SerDes Analog Supply.
+2.5V—PCI-Express SerDes PLL Analog Supply.
DD
PAV
DD
AGND
EAV
Ground for AV and PAV
.
DD
DD
+2.5V—Filtered analog voltage for Ethernet PLLs.
Ground for EAV
DD
EAGND
SPAV
.
DD
+2.5V—Filtered analog voltage for system PLL.
Ground for SPAV
DD
SPAGND
.
DD
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Device Characteristics
Table 10. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Internal logic supply voltage
Symbol
Value
0 to +1.6
Unit
V
Notes
V
DD
OV
I/O supply voltage
0 to +3.6
V
DD
E1OV
Ethernet I/O and USB supply voltage
Ethernet SGMII supply voltage
DDR2 (DDR1) SDRAM I/O supply voltage
PCI-Express SerDes analog supply voltage
System PLL analog supply voltage
Ethernet PLL analog supply voltage
PCI-Express SerDes PLL analog supply voltage
Storage Temperature Range
0 to +2.7
V
DD
E2OV
0 to +1.9
V
DD
SOV
0 to +1.9 (+2.7V)
0 to +1.6
V
DD
AV
V
1
1
1
1
DD
SPAV
0 to +2.7
V
DD
EAV
0 to +2.7
V
DD
PAV
0 to +2.7
V
DD
T
−55 to +150
−40 to +120
°C
°C
STG
T
Case temperature under bias
2
C
Notes:
1. The analog voltages (AV , EAV , SPAV , and PAV ) used for the on-chip functions can be derived from the logic voltages, but
DD
DD
DD
DD
must be filtered before entering the PPC460EX. A separate filter for each analog voltage, as shown below, is recommended:
AV
AV
L – SMT ferrite bead chip, Murata BLM18AG121SN1D
DD
V
DD
DD
C – 0.1μF ceramic
L
EAV , SPAV , and PAV
DD
DD
DD
C
L – SMT ferrite bead chip, Murata BLM15AG102SN1
C – 1μF ceramic
AGND
2. This value is not a specification of the operational temperature range; it is a stress rating only.
74
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 11. Recommended DC Operating Conditions (Part 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Logic Supply Voltage
Symbol
Minimum
+1.2
Typical
+1.25
+3.3
Maximum
+1.3
Unit
V
Notes
V
4
4
4
4
4
3
3
3
3
3
1
DD
OV
I/O Supply Voltage
+3.15
+2.4
+3.45
+2.6
V
DD
E1OV
Ethernet 1 I/O Supply Voltage
+2.5
V
DD
E2OV
Ethernet 2 I/O Supply Voltage (SGMII)
DDR2 (DDR1) SDRAM I/O Supply Voltage
PCI-Express SerDes analog Supply Voltage
System PLL Analog Supply Voltage
Ethernet PLL analog supply voltage
PCI-Express SerDes PLL analog supply voltage
+1.7
+1.8
+1.9
V
DD
SOV
+1.7 (+2.4)
+1.2
+1.8 (+2.5)
+1.25
+2.5
+1.9 (+2.6)
+1.3
V
DD
AV
V
DD
SPAV
+2.4
+2.6
V
DD
EAV
+2.4
+2.5
+2.6
V
DD
PAV
+2.4
+2.5
+2.6
V
DD
SV
0.49SOV
0.50SOV
0.51SOV
DDR2 (DDR1) SDRAM Reference Voltage
Input Logic High 3.3V LVTTL and PCI
Input Logic High 2.5V CMOS, 3.3V tolerant
V
V
V
REF
DD
DD
DD
+2.0
+1.7
+3.6
+3.6
V
IH
SV
+ 0.125
REF
Input Logic High 1.8V DDR2 (2.5V DDR1)
2.2 (3.0)
V
2
1
2
1
(0.15)
Input Logic High (1.8V SGMII)
Input Logic Low 3.3V LVTTL and PCI
Input Logic Low 2.5V CMOS
+1.1
0
+2.2
+0.8
+0.7
V
V
V
0
V
IL
SV
− 0.125
REF
Input Logic Low 1.8V DDR2 (2.5V DDR1)
−0.3 (−0.3)
V
(0.18)
Input Logic Low (1.8V SGMII)
+0.3
+2.4
+2.0
+0.8
+3.6
+2.7
V
V
V
Output Logic High 3.3V LVTTL and PCI
Output Logic High 2.5V CMOS
V
OH
SOV − 0.95
DD
SOV
Output Logic High 1.8V DDR2 (2.5V DDR1)
V
DD
(+1.95)
Output Logic High (1.8V SGMII)
+1.23
+1.385
+0.961
+1.534
+0.4
V
V
V
V
V
Output Logic Low 3.3V LVTTL and PCI
Output Logic Low 2.5V CMOS
0
1
0
+0.4
V
I
OL
Output Logic Low 1.8V DDR2 (2.5V DDR1)
Output Logic Low (1.8V SGMII)
0
+0.841
0
+0.45
+1.081
0
Input Leakage Current (no pull-up or pull-down)
μA
μA
μA
IL1
IL2
IL3
I
I
Input Leakage Current for pull-down
Input Leakage Current for pull-up
0 (LPDL)
200 (MPUL)
0 (MPUL)
5
5
−150 (LPDL)
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Preliminary Data Sheet
Table 11. Recommended DC Operating Conditions (Part 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
+3.9
Unit
V
Notes
Input Max Allowable Overshoot 2.5V CMOS
Input Max Allowable Overshoot 3.3V LVTTL
Input Max Allowable Undershoot 2.5V CMOS
Input Max Allowable Undershoot 3.3V LVTTL
Output Max Allowable Overshoot 2.5V CMOS
Output Max Allowable Overshoot 3.3V LVTTL
Output Max Allowable Undershoot 2.5V CMOS
Output Max Allowable Undershoot 3.3V LVTTL
Case Temperature
V
IMAO25
V
+3.9
V
IMAO33
V
−0.6
−0.6
V
IMAU25
V
V
IMAU33
V
+3.9
+3.9
V
OMAO25
OMAO33
OMAU25
OMAU33
V
V
V
V
−0.6
−0.6
−40
V
V
T
+85
°C
6
C
Notes:
1. PCI drivers meet PCI specifications.
2. SV
= SOV /2. SOV = +1.8V for DDR2 memory or +2.5V for DDR1 memory.
DD DD
REF
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltages, but must be filtered before entering the
PPC460EX. See “Absolute Maximum Ratings” on page 74.
4. LPDL is least positive down level; MPUL is most positive up level.
5. Case temperature, T , is measured at top center of case surface with device soldered to a circuit board.
C
Table 12. 3.3V, 2.5V, and LVDS I/O Characteristics
Output Impedance
Input Capacitance
(pF)
Interfaces
I/O
(Ω)
Ethernet (MII, RGMII), SysClk, SysErr, GPIO00:21
Ethernet (SGMII)
3.3V tolerant 2.5V CMOS
1.8V LVDS
50
-
5.7
5.0
DMA, NAND Flash External Peripheral, UART, USB, Interrupt,
JTAG, TmrClk, Halt , GPIO22:63, Trace
3.3V LVTTL
50
5.2
IIC, SPI
PCI
3.3V LVTTL
3.3V
35
-
5.2
5.7
Power Supply Sequencing
All the PPC460EX I/O designs are power supply sequence independent. There is no requirement that the power
supplies power up in any particular order. The following items are power sequence considerations:
• Logic power (VDD) is applied before the I/O supply voltages: The I/Os include internal supply sequencing
circuitry which ensures the output of the receiver connected to internal chip logic is 0 until the I/O power is
applied. When the logic power is on and the I/O power supplies are off, the I/O logic connected to the
associated ball neither sinks or sources significant current unless influenced by an internal pull-up or pull-down
resistor. While the I/O supply is ramping, the state of the I/O ball is not predictable. This power sequence is not
destructive to the I/Os or internal logic and does not cause any functional problems.
• I/O power is applied before the logic power is applied: The output driver (connected the balls) comes up in an
unknown state (driving 1, driving 0, or tri-state) until the internal logic voltage is stable within normal operating
range. This power sequence is not destructive to the I/Os or internal logic and does not cause any functional
problems.
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• External voltage should not be applied to the chip I/O balls before the associated I/O power supply voltage is
applied to the chip.
• A chip power-down cycle must complete (all I/O supply voltages and VDD are below +0.4V) before a new
power-up cycle is started
• During a power-up cycle, SysReset and TRST inputs should be asserted low. SysReset and TRST should
remain asserted until SysClock is stable and at least 32 SysClock times after all power supplies are stable
within normal operating range. Failure to follow this reset sequence during the power-up cycle can result in
unpredictable operation of the chip.
Power Specifications
The following tables contain measured power numbers. The measurement conditions are listed as Notes below
each table.
Table 13. Typical DC Power Supply Requirements Using DDR2 Memory
+2.5V Supply
+1.25V Supply
+1.8V Supply
+3.3V Supply
(OV
(E1OV +EAV
+
)
Frequency (MHz)
Total
Unit
Notes
DD
DD
(V +AV
)
(SOV +E2OV
)
)
DD
DD
DD
DD
DD
SPAV +PAV
DD
DD
600
800
2.90
3.06
3.83
0.33
0.31
0.31
0.31
0.37
3.91
4.08
4.86
W
W
W
1
1
1
0.34
0.34
0.37
0.38
1000
Notes:
1. Measured at T = +85°C, using a typical process part for each speed grade, while running Linux and test applications that exercise
C
each function with representative traffic (RGMII Ethernet).
2. 600MHz, 800MHz, and 1000MHz parts use a nominal voltage of V = +1.25V, DDR2 running at 400MHz, and the PLB running at
DD
200MHz.
Table 14. Typical DC Power Supply Requirements Using DDR1 Memory
+2.5V Supply
(E1OV +EAV
+
+1.25V Supply
+1.8V Supply
(E2OV
+3.3V Supply
(OV
DD
DD
DD
Frequency (MHz)
Total
Unit
Notes
(V +AV
)
)
SPAV +PAV
)
DD
DD
DD
DD
DD
+SOV
)
DD
600
800
2.90
3.06
3.83
0.01
0.01
0.01
1.18
1.18
1.18
0.37
4.46
4.63
5.39
W
W
W
1
1
1
0.37
0.38
1000
Notes:
1. Estimated and based on a nominal voltage of V = +1.25V, T = 85°C, while running Linux and a test application that exercises each
DD
C
function with representative traffic (RGMII Ethernet).
2. 600MHz, 800MHz, and 1000 MHz parts use a maximum voltage of V = +1.30V.
DD
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Preliminary Data Sheet
Table 15. Maxiumum DC Power Supply Requirements Using DDR2 Memory
+2.5V Supply
+1.25V Supply
+1.8V Supply
+3.3V Supply
(E1OV +EAV
+
)
Frequency (MHz)
Total
Unit
Notes
DD
DD
(V +AV
)
(SOV +E2OV
)
(OV
)
DD
DD
DD
DD
DD
SPAV +PAV
DD
DD
600
800
7.35
7.66
7.87
0.39
0.34
0.34
0.34
0.83
8.91
9.22
9.45
W
W
W
1, 2
1, 2
1, 2
0.39
0.39
0.83
0.85
1000
Notes:
1. Measured at T = +85°C, using a a best-case process (worst case power) part, while running Linux and test applications that exercise
C
each function with representative traffic (RGMII Ethernet).
2. 600MHz, 800MHz, and 1000MHz parts use a nominal voltage of V = +1.30V, DDR2 running at 400MHz, and the PLB running at
DD
200MHz.
Table 16. Maxiumum DC Power Supply Requirements Using DDR1 Memory
+2.5V Supply
(E1OV +EAV
+
+
+1.25V Supply
+1.8V Supply
(E2OV
+3.3V Supply
(OV
DD
DD
Frequency (MHz)
Total
Unit
Notes
(V +AV
)
)
SPAV +PAV
)
DD
DD
DD
DD
DD
DD
SOV
)
DD
600
800
7.35
7.66
7.87
0.01
0.01
0.01
1.22
0.83
9.41
9.72
9.98
W
W
W
1, 2
1, 2
1, 2
1.22
1.25
0.83
0.85
1000
Notes:
1. Measured at T = +85°C, using a a best-case process (worst case power) part, while running Linux and test applications that exercise
C
each function with representative traffic (RGMII Ethernet).
2. 600MHz, 800MHz, and 1000MHz parts use a nominal voltage of V = +1.30V, DDR2 running at 400MHz, and the PLB running at
DD
200MHz.
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Preliminary Data Sheet
Table 17. DC Power Supply Loads
4
3, 5
Parameter
Symbol
Unit
Notes
Typical
3065
115
124
3
Maximum
I
V
(+1.25V) active operating current
6055
250
132
50
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD
DD
I
OV (+3.3V) active operating current
ODD
DD
I
E1OV (+2.5V) active operating current
E1ODD
DD
I
E2OV (+1.8V) active operating current
E2ODD
DD
2
2
I
SOV (+1.8V) DDR2 active operating current
210
376
4
300
450
5
SODD2
DD
I
SOV (+2.5V) DDR1 active operating current
SODD1
DD
1
I
AV (+1.25V) input current
1
1
1
1
ADD
DD
1
I
EAV (+2.5V) active operating current
1
2
EADD
DD
1
I
PAV (+2.5V) active operating current
1
2
UADD
DD
1
I
SPAV (+2.5V) active operating current
1
2
UADD
DD
Notes:
1. See “Absolute Maximum Ratings” on page 74 for filter recommendations.
2. SOV will be either +2.5V or +1.8V but not both.
DD
3. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many
factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case
temperature, and the power supply voltages. Your specific application can produce significantly different results. V (logic) current and
DD
power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on).
OV (I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.
DD
4. Typical current is estimated at 1.000GHz with V = +1.25V, OV = +3.3V, E1OV = +2.5V, SOV = +2.5V (DDR1) or +1.8V
DD
DD
DD
DD
(DDR2), and T = +85°C with a typical process.
C
5. Maximum current is estimated at 1.000GHz with V = +1.3V, OV = +3.45V, E1OV = +2.6V, SOV = +2.6V (DDR1) or +1.9V
DD
DD
DD
DD
(DDR2), and T = +85°C, and best-case process (which drives worst-case power).
C
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Preliminary Data Sheet
Package Thermal Specifications
Table 18. Package Thermal Specifications
Thermal resistance values for the TE-PBGA package in a convection environment are as follows:
Airflow
ft/min
(m/sec)
Parameter
Symbol
Unit
Notes
0
100
200
300
400
600
(0)
(0.51)
(1.02)
(1.53
(2.04)
(2.55)
Junction-to-ambient thermal resistance
without heat sink
θJA
θJA
13.1
10.3
11.7
7.3
10.9
6.1
10.5
5.6
10.3
5.4
10
3
Junction-to-ambient thermal resistance
with heat sink
5.1
3, 6
Resistance Value
Junction-to-case thermal resistance
θJC
θJB
3.5
°C/W
°C/W
3
3
Junction-to-board thermal resistance
7.3
Notes:
1. Case temperature, T , is measured at top center of case surface with device soldered to circuit board.
C
2. T = T − P×θ , where T is ambient temperature and P is power consumption.
A
C
CA
A
3. TCMax = TJMax − P×θ , where TJMax is maximum junction temperature (+125°C) and P is power consumption.
JC
4. The preceding equations assume that the chip is mounted on a board with at least one signal and two power planes.
5. Values in the table were achieved using a JEDEC standard board with the following characteristics: 114.5mm x 101.6mm x 1.6mm, 4
layers. The board has 100 thermal vias (same as the number of thermal balls on the TE-PBGA package).
6. Values for an attached heat sink were achieved with a 35mm x 35mm x 15mm unit (see Thermal Management below), attached with a
0.1mm thickness of adhesive having a thermal conductivity of 1.3W/mK.
Heat Sink
The following heat sink was used in the above thermal analysis:
35W x 35L x 15H (mm)
Base thickness = 1.5mm
Fin height = 13.5mm
Fin thickness = 1.0mm
Number of Fins: 11 aluminum
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Preliminary Data Sheet
Thermal Monitor
Thermal monitoring of the chip is accomplished using the PNP transistor (β ≈ 2) provided on the chip. The collector
of the transistor is connected to ground (GND). The emitter (TherMonA) and base (TherMonB) are connected to
chip pins. A voltage measurement (VBE1 and VBE2) across the TherMonA and TherMonB pins at the two current
values I1 and I2 provides the chip temperature in °K according to the equation:
T = (q/nk)(VBE2−VBE1)/ln(I2/I1) °K where q = 1.602 176 53×10-19, n = 0.99 ± 0.05, and k = 1.380 6505×10-23
.
Note: VBE2 and VBE1 should be specified in volts. I1 and I2 can be any units of measure provided they are the
same. The small values require precision measurement and current sources.
PPC460EX
C
E
TherMonA
TherMonB
I , I (Max = 300μA)
1
2
V
, V
BE1 BE2
B
Note: The bias voltage V should be between +0.5V and +0.7V.
EB
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Clocking Specifications
Preliminary Data Sheet
Table 19. Clocking Specifications
Symbol
Parameter
Min
Max
Units
Notes
SysClk Input
F
Frequency
Period
66.66
100
MHz
ns
1
C
T
10
15
C
T
Edge stability (cycle-to-cycle jitter)
–
±0.1
ns
2
3
CS
T
High time
Low time
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
CH
T
ns
CL
Note: Input rising and falling edge slew rate ≥ 1V/ns
PLL VCO
F
T
Frequency
Period
600
2000
1.66
MHz
ns
C
C
0.50
Processor (CPU) Clock
F
T
Frequency
Period
400
1000
2.5
MHz
ns
4
C
C
1.00
MemClkOut and PLB Clock
F
T
Frequency
Period
133.33
200
7.5
MHz
ns
C
C
5
T
High time
45% of nominal period
55% of nominal period
ns
CH
OPB Clock
F
T
Frequency
Period
66.66
10
100
15
MHz
ns
5
C
C
AHB Clock
F
T
Frequency
Period
66.66
5
200
15
MHz
ns
C
C
Notes:
1. SysClk supports spread spectrum clocking with a -1% down-spread and a 40 kHz or less modulation frequency. For a 66.66 MHz
minimum SysClk, the modulation frequency range 66.00 MHz to 66.66 MHz is supported.
2. The modulation frequency of the input jitter should be lower than 100 kHz (to allow the PLL to track the jitter) or higher than 20 MHz (to
allow the PLL to filter the jitter). Within the frequency range 100 kHz to 20 MHz, the cycle to cycle jitter must be +/- 100 ps or less.
3. Slew rate is measured between 0.7V and 1.7V.
4. The maximum supported processor clock frequency for any part is specified in the part number (see “Ordering and PVR Information”
on page 5).
5. In order to support a 1-Gbps Ethernet data rate, the minimum OPB clock frequency is 66.66 MHz. If the Ethernet application is limited
to 100 Mbps, the minimum OPB clock frequency is 33.33 MHz.
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Preliminary Data Sheet
Figure 4. Timing Waveform
T
T
CL
CH
T
C
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC460EX. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC460EX the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC460EX with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
• The maximum frequency deviation of SysClk cannot exceed −1%, and the modulation frequency cannot
exceed 40kHz. In some cases, on-board PPC460EX peripherals impose more stringent requirements.
• For the PCI Express Reference Clock, the maximum spread spectrum is −0.5%, modulated between 30kHz
and 33kHz. The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million
(ppm) of each other at all times. This is specified to allow bit rate clock sources with a ± 300ppm tolerance.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that
the connected device is running at precise baud rates.
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
Important: It is up to the system designer to ensure that any SSCG used with the PPC460EX meets the above
requirements and does not adversely affect other aspects of the system.
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Preliminary Data Sheet
Table 20. Peripheral Interface Clock Timings (Part 1 of 2)
Parameter
PCI0Clk frequency
Minimum
Maximum
Units
MHz
ns
Notes
–
66.66
PCI0Clk period
15
–
PCI0Clk high time
40% of nominal period
60% of nominal period
ns
PCI0Clk low time
40% of nominal period
60% of nominal period
ns
GMCMDClk frequency
GMCMDClk period
GMCMDClk high time
GMCMDClk low time
GMCGTxClk frequency
GMCGTxClk period
GMCnTxClk frequency
GMCnTxClk period
GMCnTxClk high time
GMCnTxClk low time
GMCnRxClk frequency
GMCnRxClk period
GMCnRxClk high time
GMCnRxClk low time
GMCRefClk frequency
GMCRefClk period
GMCRefClk high time
GMCRefClk low time
GMCRefClk rise time
SGMIIRxClk frequency
PerClk frequency
–
2.5
MHz
ns
400
–
160
–
ns
160
–
ns
2.5
125
MHz
ns
8
400
2.5
25
MHz
ns
40
400
35% of nominal period
–
ns
35% of nominal period
–
ns
2.5
25
MHz
ns
40
400
35% of nominal period
–
ns
35% of nominal period
–
ns
125
125
MHz
ns
8
8
40% of nominal period
60% of nominal period
ns
2
2
4
40% of nominal period
60% of nominal period
ns
–
1
ns
625
625
MHz
MHz
ns
33
100
PerClk period
10
30
PerClk high time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
ns
PerClk low time
ns
(OPB F ) / 1024
(OPB F ) / 4
SPIClkOut frequency
IICSClk frequency
MHz
kHz
c
c
–
400
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Preliminary Data Sheet
Table 20. Peripheral Interface Clock Timings (Part 2 of 2)
Parameter
TmrClk frequency
Minimum
Maximum
Units
MHz
ns
Notes
–
100
TmrClk period
10
–
TmrClk high time
TmrClk low time
TrcClk frequency
40% of nominal period
40% of nominal period
100
60% of nominal period
60% of nominal period
ns
ns
300
MHz
3
1
1
UARTSerClk frequency
UARTSerClk period
–
MHz
ns
1000/(2T
+ 2ns)
OPB
1
–
1
1
1
2T
T
+ 2
+ 1
+ 1
OPB
1
UARTSerClk high time
UARTSerClk low time
–
ns
OPB
1
–
ns
T
OPB
USB2DClk frequency
USB2DClk period
60
16.66
60
MHz
ns
16.66
USB2DClk high time
USB2DClk low time
USB2HClk frequency
USB2HClk period
40% of nominal period
40% of nominal period
60
60% of nominal period
60% of nominal period
60
ns
ns
MHz
ns
16.66
16.66
USB2HClk high time
USB2HClk low time
USB2HClk48 frequency
USB2HClk48 period
USB2HClk48 high time
USB2HClk48 low time
Notes:
40% of nominal period
40% of nominal period
48
60% of nominal period
60% of nominal period
48
ns
ns
MHz
ns
20.8
20.8
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
1. T
is the period in ns of the OPB clock. The minimum OPB clock frequency is Ethernet application dependant (see Table 19 on
OPB
page 82). The maximum OPB clock frequency is 100 MHz.
2. An internal PLL improves this duty cycle to a worst case of 48% minimum, 52% maximum.
3. TrcClk is 1/4 CPU Clk. The maximum TrcClk supported by most instruction trace probes is 200MHz.
4. The rise time for GMCRefClk is measured between 0.7V and 1.7V.
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I/O Specifications
Preliminary Data Sheet
Figure 5. Input Setup and Hold Waveform
Clock
T
min
IS
T
min
IH
Inputs
Valid
Figure 6. Output Delay and Float Timing Waveform
Clock
max
min
max
max
min
T
T
T
OV
OV
OV
T
T
min
T
OH
Outputs
OH
OH
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
RGMII Timing
Figure 7. Setup and Hold Timing Waveforms for RGMII Signals
GMCnTxClk
TskewT
GMCnTxD/Ctl
Valid
Valid
GMCnRxClk
TskewR
GMCnRxD/Ctl
Valid
Valid
Table 21. RGMII I/O Timing
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
TskewR
(min)
TskewR
(max)
TskewT
(min)
TskewT
(max)
I/O H
(min)
I/O L
(min)
GMCnRxClk
GMCnRxD0:3
GMCnRxCtl
GMCnTxClk
GMCnTxD0:3
GMCnTxCtl
Notes:
–
–
–
–
n/a
n/a
n/a
n/a
–
1.0
1.0
v
2.8
2.8
–
n/a
n/a
–
n/a
n/a
–
GMCnRxClk
GMCnRxClk
–
1
1
n/a
n/a
5.51
5.51
5.51
7.23
7.23
7.23
n/a
n/a
n/a
n/a
-0.5
-0.5
0.5
0.5
GMCnTxClk
GMCnTxClk
1. Assumes GMCnRxClk is delayed either on the board or by the PHY to ensure adequate timing margin.
Test Conditions
Output
Pin
AC specifications are characterized with VDD = +1.20V, OVDD = +3.15V,
E1OVDD = +2.4V, TC = +85 °C and a 50pF test load as shown in the figure to the right.
50pF
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 22. AC I/O Specifications (Part 1 of 3)
Notes:
1. SGMII PHY recovers the SGMII Tx clock from the SGMII TxD0:1.
2. TDO timing is referenced to the falling edge of TCK.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
Hold Time
I/O H
(minimum)
I/O L
(minimum)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
PCI Interface
PCI0Reset
na
2.5
2.4
2.8
2.8
2.1
2.7
2.5
2.5
2.4
2.1
2.2
3
na
0
na
6
na
2
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
na
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
na
async
PCI0AD00:31
PCI0C0:3/BE0:3
PCI0Par
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
PCI0Clk
async
0
6
2
0
5.4
6
2
PCI0Frame
PCI0DevSel
PCI0IRDY
0
2
0
6
2
0
6
2
PCI0TRDY
0
6
2
PCI0Stop
0
6
2
PCI0PErr
0
6
2
PCI0SErr
0
6
2
PCI0IDSel
0
na
na
6
na
na
2
PCI0Req0:3
PCI0Gnt0:3
PCI0INT
0
na
na
na
na
na
0.5
0.5
1.5
1.5
na
5.8
2
Ethernet MII Interface
GMCMDClk
GMCMDIO
na
10
na
na
na
na
10
10
6
na
0
na
30
na
7
na
10
na
1
5.51
5.51
5.51
5.51
5.51
5.51
na
7.23
7.23
7.23
7.23
7.23
7.23
na
GMCMDClk
GMC0TxClk
GMC0TxD3:0
GMC0TxEn
GMC0TxEr
GMC0CD
na
na
na
na
10
10
10
10
10
GMC0TxClk
GMC0TxClk
GMC0TxClk
GMC0RxClk
GMC0RxClk
GMC0RxClk
GMC0RxClk
GMC0RxClk
6
1
6
1
na
na
na
na
na
na
na
na
na
na
GMC0CrS
na
na
GMC0RxD3:0
GMC0RxDV
GMC0RxEr
Ethernet GMII Interface
GMCMDClk
GMCMDIO
na
na
5
na
na
6
na
na
na
10
na
na
na
na
2
na
0
na
30
na
2.3
2.3
2.2
na
na
na
na
na
na
10
na
2
5.51
5.51
5.51
5.51
5.51
5.51
na
7.23
7.23
7.23
7.23
7.23
7.23
na
GMCMDClk
GMC0GTxClk
GMC0TxD7:0
GMC0TxEn
GMC0TxEr
GMC0CD
na
na
na
na
0
GMC0GTxClk
GMC0GTxClk
GMC0GTxClk
GMC0RxClk
GMC0RxClk
GMC0RxClk
GMC0RxClk
GMC0RxClk
2
2
na
na
na
na
na
GMC0CrS
2
0
na
na
GMC0RxD7:0
GMC0RxDV
GMC0RxEr
2
0
na
na
1.9
1.9
0
na
na
0
na
na
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 22. AC I/O Specifications (Part 2 of 3)
Notes:
1. SGMII PHY recovers the SGMII Tx clock from the SGMII TxD0:1.
2. TDO timing is referenced to the falling edge of TCK.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
Hold Time
I/O H
(minimum)
I/O L
(minimum)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
Ethernet SGMII Interface
SGMII0:1RxD
SGMII0:1RxD
0.1
na
0.1
na
na
na
na
na
na
na
SGMII0RxClk
SGMII0TxClk
SGMII0:1TxD
SGMII0:1TxD
3.35
3.35
1
Internal Peripheral Interface
IIC0:1SClk
IIC0:1SData
SCPClkOut
SPIDI
na
5
na
1.5
na
1.5
na
na
na
na
na
na
na
na
na
0
na
5
na
0
15.75
15.75
15.75
na
10.46
10.46
10.46
na
IIC0:1SClk
na
5
na
na
7
na
na
0
SCPClkOut
SCPClkOut
UARTSerClk
UARTSerClk
UARTSerClk
UARTSerClk
UARTSerClk
UARTSerClk
UARTSerClk
UARTSerClk
USB2HClk
USB2HClk
USB2HClk
USB2HClk
USB2HClk
USB2HClk
USB2HClk
USB2HClk
SPIDO
na
na
na
na
na
na
na
na
na
4.9
4.9
4.9
na
5
15.75
na
10.46
na
UARTnDCD
UARTnDSR
UARTnCTS
UARTnRTS
UARTnDTR
UARTnRI
na
na
na
na
na
na
na
na
6
na
na
na
na
na
na
na
na
2
na
na
na
na
11.08
11.08
na
7.37
7.37
na
UARTnRx
UARTnTx
USB2DD7:0
USB2DDir
USB2DNext
USB2DStop
USB2HD7:0
USB2HDir
USB2HNext
USB2HStop
Interrupts Interface
IRQ0:15
na
na
11.08
5.51
na
7.37
7.23
na
0
na
na
7
na
na
2
0
na
na
na
0
5.51
5.51
na
7.23
7.23
na
6
2
4.9
4.9
na
0
na
na
7
na
na
2
0
na
na
na
5.51
7.23
na
na
na
na
na
na
JTAG Interface
TCK
na
2
na
5.5
na
na
na
9.5
na
na
na
na
1
na
na
na
na
TDI
TCK
TCK
TDO
na
2
11.08
na
7.37
na
2
TMS
5.5
na
na
na
TCK
TRST
na
na
na
async
System Interface
SysReset
na
na
na
na
na
na
na
na
na
na
na
na
na
11.08
na
na
7.37
na
async
async
async
SysErr
Halt
Trace Interface
TrcClk
na
na
na
na
na
na
na
na
na
1.5
1.6
1.7
na
1
11.08
11.08
11.08
11.08
7.37
7.37
7.37
7.37
TrcBS0:2
TrcClk
TrcClk
TrcClk
TrcES0:4
1
TrcTS0:6
1
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 22. AC I/O Specifications (Part 3 of 3)
Notes:
1. SGMII PHY recovers the SGMII Tx clock from the SGMII TxD0:1.
2. TDO timing is referenced to the falling edge of TCK.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
Hold Time
I/O H
(minimum)
I/O L
(minimum)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
External Slave Peripheral Interface
DMAReq0:3
DMAAck0:3
EOT0:3/TC0:3
PerClk
4
na
4
1
na
1
na
5.3
5.3
na
na
1
na
na
PerClk
PerClk
PerClk
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
na
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
na
1
na
na
2
na
na
1
na
1
PerAddr02:31
PerData00:31
PerPar0:3
PerWBE0:3
PerCS0:5
PerR/W
4.5
4.9
4.9
4.8
5.3
4.5
4.5
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
async
1
2
1
1
na
na
na
na
2
na
na
na
na
1
1
1
1
PerOE
1
PerReady
PerBLast
na
1
na
2
na
1
4.5
na
11.08
na
7.37
na
PerErr
na
na
ExtReset
na
na
na
11.08
7.37
NAND Flash Interface
NFCE0:3
na
na
na
na
na
2
na
na
na
na
na
1
4.7
5.3
5.3
5.3
5.3
na
1
1
11.08
11.08
11.08
11.08
11.08
na
7.37
7.37
7.37
7.37
7.37
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
NFCLE
NFALE
1
NFREn
1
NFWEn
1
NFRdyBusy
na
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
DDR2/1 SDRAM Interface Specifications
The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed.
Note: MemClkOut can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR
programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific
application and requires a thorough understanding of the memory system in general (refer to the DDR
SDRAM Controller chapter in the PowerPC 460EX/EXr/GT Embedded Processor User’s Manual).
The signals are terminated as indicated in Figure 8 for the DDR timing data in the following sections.
Programmable Timing
When initializing the DDR controller at boot time, calibration of various programmable delays is required. The
following parameters are programmable:
• The internal delay of the DQS signals on a read is programmable. A single programmable delay globally
affects all of the DQS signals.
• The internal delay of the feedback signal on a read is programmable. The DDR controller drives and receives a
pulse at the beginning of each read burst. The feedback pulse is driven and received by MemDCFbdkD and
MemDCFbdkR. This pulse is used to adjust the sample cycle.
• The phase between the internal PLB clock and MemClkOut is programmable.
• The phase between the MemClkOut and the write DM, DQS, and data signals is programmable.
Board Layout Recommendations
The paths (traces) for the data and the associated data strobe signal should be routed with the same length
between PPC460EX and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at the
capture logic at the same time the data is in transition. Board designs must meet of the following criteria:
• Skew between the signals within any byte lane (8 DQ, 1 DQS, and 1 DM) should not exceed 50ps.
For example, traces that average 3.00 in. and 167ps/in., and meet the maximum 50ps skew requirement, have a
maximum length difference of 0.3in. and are between 2.85in. and 3.15in.
Clocking
Clocking skew to all DRAMs must be minimized. The maximum recommended flight-time skew between clocks for
different memory chips is 10ps. Because of the stringent requirements on DDR device clock inputs, it is expected
that board designers use some type of external PLL suitable to redrive the clock to the DDR SDRAMs when more
than two memory clocks are needed.. In such a system, the PLL acts as a zero-delay insertion buffer.
The PPC460EX (PPC460GT) has two identical memory clocks, MemClkOut0:1, eliminating the need to redrive the
memory clock for some board designs. Designs using a single registered DIMM or a single rank of directly attached
32-bit memory (2 x16 memory chips) does not require redriven clocks.
Feedback Signal
There are two options for handling the trace between the feedback driver and receiver, MemDCFbdkD to
MemDCFbdkR.
1. The feedback trace can be length matched to the round-trip delay measured from the rising edge of
MemClkOut0:1 to the resulting input DQS on a read operation. Matching the feedback trace to the round-trip
delay, however, can negatively affect the sample cycle used by the DDR controller during reads. For this
reason, matching the trace length is not recommended for typical applications. Even when trace lengths are
matched to the round trip delay, software calibration of the feedback delay is still required.
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Preliminary Data Sheet
2. The feedback trace can be made as short as possible such that MemDCFbdkD to MemDCFbdkR are directly
connected to one another. When using a short trace, software must calibrate the feedback timing using
MCIF0_RFDC[RFFD] . This method works well as long as the round trip flight time is less than half of a
MemClkOut cycle.
DDR I/O Characteristics
The DDR I/O operate as either 2.5V (SSTL2_25) DDR1 or 1.8V (SSTL_18) DDR2 receiver/drivers. The following
table lists the ODT termination supported, output driver impedance and input receiver capacitance.
Table 23. DDR I/O Characteristics
Signals
DDR2 ODT (Ω)
Output Impedance (Ω)
Input Capacitance (pF)
MemData00:63, ECC0:7, MemDCFdbkD, MemDCFdbkR,
MemAddr00:14, BA0:2, BankSel0:3, RAS, CAS, WE,
ClkEn0:3, DM0:8, MemODT0:3
75
36
6.4
DQS0:8/ DQS0:8
MemClkOut0:1/ MemClkOut0:1
Notes:
75
–
18 or 36
18 or 36
6.4
6.4
1. The output impedance (drive strength) for DQS0:8/ DQS0:8 and MemClkOut0:1/MemClkOut0:1 is programmable.
2. The 75-ohm internal termination for MemData00:63, DQS0:8/DQS0:8, and DM0:8 can be statically or dynamically enabled.
3. The 75-ohm internal termination is statically enabled for MemDCFdbkD, MemDCFdbkR, MemAddr00:14, BA0:2, BankSel0:3, RAS,
CAS, WE, ClkEn0:3, and MemODT0:3.
Table 24. DDR SDRAM Output Driver Specifications
Output Current (mA)
Signal Path
I/O H (maximum)
I/O L (maximum)
MemData00:63
ECC0:7
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
DM0:8
MemClkOut
MemAddr00:14
BA0:2
RAS
CAS
WE
BankSel0:3
ClkEn0:3
DQS0:8/ DQS0:8
MemODT0:3
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Preliminary Data Sheet
DDR SDRAM Timing Conditions
The following timing values are generated by means of simulation and includes logic, driver, package RLC, and
lengths. Values are calculated over best case and worst case processes with speed, junction temperature, and
voltage as follows:
Table 25. DDR SDRAM Operation Conditions
SOV
for DDR1 (V)
SOV
DD
for DDR2 (V)
Case
Process Speed
Case Temperature (°C)
DD
Best
Fast
−40
+85
+2.4
+2.6
+1.9
+1.7
Worst
Slow
Figure 8. DDR SDRAM Simulation Signal Termination Model
MemClkOut
10pF
10pF
120Ω
MemClkOut
V
= SOV /2
DD
TT
PPC460EX
50
Ω
Addr/Ctrl (DDR2)
Addr/Ctrl/Data/DQS/DM (DDR1)
30pF
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
DDR SDRAM Write Operation
The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes.
Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and
maximum values are measured under worst case conditions. The timing numbers in the following sections are
obtained using a simulation that assumes a model as shown in Figure 8.
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Preliminary Data Sheet
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 9. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut
T
SA
T
HA
Addr/Cmd
T
DS
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
= Setup time for address and command signals to MemClkOut
SA
T
= Hold time for address and command signals from MemClkOut
HA
SD
HD
T
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
T
T
DS
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 26. I/O Timing—DDR SDRAM TDS for 200 MHz
Notes:
1. All of the DQS signals are referenced to MemClkOut.
2. MemClkOut frequency is 200MHz.
T
(ns)
DS
Signal Name
DQS0:8/ DQS0:8
Minimum
Maximum
4.9
5.1
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Preliminary Data Sheet
Table 27. I/O Timing—DDR SDRAM TSA, and THA
Notes:
1. The timing values in this table apply to MemClkOut frequency of 200MHz.
2. TSA and THA are referenced to MemClkOut rising edge.
3. DDR1 is supported up to 200MHz. (400Mbps data rate).
T
(ns)
T
(ns)
HA
SA
Signal Name
Minimum
1.08
Minimum
1.18
MemAddr00:14
BA0:2
1.17
1.19
BankSel0:3
ClkEn0:3
CAS
1.12
1.15
1.11
1.15
1.16
1.14
RAS
1.17
1.13
WE
1.17
1.17
Table 28. I/O Timing—DDR SDRAM Write Timing TSD and THD
Notes:
1. TSD and THD are measured under worst case conditions.
2. The timing values in this table apply to MemClkOut frequency of 200MHz.
3. The timing values in this table include 1/4 of a cycle at 200MHz.
4. To obtain adjusted TSD and THD values for clock frequencies less than 200MHz, subtract 1.5ns from the values in the table
and add 1/4 of the cycle time for the lower clock frequency (for example, TSD − 1.5 + 0.25TCYC).
5. DDR1 is supported up to 200MHz. (400Mbps data rate).
T
(ns)
T
(ns)
HD
Signal Names
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
Reference Signal
DQS0
SD
0.96
0.995
0.990
0.980
0.980
0.980
0.983
0.982
0.985
0.980
DQS1
0.97
0.98
0.98
0.98
0.97
0.96
0.96
0.96
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
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Preliminary Data Sheet
DDR SDRAM Read Operation
The read of the incoming data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The data must be centered to these edges for correct operation.
DDR SDRAM Read Cycle Timing
The following diagram illustrates the relationship of the signals involved with a DDR read operation.
Figure 10. DDR SDRAM Memory Data and DQS
DQS
T
SD
MemData
T
HD
Table 29. I/O Timing—DDR SDRAM Read Timing TSD and THD for 200MHz
1. TSD and THD are measured under worst case conditions.
2. MemClkOut frequency is 200MHz.
3. The time values in this table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25ns).
4. To obtain adjusted T
and T
values for lower clock frequencies, subtract 0.75ns from the values in the table and add 1/4
SD
HD
of the cycle time for the lower clock frequency (e.g., T − 1.25 + 0.25T
).
CYC
SD
5. DDR1 is supported up to 200MHz. (400Mbps data rate).
Read Data vs DQS Set up
(ns)
Read Data vs DQS Hold
(ns)
Signal Names
MemData00:07
Reference Signal
T
T
HD
SD
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
0.393
0.388
0.397
0.396
0.394
0.395
0.393
0.394
0.389
0.311
0.314
0.307
0.309
0.291
0.291
0.295
0.308
0.306
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
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Preliminary Data Sheet
PCI Express Interface Specification
The following tables contain the PCI Express interface specification.
Table 30. PCI Express Transmitter Specification
Parameter
Minimum
400
Maximum
Units
ps
Notes
Unit Interval (UI)
400
1200
–
Differential Tx peak-to-peak voltage swing
Low power differential Tx peak-to-peak voltage swing
Tx de-emphasis level ratio
800
mV ppd
mV ppd
dB
400
−3.0
−4.0
–
Minimum Tx eye width
0.75
UI
Maximum time between the jitter median and maximum
deviation from the median
–
0.125
UI
Transmitter rise and fall time
0.125
–
–
22
–
UI
MHz
MHz
ps
Maximum Tx PLL bandwidth
Minimum Tx PLL BW for 3dB peaking
PCIEnTx/PCIEnTx Tx output rise/fall time
Tx AC common mode voltage
1.5
50
–
–
20
mV
Absolute delta of DC common mode voltage during L0 and
Electrical Idle
0
0
100
25
mV
mV
Absolute delta of DC common mode voltage between PCIEnTx
and PCIEnTx
Electrical Idle differential peak output voltage
Amount of voltage change allowed during receiver detection
Tx DC common mode voltage
0
-
20
600
3600
90
mV
mV
mV
mA
UI
0
Tx short-circuit current limit
–
Minimum time spent in Electrical Idle
50
–
Maximum time to transition to a valid Electrical Idle after sending
an Electrical Idle Ordered-Set
–
–
20
20
UI
UI
Maximum transition time to valid differential signaling after
leaving Electrical Idle
Tx differential return loss
−10
−6
80
–
–
–
dB
dB
Ω
Tx common mode return loss
Tx DC differential impedance
Lane-to-Lane output skew
120
1300
ps
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Preliminary Data Sheet
Table 31. PCI Express Receiver Specification
Parameter
Unit Interval (UI)
Minimum
400
−300
175
–
Maximum
Units
ps
Notes
400
+300
1200
150
–
Frequency offset between transmit and receive clocks
Differential Rx peak-to-peak voltage
Rx AC common mode voltage
ppm
mV
mV
UI
Receiver eye time opening
0.4
–
Maximum time delta between median and deviation from median
Total jitter tolerance
0.3
–
UI
0.6
−10
−6
UI
Rx differential return loss
–
dB
dB
Ω
Rx common mode return loss
–
Rx DC differential impedance
80
120
60
Rx DC common mode impedance
Rx DC common mode impedance during reset or power down
Electrical Idle detect threshold
40
Ω
200
65
–
kΩ
mV
ms
ns
175
10
Unexpected Electrical Idle enter detect threshold integration time
Lane-to-Lane output skew
–
–
20
Table 32. PCI Express Reference Clock Specification
Parameter
Reference clock frequency
Accuracy
Minimum
100
Maximum
100
Units
MHz
ppm
%
Notes
1
−300
45
+300
55
Duty cycle
-6
–
–
86
ps
ps
3
Peak-to-peak jitter for 1E-6 BER (1 x 10 bit error rate)
-12
108
3
2
Peak-to-peak jitter for 1E-6 BER (1 x 10
Spread Spectrum Clock (SSC) frequency
Differential signal amplitude
Notes:
bit error rate)
30
33
kHz
mV
200
1600
1. The reference clock frequency specification does not include ±300ppm frequency offset specification.
2. The data rate can be modulated from +0% to −0.5% of the nominal data rate frequency, at a modulation rate in the range not exceeding
30kHz–33kHz. The ±300ppm requirement remains which requires the two communcicating ports to be modulated so that they never
exceed a total of 600ppm difference. For most implementations, this requires that both ports have the same bit rate clock source when
the data is modulated with an SSC.
3. 1E-6 is the probability that the jitter is greater than 86ps peak-to-peak. 1E-12 is the probability that the jitter is greater than 108ps peak-
to-peak.
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Preliminary Data Sheet
Serial ATA (SATA) Interface Specification
The following tables contain the SATA interface specification.
Table 33. SATA Transmitter Specification
Parameter
Minimum
Maximum
Units
ps
Notes
Unit Interval (UI)
333.3
400
67
666.6
1600
–
Differential Tx peak-to-peak voltage swing
SATA0Tx/SATA0Tx Tx output rise/fall time
Tx short-circuit current limit
mV ppd
ps
–
90
mA
Tx differential return loss
−10
−6
–
dB
Tx common mode return loss
Tx DC differential impedance
Tx DC single-ended impedance
Tx OOB transmission voltage
–
dB
85
115
–
Ω
40
Ω
–
200
mV ppd
Table 34. SATA Receiver Specification
Parameter
Unit Interval (UI)
Minimum
333.3
−5350
240
Maximum
Units
ps
Notes
666.6
+350
–
Frequency offset between transmit and receive clocks
Differential Rx peak-to-peak voltage
Total jitter tolerance
ppm
mV
UI
0.65
−10
–
Rx differential return loss
–
dB
Rx common mode return loss
Rx DC differential impedance
Rx DC common mode impedance
Rx OOB voltage detection threshold
−6
–
dB
85
115
–
Ω
40
Ω
–
240
mV
Table 35. SATA Reference Clock Specification
Parameter
Reference clock frequency
Accuracy
Minimum
Maximum
120
Units
MHz
ppm
Notes
100
−350
45
–
1, 3
+350
55
Duty cycle
%
Cycle-to-cycle jitter
150
ps p-p
ps p-p
ps p-p
ps p-p
kHz
Total jitter 1kHz–1MHz
Total jitter 1MHz–20MHz
Total jitter >20MHz
–
100
–
40
–
100
Spread Spectrum Clock (SSC) frequency
Spread Spectrum Clock (SSC) variation
Notes:
30
0
33
2
2
5000
ppm
1. The reference clock frequency specification does not include 5700ppm frequency offset specification.
2. The data rate can be modulated from +0% to −0.5% of the nominal data rate frequency, at a modulation rate in the range not exceeding
30kHz–33kHz. The ±350ppm requirement remains which requires the two communcicating ports to be modulated so that they never
exceed a total of 700ppm difference. For most implementations, this requires that both ports have the same bit rate clock source when
the data is modulated with an SSC.
3. Only 100MHz or 120MHz is supported.
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Preliminary Data Sheet
PCI-E and SATA Reference Clock AC Coupling Recommendations
AC coupling is recommended for the PCIe and SATA reference clock. The following figures illustrate how to
implement AC coupling for the most common differential reference clocks.
Note: C1 and C2 may be any value from 0.01µF to 0.1µF as long as C1 equals C2. All components should be in a
0603 or smaller package and should be placed to minimize the stub length to the traces.
Figure 11. LVDS PCIe or SATA Reference Clock
C1
PCIEnRefClk/
SATA0RefClk
R1=100Ω
C2
PCIEnRefClk/
SATA0RefClk
LVDS
clock driver
PCIe or SATA RefClk receiver
with internal biasing
C1=C2=0.01µF to 0.1µF
Figure 12. LVPECL PCIe or SATA Reference Clock
3.3V
C1
R1=130Ω
R2=82Ω
3.3V
C2
R3=130Ω
R4=82Ω
LVPECL
clock driver
PCIe or SATA RefClk receiver
with internal biasing
C1=C2=0.01µF to 0.1µF
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Preliminary Data Sheet
Figure 13. CML PCIe or SATA Reference Clock
C1
C2
CML
clock driver
PCIe or SATA RefClk receiver
with internal biasing
Figure 14. HCSL PCIe or SATA Reference Clock
3.3V
C1
R1=33Ω
R2=50Ω
3.3V
C2
R3=33Ω
R4=50Ω
HCSL
clock driver
PCIe or SATA RefClk receiver
with internal biasing
C1=C2=0.01µF to 0.1µF
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460EX – PPC460EX Embedded Processor
Boot Configuration
Preliminary Data Sheet
The PPC460EX supports several configurable boot parameters that must be initialized prior to booting. These
parameters are configured by one of several default boot options or programmed by data read from an IIC serial
EEPROM (see “Serial EEPROM” below). Strap signals sampled during reset select which method is used to
initialize the boot parameters (see “Strapping” below).
Strapping
The Bootstrap Controller selects the boot options based on the state of the strap signals during reset. The strap
signals are sampled on the rising edge of SysClk while SysReset is driven low. They must not change state until
after SysReset is driven high in order to guarantee the correct boot option is selected.
These pins are used for strap functions only during reset. Following reset, they are used for normal functions. The
signal names assigned to the pins for normal operation are shown in parentheses following the pin number.
The following table lists the strapping pins along with their functions and boot strap options:
Table 36. Strapping Pin Assignments
Strapping Pins
Function
Boot Option
E31
E34
E32
(UART0CTS)
(UART0DCD)
(UART0DSR)
Serial device is disabled. Each of the six options (A–
F) is a combination of boot source, boot-source
width, and clock frequency specifications. Refer to
the PPC460EX Embedded Processor User’s Manual
for details.
A
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
B
C
D
E
F
Serial device is enabled. Boot Option G and H
enable the Bootstrap Controller to program boot
parameters using data read from an IIC serial
EEPROM. Option G and H support different IIC
addresses.
G (0xA8)
H (0xA4)
1
1
1
Serial EEPROM
Boot Options G and H enable the Bootstrap Controller to read 16 bytes of configuration data from a serial
EEPROM attached to the IIC0 bus after SysReset deasserts. The Bootstrap Controller stores the data in the
SDR0_SDSTP0:3 registers.
Note: The IIC serial EEPROM must have a one-byte base address. Multi-byte base addresses are not supported.
The initialization settings and their default values are covered in detail in the PowerPC 460EX/EXr/GT Embedded
Processor User’s Manual User’s Manual.
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Preliminary Data Sheet
Revision Log
Date
Version
1.00
Contents of Modification
04/20/2007
05/17/2007
07/18/2007
Initial creation of document.
1.00
Update to initial creation of document.
Update to initial creation of document.
1.01
Update to initial creation of document.
08/03/2007
1.02
Eliminate SRIO, EMB, second RGMII, SMII, third and forth EMACs.
Change GPIOs to alternate to default signals.
Add thermal monitor diagram.
10/01/2007
1.03
Corrected signal-to-pin (ball) assignments for nine pins.
Misc. updates and corrections.
Change all occurrences of PerDataPar to PerPar.
Swap signals assigned to balls A20 and E19.
Add updates from 460EX development which include changing the nine signal-to-pin changes
made for 1.03 back to their original state.
10/17/2007
1.04
Restore TBI and RTBI to Features on first page.
Correct ActiveLow indication on some SATA and PCIE signals.
Correct ActiveLow indication on some SATA and PCIE signals.
Remove all GMC1xxxx signals.
10/18/2007
12/21/2007
1.05
1.06
Remove all TBI and RTBI signals.
Add missing GMC1RxCtl signal to pin AJ10.
Update I/O timing.
Change PCIE calibration resistor from 1k to 1.37k.
Add RMII signals.
Misc. updates.
01/14/2008
02/11/2008
1.07
1.08
Change maximum case temperature from +105°C to +85°C.
Correct typograhical errors.
Correct DDR SDRAM Read Data Path diagram.
Update PCIEnRefClk signal description.
Add block diagram from R/C engineering specification.
Reference 802.3 Ethernet spec for GMCMDIO timing.
Add KASUMI support to security.
Change document status from Advanced to Preliminary and remove Confidential status.
Update block diagram.
04/14/2008
05/05/2008
1.09
1.10
Add power estimates.
Flag SGMIIRefClk signals as not to be used.
Update Contents to include L2 Cache/SRAM.
Delete SAV voltage from analog voltage filter diagram (Doc Issue 503).
DD
Change Thermal Monitor parameters (Doc Issue 504).
Misc. changes including Doc Issues 512, 524, and 526.
05/29/2008
07/17/2008
1.11
1.12
Doc Issue 455. Add power sequence information.
Doc Issues 530, 532, 536, 550. Update JTAG timing.
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Preliminary Data Sheet
Date
Version
Contents of Modification
Doc Issue 572. Update SysReset signal functional description.
Security is no longer optional. Remove non-security part numbers.
Doc Issue 589. PCI-E and SATA I/O specifications. Timing, power, and other misc. updates.
New RGMII wave forms.
09/26/2008
1.13
Update Security features list.
Doc Issue 595. Add pull-up and pull-down resistor values.
Additional processor speed of 1.066GHz.
New power values for 1.066GHz and lower speeds.
Change bootstrap description.
Doc Issue 4816. Change SysReset I/O designation.
Doc Issue 4892. PCI clock required even when PCI is unused
Doc Issue 4933. Change SATARefClk frequency range.
Doc Issue 4960. Remove all references to SMII and RMII.
Doc Issue 5031. PCI signal termination recommendation.
Doc Issue 5032. Change PCI Express reference clock to 100MHz .
Doc Issue 5045. Remove length constraint from DDR layout recommendation .
Doc Issue 5205. Correct SysReset signal description.
11/14/2008
1.14
12/18/2008
1/16/2009
1.15
1.16
For Rev.A parts, removed 1066MHz CPU and 266MHz PLB/Memclk.
Doc Issue 5220:
•
In Table 9, updated description for SysReset; changed “32 cycles” to “32 SysClk cycles”.
Doc Issue 5440:
•
•
In Table 19, updated OPB Clock minimum frequency and maximum period, and added note.
In Table 20, updated SPIClkOut minimum and maximum frequency, and updated Note 1.
Added Revision B, Rev.B PVR, and No Security part number.
Marked security as optional.
Clarified signal names in Table 24, Table 26, and Table 27.
Doc Issue 5857:
•
In Table 19, added notes regarding SysClk jitter and slew rate.
Doc Issue 5885:
In Table 23, corrected errors: All of the signals with the exception of the MemClkOut signals
have 75-ohm internal termination.
Doc Issue 5973:
In Table 19, added note indicating the spread spectrum modulation range when SysClk is
66.66MHz.
2/27/2009
1.17
•
•
Updated Table 17, DC Power Supply Loads.
Doc Issue 6180:
•
•
Added requirement for AC coupling on PCIEnRefClk and SATA0RefClk in Table 9.
4/30/09
6/17/09
1.18
1.19
Added section “PCI-E and SATA Reference Clock AC Coupling Recommendations” on
page 100.
Doc Issue 6361:
•
Changed CGM to GCM under “Security Function (Optional)” on page 13.
Removed iSCSI CRC32 function from I2O/DMA.
Added FSOURCE0 to signal list. This signal should be tied to ground if the SDR0_ECID0:3
(electronic chip ID) registers need to be read.
Updated GMCMDIO T specification.
OV
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460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Printed in the United States of America, June 17, 2009
The following are trademarks of AMCC Corporation in the United States, or other countries, or both:
AMCC
Other company, product, and service names may be trademarks or service marks of others.
Preliminary Edition (June 17, 2009)
This document contains information on a new product under development by AMCC.
AMCC reserves the right to change or discontinue this product without notice.
This document is a preliminary edition of the PowerPC 460EX data sheet. Make sure you are using the correct
edition for the level of the product.
While the information contained herein is believed to be accurate, such information is preliminary, and should not
be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness
are made.
The information contained in this document is subject to change or withdrawal at any time without notice
and is being provided on an "AS IS" basis without warranty or indemnity of any kind, whether express or
implied, including without limitation, the implied warranties of non-infringement, merchantability, or
fitness for a particular purpose. Any products, services, or programs discussed in this document are sold
or licensed under AMCC’s standard terms and conditions, copies of which may be obtained from your
local AMCC representative. Nothing in this document shall operate as an expressed or implied license or
indemnity under the intellectual property rights of AMCC or third parties.
Without limiting the generality of the foregoing, any performance data contained in this document was
determined in a specific or controlled environment and not submitted to any formal AMCC test. Therefore,
the results obtained in other operating environments may vary significantly. Under no circumstances will
AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or
the information contained herein.
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Preliminary Data Sheet
Applied Micro Circuits Corporation
215 Moffett Park Drive, Sunnyvale, CA 94089
Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601
http://www.amcc.com
AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and
warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available
data sheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.
AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any
liability arising out of the application or use of any product or circuit described herein, neither does it convey any license
under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of
lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS.
AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2008 Applied Micro Circuits Corporation.
All rights reserved.
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