PPC440SP-RNC667C_技术文档

Part Number 440SP

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Features

‚

• I2O Messaging Unit with two DMA controllers

• PowerPC 440 processor core operating at up to

667MHz with 32-KB I- and D-caches (with parity

checking)

• External Peripheral Bus (24-bit Address, 8-bit

Data) for up to three devices

• On-chip 256-KB SRAM configurable as L2 Cache

or Ethernet Packet/Code store memory

• One Ethernet 10/100/1000 Mbps half- or full-

duplex interface. Operational modes supported

are MII and GMII.

• Selectable Processor:Bus clock ratios (Refer to

the Clocking chapter in the PPC440SP Embedded

Processor User’s Manual for details)

• Programmable Interrupt Controller supports

interrupts from a variety of sources.

• Supports up to 4 GB (2 Chip Selects) of 64-bit/32-

bit SDRAM with ECC

• Programmable General Purpose Timers (GPT)

• Three serial ports (16750 compatible UART)

• Two IIC interfaces

– DDR1 266-333-400

– DDR2 400-533-667

• Three DDR PCI-X interfaces (32-bit or 64-bit) up

to 133 MHz (DDR 266) with support for

conventional PCI

• General Purpose I/O (GPIO) interface available

• JTAG interface for board level testing

• Processor can boot from PCI memory

• XOR Accelerator with DMA controller

• Optional: High throughput RAID 6 hardware

acceleration, performs XOR and Galois Field P &

Q parity computations, supports up to 255 drives

Description

Designed specifically to address high-end embedded

applications for storage, the PowerPC 440SP

Embedded Processor (PPC440SP) provides a high-

performance, low power solution that interfaces to a

wide range of peripherals by incorporating on-chip

power management features and lower power

dissipation.

Technology: CMOS Cu-11, 0.13mm

Package: 29mm, 783-ball, 1mm pitch, Flip Chip-

Plastic Ball Grid Array (FC-PBGA)

Power (estimated): Less than 6W @533MHz

Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V

This chip contains a high-performance RISC

processor core, a DDR2 SDRAM controller,

configurable 256KB SRAM to be used as L2 cache or

software-controlled on-chip memory, three DDR PCI-X

bus interfaces, an Ethernet interface, an I2O/DMA

controller, control for external ROM and peripherals,

optional RAID 6 acceleration, an XOR DMA unit, serial

ports, IIC interfaces, and general purpose I/O.

AMCC Proprietary

1

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Contents

Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

PPC440SP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

On-Chip SRAM/L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DDR PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DDR1/DDR2 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

I2O/DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Optional RAID 5 and RAID 6 Acceleration Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

XOR/DMA2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

29mm, 783-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Clock Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Serial Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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Data Sheet

PowerPC 440SP Embedded Processor

Figures

Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. PPC440SP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. 29mm, 783-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4. Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 5. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 6. Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 7. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 8. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 9. DDR SDRAM Read Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 10. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 11. DDR SDRAM Read Cycle Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Tables

Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. DCR Address Map (4KB of Device Configuration Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 5. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 10. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 11. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 12. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 13. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 14. I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 15. I/O Specifications—533MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 16. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 17. DDR SDRAM Read and Write I/O Timing—TSA and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 18. DDR SDRAM Clock to Write DQS Timing—TDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 19. DDR SDRAM Write Data to DQS Timing—TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 20. DDR SDRAM I/O Read Timing—T and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

HD

SD

Table 21. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

AMCC Proprietary

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Ordering and PVR Information

For information about the availability of the following parts, contact your local AMCC sales office.

Order Part Number

(see Notes:)

Rev

Level

Product Name

Package

PVR Value

JTAG ID

PPC440SP

PPC440SP-xpCfffC

29mm, 783 FC-PBGA

C

0x53221891

0x12056049

Notes:

1. x = Product Feature

A = RAID6 not enabled

R = RAID6 enabled

2. p = Module Package Type

F = leaded FC-PBGA

N = lead free FC-PGBA (RoHS compliant)

3. C = Chip Revision Level C

4. fff = Processor Frequency

533 = 533MHz

667 = 667MHz

5. C = Case Temperature Range of -40°C to +100°C

Each part number contains a revision code. This is the die mask revision number and is included in the part

number for identification purposes only.

The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain

information that uniquely identifies the part. See the PPC440SP Embedded Processor User’s Manual for details

about accessing these registers.

Note: Raid-enabled versions (Product Feature = R) require a RAID key license.

Figure 1. Order Part Number Key

PPC440SP-RNC667C

AMCC Part Number

Case Temperature Range

Product Feature

Processor Speed

Revision Level

Package

Note: The example part number above is a RAID6-enabled, lead-free package, at Chip Revision

Level C, capable of running at 667 MHz, and is shipped in tray packaging.

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

PPC440SP Functional Block Diagram

Figure 2. PPC440SP Functional Block Diagram

Clock,

Power

Control,

Reset

Mgmt

Universal

Interrupt

Controller

MMU

Timers

UART2

DCRs

UART1

UART0

IIC1

IIC0

PPC440

Processor Core

GPIO

GPT

DCR Bus

Trace

JTAG

On-chip Peripheral Bus (OPB)

32KB

D-Cache

I-Cache

OPB

Bridge

L2 Cache/SRAM

PLB

Arbiter

Processor Local Bus (PLB)

Ethernet

External

Bus Controller

(EBC)

Low Latency (LL) Segment

High Bandwidth (HB) Segment

10/100/

1000

MAL

(EMAC)

MII,

GMII

DDR PCI-X

Memory

Queue

XOR/DMA

Accelerator

Unit

I2O/DMA

Controller

(DMA0 and

DMA1)

PCI2

Local

PCI0 PCI1

Host Local

64 bits 64 bits

DDR2 SDRAM

Controller

(DMA2)

32 bits

®

The PPC440SP is a System on a chip, which uses IBM CoreConnect Bus™ Architecture.

Implemented with the Crossbar option, the IBM CoreConnect buses provide:

• 128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data

paths (10.6GB/sec total)

• 32-bit OPB interfaces up to 83.33MHz, 333MB/s

Address Maps

The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This

address map defines the possible contents of various processor accessible address regions. The second address

map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the

PPC440SP processor through the use of mtdcr and mfdcr instructions.

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 1. System Memory Address Map (Sheet 1 of 2)

Function

Sub Function

DDR SDRAM

Start Address

End Address

Size

4GB

0000 0000 0000 0000

0000 0001 0000 0000

0000 0001 0004 0000

0000 0001 0010 0000

0000 0001 0010 0100

0000 0001 0010 0200

0000 0001 0010 0300

0000 0001 0010 1000

0000 0001 0020 0000

0000 0001 0020 4000

0000 0001 F000 0000

0000 0001 F000 0200

0000 0001 F000 0208

0000 0001 F000 0300

0000 0001 F000 0308

0000 0001 F000 0400

0000 0001 F000 0420

0000 0001 F000 0500

0000 0001 F000 0520

0000 0001 F000 0600

0000 0001 F000 0608

0000 0001 F000 0700

0000 0001 F000 0780

0000 0001 F000 0800

0000 0001 F000 0900

0000 0001 F000 0A00

0000 0001 F000 0B40

0000 0001 F800 0000

0000 0001 FFC0 0000

0000 0001 FFE0 0000

0000 0002 0000 0000

0000 0008 0000 0000

0000 0000 FFFF FFFF

0000 0001 0003 FFFF

0000 0001 000F FFFF

0000 0001 0010 00FF

0000 0001 0010 01FF

0000 0001 0010 02FF

0000 0001 0010 0FFF

0000 0001 001F FFFF

0000 0001 0020 3FFF

0000 0001 EFFF FFFF

0000 0001 F000 01FF

0000 0001 F000 0207

0000 0001 F000 02FF

0000 0001 F000 0307

0000 0001 F000 03FF

0000 0001 F000 041F

0000 0001 F000 04FF

0000 0001 F000 051F

0000 0001 F000 05FF

0000 0001 F000 0607

0000 0001 F000 06FF

0000 0001 F000 077F

0000 0001 F000 07FF

0000 0001 F000 08FF

0000 0001 F000 09FF

0000 0001 F000 0B3F

0000 0001 F7FF FFFF

0000 0001 FFBF FFFF

0000 0001 FFDF FFFF

0000 0001 FFFF FFFF

0000 0007 FFFF FFFF

0000 0008 FFFF FFFF

Local Memory (LL)¹

SRAM

256KB

Reserved

I2O Registers

DMA 0 Registers

DMA 1 Registers

I20/DMA Buffers

Reserved

256B

Internal PLB Interfaces (LL)

3.25KB

XOR/DMA2

Reserved

16KB

Reserved

UART0

8B

Reserved

UART1

Reserved

IIC0

32B

Reserved

IIC1

Reserved

Internal OPB Peripherals (LL)

UART2

8B

Reserved

248B

128B

GPIO Controller Registers

Reserved

Ethernet Controller Registers

Reserved

256B

320B

General Purpose Timers

Reserved

EBC Memory

Additional Boot ROM⁶

124MB

2MB

Boot ROM^{2, 3}

2MB

Reserved

Local Memory Alias (HB)

Aliased DDR SDRAM

4GB

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 1. System Memory Address Map (Sheet 2 of 2)

Function

Sub Function

Start Address

End Address

Size

Reserved

PCIX0 I/O

PCIX1 I/O

PCIX2 I/O

0000 0009 0000 0000

0000 0009 0800 0000

0000 0009 1800 0000

0000 0009 2800 0000

0000 0009 07FF FFFF

0000 0009 0800 FFFF

0000 0009 1800 FFFF

0000 0009 2800 FFFF

64KB

PCIX0 Addressing Config. Regs

PCIX1 Addressing Config. Regs

PCIX2 Addressing Config. Regs

0000 0009 0EC0 0000

0000 0009 1EC0 0000

0000 0009 2EC0 0000

0000 0009 0EC0 0007

0000 0009 1EC0 0007

0000 0009 2EC0 0007

8B

PCIX0 Core Config. Regs

PCIX1 Core Config. Regs

PCIX2 Core Config. Regs

0000 0009 0EC8 0000

0000 0009 1EC8 0000

0000 0009 2EC8 0000

0000 0009 0EC8 0FFF

0000 0009 1EC8 0FFF

0000 0009 2EC8 0FFF

4KB

DDR PCI-X Space (HB)

PCIX0 Simple Message Passing

PCIX1 Simple Message Passing

PCIX2 Simple Message Passing

0000 0009 0EC8 1100

0000 0009 1EC8 1100

0000 0009 2EC8 1100

0000 0009 0EC8 11FF

0000 0009 1EC8 11FF

0000 0009 2EC8 11FF

256B

PCIX0 Special Cycle

PCIX1 Special Cycle

PCIX2 Special Cycle

Reserved

0000 0009 0ED0 0000

0000 0009 1ED0 0000

0000 0009 2ED0 0000

0000 0009 2EE0 0000

0000 0009 2F00 0000

0000 0009 FFC0 0000

0000 0009 FFE0 0000

0000 000A 0000 0000

0000 0010 0000 0000

0000 0009 0EDF FFFF

0000 0009 1EDF FFFF

0000 0009 2EDF FFFF

0000 0009 2EFF FFFF

0000 0009 FFBF FFFF

0000 0009 FFDF FFFF

0000 0009 FFFF FFFF

0000 000F FFFF FFFF

03FF FFFF FFFF FFFF

1MB

PCI Memory

3.3GB

Reserved

PCI Boot ROM (PCI Memory)

PCI Memory

2MB

24GB

Reserved⁴

Reserved⁵

0400 0010 0000 0000

0800 0000 0000 0000

07FF FFFF FFFF FFFF

FFFF FFFF FFFF FFFF

DDR PCI-X Space (HB)

Notes:

PCI Memory

15.7EB

1. DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.

2. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating

volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.

3. When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at 9 FFE0 0000 (128 KB).

4. Never decoded.

5. Unpredictable results on Read and Write operations.

6. Accessed by means of EBC Peripheral Bank Configuration Registers

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 2. DCR Address Map (4KB of Device Configuration Registers)

Function

Total DCR Address Space¹

Start Address

End Address

Size

1KW (4KB)¹

000

3FF

By function:

Reserved

000

00C

00E

010

012

014

020

030

040

050

060

080

090

0A0

0B0

0B2

0C0

0D0

0E0

0E8

180

200

00B

00D

00F

011

013

01F

02F

03F

04F

05F

07F

08F

09F

0AF

0B1

0BF

0CF

0DF

0E7

17F

1FF

3FF

12W

2W

Clocking Power On Reset

System DCRs

Memory Controller

External Bus Controller

Reserved

2W

12W

16W

32W

16W

2W

SRAM

L2 Controller

Memory Queue

Reserved

I2O/DMA

PLB

PLB to OPB Bridge Out

Reserved

14W

16W

8W

Interrupt Controller 0

Interrupt Controller 1

Power Management

Reserved

152W

128W

512W

Ethernet MAL

Reserved

Notes:

1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a sin-

gle 32-bit (word) register. One KW (1024W) equals 4KB (4096 bytes).

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Data Sheet

PowerPC 440SP Embedded Processor

PowerPC 440 Processor Core

The PowerPC 440 processor core is designed for high-end applications such as RAID controllers, SAN, iSCSI,

routers, switches, printers, set-top boxes, and so on. It is the first processor core to implement the Book E

PowerPC embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus

Architecture.

Features include:

• Up to 667MHz operation

• PowerPC Book E architecture

• 32KB I-cache, 32KB D-cache

– Parity on Data and Tag address - checking of parity with error injection

• Three logical regions in D-cache: Locked, Transient, and Normal

• D-cache full-line flush capability

• 41-bit virtual address, 36-bit (64GB) physical address

• Superscalar, out-of-order execution

• Seven-stage pipeline

• Three execution pipelines

• Dynamic branch prediction

• Memory management unit

– 64-entry, full associative, unified TLB with parity

– Separate instruction and data micro-TLBs

– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian

• Debug facilities

– Multiple instruction and data range breakpoints

– Data value compare

– Single step, branch, and trap events

– Non-invasive real-time trace interface

• 24 DSP instructions

– Single cycle multiply and multiply-accumulate

– 32 x 32 integer multiply

Internal Buses

The PowerPC 440SP Embedded Processor features three standard on-chip buses: the Processor Local Bus

(PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance,

high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the

DDR PCI-X bridge connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR

provides a lower bandwidth path for passing status and control information between the processor core and the

other on-chip cores.

The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments

identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU

and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB

segment allows PLB masters DMA, XOR, and PCI to exchange large blocks of data with SDRAM and PCI without

interfering with the low latency PLB masters.

Bus features include:

• PLB

– 128-bit Data implementation of the PLB architecture

– Separate and simultaneous read and write data paths

– 64-bit address

– Simultaneous control, address, and data phases

– Four levels of pipelining

– Byte enable capability supporting unaligned transfers

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PowerPC 440SP Embedded Processor

– 32- and 64-byte burst transfers

– 166MHz, maximum 5.2GB/s (simultaneous read and write)

– Processor:Bus clock ratios of N:1 and N:2

• OPB

– Dynamic bus sizing: 32-, 16-, and 8-bit data path

– 32-bit address

– 83.33MHz, maximum 333MB/s

• DCR

– 32-bit data path

– 10-bit address

On-Chip SRAM/L2 Cache

Features include:

• Four banks of 64KB each for a total of 256KB

• Configurable as either L2 cache or SRAM

• Memory cycles supported:

– Single beat read and write, 1 to 16 bytes

– Quadword Read and Write burst for 12-bit master

– Guarded memory accesses on 4KB boundaries

• Sustainable 2.6GB/s peak bandwidth at 166MHz

• Use as an L2 cache improves processor performance and reduces the PLB load

– Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) PLB or by

software

– Data Array and Tag Array parity

– Unified data and instruction cache

– Four-way set associative

– 36-bit addressing

– Full LRU replacement algorithm

– Write through, look aside

• Use as Ethernet packet store allows Ethernet packets to be held for processing by the Ethernet core

DDR PCI-X Interface

The DDR PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local

memory. There are three separate interfaces supporting 32- and 64-bit PCI-X buses in DDR mode. All three

interfaces can be configured for either host or adapter mode. PCI 32/64-bit legacy mode, compatible with PCI

Version 2.3, is also supported.

Features include:

• PCI-X 2.0

– Split transactions

– Frequency to 266MHz

– 32- and 64-bit address/data bus

– ECC supported for 266MHz Mode 2 only

• PCI 2.3 backward compatibility

– Frequency to 66MHz

– 32- and 64-bit bus

• Can be the PCI Host Bus Bridge or an Adapter Device PCI interface

• Optional PCI arbitration function with PCI and PCI-X mode 1, supporting up to four external devices, that can

be disabled for use with an external arbiter

• Support for Message Signaled Interrupts (MSI) on both in- and out-bound interrupts

• Simple message passing capability

• Asynchronous to the PLB

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Data Sheet

PowerPC 440SP Embedded Processor

• PCI Power Management Version 1.1

• PCI arbitration function with PCI-X Mode 2 support (optional)

• PCI register set addressable both from on-chip processor and PCI device sides

• Ability to boot from PCI-X bus memory

• Error tracking/status

• Supports initiation of transfer to the following address spaces:

– Single beat I/O reads and writes

– Single beat and burst memory reads and writes

– Single beat configuration reads and writes (Type 0 and Type 1)

– Single beat special cycles

• PCI-X initialization sequence support (frequency & mode determination)

• Support for unexpected split completions

• Outbound transaction split discard timers

• Vital Product Data (VPD) support

• PCI-to-PCI opaque bridge

DDR1/DDR2 SDRAM Memory Controller

The DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete

devices. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The

DDR2 SDRAM controller interfaces to the PLB through a Memory Queue (MQ) function that includes six high-

speed 1KB FIFO buffers.

Features include:

• Registered and non-registered industry standard DIMMs

• DDR1 266-333-400

• DDR2 400-533-667

• 64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)

• 5.32GB/s peak bandwidth for the 64-bit interface

• 2.66GB/s peak bandwidth for the 32-bit interface

• Two chip (bank) select signals supporting two external banks

• CAS latencies of 2, 3, 4, 5, 6, and 7 supported

• Page mode accesses (up to 32 open pages) with configurable paging policy

• Look-ahead request queue with programmable depth of four commands.

• Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current

bank)

• Up to 4GB in two external banks

• Programmable address mapping and timing

• Hardware and software initiated self-refresh

• Sync DRAM configuration by means of mode register and extended mode register set commands

• Power management (self-refresh, suspend, sleep)

• Low Latency & High Bandwidth PLB ports

• Selectable PLB read response (immediate or deferred)

• Programmable Low Latency & High Bandwidth arbitration schemes

• High Bandwidth port has four 1KB read buffers and two1KB write buffers

• Low Latency port has four 128B read buffers and two 128B write buffers

External Peripheral Bus Controller (EBC)

Features include:

• Support 2MB Boot ROM

• Up to three ROM, EPROM, SRAM, Flash memory, and slave peripherals supported

• Burst and non-burst devices

• 8-bit data bus

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Data Sheet

PowerPC 440SP Embedded Processor

• 24-bit address, 16MB address space

• Peripheral Device pacing with external “Ready”

• Latch data on Ready, synchronous or asynchronous

• Programmable access timing per device

– 256 Wait States for non-burst

– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses

– Programmable CSon, CSoff relative to address

– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS

• Programmable address mapping

Ethernet Controller Interface

The Ethernet support interfaces to the physical layer, but the PHY is not included on the chip.

Features include:

• One 10/100/1000 interface running in full- and half-duplex modes

– One full Media Independent Interface (MII) with 4-bit parallel data transfer

– One Gigabit Media Independent Interface (GMII)

I2O/DMA Controller

The I20/DMA controller provides support for I20 messaging and two DMA controllers (DMA0 and DMA1). I2O

manages message frame address (MFA) FIFOs or queues in memory in response to I2O register reads and writes

and transfers message frames. The DMAs provide normal memory access support to ease the CPU burden.

I2O features include:

• I2O pull- and push-messaging methods

• Dynamic message frame size

• Programmable FIFO size (4096 64-bit MFAs maximum)

• 64-bit and 32-bit MFA sizes

• Three interrupt gathering methods

• Registered MFA prefetch and posting

• 32-bit inbound and outbound doorbell registers

• Four 32-bit scratch pad registers

DMA features include:

• Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)

• 512-byte/1KB buffering for DMA0/DMA1

• Simultaneous fill and drain (PLB read/write pipelining)

• Any source PLB address to any destination address

• No memory alignment restrictions on source or destination

• 32-byte command descriptor block

• Maximum transfer size of 16MB

• 64-bit addressing

• Prefetch indicators for PCI-X buffer management (DMA1 only)

Optional RAID 5 and RAID 6 Acceleration Hardware

The 440SP provides integrated acceleration hardware that implements high throughput RAID 5 and RAID 6

algorithms to compute the single parity P for RAID 5, and dual parity P & Q for RAID 6. RAID 5 is used to recover

data in the case of a single disk drive failure, and RAID 6 provides for data recovery if two disk drives fail.

The 440SP offers a choice of two XOR engines for computing the P parity. The first choice is available with the

XOR/DMA2 acceleration unit and is used for RAID 5. The second choice for XOR parity computation, along with

8

the RAID 6 Galois Field GF(2 )-based polynomial computations, resides inside the Memory Queue functional block

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Data Sheet

PowerPC 440SP Embedded Processor

of the Memory Controller unit.

The RAID 5 and RAID 6 parity computations performed in the Memory Queue are assisted by the two-channel

DMA engine of the I2O/DMA controller unit, designated as DMA0 and DMA1. The RAID acceleration hardware

also provides various alternatives for balancing load and performance, depending on customer-specific application

firmware. The two-way crossbar bus architecture can perform data read and write operations simultaneously,

resulting in extremely high throughput.

RAID 6 capability is available only with the RAID-enabled part numbers (PPC440SP-RpCfffC) as indicated in the

ordering information section of this data sheet.

For more information about the RAID 6 implementation, description, and configuration of the acceleration

hardware, refer to the following AMCC documents:

• PowerPC 440SP/440SPe RAID Support Application Note

• PowerPC 440SP RAID Addendum to the User’s Manual

XOR/DMA2 Controller

The XOR/DMA2 controller performs the XOR functions needed to support RAID 5 applications including parity

generation and check functions used across data stripes in a RAID 5 system.

Features include:

• Computes a bit-wise XOR on up to 16 data streams with result stored in designated target

• Performs XOR check on up to 16 data streams

• Driven by a linked list Command Block structure specifying control information, source operands, target

operand, status information, and link

• Source and target streams may reside anywhere in PLB address space.

• Provides completion status per Command Block to be handled by software at a later time

• 96-byte and 160-byte Command Block formats are supported

• No memory alignment restrictions on operands or target

• Internal register arrays and data buffers are parity protected

• Can be used as a DMA controller (DMA2) with single source and target addresses

Serial Port

‚

The serial port is compatible with the NS 16570 UART interface.

Features include:

• One 8-pin, one 4-pin, and one 2-pin interfaces are provided

• Selectable internal or external serial clock to allow wide range of baud rates

• Register compatibility with 16750 register set

• Complete status reporting capability

• Fully programmable serial-interface characteristics

IIC Bus Interface

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Data Sheet

PowerPC 440SP Embedded Processor

Features include:

• Two IIC interfaces provided

‚

2

• Support for Philips Semiconductors I C Specification, dated 1995

• Operation at 100kHz or 400kHz

• 8-bit data

• 10- or 7-bit address

• Slave transmitter and receiver

• Master transmitter and receiver

• Multiple bus masters

• Supports fixed V IIC interface

DD

• Two independent 4 x 1 byte data buffers

• Twelve memory-mapped, fully programmable configuration registers

• One programmable interrupt request signal

• Full management of all IIC bus protocols

• Programmable error recovery

• Port 0 supports serial Bootstrap ROM with default parameters override at initialization

General Purpose Timers (GPT)

Provides a time base counter and system timers additional to those defined in the processor core.

• 32-bit time base counter driven by the OPB bus clock

• Seven 32-bit compare timers

General Purpose IO (GPIO) Controller

• Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB

bus master accesses.

• The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO

capabilities acts as a GPIO or is used for another purpose.

• Each GPIO output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain).

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Data Sheet

PowerPC 440SP Embedded Processor

Universal Interrupt Controller (UIC)

Two cascaded Universal Interrupt Controllers (UIC) process internal on-chip and external processor interrupts.

Note: Processor specific interrupts (for example, page faults) do not use UIC resources.

Features include:

• 6 external interrupts

• 56 internal interrupts

• Edge-triggered or level-sensitive

• Positive- or negative-active

• Non-critical or critical interrupt to the on-chip processor core

• Programmable interrupt priority ordering

• Programmable critical interrupt vector for faster vector processing

JTAG

Features include:

• IEEE 1149.1 Test Access Port

• IBM RISCWatch Debugger support

• JTAG Boundary Scan Description Language (BSDL)

AMCC Proprietary

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Data Sheet

PowerPC 440SP Embedded Processor

Figure 3. 29mm, 783-Ball FC-PBGA Core Package

Top View

A1 Corner

1

24

A

®

PPC440SP

Part Number

xpCfffC

AAAAAAAA

Lot Number

AD

Note: All dimensions are in mm.

Bottom View

29.0 ± 0.2

AH

1.00 TYP

AG

AF

AD

AB

Y

AE

AC

AA

W

U

V

T

R

29.0 ± 0.2

P

N

M

K

L

J

H

G

E

F

D

C

B

A

0.4 MIN

3.27 MAX

19 21 23 25 27

01 03 05 07 09 11 13 15 17

08 10

06

12 14

16 18

04

22

02

20 24 26

28

0.6 ± 0.1 SOLDERBALL x 783

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Data Sheet

PowerPC 440SP Embedded Processor

Signal Lists

This section contains two tables that list external signals.

Table 3 lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal

appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate

signal or signals in brackets.

Multiplexed signals appear alphabetically multiple times in the list—once for each signal name on the ball. The

page number listed gives the page in “Signal Functional Description” on page 56 where the signals in the indicated

interface group begin.

Table 4 on page 47 lists all the external signals in order by ball (pin) number.

Signal List—Alphabetic Order

Table 3. Signals Listed Alphabetically (Sheet 1 of 30)

Signal Name

Ball

B01

Interface Group

Page

A1GND

A2GND

A1V_DD

AG28

C01

A2V_DD

AF28

AG01

AF01

B28

AP0GND

AP0V_DD

Power

62

AP1GND

AP1V_DD

C28

AP2GND

AP2V_DD

T01

R01

BA0

AD21

AE20

AE25

T23

BA1

BA2

BankSel0

BankSel1

CAS

DDR SDRAM

58

P22

AH25

AE23

AE24

ClkEn0

ClkEn1

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 2 of 30)

Signal Name

Ball

AE26

AA26

V25

Interface Group

Page

DM0

DM1

DM2

DM3

P26

DM4

K27

DM5

M21

R21

DM6

DM7

U19

DM8

AA24

AD26

AD25

AA28

AA27

U26

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

DDR SDRAM

58

U25

N27

N28

K25

K26

L25

L26

R26

R25

W27

W26

AB26

AB25

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 3 of 30)

Signal Name

Ball

AC24

Y23

Interface Group

Page

ECC0

ECC1

ECC2

ECC3

ECC4

ECC5

ECC6

ECC7

Y21

AC23

AD23

AA23

W19

DDR SDRAM

58

AF20

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 4 of 30)

Signal Name

Ball

D02

Interface Group

Page

EMCCD

EMCCrS

E03

D01

E04

D12

D03

F04

G04

F03

G01

H03

H02

F05

F06

F07

J01

EMCMDClk

EMCMDIO

EMCRefClk

EMCRxClk

EMCRxD0

EMCRxD1

EMCRxD2

EMCRxD3

EMCRxD4

EMCRxD5

EMCRxD6

EMCRxD7

EMCRxDV

EMCRxErr

EMCTxClk

Ethernet

59

E01

B08

F02

F01

H01

G03

H04

K04

K03

A02

C04

A03

H11

EMCGTxClk

EMCTxD0

EMCTxD1

EMCTxD2

EMCTxD3

EMCTxD4

EMCTxD5

EMCTxD6

EMCTxD7

EMCTxEn

EMCTxErr

ExtReset

External Slave Peripheral

59

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 5 of 30)

Signal Name

Ball

B02

Interface Group

Page

GND

B05

B09

B20

B24

B27

C13

C16

E02

E07

E11

E18

E22

E27

F14

F15

G05

G09

G13

G16

G20

G24

J02

J07

J11

J18

J22

J27

L05

L09

L13

L16

Power

62

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 6 of 30)

Signal Name

Ball

L20

Interface Group

Page

GND

L24

N03

N07

N11

N14

N15

N18

N22

N26

P06

P13

P16

P23

R06

R13

R16

R23

T03

T07

T11

T14

T15

T18

T22

T26

V05

V09

V13

V16

V20

V24

Y02

Y07

Power

62

22

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 7 of 30)

Signal Name

Ball

Y11

Interface Group

Page

GND

Y18

Y22

Y27

AB05

AB09

AB13

AB16

AB20

AB24

AC14

AC15

AD02

AD07

AD11

AD18

AD22

AD27

AF13

AF16

AG02

AG05

AG09

AG20

AG24

AG27

Power

62

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 8 of 30)

Signal Name

[GPIO00] [TrcClk] PCIX0Req2

[GPIO01] [TrcBS0] PCIX0Req3

[GPIO02] [TrcBS1] PCIX0Gnt2

[GPIO03] [TrcBS2] PCIX0Gnt3

[GPIO04] [TrcES0] PCIX1Req2

[GPIO05] [TrcES1] PCIX1Req3

[GPIO06] [TrcES2] PCIX1Gnt2

[GPIO07] [TrcES3] PCIX1Gnt3

[GPIO08] [TrcES4] PerReady

[GPIO09] PerCS1 [TrcTS0]

[GPIO10] PerCS2 [TrcTS1]

[GPIO11] IRQ0 [TrcTS2]

[GPIO12] IRQ1 [TrcTS3]

[GPIO13] IRQ2 [TrcTS4]

[GPIO14] IRQ3 [TrcTS5]

[GPIO15] IRQ4 [TrcTS6]

[GPIO16] IRQ5 [UART2_Rx]

[GPIO17] PerBE0 [UART2_Tx]

[GPIO18] PCIX0Gnt0

Ball

AA12

Y12

Interface Group

Page

AC13

AF11

C23

E23

D21

D23

G12

E12

H10

C07

C06

A05

C05

D06

D05

R09

AF14

AG13

AH11

AG12

B19

System

61

[GPIO19] PCIX0Gnt1

[GPIO20] PCIX0Req0

[GPIO21] PCIX0Req1

[GPIO22] PCIX1Gnt0

[GPIO23] PCIX1Gnt1

C19

C20

C22

P01

[GPIO24] PCIX1Req0

[GPIO25] PCIX1Req1

[GPIO26] PCIX2Gnt0

[GPIO27] PCIX2Gnt1

P03

[GPIO28] PCIX2Req0

U05

N04

A07

[GPIO29] PCIX2Req1

[GPIO30] UART1_Rx

[GPIO31] UART1_Tx

A06

Halt

K18

HISRRst

B06

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 9 of 30)

Signal Name

Ball

D09

Interface Group

Page

IIC0SClk

IIC0SDA

IIC1SClk

IIC1SDA

E08

IIC Peripheral

60

F08

E10

IRQ0 [GPIO11] [TrcTS2]

IRQ1 [GPIO12] [TrcTS3]

IRQ2 [GPIO13] [TrcTS4]

IRQ3 [GPIO14] [TrcTS5]

IRQ4 [GPIO15] [TrcTS6]

IRQ5 [GPIO16] [UART2_Rx]

MemAddr00

C07

C06

A05

Interrupts

60

C05

D06

D05

AF23

AE21

AD19

AE19

AH22

AH23

AE22

AF21

AF22

AG23

AG21

AF19

AH20

AH21

AF24

AG26

AG25

AH26

AH27

MemAddr01

MemAddr02

MemAddr03

MemAddr04

MemAddr05

MemAddr06

MemAddr07

MemAddr08

MemAddr09

DDR SDRAM

58

MemAddr10

MemAddr11

MemAddr12

MemAddr13

MemAddr14

MemClkOut0

MemClkOut1

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 10 of 30)

Signal Name

Ball

AD28

AE27

AF27

AC26

AC27

AE28

AF25

AC25

Y26

Interface Group

Page

MemData00

MemData01

MemData02

MemData03

MemData04

MemData05

MemData06

MemData07

MemData08

MemData09

MemData10

MemData11

MemData12

MemData13

MemData14

MemData15

MemData16

MemData17

MemData18

MemData19

MemData20

MemData21

MemData22

MemData23

MemData24

MemData25

MemData26

MemData27

MemData28

MemData29

MemData30

MemData31

AB28

AC28

Y28

Y25

AA25

AB23

W25

U27

DDR SDRAM

58

V28

W28

T25

T27

V26

W23

T28

N25

P28

R28

M27

M26

P25

U24

M25

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 11 of 30)

Signal Name

Ball

J26

Interface Group

Page

MemData32

MemData33

MemData34

MemData35

MemData36

MemData37

MemData38

MemData39

MemData40

MemData41

MemData42

MemData43

MemData44

MemData45

MemData46

MemData47

MemData48

MemData49

MemData50

MemData51

MemData52

MemData53

MemData54

MemData55

MemData56

MemData57

MemData58

MemData59

MemData60

MemData61

MemData62

MemData63

K28

L28

H28

H27

J28

P21

H26

P20

M23

M22

N23

N21

K24

M24

N19

U23

R22

R24

U22

T19

R20

P24

T21

W22

U20

U21

W24

W21

V23

V21

W20

AB21

AC21

DDR SDRAM

58

MemDCFdbkD

MemDCFdbkR

AMCC Proprietary

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 12 of 30)

Signal Name

Ball

AA22

AC22

AA20

AA21

A01

Interface Group

Page

58

MemODT0

MemODT1

MemVRef0

MemVRef1

No ball

DDR SDRAM

A physical ball does not exist at this coordinate

na

OV_DD

B07

OV_DD

B11

B14

B15

C03

G02

G07

G11

K14

K15

L02

L07

L11

P10

P14

Power

62

28

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 13 of 30)

Signal Name

Ball

R14

Interface Group

Page

P0V_DD

P1V_DD

P2V_DD

W14

W15

AB07

AB11

AB18

AB22

AG07

AG11

AG14

AG15

AG18

AG22

B18

B22

C26

Power

62

G18

G22

G27

L18

L22

L27

P15

P02

R02

R10

V02

V07

V11

AB02

AF03

AMCC Proprietary

29

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 14 of 30)

Signal Name

PCIX0Ack64 [PCIX0ECC1]

PCIX0AD00

PCIX0AD01

PCIX0AD02

PCIX0AD03

PCIX0AD04

PCIX0AD05

PCIX0AD06

PCIX0AD07

PCIX0AD08

PCIX0AD09

PCIX0AD10

PCIX0AD11

PCIX0AD12

PCIX0AD13

PCIX0AD14

PCIX0AD15

PCIX0AD16

PCIX0AD17

PCIX0AD18

PCIX0AD19

PCIX0AD20

PCIX0AD21

PCIX0AD22

PCIX0AD23

PCIX0AD24

PCIX0AD25

PCIX0AD26

PCIX0AD27

PCIX0AD28

PCIX0AD29

PCIX0AD30

PCIX0AD31

Ball

AH06

AE12

AE11

AE10

AE09

AF10

AH08

AH09

AA11

AC09

AA09

AC08

AD08

AD10

AA10

AB10

AH07

AF06

AF07

AE08

AF05

AF04

AD06

AG04

AF08

AH02

AH03

AF02

AE03

AD04

AE05

AE01

AE02

Interface Group

Page

PCI-X0

56

30

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 15 of 30)

Signal Name

Ball

AE18

AF18

AH19

AG19

AD17

AA18

W18

Interface Group

Page

PCIX0AD32

PCIX0AD33

PCIX0AD34

PCIX0AD35

PCIX0AD36

PCIX0AD37

PCIX0AD38

PCIX0AD39

PCIX0AD40

PCIX0AD41

PCIX0AD42

PCIX0AD43

PCIX0AD44

PCIX0AD45

PCIX0AD46

PCIX0AD47

PCIX0AD48

PCIX0AD49

PCIX0AD50

PCIX0AD51

PCIX0AD52

PCIX0AD53

PCIX0AD54

PCIX0AD55

PCIX0AD56

PCIX0AD57

PCIX0AD58

PCIX0AD59

PCIX0AD60

PCIX0AD61

PCIX0AD62

PCIX0AD63

AC20

AE17

Y17

W17

AA17

AC19

AB17

AC17

AB19

AC18

AH18

AG16

AF17

AF15

AH15

AE15

AD15

AB14

AB15

AA14

Y15

PCI-X0

56

W16

AA16

AC16

AA15

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 16 of 30)

Signal Name

Ball

AF09

AG10

AE07

AE06

AH16

AG17

AE16

AE14

AA08

Y19

Interface Group

Page

PCIX0BE0

PCIX0BE1

PCIX0BE2

PCIX0BE3

PCIX0BE4

PCIX0BE5

PCIX0BE6

PCIX0BE7

PCIX0CalG0

PCIX0CalG1

PCIX0CalR0

AB08

AA19

AA13

AF12

Y10

PCIX0CalR1

PCIX0Cap

PCIX0Clk

PCIX0DevSel

[PCIX0ECC0] PCIX0Par

[PCIX0ECC1] PCIX0Ack64

PCIX0ECC2

AG06

AH06

AG03

AH04

AH05

AD03

AG08

AH14

AC12

AF14

AG13

AC13

AF11

Y14

PCI-X0

56

PCIX0ECC3

PCIX0ECC4

PCIX0ECC5

[PCIX0ECC6] PCIX0Req64

[PCIX0ECC7] PCIX0Par64

PCIX0Frame

PCIX0Gnt0 [GPIO18]

PCIX0Gnt1 [GPIO19]

PCIX0Gnt2 [GPIO02] [TrcBS1]

PCIX0Gnt3 [GPIO03] [TrcBS2]

PCIX0IDSel

PCIX0INTA

AB12

W13

PCIX0IRDY

32

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 17 of 30)

Signal Name

PCIX0M66En

Ball

AD14

AG06

AH14

W11

Interface Group

Page

PCIX0Par [PCIX0ECC0]

PCIX0Par64 [PCIX0ECC7]

PCIX0PErr

PCIX0Req0 [GPIO20]

PCIX0Req1 [GPIO21]

PCIX0Req2 [GPIO00] [TrcClk]

PCIX0Req3 [GPIO01] [TrcBS0]

PCIX0Req64 [PCIX0ECC6]

PCIX0Reset

AH11

AG12

AA12

Y12

PCI-X0

56

AG08

AH13

AD12

AE13

W12

PCIX0SErr

PCIX0Stop

PCIX0TRDY

PCIX0VC

AH10

AC11

AC10

PCIX0VRef0

PCIX0VRef1

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 18 of 30)

Signal Name

PCIX1Ack64 [PCIX1ECC1]

PCIX1AD00

PCIX1AD01

PCIX1AD02

PCIX1AD03

PCIX1AD04

PCIX1AD05

PCIX1AD06

PCIX1AD07

PCIX1AD08

PCIX1AD09

PCIX1AD10

PCIX1AD11

PCIX1AD12

PCIX1AD13

PCIX1AD14

PCIX1AD15

PCIX1AD16

PCIX1AD17

PCIX1AD18

PCIX1AD19

PCIX1AD20

PCIX1AD21

PCIX1AD22

PCIX1AD23

PCIX1AD24

PCIX1AD25

PCIX1AD26

PCIX1AD27

PCIX1AD28

PCIX1AD29

PCIX1AD30

PCIX1AD31

Ball

K23

Interface Group

Page

D18

C18

F18

A19

F16

H20

F20

F21

C17

D16

B17

B16

E17

H19

F19

G19

A15

C14

C15

A16

D15

H17

G17

H18

D13

B13

B12

C12

E15

K16

H16

J15

PCI-X1

56

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 19 of 30)

Signal Name

Ball

E28

Interface Group

Page

PCIX1AD32

PCIX1AD33

PCIX1AD34

PCIX1AD35

PCIX1AD36

PCIX1AD37

PCIX1AD38

PCIX1AD39

PCIX1AD40

PCIX1AD41

PCIX1AD42

PCIX1AD43

PCIX1AD44

PCIX1AD45

PCIX1AD46

PCIX1AD47

PCIX1AD48

PCIX1AD49

PCIX1AD50

PCIX1AD51

PCIX1AD52

PCIX1AD53

PCIX1AD54

PCIX1AD55

PCIX1AD56

PCIX1AD57

PCIX1AD58

PCIX1AD59

PCIX1AD60

PCIX1AD61

PCIX1AD62

PCIX1AD63

F28

F27

D28

G28

M20

M19

L23

A27

G26

C27

D27

F26

K22

K21

K20

H25

J25

PCI-X1

56

E25

B26

E26

J23

J21

H23

B25

C24

D24

C25

A26

A25

D25

F24

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 20 of 30)

Signal Name

Ball

F17

Interface Group

Page

PCIX1BE0

PCIX1BE1

PCIX1BE2

PCIX1BE3

PCIX1BE4

PCIX1BE5

PCIX1BE6

PCIX1BE7

D17

D14

E14

D26

F25

G25

F22

L19

G14

L21

H14

G21

E21

D19

K19

K23

H21

H22

H15

F23

H24

A24

B21

B19

C19

D21

D23

B23

A22

D22

G23

PCIX1CalG0

PCIX1CalG1

PCIX1CalR0

PCIX1CalR1

PCIX1Cap

PCIX1Clk

PCIX1DevSel

[PCIX1ECC0] PCIX1Par

[PCIX1ECC1] PCIX1Ack64

PCIX1ECC2

PCI-X1

56

PCIX1ECC3

PCIX1ECC4

PCIX1ECC5

[PCIX1ECC6] PCIX1Req64

[PCIX1ECC7] PCIX1Par64

PCIX1Frame

PCIX1Gnt0 [GPIO22]

PCIX1Gnt1 [GPIO23]

PCIX1Gnt2 [GPIO06] [TrcES2]

PCIX1Gnt3 [GPIO07] [TrcES3]

PCIX1IDSel

PCIX1INTA

PCIX1IRDY

PCIX1M66En

36

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 21 of 30)

Signal Name

PCIX1Par [PCIX1ECC0]

PCIX1Par64 [PCIX1ECC7]

PCIX1PErr

Ball

K19

Interface Group

Page

A24

D20

C20

C22

C23

E23

H24

A20

A23

C21

E19

A21

J17

PCIX1Req0 [GPIO24]

PCIX1Req1 [GPIO25]

PCIX1Req2 [GPIO04] [TrcES0]

PCIX1Req3 [GPIO05] [TrcES1]

PCIX1Req64 [PCIX1ECC6]

PCIX1Reset

PCI-X1

56

PCIX1SErr

PCIX1Stop

PCIX1TRDY

PCIX1VC

PCIX1VRef0

PCIX1VRef1

K17

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 22 of 30)

Signal Name

Ball

AC03

AC04

AC05

AD01

AB01

AB04

AC01

AC02

Y04

Interface Group

Page

PCIX2AD00

PCIX2AD01

PCIX2AD02

PCIX2AD03

PCIX2AD04

PCIX2AD05

PCIX2AD06

PCIX2AD07

PCIX2AD08

PCIX2AD09

PCIX2AD10

PCIX2AD11

PCIX2AD12

PCIX2AD13

PCIX2AD14

PCIX2AD15

PCIX2AD16

PCIX2AD17

PCIX2AD18

PCIX2AD19

PCIX2AD20

PCIX2AD21

PCIX2AD22

PCIX2AD23

PCIX2AD24

PCIX2AD25

PCIX2AD26

PCIX2AD27

PCIX2AD28

PCIX2AD29

PCIX2AD30

PCIX2AD31

PCIX2BE0

AA01

Y03

Y01

AA03

AA04

AB06

AC06

W02

W01

W03

W04

V04

PCI-X2

56

Y06

Y08

AA05

V01

U03

T04

T02

U04

W07

W06

W05

AB03

AA02

PCIX2BE1

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 23 of 30)

Signal Name

Ball

V03

Interface Group

Page

PCIX2BE2

PCIX2BE3

U02

W08

W09

T08

PCIX2CalG0

PCIX2CalR0

PCIX2Cap

PCIX2Clk

R03

M03

AC07

W10

AA07

U09

N01

AA06

AE04

U08

P01

P03

T10

PCIX2DevSel

[PCIX2ECC0] PCIX2Par

PCIX2ECC1

PCIX2ECC2

PCIX2ECC3

PCIX2ECC4

PCIX2ECC5

PCIX2ECC6

PCIX2Frame

PCIX2Gnt0 [GPIO26]

PCIX2Gnt1 [GPIO27]

PCIX2IDSel

PCI-X2

56

PCIX2INTA

U07

P04

T06

PCIX2IRDY

PCIX2M66En

PCIX2Par [PCIX2ECC0]

PCIX2PErr

AC07

U06

U05

N04

V06

V08

M02

N02

V10

R04

U10

PCIX2Req0 [GPIO28]

PCIX2Req1 [GPIO29]

PCIX2Reset

PCIX2SErr

PCIX2Stop

PCIX2TRDY

PCIX2VC

PCIX2VRef0

PCIX2VRef1

AMCC Proprietary

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 24 of 30)

Signal Name

Ball

J04

Interface Group

Page

PerAddr00

PerAddr01

PerAddr02

PerAddr03

PerAddr04

PerAddr05

PerAddr06

PerAddr07

PerAddr08

PerAddr09

PerAddr10

PerAddr11

PerAddr12

PerAddr13

PerAddr14

PerAddr15

PerAddr16

PerAddr17

PerAddr18

PerAddr19

PerAddr20

PerAddr21

PerAddr22

PerAddr23

K06

K05

M08

L06

M07

L08

K07

K08

M05

N08

N06

P08

P05

P07

L03

L04

L01

M04

K01

K02

R07

R05

R08

R09

B04

A04

M06

E12

H10

External Slave Peripheral

59

PerBE0 [GPIO17] [UART2_Tx]

PerBLast

PerClk

PerCS0

PerCS1 [GPIO09] [TrcTS0]

PerCS2 [GPIO10] [TrcTS1]

40

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 25 of 30)

Signal Name

Ball

H05

Interface Group

Page

PerData0

PerData1

PerData2

PerData3

PerData4

PerData5

PerData6

PerData7

PerErr

J08

H07

D04

G08

E06

G06

J06

External Slave Peripheral

59

B03

F12

C02

G12

H06

K10

M12

M17

U12

U17

AH24

PerOE

PerPar0

PerReady [GPIO08] [TrcES4]

PerR/W

PerWE

PSRO

RAS

PSRO

62

58

DDR SDRAM

AMCC Proprietary

41

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 26 of 30)

Signal Name

Ball

D07

Interface Group

Page

Reserved

F09

F13

H08

H09

H13

J10

J12

J14

K09

K11

K12

K13

L10

L12

L14

L15

L17

M09

M10

M11

M13

M14

M15

M16

M18

N10

N12

N17

P09

P11

P12

P17

Reserved

62

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Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 27 of 30)

Signal Name

Ball

P18

Interface Group

Page

Reserved

SV_DD

R11

R12

R17

R18

T12

T17

U11

U13

U14

U15

U16

U18

V12

V14

V15

V17

P19

Reserved

62

SV_DD

P27

R15

R19

R27

V18

V22

V27

AB27

Power

62

AF26

J03

SysClk

SysErr

J19

System

61

SysPartSel

SysReset

A14

G15

AMCC Proprietary

43

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 28 of 30)

Signal Name

Ball

D10

Interface Group

Page

TCK

TDI

A10

D11

A18

D08

C10

AA12

Y12

AC13

AF11

C23

E23

D21

D23

G12

E12

H10

C07

C06

A05

C05

D06

B10

C09

A08

C11

A11

A13

F11

H12

C08

JTAG

61

TDO

TestEn

TmrClk

TMS

System

JTAG

61

[TrcClk] [GPIO00] PCIX0Req2

[TrcBS0] [GPIO01] PCIX0Req3

[TrcBS1] [GPIO02] PCIX0Gnt2

[TrcBS2] [GPIO03] PCIX0Gnt3

[TrcES0] [GPIO04] PCIX1Req2

[TrcES1] [GPIO05] PCIX1Req3

[TrcES2] [GPIO06] PCIX1Gnt2

[TrcES3] [GPIO07] PCIX1Gnt3

[TrcES4] [GPIO08] PerReady

[TrcTS0] PerCS1 [GPIO09]

[TrcTS1] PerCS2 [GPIO10]

[TrcTS2] [GPIO11] IRQ0

[TrcTS3] [GPIO12] IRQ1

[TrcTS4] [GPIO13] IRQ2

[TrcTS5] [GPIO14] IRQ3

[TrcTS6] [GPIO15] IRQ4

TRST

Trace

61

JTAG

61

UART0_CTS

UART0_DCD

UART0_DSR

UART0_DTR

UART Peripheral

60

UART0_RI

UART0_RTS

UART0_Rx

UART0_Tx

44

AMCC Proprietary

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 29 of 30)

Signal Name

UART1_DSR/CTS

Ball

F10

Interface Group

Page

UART1_RTS/DTR

G10

A07

A06

D05

R09

A09

A12

A17

A28

E05

E09

E13

E16

E20

E24

J05

J09

J13

J16

J20

J24

M01

M28

N05

N09

N13

N16

N20

N24

T05

T09

UART1_Rx [GPIO30]

UART1_Tx [GPIO31]

UART Peripheral

60

[UART2_Rx] [GPIO16] IRQ5

[UART2_Tx] [GPIO17] PerBE0

UARTSerClk

V_DD

Power

62

AMCC Proprietary

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Table 3. Signals Listed Alphabetically (Sheet 30 of 30)

Signal Name

Ball

T13

Interface Group

Page

V_DD

WE

T16

T20

T24

U01

U28

Y05

Y09

Y13

Y16

Y20

Power

62

Y24

AD05

AD09

AD13

AD16

AD20

AD24

AH01

AH12

AH17

AH28

V19

DDR SDRAM

58

46

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Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Signal List—Ball Assignment Order

In the following table, only the primary (default) signal name is shown for each pin. Multiplexed pins are marked

with an asterisk (*). To determine the other signals that share a pin, look up the primary signal name in Table 3 on

page 17.

Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)

Ball

A01

A02

A03

A04

A05

Signal Name

Ball

B01

B02

B03

B04

B05

Signal Name

Ball

C01

C02

C03

C04

C05

Signal Name

A1V_DD

Ball

D01

D02

D03

D04

D05

Signal Name

EMCMDClk

No ball

A1GND

EMCTxD7

EMCTxErr

PerClk

GND

PerPar0

OV_DD

EMCCD

EMCRxClk

PerData3

IRQ5*

PerErr

PerBLast

GND

EMCTxEn

IRQ3*

IRQ2*

A06

B06

HISRRst

OV_DD

C06

D06

UART1_Tx*

IRQ1*

IRQ4*

A07

A08

A09

A10

A11

B07

B08

B09

B10

B11

C07

C08

C09

C10

C11

D07

D08

D09

D10

D11

Reserved

TmrClk

IIC0SClk

TCK

UART1_Rx*

UART0_DCD

UARTSerClk

TDI

IRQ0*

EMCGTxClk

GND

UART0_Tx

UART0_CTS

TMS

TRST

OV_DD

UART0_DTR

V_DD

UART0_DSR

TDO

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

PCIX1AD26

PCIX1AD25

OV_DD

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

PCIX1AD27

GND

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

EMCRefClk

PCIX1AD24

PCIX1BE2

UART0_RI

SysPartSel

PCIX1AD17

PCIX1AD18

GND

OV_DD

PCIX1AD16

PCIX1AD19

V_DD

PCIX1AD20

PCIX1AD09

PCIX1BE1

PCIX1AD11

PCIX1AD10

P1V_DD

PCIX1AD08

PCIX1AD01

TestEn

PCIX1AD00

PCIX1DevSel

PCIX1PErr

PCIX1Gnt2*

PCIX1IRDY

PCIX1AD03

PCIX1Reset

PCIX1VC

PCIX1Gnt0*

GND

PCIX1Gnt1*

PCIX1Req0*

PCIX1Stop

PCIX1Frame

P1V_DD

A22

A23

PCIX1INTA

PCIX1SErr

B22

B23

C22

C23

D22

D23

PCIX1Req1*

PCIX1Req2*

PCIX1IDSel

PCIX1Gnt3*

PCIX1AD58

PCIX1AD62

PCIX1BE4

A24

A25

A26

A27

A28

B24

B25

B26

B27

B28

GND

C24

C25

C26

C27

C28

PCIX1AD57

PCIX1AD59

P1V_DD

D24

D25

D26

D27

D28

PCIX1Par64*

PCIX1AD61

PCIX1AD60

PCIX1AD40

V_DD

PCIX1AD56

PCIX1AD51

GND

PCIX1AD42

AP1V_DD

PCIX1AD43

PCIX1AD35

AP1GND

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Data Sheet

PowerPC 440SP Embedded Processor

Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)

Ball

E01

E02

E03

E04

E05

E06

E07

E08

E09

Signal Name

Ball

F01

F02

F03

F04

F05

F06

F07

F08

F09

Signal Name

Ball

G01

G02

G03

G04

G05

G06

G07

G08

G09

Signal Name

EMCRxD3

Ball

H01

H02

H03

H04

H05

H06

H07

H08

H09

Signal Name

EMCTxD2

EMCTxClk

EMCTxD1

OV_DD

GND

EMCTxD0

EMCRxD2

EMCRxD0

EMCRxD6

EMCRxD7

EMCRxDV

IIC1SClk

EMCRxD5

EMCRxD4

EMCTxD4

PerData0

PerR/W

EMCCrS

EMCMDIO

V_DD

EMCTxD3

EMCRxD1

GND

PerData5

GND

PerData6

OV_DD

PerData2

Reserved

IIC0SDA

V_DD

PerData4

GND

Reserved

E10

E11

E12

IIC1SDA

GND

F10

F11

F12

UART1_DSR/CTS

UART0_RTS

PerOE

G10

G11

G12

UART1_RTS/DTR

OV_DD

H10

H11

H12

PerCS2*

ExtReset

UART0_Rx

PerCS1*

V_DD

PerReady*

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

Reserved

GND

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

GND

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

Reserved

PCIX1BE3

PCIX1AD28

V_DD

PCIX1CalG1

SysReset

GND

PCIX1CalR1

PCIX1ECC4

PCIX1AD30

PCIX1AD21

PCIX1AD23

PCIX1AD13

PCIX1AD05

PCIX1ECC2

PCIX1ECC3

GND

PCIX1AD04

PCIX1BE0

PCIX1AD02

PCIX1AD14

PCIX1AD06

PCIX1AD07

PCIX1BE7

PCIX1AD12

GND

PCIX1AD22

P1V_DD

PCIX1TRDY

V_DD

PCIX1AD15

GND

PCIX1Clk

GND

PCIX1Cap

P1V_DD

E23

F23

PCIX1ECC5

G23

PCIX1M66En

H23

PCIX1AD55

PCIX1Req3*

V_DD

E24

E25

E26

E27

E28

F24

F25

F26

F27

F28

PCIX1AD63

PCIX1BE5

G24

G25

G26

G27

G28

GND

H24

H25

H26

H27

H28

PCIX1Req64*

PCIX1AD48

MemData39

MemData36

MemData35

PCIX1AD50

PCIX1AD52

GND

PCIX1BE6

PCIX1AD41

P1V_DD

PCIX1AD44

PCIX1AD34

PCIX1AD33

PCIX1AD32

PCIX1AD36

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Data Sheet

PowerPC 440SP Embedded Processor

Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

PerAddr17

Ball

Signal Name

V_DD

J01

EMCRxErr

K01

PerAddr19

L01

M01

OV_DD

J02

J03

J04

J05

J06

J07

J08

J09

J10

J11

J12

J13

GND

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

K12

K13

PerAddr20

EMCTxD6

EMCTxD5

PerAddr02

PerAddr01

PerAddr07

PerAddr08

Reserved

PerWE

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

L12

L13

M02 PCIX2Stop

M03 PCIX2DevSel

M04 PerAddr18

M05 PerAddr09

M06 PerCS0

SysClk

PerAddr00

V_DD

PerAddr15

PerAddr16

GND

PerData7

GND

PerAddr04

OV_DD

M07 PerAddr05

M08 PerAddr03

M09 Reserved

M10 Reserved

M11 Reserved

M12 PSRO

PerData1

V_DD

PerAddr06

GND

Reserved

GND

Reserved

OV_DD

Reserved

OV_DD

Reserved

V_DD

Reserved

GND

M13 Reserved

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

Reserved

PCIX1AD31

V_DD

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

Reserved

M14 Reserved

M15 Reserved

M16 Reserved

M17 PSRO

OV_DD

PCIX1AD29

PCIX1VRef1

Halt

GND

PCIX1VRef0

GND

Reserved

P1V_DD

M18 Reserved

M19 PCIX1AD38

M20 PCIX1AD37

M21 DM5

SysErr

PCIX1CalG0

PCIX1Par*

PCIX1AD47

PCIX1AD46

PCIX1AD45

V_DD

GND

PCIX1AD54

GND

PCIX1CalR0

P1V_DD

M22 MemData42

M23 MemData41

PCIX1AD53

V_DD

PCIX1AD39

PCIX1Ack64*

J24

J25

J26

J27

K24

K25

K26

K27

MemData45

DQS4

L24

L25

L26

L27

GND

M24 MemData46

M25 MemData31

M26 MemData28

M27 MemData27

PCIX1AD49

MemData32

GND

DQS5

P1V_DD

DQS4

DM4

V_DD

J28

MemData37

K28

MemData33

L28

MemData34

M28

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Data Sheet

PowerPC 440SP Embedded Processor

Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7)

Ball

N01

N02

N03

N04

Signal Name

Ball

P01

P02

P03

P04

Signal Name

Ball

R01

R02

R03

R04

Signal Name

AP2V_DD

Ball

T01

T02

T03

T04

Signal Name

AP2GND

PCIX2ECC4

PCIX2Gnt0*

P2V_DD

PCIX2TRDY

GND

PCIX2AD27

GND

PCIX2Clk

PCIX2VRef0

PCIX2Gnt1*

PCIX2IRDY

PCIX2AD26

V_DD

PCIX2Req1*

V_DD

N05

N06

N07

N08

N09

P05

P06

P07

P08

P09

PerAddr13

GND

R05

R06

R07

R08

R09

PerAddr22

GND

T05

T06

T07

T08

T09

PerAddr11

GND

PCIX2M66En

GND

PerAddr14

PerAddr12

Reserved

OV_DD

PerAddr21

PerAddr23

PerAddr10

V_DD

PCIX2Cap

V_DD

PerBE0*

P2V_DD

N10

N11

N12

N13

Reserved

GND

P10

P11

P12

P13

R10

R11

R12

R13

T10

T11

T12

T13

PCIX2IDSel

GND

Reserved

GND

Reserved

GND

Reserved

V_DD

Reserved

V_DD

OV_DD

P0V_DD

N14

N15

GND

V_DD

P14

P15

R14

R15

T14

T15

GND

V_DD

P1V_DD

SV_DD

N16

N17

N18

N19

P16

P17

P18

P19

GND

R16

R17

R18

R19

GND

T16

T17

T18

T19

Reserved

GND

Reserved

SV_DD

Reserved

SV_DD

Reserved

GND

MemData47

V_DD

MemData52

V_DD

N20

N21

N22

N23

N24

N25

N26

N27

N28

P20

P21

P22

P23

P24

P25

P26

P27

P28

MemData40

MemData38

BankSel1

GND

R20

R21

R22

R23

R24

R25

R26

R27

R28

MemData53

DM6

T20

T21

T22

T23

T24

T25

T26

T27

T28

MemData44

GND

MemData55

GND

MemData49

GND

MemData43

V_DD

BankSel0

V_DD

MemData54

MemData29

DM3

MemData50

DQS6

MemData24

GND

MemData19

GND

DQS6

SV_DD

DQS3

MemData20

MemData23

DQS3

MemData25

MemData26

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Data Sheet

PowerPC 440SP Embedded Processor

Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

PCIX2AD11

V_DD

U01

V01

PCIX2AD24

W01 PCIX2AD17

Y01

P2V_DD

U02

U03

U04

U05

U06

U07

U08

U09

U10

U11

PCIX2BE3

PCIX2AD25

PCIX2AD28

V02

V03

V04

V05

V06

V07

V08

V09

V10

V11

W02 PCIX2AD16

W03 PCIX2AD18

W04 PCIX2AD19

W05 PCIX2AD31

W06 PCIX2AD30

W07 PCIX2AD29

W08 PCIX2CalG0

W09 PCIX2CalR0

W10 PCIX2ECC1

W11 PCIX0PErr

Y02

Y03

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

GND

PCIX2BE2

PCIX2AD20

GND

PCIX2AD10

PCIX2AD08

V_DD

PCIX2Req0*

PCIX2PErr

PCIX2INTA

PCIX2Frame

PCIX2ECC3

PCIX2VRef1

Reserved

PCIX2Reset

P2V_DD

PCIX2AD21

GND

PCIX2SErr

GND

PCIX2AD22

V_DD

PCIX2VC

P2V_DD

PCIX0DevSel

GND

U12

U13

U14

U15

PSRO

V12

V13

V14

V15

Reserved

GND

W12 PCIX0TRDY

W13 PCIX0IRDY

Y12

Y13

Y14

Y15

PCIX0Req3*

V_DD

Reserved

P0V_DD

Reserved

W14

W15

PCIX0IDSel

PCIX0AD59

V_DD

Reserved

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

U27

Reserved

PSRO

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

V27

GND

W16 PCIX0AD60

W17 PCIX0AD42

W18 PCIX0AD38

W19 ECC6

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

Y27

Reserved

SV_DD

PCIX0AD41

GND

Reserved

DM7

WE

PCIX0CalG1

V_DD

MemData57

MemData58

MemData51

MemData48

MemData30

DQS2

GND

W20 MemData63

W21 MemData60

W22 MemData56

W23 MemData22

W24 MemData59

W25 MemData15

W26 DQS7

MemData62

SV_DD

ECC2

GND

ECC1

V_DD

MemData61

GND

DM2

MemData12

MemData08

GND

DQS2

MemData21

SV_DD

MemData16

V_DD

W27 DQS7

U28

V28

MemData17

W28 MemData18

Y28

MemData11

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Data Sheet

PowerPC 440SP Embedded Processor

Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7)

Ball

Signal Name

Ball

AB01 PCIX2AD04

P2V_DD

Signal Name

Ball

Signal Name

Ball

Signal Name

AA01 PCIX2AD09

AA02 PCIX2BE1

AA03 PCIX2AD12

AA04 PCIX2AD13

AA05 PCIX2AD23

AA06 PCIX2ECC5

AA07 PCIX2ECC2

AA08 PCIX0CalG0

AA09 PCIX0AD09

AA10 PCIX0AD13

AA11 PCIX0AD07

AC01 PCIX2AD06

AC02 PCIX2AD07

AC03 PCIX2AD00

AC04 PCIX2AD01

AC05 PCIX2AD02

AC06 PCIX2AD15

AD01 PCIX2AD03

AD02 GND

AB02

AB03 PCIX2BE0

AB04 PCIX2AD05

AB05 GND

AD03 PCIX0ECC5

AD04 PCIX0AD28

V_DD

AD05

AB06 PCIX2AD14

AD06 PCIX0AD21

AD07 GND

P0V_DD

AB07

AC07

PCIX2Par*

AB08 PCIX0CalR0

AB09 GND

AC08 PCIX0AD10

AC09 PCIX0AD08

AC10 PCIX0VRef1

AC11 PCIX0VRef0

AC12 PCIX0Frame

AD08 PCIX0AD11

V_DD

AD09

AB10 PCIX0AD14

AD10 PCIX0AD12

AD11 GND

P0V_DD

AB11

AA12

AB12 PCIX0INTA

AD12 PCIX0SErr

PCIX0Req2*

V_DD

AA13 PCIX0Cap

AA14 PCIX0AD58

AA15 PCIX0AD63

AA16 PCIX0AD61

AA17 PCIX0AD43

AA18 PCIX0AD37

AA19 PCIX0CalR1

AA20 MemVRef0

AA21 MemVRef1

AA22 MemODT0

AA23 ECC5

AB13 GND

AC13

AD13

PCIX0Gnt2*

AB14 PCIX0AD56

AB15 PCIX0AD57

AB16 GND

AC14 GND

AD14 PCIX0M66En

AD15 PCIX0AD55

AC15 GND

V_DD

AC16 PCIX0AD62

AC17 PCIX0AD46

AC18 PCIX0AD48

AC19 PCIX0AD44

AC20 PCIX0AD39

AC21 MemDCFdbkR

AC22 MemODT1

AC23 ECC3

AD16

AB17 PCIX0AD45

AD17 PCIX0AD36

AD18 GND

P0V_DD

AB18

AB19 PCIX0AD47

AB20 GND

AD19 MemAddr02

V_DD

AD20

AB21 MemDCFdbkD

AD21 BA0

AD22 GND

AD23 ECC4

P0V_DD

AB22

AB23 MemData14

AB24 GND

V_DD

AA24 DM8

AC24 ECC0

AD24

AA25 MemData13

AA26 DM1

AB25 DQS8

AB26 DQS8

AC25 MemData07

AC26 MemData03

AC27 MemData04

AC28 MemData10

AD25 DQS0

AD26 DQS0

AD27 GND

SV_DD

AA27 DQS1

AB27

AA28 DQS1

AB28 MemData09

AD28 MemData00

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Data Sheet

PowerPC 440SP Embedded Processor

Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

AP0V_DD

V_DD

AE01 PCIX0AD30

AE02 PCIX0AD31

AE03 PCIX0AD27

AE04 PCIX2ECC6

AE05 PCIX0AD29

AE06 PCIX0BE3

AF01

AG01 AP0GND

AG02 GND

AH01

AF02 PCIX0AD26

P2V_DD

AH02 PCIX0AD24

AH03 PCIX0AD25

AH04 PCIX0ECC3

AH05 PCIX0ECC4

AF03

AG03 PCIX0ECC2

AG04 PCIX0AD22

AG05 GND

AF04 PCIX0AD20

AF05 PCIX0AD19

AF06 PCIX0AD16

AG06

AG07

AG08

AH06

PCIX0Par*

P0V_DD

PCIX0Ack64*

AE07 PCIX0BE2

AF07 PCIX0AD17

AH07 PCIX0AD15

AE08 PCIX0AD18

AE09 PCIX0AD03

AE10 PCIX0AD02

AE11 PCIX0AD01

AF08 PCIX0AD23

AF09 PCIX0BE0

AF10 PCIX0AD04

AH08 PCIX0AD05

AH09 PCIX0AD06

AH10 PCIX0VC

PCIX0Req64*

AG09 GND

AG10 PCIX0BE1

P0V_DD

AF11

AG11

AG12

AG13

AG14

AG15

AH11

AH12

PCIX0Gnt3*

PCIX0Req0*

V_DD

AE12 PCIX0AD00

AE13 PCIX0Stop

AF12 PCIX0Clk

AF13 GND

PCIX0Req1*

PCIX0Gnt1*

P0V_DD

AH13 PCIX0Reset

AH14

AE14 PCIX0BE7

AE15 PCIX0AD54

AE16 PCIX0BE6

AE17 PCIX0AD40

AF14

PCIX0Gnt0*

PCIX0Par64*

P0V_DD

AF15 PCIX0AD52

AF16 GND

AH15 PCIX0AD53

AH16 PCIX0BE4

AG16 PCIX0AD50

AG17 PCIX0BE5

V_DD

AF17 PCIX0AD51

AH17

P0V_DD

AE18 PCIX0AD32

AE19 MemAddr03

AE20 BA1

AF18 PCIX0AD33

AF19 MemAddr11

AF20 ECC7

AG18

AH18 PCIX0AD49

AH19 PCIX0AD34

AH20 MemAddr12

AH21 MemAddr13

AH22 MemAddr04

AH23 MemAddr05

AH24 RAS

AG19 PCIX0AD35

AG20 GND

AE21 MemAddr01

AE22 MemAddr06

AE23 ClkEn0

AF21 MemAddr07

AF22 MemAddr08

AF23 MemAddr00

AF24 MemAddr14

AF25 MemData06

AG21 MemAddr10

P0V_DD

AG22

AG23 MemAddr09

AG24 GND

AE24 ClkEn1

AE25 BA2

AG25 MemClkOut0

AG26 MemClkOut0

AG27 GND

AH25 CAS

SV_DD

AF27 MemData02

A2V_DD

AE26 DM0

AF26

AH26 MemClkOut1

AH27 MemClkOut1

AE27 MemData01

AE28 MemData05

V_DD

AF28

AG28 A2GND

AH28

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Data Sheet

PowerPC 440SP Embedded Processor

Signal Description

The PPC440SP embedded controller is packaged in a 783-ball flip-chip plastic ball grid array (FC-PBGA). The

following table describes the package level pinout.

Table 5. Pin Summary

Group

Signal pins, non-multiplexed

Signal pins, multiplexed

Total Signal Pins

AxV_DD

No. of Pins

496

32

528

2

APxV_DD

3

AxGND

5

OV_DD(3.3V I/Os)

15

31

10

PxV_DD(3.3V-1.5V PCI)

SV_DDG(2.5-1.8V SDRAM)

V_DD(1.5V Logic)

47

92

GND

Total Power Pins

Reserved

205

50

Total Pins

783

In the table “Signal Functional Description” on page 56, each I/O signal is listed along with a short description of its

function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed

Alphabetically” on page 17 for the pin (ball) number to which each signal is assigned.

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Data Sheet

PowerPC 440SP Embedded Processor

Multiplexed Signals

Some signals are multiplexed on the same pin so that the pin can be used for different functions. The signal names

shown in Signal Functional Description are not accompanied by signal names that might be multiplexed on the

same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in

“Signals Listed Alphabetically” on page 17. It is expected that in any single application a particular pin will always

be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin

selection than would otherwise be possible.

Strapping Pins

One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only

during reset and are used for other functions during normal operation (see “Strapping” on page 83). Note that

these are not multiplexed pins since the function of the pins is not programmable.

Multipurpose Signals

In addition to multiplexing, some pins are also multi-purpose. For example, the PCIX0Ack can function instead as

PCIX0ECC1 depending on the PCI interface mode of operation.

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Data Sheet

PowerPC 440SP Embedded Processor

Table 6. Signal Functional Description (Sheet 1 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PCI-X0:2 Interfaces

Ack64 or ECC1.

Normally used as Ack64 indicating that the target can

transfer data using 64 bits.

3.3V PCI or

PCIX0:1Ack64/PCIX0:1ECC1

I/O

4

1.5V PCI for mode 2

or

Used as ECC1 for PCI-X mode 2.

PCIX0:1AD63:00

PCIX2AD31:00

Address/Data bus (bidirectional) for PCI-X0 and PCI-X1.

Address/Data bus (bidirectional) for PCI-X 2.

3.3V PCI or

I/O

1.5V PCI for mode 2

PCI-X Byte Enables for PCI-X0 and PCI-X1.

PCI-X Byte Enables for PCI-X2.

PCIX0:1BE7:0

PCIX2BE3:0

3.3V PCI or

1.5V PCI for mode 2

PCIX0:1CalG0:1

PCIX2CalG0

External calibration resistor pads (G) for PCI-X0:2 (one

pad for each 32-bit bus group).

I

na

PCIX0:1CalR0:1

PCIX2CalR0

External calibration resistor pads (R) for PCIX0:2 (one

pad for each 32-bit bus group).

Capable of PCI-X operation.

This analog input is sampled to configure PCI and

determine the state of the PCIX0:2VC output signal:

0.00V_DD(0.0V) = Conventional PCI & PCIX0:2VC = 0

PCIX0:2Cap

I

na

0.49V_DD(1.6V) = PCI-X DDR 266 Mode 2 &

PCIX0:2VC = 1

0.75V_DD(2.5V) = PCI-X 66 & PCIX0:2VC = 0

1.00V_DD(3.3V) = PCI-X 133 & PCIX0:2VC = 0

Provides timing to the PCI interface for PCI transactions.

Note:If the PCI-X interface is not being used, drive this

pin with a 3.3V clock signal at a frequency

between 1 and 66MHz

PCIX0:2Clk

I

3.3V PCI

Indicates the driving device has decoded its address as

the target of the current access.

PCIX0:2DevSel

I/O

4

ECC check bits 5–2. All ECC bits are valid only for PCIX

DDR mode 2.

PCIX0:2ECC5:2

PCIX2ECC1

PCIX2ECC6

3.3V PCI or

Note:See PCIX0:2Par for ECC0.

See PCIX0:1Ack64 for ECC1.

See PCIX0:1Req64 for ECC6.

See PCIX0:1Par64 for ECC7.

I/O

1.5V PCI for mode 2

Driven by the current master to indicate beginning and

duration of an access.

PCIX0:2Frame

I/O

3.3V PCI

4

5

Indicates that the specified agent is granted access to

the bus. When using an external PCI/PCI-X arbiter,

connect the external arbiter's Grant line to this signal.

PCIX0:2Gnt0:1

PCIX0:1Gnt2:3

Used as a chip select during configuration read and

write transactions.

PCIX0:2IDSel

PCIX0:2INTA

PCIX0:2IRDY

I

3.3V PCI

Level sensitive PCI interrupt.

O

Indicates initiating agent’s ability to complete the current

data phase of the transaction.

I/O

4

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Data Sheet

PowerPC 440SP Embedded Processor

Table 6. Signal Functional Description (Sheet 2 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

PCIX0M66En

Description

Capable of 66MHz operation.

I/O

Type

Notes

5

3.3V PCI or

I

1.5V PCI for mode 2

3.3V PCI or

PCIX1:2M66En

Capable of 66MHz operation.

Even parity indicator or ECC0.

I

1.5V PCI for mode 2

3.3V PCI or

Normally used to indicate even parity across

PCIAD31:00 and BE3:0.

PCIX0:2Par/PCIX0:2ECC0

I/O

1.5V PCI for mode 2

Used as ECC0 for PCIX0:2 mode 2.

Even parity indicator or ECC7.

Normally used to indicate even parity across

PCIAD63:32 and BE7:4 for PCI0 and PCI1.

3.3V PCI or

PCIX0:1Par64/PCIX0:1ECC7

PCIX0:2PErr

I/O

1.5V PCI for mode 2

or

Used as ECC7 for PCIX0:1 mode 2.

Reports data parity errors during all PCI transactions

except a Special Cycle.

I/O

3.3V PCI

4

An indication to the PCI-X arbiter that the specified

agent wishes to use the bus. When using an external

PCI/PCI-X arbiter, connect the external arbiter's

Request line to this signal.

PCIX0:2Req0:1

PCIX0:1Req2:3

Request 64-bit transfer or ECC6.

Normally used by the current bus master to indicate a

64-bit transfer.

3.3V PCI or

PCIX0:1Req64/PCIX0:1ECC6

I/O

4

1.5V PCI for mode 2

or

Used as ECC6 for PCIX2 mode 2.

PCIX0:2Reset

PCIX0:2SErr

Sets PCI device registers and logic to a consistent state.

O

3.3V PCI

Reports address parity errors, data parity errors on the

Special Cycle command, or other catastrophic system

errors.

I/O

4

Indicates the current target is requesting the master to

stop the current transaction.

PCIX0:2Stop

I/O

3.3V PCI

4

Indicates the target agent’s ability to complete the

current data phase of the transaction.

PCIX0:2TRDY

Voltage control output. Used to control the voltage

regulator supplying the PCI I/O voltage. See PCI-XCap

signal.

PCIX0:2VC

O

I

3.3(1.5)V PCI

VPCIXDDR

0 = 3.3V (PCI I/O)

1 =1.5V (PCI-X DDR)

Voltage reference input for PCI-X mode 2/DDR (1.5V)

I/O. Not used for PCI or PCI-X mode 1.

PCIX0:2VRef0:1

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PowerPC 440SP Embedded Processor

Table 6. Signal Functional Description (Sheet 3 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

DDR SDRAM Interface

2.5(1.8)V

DDR SDRAM

BA0:2

Bank Address supporting up to eight internal banks.

Selects up to two external DDR SDRAM banks.

Column Address Strobe.

O

2.5(1.8)V

DDR SDRAM

BankSel0:1

CAS

2.5(1.8)V

DDR SDRAM

2.5(1.8)V

DDR SDRAM

ClkEn0:1

DM0:8

Clock Enable. One for each external bank.

Memory write data byte lane masks. MEMDM8 is the

byte lane mask for the ECC byte lane.

2.5(1.8)V

DDR SDRAM

2.5(1.8)V

DDR SDRAM

DIFF

DQS0:8

Byte lane data strobe. DQS8 is the data strobe for the

ECC byte lane. These signals are differential pairs.

I/O

2.5(1.8)V

DDR SDRAM

ECC0:7

ECC check bits 0:7.

I/O

O

Memory address bus.

2.5(1.8)V

DDR SDRAM

MemAddr14:00

Note:MemAddr14 is the most significant bit (msb).

2.5(1.8)V

DDR SDRAM

DIFF

MemClkOut0:1

Subsystem clocks. These signals are differential pairs.

O

Memory data bus.

2.5(1.8)V

DDR SDRAM

MemData63:00

I/O

Note:MemData63 is the most significant bit (msb).

2.5(1.8)V

DDR SDRAM

MemDCFdbkD

MemDCFdbkR

MemODT0:1

Feedback driver, for I/O timing measurements.

O

I

Feedback receiver. Connect externally to

MemDCFdbkD.

2.5(1.8)V

DDR SDRAM

2.5(1.8)V

DDR SDRAM

Memory on-die termination control.

O

2.5(1.8)V

DDR SDRAM Volt Ref

Rcv

Memory reference voltage (SV_REF) input.

MemVRef0

MemVRef1

I

2.5(1.8)V

DDR SDRAM Volt Ref

Sup

Memory reference voltage (SV_REF) supplemental input.

2.5(1.8)V

DDR SDRAM

RAS

WE

Row Address Strobe.

Write Enable.

O

2.5(1.8)V

DDR SDRAM

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PowerPC 440SP Embedded Processor

Table 6. Signal Functional Description (Sheet 4 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Ethernet Interface

Description

I/O

Type

Notes

EMCCD

Collision detection.

Carrier sense.

I

3.3V LVTTL

EMCCrS

EMCMDClk

Management data clock.

O

Transfer command and status information between MII

and PHY.

EMCMDIO

I/O

3.3V LVTTL

EMCRxD0:7

EMCRxDV

EMCRxErr

EMCRxClk

EMCRefClk

EMCTxClk

EMCGTxClk

EMCTxD0:7

EMCTxEn

Receive data.

I

3.3V LVTTL

Receive data valid.

Receive error.

I

Receive clock.

I

Reference clock.

Transmit clock.

I

Ethernet gigabit transmit clock.

Transmit data.

O

Transmit data enabled.

Transmit error.

EMCTxErr,

External Slave Peripheral Interface

Peripheral address bus.

PerAddr00:23

O

3.3V LVTTL

1

Note:PerAddr00 is the most significant bit (msb).

PerBE0

External peripheral data bus byte enable.

O

3.3V LVTTL

Used by the peripheral controller to indicates the last

transfer of a memory access.

PerBLast

PerCS0:2

External peripheral device select.

Peripheral data bus.

PerData0:7

I/O

3.3V LVTTL

1

Note:PerData0 is the most significant bit (msb).

Used by peripheral controller or DMA controller

depending upon the type of transfer involved. When the

PPC440SP is the bus master, it enables the selected

device to drive the bus.

PerOE

O

3.3V LVTTL

PerPar0

External peripheral data bus byte parity.

I/O

I

3.3V LVTTL

1

Used by a peripheral slave to indicate it is ready to

transfer data.

PerReady

Used as output by the peripheral controller. High

indicates a read from memory, low indicates a write to

memory.

PerR/W

O

3.3V LVTTL

PerWE

PerClk

Write Enable.

O

3.3V LVTTL

Peripheral clock used by synchronous peripheral slaves.

External error used as an input to record external slave

peripheral errors.

PerErr

I

3.3V LVTTL

1, 5

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Data Sheet

PowerPC 440SP Embedded Processor

Table 6. Signal Functional Description (Sheet 5 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

1, 4

UART Peripheral Interface

Serial clock input that provides an alternative to the

internally generated serial clock. Used in cases where

the allowable internally generated clock rates are not

satisfactory.

UARTSerClk

I

3.3V LVTTL

UART0_Rx

UART0 Receive data.

I

O

I

3.3V LVTTL

1, 4

4

UART0_Tx

UART0 Transmit data.

UART0_DCD

UART0_DSR

UART0_CTS

UART0_DTR

UART0_RTS

UART0 Data Carrier Detect.

UART0 Data Set Ready.

UART0 Clear To Send.

UART0 Data Terminal Ready.

UART0 Request To Send.

6

I

6

I

1, 4

4

O

4

3.3V LVTTL

w/pull-up

UART0_RI

UART0 Ring Indicator.

I

1, 4

UART1_Rx

UART1_Tx

UART1 Receive data.

UART1 Transmit data.

I

3.3V LVTTL

1, 4

O

UART1 Data Set Ready or Clear To Send. The choice is

determined by a DCR register bit setting.

UART1_DSR/CTS

UART1_DTR/RTS

I

3.3V LVTTL

1, 4

UART1 Request To Send or Data Terminal Ready. The

choice is determined by a DCR register bit setting.

O

UART2_Rx

UART2_Tx

IIC Peripheral Interface

IIC0SClk

UART2 Receive data.

UART2 Transmit data.

I

3.3V LVTTL

1, 4

O

IIC0 Serial Clock.

IIC0 Serial Data.

IIC1 Serial Clock.

IIC1 Serial Data.

I/O

3.3V IIC

1, 2

IIC0SDA

IIC1SClk

IIC1SDA

Interrupts Interface

IRQ0:5

External interrupt Requests 0 through 5.

I

3.3V LVTTL

1, 5

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Table 6. Signal Functional Description (Sheet 6 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

System Interface

Description

I/O

Type

Notes

1, 4

Halt

Halt from external debugger.

I

3.3V LVTTL

General purpose I/O 0 through 17. To access these

functions, software must set DCR register bits.

GPIO00:17

I/O

General purpose I/O 18 through 29. To access these

functions, software must set DCR register bits.

GPIO18:29

GPIO30:31

I/O

3.3V PCI

General purpose I/O 30 through 31. To access these

functions, software must set DCR register bits.

3.3V LVTTL

SysClk

Main system clock input.

Set to 1 when a machine check is generated.

Not used.

I

O

I

3.3V LVTTL

na

SysErr

SysPartSel

3

Main system reset. External logic can drive this

bidirectional pin low (minimum of 16 cycles) to initiate a

system reset. A system reset can also be initiated by

software.

SysReset

I

3.3V LVTTL

1, 2

HISRRst

ExtReset

Hardware initiated self-refresh and system reset.

I

3.3V LVTTL

External Reset. During the PPC440SP’s reset phase,

this signal is at down level.

O

TestEn

TmrClk

JTAG Interface

TCK

Test Enable.

I

3.3V LVTTL

3

Processor timer external input clock.

Test Clock.

I

3.3V LVTTL

3.3V LVTTL w/pull-down

3.3V LVTTL

1

4

TDI

Test Data In.

TDO

Test Data Out.

Test Mode Select.

O

I

TMS

3.3V LVTTL with pull-up

1

5

Test Reset. During chip power-up, this signal must be

low from the start of VDD ramp-up until at least 16

SysClk cycles after VDD is stable in order to initialize the

JTAG controller.

TRST

I

3.3V LVTTL with pull-up

Trace Interface

TrcClk

Trace data capture clock, runs at 1/4 the frequency of

the processor.

O

3.3V LVTTL

TrcBS0:2

Trace branch execution status.

Trace Execution Status is presented every fourth

processor clock cycle.

TrcES0:4

Additional information on trace execution and branch

status.

TrcTS0:6

O

3.3V LVTTL

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Data Sheet

PowerPC 440SP Embedded Processor

Table 6. Signal Functional Description (Sheet 7 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

Power

AxGND

Analog ground.

na

Analog voltage—1.5V.

Filtered voltages input for PCI PLLs (analog circuits).

APxV_DD

na

Note:A separate filter for all analog voltages is

recommended.

Analog voltage—1.5V.

Filtered voltages input for system PLLs (analog circuits).

AxV_DD

Note:A separate filter for all analog voltages is

recommended.

GND

Logic and I/O ground.

na

OV_DD

I/O supply (except DDR SDRAM and PCI-X)— 3.3V.

PCI-X I/O voltage supply.

PxV_DD

SV_DD

na

Note:PCI-X operates at 3.3V.

PCI-X 266 DDR operates at 1.5V

DDR SDRAM I/O voltage supply.

na

Note:DDR SDRAM operates at 2.5V

DDR2 SDRAM operates as 1.8V

V_DD

Logic voltage supply—1.5V.

PSRO

Performance Screen Ring Oscillator.

PSRO

na

Note:All PSRO signals should be connected to logic

ground (GND).

Reserved

Do not connect voltage, ground, or any signals to these

pins.

Reserved

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Data Sheet

PowerPC 440SP Embedded Processor

Device Characteristics

Table 7. Absolute Maximum Ratings

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause

permanent damage to the device. None of the performance specifications contained in this document are guaranteed when

operating at these maximum ratings.

Characteristic

Symbol

Value

Unit

Notes

V_DD

1.5V Supply Voltage (Internal logic)

0 to +1.6

V

3.3V Supply Voltage (I/O interface, except DDR

SDRAM)

OV_DD

0 to +3.6

V

PxV_DD

AxV_DD

APxV_DD

SV_DD

V_IN

3.3V Supply Voltage (PCI-X I/O)

1.5V Supply Voltage (PCI-X DDR I/O)

1.5V Supply Voltages (System PLLs)

1.5V Supply Voltages (PCI-X PLLs)

2.5V Supply Voltage (DDR SDRAM logic)

1.8V Supply Voltage (DDR2 SDRAM logic)

3.3V LVTTL receivers Input Voltage

Storage temperature range

0 to +3.6

0 to +1.6

0 to +2.7

0 to +1.95

0 to +3.6

-55 to +150

-40 to +120

V

1

V

T_STG

°C

T_C

Case temperature under bias

2

Notes:

1. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the

PPC440SP. A separate filter, as shown below, is recommended for each voltage:

AxV_DD, APxV_DD

V_DD

L

L – SMT ferrite bead chip, Murata BLM31A700S

C

C – 0.1μF ceramic

2. This value is not a specification of the operational temperature range, it is a stress rating only.

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Data Sheet

PowerPC 440SP Embedded Processor

Table 8. Package Thermal Specifications

Thermal resistance values for the PPC440SP package in a convection environment are as follows:

Airflow

ft/min (m/sec)

Parameter

Symbol

Unit

Notes

0 (0)

100 (0.51)

200 (1.02)

Junction-to-case thermal resistance

θ_JC

θ_CA

0.6

°C/W

1

2

Case-to-ambient thermal resistance (w/o heat sink)

15.5

13.1

11.9

Range

Minimum

Maximum

Junction-to-ball (typical)

θ_JB

6.5

°C/W

3

Notes:

1. Case temperature, T_C, is measured at top center of case surface with device soldered to circuit board. For this part the junction

temperature and the case temperature are essentially identical.

2. The case-to-ambient thermal resistance is measured in a JEDEC JESD51-6 standard environment; and may not accurately

predict thermal performance in production equipment environments. The operational case temperature must be maintained.

^{3. 6.5 °C/W is the theoretical}θ_JBusing an infinite heat sink. The larger number applies to the module mounted on a 1.8mm thick,

2P card using 1oz. copper power planes, with an effective heat transfer area of 75mm².

Table 9. Recommended DC Operating Conditions (Sheet 1 of 3)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Logic Supply Voltage 533 MHz

Logic Supply Voltage 667 MHz

I/O Supply Voltage

Symbol

Minimum

+1.4

Typical

+1.5

Maximum

+1.6

Unit

V

Notes

V_DD

4

V_DD

+1.425

+3.0

+1.5

+1.575

+3.6

V

OV_DD

+3.3

V

PCI-X I/O Supply Voltage

PCI-X DDR

+3.0

+3.3

1.5

+3.6

PxV_DD

V

4

1.425

1.575

Voltage Reference Input for PCI-X DDR mode 2

PCIX0VRef0:1

SV_DD

+1.425

+1.5

+1.575

DDR1 SDRAM Supply Voltage

DDR2 SDRAM

+2.3

1.7

+2.5 (2.6)

1.8

+2.7

1.9

AxV_DD

APxV_DD

SV_REF

System PLL Supply Voltages

PCI-X PLL Supply Voltages

+1.4

+1.5

+1.6

V

3

DDR1 SDRAM Reference Voltage

DDR2 SDRAM Reference Voltage

+1.15

+1.25

+1.35

0.49 x SV_DD

0.50 x SV_DD

0.51 x SV_DD

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Data Sheet

PowerPC 440SP Embedded Processor

Table 9. Recommended DC Operating Conditions (Sheet 2 of 3)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

V

Notes

SV_REF+0.18

SV_DD+0.3

Input Logic High (2.5V DDR SDRAM)

Input Logic High (1.8V DDR2 SDRAM)

2

SV_REF+0.125

1.7

SV_DD+0.3

V

Input Logic High (2.5V CMOS, 3.3V tolerant

receiver)

V

V_IH

0.5OV_DD

V_REF+0.10

+2.0

OV_DD+0.5

V_I/O+0.50

Input Logic High (3.3V PCI-X)

V

1

Input Logic High (1.5V PCI-X DDR)

Input Logic High (3.3V LVTTL)

+3.6

SV_REF-0.18

Input Logic Low (2.5V DDR SDRAM)

Input Logic Low (1.8V DDR2 SDRAM)

-0.3

SV_REF-0.125

0.7

-0.3

Input Logic Low (2.5V CMOS, 3.3V tolerant

receiver)

V

V_IL

0.35OV_DD

Input Logic Low (3.3V PCI-X)

-0.5

V

1

V_REF-0.10V

Input Logic Low (1.5V PCI-X DDR)

Input Logic Low (3.3V LVTTL)

0

+0.8

SV_DD

Output Logic High (2.5V DDR SDRAM)

Output Logic High (1.8V DDR2 SDRAM)

+1.95

SV_DD-0.45

SV_DD

Output Logic High (2.5V CMOS, 3.3V tolerant

receiver)

2.0

V

V_OH

0.9OV_DD

OV_DD

Output Logic High (3.3V PCI-X)

V

1

Output Logic High (1.5V PCI-X DDR)

Output Logic High (3.3V LVTTL)

+2.4

0

Output Logic Low (2.5V DDR SDRAM)

Output Logic Low (1.8V DDR2 SDRAM)

0.45

0

Output Logic Low (2.5V CMOS, 3.3V tolerant

receiver)

0.4

V

V_OL

0.1OV_DD

Output Logic Low (3.3V PCI-X)

Output Logic Low (1.5V PCI-X DDR)

Output Logic Low (3.3V LVTTL)

V

1

0

+0.4

1

Input Leakage Current (with no internal pull-up

or pull-down)

I_IL1

I_IL2

I_IL3

μA

Input Leakage Current (with internal pull-down)

Input Leakage Current (with internal pull-up)

0 (LPDL)

200 (MPUL)

0 (MPUL)

μΑ

5

-150 (LPDL)

μA

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PowerPC 440SP Embedded Processor

Table 9. Recommended DC Operating Conditions (Sheet 3 of 3)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

V

Notes

V_IMAO

Input Max Allowable Overshoot (3.3V LVTTL)

Input Max Allowable Undershoot (3.3V LVTTL)

Output Max Allowable Overshoot (3.3V LVTTL)

+3.9

V_IMAU

-0.6

V

V_OMAO

+3.9

V

Output Max Allowable Undershoot (3.3V

LVTTL)

V_OMAU3

T_C

-0.6

-40

V

Case Temperature

+100

°C

6

Notes:

1. PCI-X drivers meet PCI-X specifications.

2. SV_REF= SV_DD/2

3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the

PPC440SP. See “Absolute Maximum Ratings” on page 63.

4. Power supply sequencing: It is recommended that the 1.5V Vdd of the core reach its nominal value before applying power to the

I/Os. Voltage applied to I/Os from an external source must not be allowed to exceed the 0Vdd ramp. A power down cycle must

complete (0Vdd and Vdd are below 0.4V) before a new power up cycle is started.

5. LPDL is least positive down level; MPUL is most positive up level.

6. Case temperature, T_C, is measured at top center of case surface with device soldered to circuit board.

Table 10. Input Capacitance

Parameter

Group 1 (2.5V SSTL I/O)

Symbol

Maximum

5.2

Unit

pF

Notes

C_IN1

C_IN2

C_IN3

C_IN4

C_IN5

Group 2 (3.3V LVTTL I/O)

Group 3 (PCI-X I/O)

7.1

pF

5.7

pF

Group 4 (Receivers)

6.9

pF

Group 5 (3.3V tolerant CMOS I/O)

3.4

pF

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Data Sheet

PowerPC 440SP Embedded Processor

Table 11. DC Power Supply Loads

Parameter

Symbol

Minimum

Typical

Maximum

3000

40

Unit

mA

Notes

V

_DD(1.5V) active operating current

I_DD

2

OV_DD(3.3V) active operating current

PxV_DD(3.3V) active operating current

PxV_DD(1.5V) active operating current

SV_DD(2.5V) active operating current

SV_DD(1.8V) active operating current

AxV_DD(1.5V) input current

I_ODD

I_PDD

I_SDD

I_ADD

I_APDD

730

1600

1100

750

2

33

1, 2

APxV_DD(1.5V) input current

Notes:

1. See “Absolute Maximum Ratings” on page 63 for filter recommendations.

2. Valid only for CPU/PLB/OPB = 533.33/133.33/66.66 MHz.

Output

Clock Test Conditions

Clock timing and switching characteristics are specified in accordance with operating

conditions shown in the table “Recommended DC Operating Conditions.” AC

C

10pF

specifications are characterized with V = 1.5V, T = +85°C and a 10pF test load as

DD

C

shown in the figure to the right.

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Data Sheet

PowerPC 440SP Embedded Processor

Table 12. Clocking Specifications

Symbol

SysClk Input

F_C

Parameter

Min

Max

Units

Frequency

Period

33.33

83.33

30

MHz

ns

T_C

12

T_CS

T_CH

T_CL

Edge stability (cycle-to-cycle jitter)

–

±0.15

ns

High time

Low time

40% of nominal period

60% of nominal period

ns

Note:Input slew rate ≥ 1V/ns

PLL VCO

F_C

T_C

Frequency

Period

600

1333.33

1.66

MHz

ns

0.75

Processor Clock (CPU Clock)

F_C

T_C

Frequency

Period

400

1.5

666.66

2.5

MHz

ns

MemClkOut

F_C

Frequency

Period

200

333.33

MHz

ns

T_C

3

5

T_CH

High time

45% of nominal period

55% of nominal period

ns

OPB Clock and PerClk

F_C

T_C

Frequency

Period

–

83.33

–

MHz

ns

12

MAL Clock

F_C

Frequency

Period

45

12

83.33

22.2

MHz

ns

T_C

Figure 4. Clock Timing Waveform

T

CL

CH

T

C

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Data Sheet

PowerPC 440SP Embedded Processor

Spread Spectrum Clocking

Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440SP. This controller

uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to

as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the

SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the

PPC440SP the following conditions must be met:

• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the

PPC440SP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower

the frequency.

• The maximum frequency deviation cannot exceed -1%, and the modulation frequency cannot exceed 40 kHz.

In some cases, on-board PPC440SP peripherals impose more stringent requirements.

• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the

modulation.

• Use the DDR SDRAM MemClkOut since it also tracks the modulation.

• For PCI-X and PCI 66 the maximum spread spectrum is -1% modulated between 30kHz and 33kHz.

Notes:

1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of

approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that

the connected device is running at precise baud rates.

2. Ethernet operation is unaffected.

3. IIC operation is unaffected.

Important: It is up to the system designer to ensure that any SSCG used with the PPC440SP meets the above

requirements and does not adversely affect other aspects of the system.

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Data Sheet

PowerPC 440SP Embedded Processor

I/O Specifications

Table 13. Peripheral Interface Clock Timings

Parameter

PCIXxClk input frequency (asynchronous mode)

PCIXxClk period (asynchronous mode)

PCIXxClk input high time

PCIXxClk input low time

Min

Max

Units

MHz

ns

Notes

–

133.33

2

7.5

–

40% of nominal period

60% of nominal period

ns

40% of nominal period

60% of nominal period

ns

EMCMDClk output frequency

EMCMDClk period

–

2.5

MHz

ns

400

–

EMCMDClk output high time

EMCMDClk output low time

EMCTxClk input frequency

EMCTxClk period

160

–

ns

160

–

ns

2.5

25

MHz

ns

40

400

EMCTxClk input high time

EMCTxClk input low time

EMCRxClk input frequency

EMCRxClk period

35% of nominal period

–

ns

35% of nominal period

–

ns

2.5

25

MHz

ns

40

400

EMCRxClk input high time

EMCRxClk input low time

PerClk output frequency (for sync. slaves)

PerClk period

35% of nominal period

–

ns

35% of nominal period

–

ns

–

83.33

MHz

ns

12

50% of nominal period

33% of nominal period

–

PerClk output high time

66% of nominal period

50% of nominal period

1000/(2T_OPB+2ns)

ns

PerClk output low time

ns

UARTSerClk input frequency

MHz

1

2T_OPB+2

UARTSerClk period

–

ns

T_OPB+1

UARTSerClk input high time

T_OPB+1

UARTSerClk input low time

TmrClk input frequency

TmrClk period

–

ns

MHz

ns

–

100

10

–

TmrClk input high time

TmrClk input low time

Notes:

40% of nominal period

60% of nominal period

ns

1. T_OPBis the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of

the PLB clock. The maximum OPB clock frequency is 83.33 MHz. Refer to the Clocking chapter of the PPC440SP

Embedded Processor User’s Manual for details.

2. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk frequency is 66.66MHz.

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PowerPC 440SP Embedded Processor

Input/Output Timing

These timing diagrams illustrate the relationship of the timing parameters defined in the I/O Specification tables

that follow.

Figure 5. Input Setup and Hold Timing Waveform

Clock

T

min

IS

T

min

IH

Inputs

Valid

Figure 6. Output Delay and Hold Timing Waveform

Clock

max

min

max

min

T

OV

T

min

T

OH

Outputs

OH

High (Drive)

Float (High-Z)

Valid

Low (Drive)

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Data Sheet

PowerPC 440SP Embedded Processor

Table 14. I/O Specifications—All Speeds

(Sheet 1 of 3)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz

and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time

requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.

3. These are DDR signals that can change on both the positive and negative clock transitions.

Input (ns)

Output (ns)

Output Current (mA)

I/O H I/O L

(minimum) (minimum)

Signal

Clock

Notes

Setup Time Hold Time Valid Delay

Hold Time

(T_OHmin)

(T_ISmin)

(T_IHmin)

(T_OVmax)

PCI-X Interfaces

PCIX0:2Ack64

PCIX0:1AD63:00

PCIX2AD31:00

PCIX0:1BE7:0

PCIX2BE3:0

Note 2 (2)

0.5(0)

3.5(6)

0.7 (Note 2)

0.5

1.5

PCIX0:2Clk

2

Note 2 (2)

0.5(0)

3.5(6)

0.7 (Note 2)

0.5

1.5

PCIX0:2Clk

2

PCIX0:2CalG0:1

PCIX0:1CalR0:1

PCIX0:2Cap

Note 2 (2)

dc

0.5(0)

dc

na

2

na

async

Note 2 (2)

na

0.5(0)

na

3.5(6)

na

0.7 (Note 2)

na

0.5

na

1.5

na

PCIX0:2Clk

2

PCIX0:2Clk

PCIX0:2DevSel

PCIX0:2ECC5:2

PCIX0:2Frame

PCIX0:2Gnt0

PCIX0:2Gnt1

PCIX0:1Gnt2:3

PCIX0:2IDSel

PCIX0:2INTA

PCIX0:2IRDY

PCIX0:1M66En

PCIX0:2Par

na

Note 2 (2)

0.5(0)

3.5(6)

na

0.7 (Note 2)

na

0.5

na

1.5

na

PCIX0:1Par64

PCIX0:2PErr

na

PCIX0:1Req0

PCIX0:1Req1:3

PCIX2Req1

na

PCIX0:2Clk

2

PCIX0:2Req64

PCIX0:2Reset

PCIX0:2SErr

Note 2 (2)

0.5(0)

3.5(6)

0.7 (Note 2)

0.5

1.5

PCIX0:2Clk

2

PCIX0:2Stop

PCIX0:2TRDY

PCIX0:2VC

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Table 14. I/O Specifications—All Speeds

(Sheet 2 of 3)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz

and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time

requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.

3. These are DDR signals that can change on both the positive and negative clock transitions.

Input (ns)

Output (ns)

Output Current (mA)

I/O H I/O L

(minimum) (minimum)

Signal

Clock

Notes

Setup Time Hold Time Valid Delay

Hold Time

(T_OHmin)

(T_ISmin)

(T_IHmin)

(T_OVmax)

Ethernet Interface

EMCCD

na

19.1

8.7

1, async

EMCCrS

EMCMDClk

EMCMDIO

EMCRxD0:7

EMCRxDV

EMCRxErr

EMCRxClk

EMCRefClk

EMCTxClk

EMCGTxClk

EMCTxD0:7

EMCTxEn

na

EMCMDClk

EMCRxClk

4

1

na

15

na

2

1, async

na

1, async

EMCTxClk

2

EMCTxErr,

2

Internal Peripheral Interface

IIC0SClk

na

15.3

19.1

10.2

8.7

IIC0SDA

IIC0SClk

IIC1SClk

IIC1SDA

UARTSerClk

UART0_Rx

UART0_Tx

UART0_DCD

UART0_DSR

UART0_CTS

UART0_DTR

UART0_RI

UART0_RTS

UART1_Rx

UART1_Tx

UART1_DSR/CTS

UART1_RTS/DTR

UART2_Rx

UART2_Tx

Interrupts Interface

IRQ0:5

na

UARTSerClk

async

19.1

8.7

na

async

na

async

na

async

19.1

8.7

async

UARTSerClk

async

UARTSerClk

na

async

JTAG Interface

TDI

n/a

8.7

n/a

async

TMS

TDO

n/a

19.1

n/a

TCK

n/a

TRST

n/a

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PowerPC 440SP Embedded Processor

Table 14. I/O Specifications—All Speeds

(Sheet 3 of 3)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz

and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time

requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.

3. These are DDR signals that can change on both the positive and negative clock transitions.

Input (ns)

Output (ns)

Output Current (mA)

I/O H I/O L

(minimum) (minimum)

Signal

Clock

Notes

Setup Time Hold Time Valid Delay

Hold Time

(T_OHmin)

(T_ISmin)

(T_IHmin)

(T_OVmax)

System Interface

Halt

n/a

19.1

n/a

8.7

n/a

8.7

n/a

8.7

n/a

async

n/a

GPIO00:31

SysClk

SysErr

n/a

19.1

n/a

async

n/a

SysPartSel

SysReset

HISRRst

TestEn

n/a

19.1

n/a

TmrClk

n/a

Trace Interface

TrcClk

n/a

19.1

8.7

TrcBS0:2

TrcES0:4

TrcTS0:6

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PowerPC 440SP Embedded Processor

Table 15. I/O Specifications—533MHz

Notes:

1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.

Input (ns)

Output (ns)

Output Current (mA)

I/O H I/O L

(minimum) (minimum)

Signal

Clock

Notes

Setup Time Hold Time Valid Delay

Hold Time

(T_OHmin)

(T_ISmin)

(T_IHmin)

(T_OVmax)

External Slave Peripheral Interface

PerAddr00:23

PerBE0

n/a

1

6.2

0

19.1

27.7

19.1

8.7

12.8

8.7

PerClk

n/a

PerBLast

PerCS0:2

PerData0:7

PerOE

n/a

1.2

n/a

1.7

3.6

n/a

1.2

1

n/a

1

5.7

5.9

6

n/a

0

n/a

1

5.8

5.7

n/a

5.7

n/a

0

PerPar0

PerReady

PerR/W

n/a

0

1

PerWE

n/a

ExtReset

PerClk

n/a

PerClk

PLB clk

PerClk

PerErr

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Data Sheet

PowerPC 440SP Embedded Processor

DDR SDRAM I/O Specifications

The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from

the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the

same frequency as the PLB clock signal and is in phase with the PLB clock signal.

Note: MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR

programming register. In a typical system, users advance MemClkOut by 90×. This depends on the specific

application and requires a thorough understanding of the memory system in general (refer to the DDR

SDRAM controller chapter in the PPC440SP Embedded Processor User’s Manual).

In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and

MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90°. Advancing MemClkOut0 by 90°

creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to

MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.

The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths.

It is not to be used as a circuit design recommendation. Values are calculated over best case and worst case

processes with speed, temperature, and voltage as follows:

Best Case = Fast process, -40×C, +1.6V

Worst Case = Slow process, +85×C, +1.4V

Note: In all the following DDR tables and timing diagrams, minimum values are measured under best case

conditions and maximum values are measured under worst case conditions.

The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.

Figure 7. DDR SDRAM Simulation Signal Termination Model

MemClkOut0

10pF

120W

10pF

MemClkOut0

PPC440SP

V

= SV /2

DD

TT

50W

Addr/Ctrl/Data/DQS

30pF

Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.

It is not a recommended physical circuit design for this interface. An actual interface design will depend on many

factors, including the type of memory used and the board layout.

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Data Sheet

PowerPC 440SP Embedded Processor

Table 16. DDR SDRAM Output Driver Specifications

Output Current (mA)

I/O L (minimum)

Signal Path

I/O H (maximum)

Write Data

MemData00:07

MemData08:15

MemData16:23

MemData24:31

MemData32:39

MemData40:47

MemData48:55

MemData56:63

ECC0:7

15.2

DM0:8

MemClkOut0

MemAddr00:12

BA0:1

RAS

CAS

WE

BankSel0:3

ClkEn0:3

DQS0:8

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Data Sheet

PowerPC 440SP Embedded Processor

DDR SDRAM Write Operation

The following timing chart shows the relationship between the signals involved in a DDR write operation.

Figure 8. DDR SDRAM Write Cycle Timing

PLB Clk

MemClkOut

T

DS

T

HA

SA

Addr/Cmd

DQS

T

SD

T

SD

MemData

T

HD

T

HD

T

= Setup time for address and command signals to MemClkOut

SA

HA

SD

HD

DS

= Hold time for address and command signals from MemClkOut

= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)

= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)

= Delay from rising/falling edge of clock to the rising/falling edge of DQS

DDR SDRAM Read and Write I/O Timing—T and T

SA

HA

Note 1: Clock speed is 333 MHz. T and T are referenced to MemClkOut.

SA

HA

Note 2: Memory clock signal is shifted by 90° from the internal clock.

Table 17. DDR SDRAM Read and Write I/O Timing—T and T

SA

HA

T

(ns)

T

(ns)

HA

SA

Signal Name

Minimum

1.32

Minimum

1.2

MemAddr00:12

BA0:1

1.15

1.49

BankSel0:3

ClkEn0:3

CAS

1.12

1.52

1.29

1.45

1.24

1.14

RAS

1.29

1.48

WE

1.35

1.43

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PowerPC 440SP Embedded Processor

DDR SDRAM Clock to Write DQS Timing—T

DS

Note 1: All of the DQS signals are referenced to MemClkOut.

Note 2: Clock speed is 333 MHz.

Note 3: The TDS values in the table include 1.5 × 3ns cycle at 333 MHz (3 ns × 1.5 = 4.5 ns).

Note 4: To obtain adjusted values for lower clock frequencies, subtract 4 ns from the values in the following table

and add × 1.5 of the cycle time for the lower clock frequency (T - 4.5 + 1.5 T

).

DS

CYC

Table 18. DDR SDRAM Clock to Write DQS Timing—T

DS

T

(ns)

DS

Signal Name

Minimum

4.76

Maximum

5.07

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

4.78

5.09

4.78

5.10

4.76

5.07

4.79

5.11

4.80

5.13

4.81

5.11

4.79

5.11

4.77

5.07

DDR SDRAM Write Data to DQS Timing—T

T

SD and HD

Note 1: T and T are measured under worst-case conditions.

SD

HD

Note 2: Clock speed for the values in the following table is 333 MHz.

Table 19. DDR SDRAM Write Data to DQS Timing—T and T

SD

HD

T_HD(ns)

T_SD(ns)

Signal Name

Reference Signal

DQS0

MemData00:07, DM0

MemData08:15, DM1

MemData16:23, DM2

MemData24:31, DM3

MemData32:39, DM4

MemData40:47, DM5

MemData48:55, DM6

MemData56:63, DM7

ECC0:7, DM8

0.58

0.62

0.63

0.68

0.67

0.62

0.65

0.63

0.64

0.55

0.60

0.57

0.54

0.52

0.61

0.55

0.61

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

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PowerPC 440SP Embedded Processor

DDR SDRAM Read Operation

The read of the incoming data from the SDRAM is done on the rising and falling edges of the differential DQS

signal. The data must be centered on these edges for correct operation.

The PPC440SP can delay in very small increments the DQS by means of the programming of the

MCIF0_RODC[RQFD] register field.

DDR SDRAM MemClkOut0 and Read Clock Delay

To accommodate timing variations introduced by the system designs using this chip, the three-stage data path

shown in Figure 9, below, is used to eliminate metastability and allow data sampling to be adjusted for minimum

latency. The data is stored in the eight Flip Flops of Stage 1, so that it can be transferred later, within an 8X period.

Figure 9. DDR SDRAM Read Data Path.

FF: Flip-Flop

DDR 1X Clock

Ext FeedBack

Signals

Driver

MemDCFdbkD

FeedBack

Signal Gen

Coarse Delay

MCIF0_RFDC[RFFD]

Fine Delay

Read Start

Read Latency adjust circuit

CAS Lat Delay

DDR 1X Clock

Rec

Stage 2 Store

Oversampling

Fine Delay

MemDCFdbkR

DQS aligned

FBK signal

Cycles

Delay

+1

MCIF0_RFDC[RFOS]

Feedback

Data Capture

Window

T1 T2 T3 T4

MCIF0_RDCC[RDSS]

adjust

Oversampling

Clock

0

1

Q2_Ovs

7

Package

pins

Mux

0

2

4

6

FF

Compare

FF

Q2

PLB bus

[0:63]

D

Read FIFO

Upper

(x64)

C

Mux

DQS Rising

Edge Sync

DQ

Data

(x64)

Stage 2

Stage 3

Stage 1

Lower

FF

1

3

5

Q3

PLB bus

[64:127]

FF

D

(x64)

7

C

Programmed

Read DQS

Delay

DQS Falling

Edge Sync

DQS

(Diff)

DDR 1X Clock

PLB 1X Clock

MCIF0_RQDC[RQFD]

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Data Sheet

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Table 20. DDR SDRAM I/O Read Timing—T and T

SD

HD

Notes:

1. T_SDand T_HDare measured under worst case conditions.

2. Clock speed for the values in the table is 333.33MHz.

3. The time values in the table include 1/4 of a cycle at 166MHz (3ns x 0.25 = 0.75 ns).

4. To obtain adjusted T_SDand T_HDvalues for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4

of the cycle time for the lower clock frequency (e.g., T_SD- 0.75 + 0.25T_CYC).

Read Data vs DQS Setup

T_SD(ns)

Read Data vs DQS Hold

T_HD(ns)

Signal Names

MemData00:07

Reference Signal

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

0.00

1.00

MemData08:15

MemData16:23

MemData24:31

MemData32:39

MemData40:47

MemData48:55

MemData56:63

ECC0:7

Figure 10 shows the data strobe (DQS) and the data to be coincident. There is actually a slight skew as specified

by the SDRAM specifications, and there can be additional skew due to loading and signal routing. It is

recommended that the signal length for all of the eight DQS signals be matched.

Figure 10. DDR SDRAM Memory Data and DQS

DQS

TSD

MemData

THD

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PowerPC 440SP Embedded Processor

The following figure shows the timing relationship between SDRAM DDR Data at the input pin and the store of the

data in stage 1.

Figure 11. DDR SDRAM Read Cycle Timing Example

Oversampling Guard Band

DDR 1X Clock

DDR 2X Clock

Memclk (Diff.)

DQS at

MemCntl pin

Data at pin

D0

D1

D2

D3

D4

T2

D5

D6

D7

D8

D9

Store 1st Data in Stage 2

T3

FeedBack

output

1X DDR Clk cycle

T1

T4

Delayed DQS

Data out Stage 1 (0)

Data out Stage 1 (1)

Data out Stage 1 (2)

Valid

High

Low

D0

D1

D2

D3

Data out Stage 2

PLB 1X Clock

82

AMCC Proprietary

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Initialization

The PPC440SP provides an option for setting initial parameters based on default values or by reading them from a

serial “bootstrap” ROM attached to the IIC0 bus. These options are defined by strapping on three external pins

(see “Strapping” below).

Strapping

While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default

initial conditions prior to PPC440SP start-up. The actual capture instant is the nearest SysClk edge before the

deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)

resistors to select the desired default conditions. They are used for strap functions only during reset. Following

reset they are used for normal functions.

Figure 21 lists the strapping pins along with their functions and strapping options:

Table 21. Strapping Pin Assignments

Pin Strapping

Bit 1

Bit2

Function

Option

Bit 0

A08

(UART0_DCD)

C11

(UART0_DSR)

C09

(UART0_CTS)

Serial Bootstrap ROM is disabled (Bit 0 off).

Refer to the IIC Bootstrap Controller chapter in the

PPC440SP Embedded Processor User’s Manual

for details.

Boot from EBC

Boot from PCI

0x54

0

1

0

1

0

1

0

1

Serial Bootstrap ROM is enabled (Bit 0 on).

The options being selected are the IIC0 slave

address that responds with strapping data and

reading 128 bits from the Bootstrap ROM.

0

1

0x50

Serial Bootstrap ROM is enabled (Bit 0 on).

The options being selected are the IIC0 slave

address that responds with strapping data and

reading 256 bits from the Bootstrap ROM.

0x54

0x50

Serial Bootstrap ROM

During reset, if the serial device is enabled, initial conditions can be read from a ROM connected to the IIC0 port. In

this case, at the de-assertion of SysReset, the PPC440SP sequentially reads up to 32 bytes from the ROM device

on the IIC0 port and sets the SDR0_SDSTP0 - SDR0_SDSTP7 registers accordingly.

The initialization settings and their default values are described in detail in the PPC440SP Embedded Processor

User’s Manual.

AMCC Proprietary

83

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Document Revision History

Revision

Date

Description

Corrected Package Thermal Specifications table where the letter q appeared instead of the symbol

for theta.

1.23

Sept 26, 2006

1.22

1.21

Sept 22, 2006

Sept 12, 2006

Updated Recommended DC Operating Conditions table.

Updated Processor Clock values in Clocking Specifications table.

Updated Recommended DC Op Conditions and Signal Functional Description tables for PCI-X

DDR mode 2.

1.20

1.19

1.18

June 27, 2006

June 14, 2006

May 23, 2006

Updated signal lists.

Fixed doc issue for PEROE signal in Signal Functional Description table. Updated Clocking

Specifications table and Serial Bootstrap ROM paragraph.

Updated core package graphic in Figure 3. Added RAID acceleration section to Features,

Description, and functional details sections.

1.17

1.16

1.15

1.14

1.13

May 1, 2006

March 8, 2006

March 7, 2006

March 6, 2006

February 9, 2006

Updated ordering and PVR information, part number list, and package diagram. GJG

Removed DMA statement from Serial Port feature statement. Removed reference to notes from

PERBLAST entry in signal functional description table. GJG

Updated description of On-Chip SRAM/L2 Cache in Introduction. GJG

Updated Signal Function Description table per JB, updated mailing address and copyright date in

disclaimer. GJG

Clarified information about DDR SDRAM I/O specifications, updated note in system memory

address map table per GB, updated ordering and PVR information, part number list, and package

diagram, deleted Preliminary from running head. GJG

1.12

Nov 15, 2005

1.11

1.10

July 12, 2005

May 23, 2005

Updated leakage current info, case temp range, DDR SDRAM Signal Termination graphic. GJG

Changed PVR numbers for pass 2. Corrected functional block diagram. Updated Write timing

diagrams. GJG

Changed part numbers in Ordering and PVR Information section to reflect pass 2. Removed text for

unsupported COLA component. GJG

1.09

1.08

Mar 8, 2005

Added table to document muxed usage of GPIO signals. Removed additional references to

unsupported COLA serial interface. Reformatted LOF and LOT to comply with AMCC style.

Updated Description information on first page, sections on DC power supply loads and

recommended DC operating conditions. GJG

Feb 16, 2005

1.07

1.06

Jan 19, 2005

Dec 21, 2004

Remove references to unsupported COLA serial interface. GJG

Update max case temp in Recommended DC Op Conditions table to match Ordering and PVR

Information table. GJG

Update Order Part Number Key information, DDR SDRAM Read data Path block diagram, and

DDR SDRAM Read Cycle Timing example diagram per GB. GJG

1.05

1.04

1.03

Dec 14, 2004

Dec 01, 2004

Oct 19, 2004

Update Ordering and PVR information. GJG

Update table in Recommended DC Operating Conditions section per Docs Issue Database ID #12.

GJG

Update functional block diagram and text, signal functional description table, and recommended

DC operating conditions section with GB’s comments. GJG

1.02

Oct 12, 2004

1.01

1.00

Sept 08, 2004

Dec 31, 2003

First official draft. GJG

Create initial data sheet.

84

AMCC Proprietary

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Applied Micro Circuits Corporation

215 Moffett Park Dr., Sunnyvale, CA 94089

Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885

http://www.amcc.com

AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war-

rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available

datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.

AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia-

bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under

its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower

grade.

AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE

SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL

APPLICATIONS.

AMCC Proprietary

85


型号：	PPC440SP-RNC667C
厂家：	APPLIED MICRO CIRCUITS CORPORATION
描述：	PowerPC 440SP Embedded Processor 的PowerPC 440SP嵌入式处理器微控制器和处理器外围集成电路微处理器 PC 时钟
文件：	总85页 (文件大小：1264K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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