5AGTFD3D427I4N_技术文档

Arria V Device Handbook Volume 1: Device Overview and

Datasheet

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Document last updated for Altera Complete Design Suite version:

Document publication date:

11.1

February 2012

AV-5V1-1.3

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

ISO

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

Contents

Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Chapter 1. Overview for the Arria V Device Family

Arria V Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Arria V Family Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Low-Power Serial Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7

PMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

PCS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

PCIe Gen1 and Gen2 Hard IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10

FPGA GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10

External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11

ALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

Variable-Precision DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14

Dynamic and Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14

Clock Networks and PLL Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15

Enhanced Configuration and Configuration via Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16

SoC FPGA with HPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17

Features of the HPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17

System Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18

HPS-FPGA AXI Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18

HPS SDRAM Controller Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18

FPGA Configuration and Processor Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18

Hardware and Software Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–20

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21

Chapter 2. Device Datasheet for Arria V Devices

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Internal Weak Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Transceiver Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Core Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

DSP Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

Temperature Sensing Diode Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

DQS Logic Block and Memory Output Clock Jitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . 2–35

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

iv

Contents

OCT Calibration Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Duty Cycle Distortion (DCD) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Configuration Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

POR Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

JTAG Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

DCLK-to-DATA[] Ratio (r) for FPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

FPP Configuration Timing when DCLK to DATA[] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

FPP Configuration Timing when DCLK to DATA[] > 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

AS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43

PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–44

Remote System Upgrades Circuitry Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

User Watchdog Internal Oscillator Frequency Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47

Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47

Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51

Additional Information

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter Revision Dates

The chapters in this document, Volume 1: Device Overview and Datasheet, were

revised on the following dates. Where chapters or groups of chapters are available

separately, part numbers are listed.

Chapter 1. Overview for the Arria V Device Family

Revised: February 2012

Part Number: AV51001-1.3

Chapter 2. Device Datasheet for Arria V Devices

Revised:

February 2012

Part Number: AV-51002-1.3

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

vi

Chapter Revision Dates

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

1. Overview for the Arria V Device Family

February 2012

AV51001-1.3

Built on the 28-nm low-power process technology, Arria^®V devices offer the lowest

power and lowest system cost for mainstream applications. Arria V devices include

unique innovations such as the lowest static power in its class, the lowest power

transceivers of any midrange family, support for serial data rates up to

10.3125 gigabits per second (Gbps), a powerful collection of integrated hard

intellectual property (IP), and a power-optimized core architecture, making Arria V

devices ideal for the following applications:

■

Power sensitive wireless infrastructure equipment

20G/40G bridging, switching, and packet processing applications

High-definition video processing and image manipulation

Intensive digital signal processing (DSP) applications

Arria V devices are available in the following variants:

■

Arria V GX—FPGA with integrated 6-Gbps transceivers, this variant provides

bandwidth, cost, and power levels that are optimized for high-volume data and

signal-processing applications.

■

Arria V GT—FPGA with integrated 10-Gbps transceivers, this variant provides

enhanced high-speed serial I/O bandwidth for cost-sensitive data and signal

processing applications.

■

Arria V SX—system-on-a-chip (SoC) FPGA with integrated Arria V FPGA and

ARM^®-based hard processor system (HPS).

Arria V ST—SoC FPGA with integrated Arria V FPGA, ARM-based HPS, and

10-Gbps transceivers.

The Arria V SoC FPGA variants feature an FPGA integrated with an HPS that consists

of a dual-core ARM Cortex™-A9 MPCore™ processor, a rich set of peripherals, and a

shared multiport SDRAM memory controller.

The unique feature set in Arria V devices was chosen to optimize power, cost, and

performance. These features include a redesigned adaptive logic module (ALM),

distributed memory, new 10-Kbit (M10K) internal memory blocks, variable-precision

DSP blocks, and fractional clock synthesis phase-locked loops (PLLs) with a highly

flexible clocking network, all interconnected by a power-optimized MultiTrack

routing architecture.

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012

Subscribe

1–2

Chapter 1: Overview for the Arria V Device Family

Arria V Feature Summary

Arria V devices provide interface support flexibility with up to 10-Gbps transceivers,

1.25-Gbps LVDS, 1.333-Gbps memory interfaces with low latency, and support for all

mainstream single-ended and differential I/O standards, including 3.3 V. Arria V

devices also offer the lowest system cost by requiring only three power supplies to

operate the devices and a thermal composite flip chip ball-grid array (BGA)

packaging option. Arria V devices also support innovative features, such as

configuration via protocol (CvP), partial reconfiguration, and design security.

Arria V devices provide the power, features, and cost you require to succeed with

your designs. With these innovations, Arria V devices deliver ideal performance and

capability for a wide range of applications.

Arria V Feature Summary

Table 1–1 lists the Arria V device features.

Table 1–1. Feature Summary for Arria V Devices (Part 1 of 3)

Feature

Details

■ 28-nm TSMC low-power process technology

■ Lowest static power in its class (less than 800 mW for 500 K logic elements (LEs) at 85°C

Technology

junction under typical conditions)

■ 1.1-V core nominal voltage

■ 611-Mbps to 10.3125-Gbps integrated transceivers

■ Transmit pre-emphasis and receiver equalization

■ Dynamic reconfiguration of individual channels

■ 1.25-Gbps LVDS

Lowest-power serial

transceivers of any

midrange FPGA

■ 667-MHz/1.333-Gbps external memory interface

■ On-chip termination (OCT)

FPGA General-purpose

I/Os (GPIOs)

■ 3.3-V support

■ Custom implementation up to 10.3125 Gbps

■ PCI Express^®(PCIe^®) Gen1 and Gen2

■ Gbps Ethernet (GbE) and XAUI physical coding sublayer (PCS)

■ Common Public Radio Interface (CPRI) PCS

■ Gigabit-capable passive optical network (GPON) PCS

Embedded transceiver

hard IP

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for the Arria V Device Family

1–3

Arria V Feature Summary

Table 1–1. Feature Summary for Arria V Devices (Part 2 of 3)

Feature

Details

■ Dual-core ARM Cortex-A9 MPCore processor. Up to 800 MHz maximum frequency that

supports symmetric and asymmetric multiprocessing

■ Interface peripherals—10/100/1000 Ethernet media access control (MAC), USB 2.0 On-

The-Go (OTG) controller, Quad SPI flash controller, NAND flash controller, and

SD/MMC/SDIO controller, UART, serial peripheral interface (SPI), I2C interfaces, and up to

86 GPIO interfaces

■ System peripherals—general-purpose and watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

HPS (Arria V SX and ST

devices only)

■ On-chip RAM and boot ROM

■ HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-

FPGA bridges that allow the FPGA fabric to master transactions to slaves in the HPS, and

vice versa

■ FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the

multiport front end of the HPS SDRAM controller

■ ARM CoreSight™ JTAG debug, trace port, and on-chip trace storage

■ Three fractional PLLs

Physical medium

attachment (PMA) with

soft PCS

■ 10GBASE-R

■ 9.8304-Gbps CPRI

■ Enhanced ALM with four registers

High-performance core

fabric

■ Improved routing architecture to reduce congestion and improve compilation time

■ Natively supports three-signal processing precision ranging from 9 x 9, 18 x 19, or 27 x 27

in the same DSP block

Variable-precision DSP

blocks

■ 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)

■ Embedded internal coefficient memory

■ Pre-adder/subtractor improves efficiency

■ M10K, 10 Kbit with soft error correction code (ECC)

■ Memory logic array block (MLAB), 640-bit distributed LUTRAM—you can use up to 25% of

Internal memory blocks

the LEs as MLAB memory

■ Hardened double data rate3 (DDR3) and DDR2 memory controllers

■ Integer mode and fractional mode

High-resolution Fractional

PLLs

■ Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

■ 625-MHz global clock network

Clock networks

■ Global, quadrant, and peripheral clock networks

■ Unused clock networks can be powered down to reduce dynamic power

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–4

Chapter 1: Overview for the Arria V Device Family

Arria V Family Plan

Table 1–1. Feature Summary for Arria V Devices (Part 3 of 3)

Feature

Details

■ Partial and dynamic reconfigurations

■ CvP

■ Configuration via HPS

Configuration

■ Serial and parallel flash interface

■ Enhanced advanced encryption standard (AES) design security features

■ Tamper protection

■ Remote system upgrade

■ Thermal composite flip chip BGA packaging

■ Multiple device densities with identical package footprints for seamless migration between

Packaging

different device densities

■ Lead, lead-free (Pb-free), and RoHS-compliant options

Arria V Family Plan

Arria V devices offer various thermal composite flip chip BGA packaging options

with differing price and performance points. Table 1–2 and Table 1–3 list the Arria V

devices features.

Table 1–2. Maximum Resource Counts for Arria V GX Devices —Preliminary

Arria V GX Device

Feature

5AGXA1 5AGXA3 5AGXA5 5AGXA7 5AGXB1 5AGXB3 5AGXB5 5AGXB7

ALMs

LE (K)

28,302

75

56,100

148

1,051

873

10,510

396

792

10

71,698

190

91,680 113,208 136,880 158,491 190,240

242

1,366

1,448

13,660

800

1,600

12

300

1,510

1,852

15,100

920

1,840

12

362

1,726

2,098

17,260

1,045

2,090

12

420

2,054

2,532

20,540

1,092

2,184

16

504

2,414

2,906

24,140

1,139

2,278

16

M10K memory blocks

MLAB memory (Kbit)

Block memory (Kbit)

Variable-precision DSP blocks

18 x 19 multipliers

Fractional PLLs ⁽¹⁾

800

463

8,000

240

480

10

1,180

1,173

11,800

600

1,200

12

GPIO

480

68

480

68

544

120

136

2

704

160

176

2

704

LVDS transmitter (TX) ⁽²⁾

LVDS receiver (RX) ⁽²⁾

PCIe hard IP blocks

Hard memory controllers

Notes to Table 1–2:

120

160

156

160

80

136

176

172

176

1

2

4

(1) The total number of available fractional PLLs is a combination of general-purpose and transceiver PLLs. Transceiver fractional PLLs that are

not used by the transceiver I/O can be used as general-purpose fractional PLLs.

(2) For the LVDS channels count for each package, refer to the High-Speed Differential I/O Interfaces with DPA in Arria V Devices chapter.

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for the Arria V Device Family

1–5

Arria V Family Plan

Table 1–3. Maximum Resource Counts for Arria V GT, SX, and ST Devices—Preliminary

Arria V GT Device

Arria V SX Device

Arria V ST Device

Feature

5AGTD3

5AGTD7

190,240

504

5ASXB3

5ASXB5

174,340

462

5ASTD3

5ASTD5

174,340

462

ALMs

LE (K)

136,880

362

1,726

2,098

17,260

1,045

2,090

12

132,075

350

132,075

350

M10K memory blocks

MLAB memory (Kb)

Block memory (Kb)

Variable-precision DSP blocks

18 x 19 multipliers

FPGA Fractional PLLs ⁽¹⁾

HPS PLLs ⁽¹⁾

2,414

2,906

24,140

1,156

2,312

16

1,729

2,014

17,288

809

2,282

2,658

22,820

1,068

2,186

TBD

528

1,729

2,014

17,288

809

2,282

2,658

22,820

1,068

2,186

TBD

528

1,618

TBD

528

1,618

TBD

528

—

FPGA GPIO

704

—

704

HPS I/O

—

216

LVDS TX ⁽²⁾

LVDS RX ⁽²⁾

160

176

2

160

120

176

120

PCIe hard IP blocks

Hard memory controllers

HPS memory controllers

2

4

3

—

1

ARM Cortex–A9 MPCore

processor

—

Dual-core

Notes to Table 1–3:

(1) The total number of available fractional PLLs is a combination of general-purpose and transceiver PLLs. Transceiver fractional PLLs,

when not used by the transceiver I/O, can be used as a general-purpose fractional PLL.

(2) For the LVDS channels count for each package, refer to the High-Speed Differential I/O Interfaces with DPA in Arria V Devices chapter.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–6

Chapter 1: Overview for the Arria V Device Family

Arria V Family Plan

Table 1–4 lists the Arria V package plan. The package plan shows the GPIO counts,

the maximum number of 6-Gbps transceivers available, and the maximum number of

10-Gbps transceivers available per density and package. Various combinations of

6-Gbps and 10-Gbps transceiver counts are available.

Table 1–4. Package Plan for Arria V Devices —Preliminary ⁽¹⁾

F672 (27 mm)

Flip Chip

F896 (31 mm)

Flip Chip

F1152 (35 mm)

Flip Chip

F1517 (40 mm)

Flip Chip

Varients

Devices

GPIO

HPS

I/O

HPS

GPIO XCVR

XCVR

GPIO

XCVR

GPIO

XCVR

(2)

I/O

5AGXA1

5AGXA3

5AGXA5

5AGXA7

5AGXB1

5AGXB3

5AGXB5

5AGXB7

5AGTD3

5AGTD7

5ASXB3

5ASXB5

5ASTD3

5ASTD5

336

—

9

480

384

—

12

—

9

—

9

—

18

544

350

—

24

—

9

—

18

—

24

—

Arria V GX

(3)

—

18

—

24

704

528

—

24

—

18

—

24

—

24

—

24

—

36

—

24

—

36

—

384

—

12, 2

—

12, 4

18

—

12, 4

12, 8

30

Arria V GT

(4) (5)

,

—

178

216

12

216

Arria V SX

(3)

—

12

18

30

—

6, 2

12, 2

12, 6

Arria V ST

(4), (5)

—

Notes to Table 1–4:

(1) The arrows indicate the package vertical migration capability. Vertical migration allows you to migrate across device densities for devices having

the same dedicated pins, configuration pins, and power pins for a given package.

(2) In the F896 package, the PCIe hard IP block on the right side of the 5AGXA5, 5AGXA7, 5AGXB1, 5AGXB3, and 5AGTD3 devices supports x1 for

Gen1 and Gen2 data rates.

(3) The transceiver counts listed are for 6-Gbps transceivers.

(4) The transceiver counts listed are for 6-Gbps and 10-Gbps transceivers, respectively.

(5) You can alternatively configure any pair of 10-Gbps channels as six 6-Gbps channels. For instance, you can alternatively configure the 5AGTD7

device in the F1517 package as eighteen 6-Gbps and six 10-Gbps, twenty-four 6-Gbps and four 10-Gbps, or thirty 6-Gbps and two 10-Gbps

channels.

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for the Arria V Device Family

1–7

Low-Power Serial Transceivers

Arria V devices deliver the industry’s lowest power 10-Gbps transceivers at less than

140 mW and 6-Gbps transceivers at less than 100 mW power consumption per

channel. Arria V transceivers are designed to be standard compliant for a wide range

of protocols and data rates.

The transceivers are positioned on the left and right outer edges of the device, as

shown in Figure 1–1.

(1), (2)

Figure 1–1. Device Chip Overview for Arria V Devices

General Purpose I/Os (LVDS, Memory Interface)

Integrated Multiport Memory Controllers

ALM

M10K Internal Memory Blocks

Variable-Precision DSP Blocks

Integrated Multiport Memory Controllers

General Purpose I/Os (LVDS, Memory Interface)

Notes to Figure 1–1:

(1) This figure represents an Arria V device with transceivers. Other Arria V devices may have a different floor plan than the one shown here.

(2) This figure is a graphical representation of a top view of the silicon die, which corresponds to a reverse view for flip chip packages.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–8

Chapter 1: Overview for the Arria V Device Family

Low-Power Serial Transceivers

PMA Support

To prevent core and I/O noise from coupling into the transceivers, the PMA block is

isolated from the rest of the chip, ensuring optimal signal integrity. The transceiver

channels consist of the PMA, PCS, and clock networks. You can also use the unused

receiver PMA channels as additional transmit PLLs.

Table 1–5 lists the transceiver PMA features.

Table 1–5. Transceiver PMA Features for Arria V Devices

Features

Capability

Up to 16” FR4 PCB fabric drive capability at up

to 6.5536 Gbps

Backplane support

Chip-to-chip support

Up to 10.3125 Gbps

PLL-based clock recovery

Superior jitter tolerance

Programmable serializer and deserializer

(SERDES)

Flexible SERDES width

Up to 6 dB of pre-emphasis and 4 dB of

equalization

Equalization and pre-emphasis

Ring oscillator transmit PLLs

Input reference clock range

611 Mbps to 10.3125 Gbps

27 MHz to 710 MHz

Allows reconfiguration of single channels

without affecting operation of other channels

Transceiver dynamic reconfiguration

PCS Support

The Arria V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, or 40-bit

interface, depending on the transceiver data rate and protocol. Arria V devices

contain PCS hard IP to support PCIe Gen1 and Gen2, XAUI, GbE, Serial

RapidIO^®(SRIO), and CPRI protocols. All other standard and proprietary protocols

from 611 Mbps to 6.5536 Gbps are supported through the custom double-width mode

(up to 6.5536 Gbps) and custom single-width mode (up to 3.75 Gbps) transceiver PCS

hard IP. A dedicated 80-bit interface to the core logic connects directly from the PMA,

bypassing the PCS hard IP, to support all protocols beyond 6.5536 Gbps up to 10.3125

Gbps.

Table 1–6 lists the transceiver PCS features.

Table 1–6. Transceiver PCS Features for Arria V Devices (Part 1 of 2)

(1)

PCS Support

Data Rates (Gbps)

Transmitter Data Path

Receiver Data Path

Word aligner, 8B/10B decoder, byte

deserializer, and phase

compensation FIFO

Custom single- and

double-width modes

Phase compensation FIFO, byte

serializer, and 8B/10B encoder

0.61 to ~6.5536

The same as custom single- and

double-width modes, plus rate

match FIFO and PIPE 2.0 interface

to the core logic

The same as custom single- and

double-width modes, plus PIPE 2.0

interface to the core logic

PCIe Gen1: x1, x2, x4, x8

PCIe Gen2: x1, x2, x4

2.5 and 5.0

1.25

(2)

The same as custom single- and

double-width modes, plus rate

match FIFO

The same as custom single- and

double-width modes

GbE

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for the Arria V Device Family

1–9

Low-Power Serial Transceivers

Table 1–6. Transceiver PCS Features for Arria V Devices (Part 2 of 2)

(1)

PCS Support

Data Rates (Gbps)

Transmitter Data Path

Receiver Data Path

The same as custom single- and

double-width modes, plus the XAUI double-width modes, plus the XAUI

XAUI

3.125

state machine for bonding four

channels

state machine for realigning four

channels, and deskew FIFO circuitry

The same as custom single- and

double-width modes

The same as custom single- and

double-width modes

SRIO

SDI

1.25 to 6.25

Phase compensation FIFO, byte

serializer

Byte deserializer and phase

compensation FIFO

0.27 ⁽³⁾, 1.485, 2.97

Phase compensation FIFO, byte

deserializer, word aligner, and

8B/10B decoder

Phase compensation FIFO, byte

serializer, 8B/10B encoder

Serial ATA

CPRI ⁽⁴⁾

1.5, 3.0, 6.0

The same as custom single- and

double-width modes, plus the TX

deterministic latency

The same as custom single- and

double-width modes, plus the RX

deterministic latency

0.6144 to 6.144

1.25 and 2.5

Phase compensation FIFO and byte Phase compensation FIFO and byte

serializer deserializer

(5)

GPON

Notes to Table 1–6:

(1) Data rates above 6.5536 Gbps up to 10.3125 Gbps, such as 10GBASE-R, are supported through soft PCS.

(2) PCIe Gen2 is supported with the PCIe hard IP only.

(3) The 0.27-Gbps data rate is supported using oversampling user logics that you must implement in the FPGA fabric.

(4) CPRI data rates above 6.5536 Gbps, such as 9.8304 Gbps, are supported through soft PCS.

(5) The GPON standard does not support burst mode.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–10

Chapter 1: Overview for the Arria V Device Family

PCIe Gen1 and Gen2 Hard IP

Arria V devices contain PCIe hard IP designed for performance, ease-of-use, and

increased functionality. The PCIe hard IP consists of the PHY MAC, data link, and

transaction layers. The PCIe hard IP supports PCIe Gen2 end point and root port for

up to x4 lane configurations, and PCIe Gen1 end point and root port for up to x8 lane

configurations. PCIe endpoint support includes multifunction support for up to eight

functions, as shown in Figure 1–2.

Figure 1–2. PCIe Multifunction for Arria V Devices

FPGA

Host CPU

PCIe Link

Root

Complex

Local

Periph 1

Periph 2

The Arria V PCIe hard IP operates independently from the core logic, which allows

the PCIe link to wake up and complete link training in less than 100 ms, while the

Arria V device completes loading the programming file for the rest of the device. In

addition, the Arria V PCIe hard IP has improved end-to-end data path protection

using ECC.

FPGA GPIOs

Arria V devices offer highly configurable GPIOs. The following list describes the

many features of the GPIOs:

■

Programmable bus hold and weak pull-up.

■

LVDS output buffer with programmable differential output voltage (V_OD) and

programmable pre-emphasis.

■

Dynamic on-chip parallel termination (R_TOCT) for all I/O banks with OCT

calibration to limit the termination impedance variation.

On-chip dynamic termination to swap between serial and parallel termination,

depending on whether there is reading or writing on a common bus for signal

integrity.

■

Configurable unused voltage reference (VREF) pins as user I/Os.

Easy timing closure support using the hardened read FIFO in the input register

path, and delay-locked loop (DLL) delay chain with fine and coarse architecture.

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 1: Overview for the Arria V Device Family

1–11

External Memory

Arria V devices support up to four hardened memory controllers for DDR3 and

DDR2 SDRAM. Each controller supports 8- to 32-bit components up to 4 gigabits (Gb)

in density with two-chip select and optional ECC. Arria V devices do not support

DDR3 SDRAM leveling.

Arria V devices also support soft memory controllers for DDR3, DDR2, LPDDR2, and

LPDDR SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM for maximum flexibility.

Table 1–7 lists the external memory interface block performance.

Table 1–7. External Memory Interface Performance for Arria V Devices

Interface

Voltage (V)

1.5

Hard Controller (MHz) Soft Controller (MHz)

533

400

667

400

200

400

DDR3 SDRAM

1.35

1.25

1.8

DDR2 SDRAM

RLDRAM II

1.5

400

(1)

1.8

(1)

1.8

QDR II+ SRAM

1.5

1.8

QDR II SRAM

1.5

1.8

DDR II+ SRAM ⁽²⁾

1.5

LPDDR SDRAM ⁽²⁾

LPDDR2 SDRAM ⁽²⁾

Notes to Table 1–7:

1.8

1.2

(1) These memory interfaces are not supported in the hard memory controller.

®

(2) These memory interfaces are not available as Altera IP.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–12

Chapter 1: Overview for the Arria V Device Family

ALM

Arria V devices use a 28-nm ALM as the basic building block of the device fabric. The

ALM shown in Figure 1–3 uses an 8-input fracturable look-up table (LUT) with four

dedicated registers to help improve timing closure in register-rich designs and

achieve an even higher design packing capability than previous generations.

You can configure up to 25% of the ALMs in Arria V devices as distributed MLABs.

For more information, refer to “Embedded Memory” on page 1–14.

Figure 1–3. ALM for Arria V Devices

Reg

1

Full

Adder

2

3

4

5

6

7

Reg

Adaptive

LUT

8

Full

Adder

Reg

Variable-Precision DSP Block

Arria V devices feature a variable-precision DSP block that you can configure to

support signal processing with precision ranging from 9 x 9, 18 x 19, and 27 x 27 bits

natively.

You can independently configure each DSP block during compilation as a triple 9 x 9,

a dual 18 x 19 multiply, or a single 27 x 27. With a dedicated 64-bit cascade bus, you

can cascade multiple variable-precision DSP blocks to implement even higher

precision DSP functions efficiently.

The variable precision DSP block also supports these features:

■

64-bit accumulator that is the largest in the industry,

Double accumulator

Hard pre-adder that is available in both 18- and 27-bit modes

Cascaded output adders for efficient systolic FIR filters

Dynamic coefficients

18-bit internal coefficient register banks

Enhanced independent multiplier operation

Efficient support for single floating point arithmetic

Inferability of all modes by the Altera Complete Design Suite

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 1: Overview for the Arria V Device Family

1–13

Variable-Precision DSP Block

Table 1–8 lists the accommodation of different configurations in a DSP block.

Table 1–8. Variable-Precision DSP Block Configurations for Arria V Devices

Multiplier Size (Bit)

Three 9 x 9

DSP Block Resources

Expected Usage

1 variable-precision DSP block

1 of variable-precision DSP block

Low precision fixed point for video applications

Medium precision fixed point in FIR filters

Two18 x 19

Two 18 x 19 with

accumulate

1 variable-precision DSP block

FIR filters

One 27 x 27

Single precision floating point

Table 1–9 lists the number of multipliers in Arria V devices.

Table 1–9. Number of Multipliers in Arria V Devices

Independent Input and Output

Multiplications Operator

18 x 18

Multiplier

Adder

Variable

18 x 19

Multiplier

Adder Mode

Variants

Devices

Precision

Summed

with 36-bit

Input

9 x 9

18 x 19

Multipliers

27 x 27

Multipliers

DSP Blocks

Multipliers

5AGXA1

5AGXA3

5AGXA5

5AGXA7

5AGXB1

5AGXB3

5AGXB5

5AGXB7

5AGTD3

5AGTD7

5ASXB3

5ASXB5

5ASTD3

5ASTD5

240

396

720

480

240

396

240

396

240

396

1,188

1,800

2,400

2,760

3,135

3,276

3,417

3,135

3,417

2,427

3,204

2,427

3,204

792

600

1,200

1,600

1,840

2,090

2,184

2,278

2,090

2,278

1,618

2,136

1,618

2,136

600

800

Arria V GX

920

1,045

1,092

1,139

1,045

1,139

809

1,045

1,092

1,139

1,045

1,139

809

1,045

1,092

1,139

1,045

1,139

809

1,045

1,092

1,139

1,045

1,139

809

Arria V GT

Arria V SX

Arria V ST

1,068

809

1068

809

1,068

809

1,068

809

1,068

1068

1,068

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–14

Chapter 1: Overview for the Arria V Device Family

Embedded Memory

The Arria V memory blocks are flexible and designed to provide an optimal amount

of small- and large-sized memory arrays. Arria V devices contain two types of

embedded memory blocks:

■

640-bit MLAB blocks—for wide and shallow memories. You can use up to 25% of

the device LABs as MLAB. The MLAB operates at up to 500 MHz.

■

10-Kb M10K blocks—for larger memory configurations. The M10K embedded

memory operates at up to 400 MHz.

Table 1–10 lists the supported memory configurations for Arria V devices.

Table 1–10. Embedded Memory Block Configuration for Arria V Devices

Memory Block

Depth (bits)

Programmable Widths

x16, x18, or x20

x40 or x32

x20 or x16

x10 or x8

x5 or x4

MLAB

32

256

512

1K

M10K

2K

4K

x2

8K

x1

Dynamic and Partial Reconfiguration

Dynamic reconfiguration enables transceiver data rates or encoding schemes to be

changed dynamically while maintaining data transfer on adjacent transceiver

channels in Arria V devices. Dynamic reconfiguration is ideal for applications

requiring on-the-fly multi-protocol or multi-rate support. You can reconfigure the

PMA, PCS, and PCIe hard IP blocks with dynamic reconfiguration.

Partial reconfiguration allows you to reconfigure part of the device while other

sections remain running. Partial reconfiguration is required in systems where the

uptime is critical because it allows you to make updates or adjust functionality

without disrupting other services. While lowering power and cost, partial

reconfiguration also increases the effective logic density by removing the necessity to

place the device functions that do not operate simultaneously. Instead, you can store

these functions in external memory and load them as required. This reduces the size

of the required device by allowing multiple applications on a single device, which

saves board space and reduces power consumption.

Altera simplifies the time-intensive task of partial reconfiguration by building the

partial reconfiguration capability on top of the proven incremental compile and

design flow in the Quartus^®II software. With this Altera solution, you do not need to

know all the intricate device architecture details to perform a partial reconfiguration.

Partial reconfiguration is supported through the FPP x16 configuration interface. You

can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to

enable partial reconfiguration of both the core and transceiver simultaneously.

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 1: Overview for the Arria V Device Family

1–15

Clock Networks and PLL Clock Sources

The Arria V clock network architecture is based on Altera’s proven global, quadrant,

and peripheral clock structure, which is supported by dedicated clock input pins and

fractional PLLs. Arria V devices have 16 global clock networks capable of up to

625 MHz operation. The Quartus II software identifies all unused sections of the clock

network and powers them down, which reduces power consumption.

Arria V devices have up to 16 PLLs with 18 output counters per PLL. One fractional

PLL can use up to 18 output counters and two adjacent fractional PLLs share the 18

output counters. You can use fractional PLLs to reduce the number of oscillators

required on your board, as well as reduce the clock pins used in the device by

synthesizing multiple clock frequencies from a single reference clock source. You can

use the PLLs for frequency synthesis, on-chip clock deskew, jitter attenuation,

dynamic phase-shift, zero delay buffers, counters reconfiguration, bandwidth

reconfiguration, programmable output clock duty cycles, PLL cascading, and

reference clock switchover.

Arria V devices use a fractional PLL architecture in addition to the historical integer

PLL. When you use fractional PLL mode, you can use the PLLs for precision

fractional-N frequency synthesis—removing the need for an off-chip reference clock.

Transceiver fractional PLLs, when not used by the Transceiver I/O, can be used as

general-purpose fractional PLLs by the FPGA fabric.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–16

Chapter 1: Overview for the Arria V Device Family

Enhanced Configuration and Configuration via Protocol

Arria V devices support 3.3-V programming voltage and the following configuration

modes:

■

active serial (AS)

passive serial (PS)

fast passive parallel (FPP)

CvP

Configuration via HPS

configuration through JTAG

You can configure Arria V devices through PCIe using CvP instead of an external

flash or ROM. The CvP mode offers the fastest configuration rate and flexibility with

the easy-to-use PCIe hard IP block interface. The Arria V CvP implementation

conforms to the PCIe 100-ms power-up-to-active time requirement.

f

For more information regarding CvP, refer to the Configuration via Protocol (CvP)

Implementation in Altera FPGAs User Guide.

Table 1–11 lists the configuration modes that Arria V devices support.

Table 1–11. Configuration Modes and Features for Arria V Devices

Maximum

Clock Rate

(MHz)

Maximum

Data Rate Decompression

(Mbps)

Remote

System

Update

Design

Security

Partial

Reconfiguration

Mode

Data Width (Bit)

AS

PS

1, 4

1

100

125

—

v

—

125

—

Parallel

flash loader

FPP

CvP

HPS

8, 16

125

—

33

v

—

v

—

16-bit only

x1, x2, x4, x8 ⁽¹⁾

v

—

Parallel

32

1

125

33

flash loader

JTAG

—

Note to Table 1–11:

(1) Number of lanes instead of bits.

Power Management

Arria V devices leverage FPGA architectural features and process technology

advancements to reduce the total device core power consumption by as much as 50%

when compared with Stratix IV devices at the same performance level.

Additionally, Arria V devices have a number of hard IP blocks that not only reduce

logic resources but also deliver substantial power savings when compared with soft

implementations. The list includes PCIe Gen1 and Gen2, XAUI, GbE, SRIO, GPON

and CPRI protocols. The hard IP blocks consume up to 25% less power than

equivalent soft implementations.

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 1: Overview for the Arria V Device Family

1–17

SoC FPGA with HPS

Arria V transceivers are also designed for power efficiency. As a result, the transceiver

channels consume 50% less power than the previous generation of Arria devices.

SoC FPGA with HPS

Each SoC FPGA device combines an FPGA fabric and an HPS in a single device. This

combination delivers the flexibility of programmable logic with the power and cost

savings of hard IP in the following ways:

■

Reduces board space, system power, and bill of materials cost by eliminating a

discrete embedded processor

Allows you to differentiate the end product in both the hardware and software,

and to support virtually any interface standard

Extends the product life and revenue through in-field hardware and software

updates

Features of the HPS

The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of

peripherals, and a shared multiport SDRAM memory controller, as shown in

Figure 1–4..

Figure 1–4. HPS with Dual-Core ARM Cortex-A9 MPCore Processor

Configuration

Controller

Lightweight

HPS-to-FPGA

FPGA Fabric

FPGA-to-HPS HPS-to-FPGA

FPGA-to-HPS SDRAM

FPGA

Manager

HPS

Ethernet

MAC (2x)

ARM Cortex-A9 MPCore

CPU0

(ARM Cortex-A9

with NEON/FPU,

CPU1

(ARM Cortex-A9

with NEON/FPU,

USB

OTG (2x)

64 KB

Boot

ROM

32 KB Instruction Cache, 32 KB Instruction Cache,

32 KB Data Cache, and 32 KB Data Cache, and

Memory Management Unit) Memory Management Unit)

NAND Flash

Controller

Multiport

DDR SDRAM

Controller

with

SD/MMC/SDIO

Controller

Level 3

Interconnect

ACP

SCU

Optional ECC

DMA

Controller

L2 Cache (512 KB)

64 KB

On-Chip

RAM

ETR

(Trace)

Debug

Access Port

Low Speed Peripherals

(Timers, GPIOs, UART, SPI, I2C, Quad SPI Flash Controller, System Manager, Clock Manager, Reset Manager, and Scan Manager)

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–18

Chapter 1: Overview for the Arria V Device Family

SoC FPGA with HPS

System Peripherals

The Ethernet MAC, USB OTG controller, NAND flash controller and SD/MMC/SDIO

controller modules have an integrated DMA controller. For modules without an

integrated DMA controller, an additional DMA controller module provides up to

eight channels for high-bandwidth data transfers. The debug access port provides

interfaces to industry standard JTAG debug probes and supports ARM CoreSight

debug and core traces to facilitate software development.

HPS-FPGA AXI Bridges

The HPS–FPGA bridges, which support the Advanced Microcontroller Bus

Architecture (AMBA^®) Advanced eXtensible Interface (AXI^™) specifications, consist

of the following bridges:

■

FPGA-to-HPS AXI bridge—a high-performance bus supporting 32-, 64-, and

128-bit data widths that allows the FPGA fabric to master transactions to the slaves

in the HPS

HPS-to-FPGA AXI bridge—a high-performance bus supporting 32-, 64-, and

128-bit data widths that allows the HPS to master transactions to the slaves in the

FPGA fabric.

Lightweight HPS-to-FPGA AXI bridge—a lower performance 32-bit width bus

that allows the HPS to master transactions to the slaves in the FPGA fabric.

The HPS–FPGA AXI bridges also allow the FPGA fabric to access the memory shared

by one or both microprocessors, and provide asynchronous clock crossing with the

clock from the FPGA fabric.

HPS SDRAM Controller Subsystem

The HPS SDRAM controller subsystem contains a multiport SDRAM controller and

DDR PHY that is shared between the FPGA fabric (through the

FPGA-to-HPS SDRAM interface), the level 2 (L2) cache, and the level 3 (L3) system

interconnect. The FPGA-to-HPS SDRAM interface supports AMBA AXI and Avalon^®

Memory-Mapped (Avalon-MM) interface standards, and provides up to four ports

with separate read and write directions.

To maximize memory performance, the HPS SDRAM controller subsystem supports

command and data reordering, deficit round-robin arbitration with aging, and

high-priority bypass features. The HPS SDRAM controller subsystem supports DDR2,

DDR3, LPDDR, or LPDDR2 devices up to 4 Gb and runs up to 533 MHz (1066 Mbps

data rate).

For easy migration, the FPGA-to-HPS SDRAM interface is compatible with the

interface of the soft SDRAM memory controller IPs and hard SDRAM memory

controllers in the FPGA fabric.

FPGA Configuration and Processor Booting

The FPGA fabric and HPS in the SoC FPGA are powered independently. You can

reduce the clock frequencies or gate the clocks to reduce dynamic power, or shut

down the entire FPGA fabric to reduce total system power.

You can configure the FPGA fabric and boot the HPS independently, in any order,

providing you with more design flexibility:

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 1: Overview for the Arria V Device Family

1–19

SoC FPGA with HPS

■

You can boot the HPS before you power up and configure the FPGA fabric. After

the system is running, the HPS reconfigures the FPGA fabric at any time under

program control or through the FPGA configuration controller.

You can power up both the HPS and the FPGA fabric together, configure the FPGA

fabric first, and then upload the boot code to the HPS from the FPGA fabric.

Hardware and Software Development

For hardware development, you can configure the HPS and connect your soft logic in

the FPGA fabric to the HPS interfaces using the Qsys system integration tool in the

Quartus II software.

For software development, the ARM-based SoC FPGA devices inherit the rich

software development ecosystem available for the ARM Cortex-A9 MPCore

processor. The software development process for Altera SoC FPGAs follows the same

steps as those for other SoC devices. Altera also provides support for the Linux and

VxWorks^®operating systems.

You can begin device-specific firmware and software development on the Altera

SoC FPGA Virtual Target. The Virtual Target is a PC-based fast-functional simulation

of a target development system—a model of a complete development board that runs

on a PC. The Virtual Target enables the development of device-specific production

software that can run unmodified on actual hardware.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–20

Chapter 1: Overview for the Arria V Device Family

Ordering Information

This section describes the ordering information for Arria V devices.

Figure 1–5 and Figure 1–6 show the ordering codes for Arria V devices.

Figure 1–5. Ordering Information for Arria V GX and GT Devices

PackageType

Transceiver Count

Embedded Hard IPs

F

: FineLine BGA (FBGA)

D

E

: 9

: 12

B

: No hard PCIe or hard

memory controller

G : 18

OperatingTemperature

M : 1 hard PCIe and 2 hard

memory controller

H

K

: 24

: 36

C

I

: Commercial temperature (T_J= 0° C to 85° C)

: Industrial temperature (T_J= -40° C to 100° C)

F

: Maximum 2 hard PCIe and

4 hard memory controllers

Optional Suffix

Indicates specific device

options or shipment method

Family Signature

5A GX

M

A5

G

4

F

31

C

4

N

5A : Arria V

N

: Lead-free packaging

ES : Engineering sample

FPGA Fabric Speed Grade

Family Variant

GX : 6-Gbps transceivers

GT : 10-Gbps transceivers

Package Code

GX Variant

4 (fastest)

FBGA PackageType

27 : 672 pins

31 : 896 pins

Member Code

GX Variant

5

6

Transceiver Speed Grade

GX Variant

35 : 1,152 pins

40 : 1,517 pins

A1: 75K logic elements

A3: 149K logic elements

A5: 190K logic elements

A7: 243K logic elements

B1: 300K logic elements

B3: 362K logic elements

B5: 420K logic elements

B7: 503K logic elements

GT Variant

5

4

6

: 6-Gbps

: 3-Gbps

GT Variant

: 10-Gbps

3

D3: 362K logic elements

D7: 503K logic elements

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 1: Overview for the Arria V Device Family

1–21

Document Revision History

Figure 1–6. Ordering Information for Arria V SX and ST Devices

Transceiver Count

SX Variant

(6-Gbps)

Embedded Hard IPs

D

E

: 9

: 12

PackageType

B

: No hard PCIe or hard

memory controller

F

: FineLine BGA (FBGA)

G : 18

: 24

ST Variant

M : 1 hard PCIe and 2 hard

memory controller

H

OperatingTemperature

F

: Maximum 2 hard PCIe and

3 hard memory controllers

(6-Gbps, 10-Gbps)

C

I

: Commercial temperature (T_J= 0° C to 85° C)

: Industrial temperature (T_J= -40° C to 100° C)

E

: 6, 2

G : 18, 2

: 12, 6

(These numbers do not include the

hard memory controllers in the HPS)

K

Optional Suffix

Indicates specific device

options or shipment method

Family Signature

5A : Arria V

5A

ST

F

D5

K

4

F

40

I

5

N

: Lead-free packaging

ES : Engineering sample

FPGA Fabric Speed Grade

Family Variant

SX : 6-Gbps transceivers

ST : 10-Gbps transceivers

Package Code

SX Variant

4 (fastest)

FBGA PackageType

31 : 896 pins

Member Code

5

6

35 : 1,152 pins

40 : 1,517 pins

SX Variant

B3 : 350K logic elements

B5 : 460K logic elements

Transceiver Speed Grade

SX Variant

ST Variant

5

4

6

: 6-Gbps

: 3-Gbps

ST Variant

D3 : 350K logic elements

D5 : 460K logic elements

ST Variant

: 10-Gbps

3

Document Revision History

Table 1–12 lists the revision history for this chapter.

Table 1–12. Document Revision History

Date

Version

1.3

Changes

■ Updated Table 1–2 and Table 1–3.

■ Updated Figure 1–5 and Figure 1–6.

■ Minor text edits.

February 2012

December 2011

1.2

■ Minor text edits.

■ Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–6, Table 1–7, Table 1–9, and

Table 1–10.

■ Added “SoC FPGA with HPS” section.

■ Updated “Clock Networks and PLL Clock Sources” and “Ordering Information” sections.

November 2011

August 2011

1.1

1.0

■ Updated Figure 1–5.

■ Added Figure 1–6.

■ Minor text edits.

Initial release.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

1–22

Chapter 1: Overview for the Arria V Device Family

Document Revision History

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

2. Device Datasheet for Arria V Devices

February 2012

AV-51002-1.3

This chapter describes the electrical characteristics, switching characteristics, and

configuration specifications for Arria^®V devices. Electrical characteristics include

operating conditions and power consumption. Switching characteristics include

transceiver specifications, and core and periphery performance. Configuration

specifications include power-on reset (POR) specification, initialization clock source

option and timing, various configuration mode timing parameters, remote system

upgrades timing, and user watchdog internal oscillator frequency specification. This

chapter also describes I/O timing, including programmable I/O element (IOE) delay

and programmable output buffer delay.

f

For more information about the densities and packages of devices in the Arria V

family, refer to the Overview for Arria V Device Family chapter.

Electrical Characteristics

The following sections describe the electrical characteristics of Arria V devices.

Operating Conditions

When you use Arria V devices, they are rated according to a set of defined

parameters. To maintain the highest possible performance and reliability of the

Arria V devices, you must consider the operating requirements described in this

chapter.

Arria V devices are offered in commercial and industrial grades. Commercial devices

are offered in –4 (fastest), –5, and –6 speed grades. Industrial grade devices are offered

in the –5 speed grade.

Absolute Maximum Ratings

Absolute maximum ratings define the maximum operating conditions for Arria V

devices. The values are based on experiments conducted with the devices and

theoretical modeling of breakdown and damage mechanisms. The functional

operation of the device is not implied for these conditions.

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012

Subscribe

2–2

Chapter 2: Device Datasheet for Arria V Devices

Electrical Characteristics

c

Conditions other than those listed in Table 2–1 may cause permanent damage to the

device. Additionally, device operation at the absolute maximum ratings for extended

periods of time may have adverse effects on the device.

Table 2–1. Absolute Maximum Ratings for Arria V Devices—Preliminary

Symbol Description

V_CC

Minimum

Maximum

Unit

Core voltage power supply

–0.5

1.35

V

Periphery circuitry, PCIe^®hard IP block, and transceiver physical

coding sublayer (PCS) power supply

V_CCP

–0.5

1.35

V

V_CCPGM

V_CCAUX

V_CCBAT

V_CCPD

Configuration pins power supply

Auxiliary supply

–0.5

–25

3.75

3.9

V

Battery back-up power supply for design security volatile key register

I/O pre-driver power supply

I/O power supply

V

V_CCIO

V

V_{CCD_FPLL}

V_{CCA_FPLL}

V_{CCA_GXB}

V_{CCH_GXB}

V_{CCR_GXB}

V_{CCT_GXB}

V_{CCL_GXB}

V_I

Phase-locked loop (PLL) digital power supply

PLL analog power supply

Transceiver high voltage power

Transmitter output buffer power

Receiver power

1.8

V

3.75

1.8

V

1.21

4

V

Transmitter power

V

Clock network power

V

DC input voltage

V

I_OUT

DC output current per pin

Operating junction temperature

Storage temperature (No bias)

Core voltage power supply

I/O pre-driver power supply

I/O power supply

40

mA

°C

V

T_J

–55

125

150

1.35

3.75

3.9

T_STG

–65

V_{CC_HPS}

V_{CCPD_HPS}

V_{CCIO_HPS}

–0.5

V

V_{CCRSTCLK_HPS}Configuration pins power supply

V_{CCPLL_HPS}PLL analog power supply

3.75

V

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–3

Electrical Characteristics

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in Table 2–2 and

undershoot to –2.0 V for input currents less than 100 mA and periods shorter than

20 ns.

Table 2–2 lists the maximum allowed input overshoot voltage and the duration of the

overshoot voltage as a percentage of device lifetime. The maximum allowed

overshoot duration is specified as a percentage of high time over the lifetime of the

device. A DC signal is equivalent to 100% duty cycle. For example, a signal that

overshoots to 3.95 V can only be at 3.95 V for ~5% over the lifetime of the device; for a

device lifetime of 10 years, this amounts to half a year.

Table 2–2. Maximum Allowed Overshoot During Transitions for Arria V Devices—Preliminary

Overshoot Duration as %

Symbol

Description

Condition (V)

Unit

of High Time

3.7

3.75

3.8

100

%

59.79

33.08

18.45

10.36

5.87

3.85

3.9

Vi (AC)

AC input voltage

3.95

4

3.34

4.05

4.1

1.92

1.11

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–4

Chapter 2: Device Datasheet for Arria V Devices

Electrical Characteristics

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters for

Arria V devices. Table 2–3 lists the steady-state voltage values expected from Arria V

devices. Power supply ramps must all be strictly monotonic, without plateaus.

Table 2–3. Recommended Operating Conditions for Arria V Devices—Preliminary

Symbol

V_CC

Description

Condition

Minimum

Typical

Maximum Unit

Core voltage power supply

—

1.07

1.1

1.13

V

Periphery circuitry, PCIe hard IP block, and

transceiver PCS power supply

V_CCP

—

1.07

1.1

1.13

V

V_CCAUX

Auxiliary supply

—

2.375

3.135

2.85

2.5

3.3

3.0

2.5

3.3

3.0

2.5

1.8

1.5

1.35

1.25

1.2

3.3

3.0

2.5

1.8

2.5

1.5

2.625

3.465

3.15

V

I/O pre-driver (3.3 V) power supply

I/O pre-driver (3.0 V) power supply

I/O pre-driver (2.5 V) power supply

I/O buffers (3.3 V) power supply

I/O buffers (3.0 V) power supply

I/O buffers (2.5 V) power supply

I/O buffers (1.8 V) power supply

I/O buffers (1.5 V) power supply

I/O buffers (1.35 V) power supply

I/O buffers (1.25 V) power supply

I/O buffers (1.2 V) power supply

Configuration pins (3.3 V) power supply

Configuration pins (3.0 V) power supply

Configuration pins (2.5 V) power supply

Configuration pins (1.8 V) power supply

PLL analog voltage regulator power supply

PLL digital voltage regulator power supply

(1)

V_CCPD

2.375

3.135

2.85

2.625

3.465

3.15

2.375

1.71

2.625

1.89

V_CCIO

1.425

1.283

1.19

1.575

1.418

1.31

1.14

1.26

3.135

2.85

3.465

3.15

V_CCPGM

2.375

1.71

2.625

1.89

V_{CCA_FPLL}

V_{CCD_FPLL}

2.375

1.425

2.625

1.575

Battery back-up power supply

(For design security volatile key register)

(2)

V_CCBAT

—

1.2

—

3.0

V

V_I

DC input voltage

Output voltage

—

–0.5

0

—

3.6

V_CCIO

85

V

V_O

Commercial

Industrial

0

°C

T_J

Operating junction temperature

–40

100

Slow POR

(PORSEL=0)

200 µs

—

100 ms

4 ms

—

(3)

t_RAMP

Power supply ramp time

Fast POR

(PORSEL=1)

Notes to Table 2–3:

(1) V_CCPDmust be 2.5 V when V_CCIOis 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. V_CCPDmust be 3.0 V when V_CCIOis 3.0 V.

(2) If you do not use the design security feature in Arria V devices, connect V_CCBATto a 1.5-V, 2.5-V or 3.0-V power supply. Arria V POR circuitry

monitors V_CCBAT. Arria V devices do not exit POR if V_CCBATstays low.

(3) When power is applied to an Arria V device, a POR occurs if the power supply reaches the recommended operating range in the maximum

power supply ramp.

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–5

Electrical Characteristics

Table 2–4 lists the transceiver power supply recommended operating conditions for

Arria V devices.

Table 2–4. Transceiver Power Supply Operating Conditions for Arria V GX and GT Devices—Preliminary

Symbol

V_{CCA_GXBL}

Description

Transceiver high voltage power (left side)

Transceiver high voltage power (right side)

Receiver power (left side)

Minimum

Typical

Maximum

Unit

2.375

2.5

2.625

V

V_{CCA_GXBR}

V_{CCR_GXBL}

V_{CCR_GXBR}

V_{CCT_GXBL}

V_{CCT_GXBR}

V_{CCH_GXBL}

V_{CCH_GXBR}

V_{CCL_GXBL}

V_{CCL_GXBR}

1.07

1.1

1.5

1.13

Receiver power (right side)

Transmitter power (left side)

Transmitter power (right side)

Transmitter output buffer power (left side)

Transmitter output buffer power (right side)

Clock network power (left side)

Clock network power (right side)

1.425

1.575

1.07

1.1

1.13

V

Table 2–5 lists the steady-state voltage and current values expected from Arria V

system-on-a-chip (SoC) FPGA with ARM^®-based hard processor system (HPS). Power

supply ramps must all be strictly monotonic, without plateaus.

Table 2–5. HPS Power Supply Operating Conditions for Arria V SX and ST Devices—Preliminary

Symbol

V_{CC_HPS}

Description

Minimum

1.07

Typical

1.1

3.3

3.0

2.5

3.3

3.0

2.5

1.8

1.5

1.2

3.3

3.0

2.5

1.8

2.5

Maximum

1.13

Unit

V

HPS Core voltage and periphery circuitry power supply

HPS I/O pre-driver (3.3 V) power supply

HPS I/O pre-driver (3.0 V) power supply

HPS I/O pre-driver (2.5 V) power supply

HPS I/O buffers (3.3 V) power supply

3.135

2.85

3.465

3.15

V

V_{CCPD_HPS}

V

2.375

3.135

2.85

2.625

3.465

3.15

V

HPS I/O buffers (3.0 V) power supply

V

HPS I/O buffers (2.5 V) power supply

2.375

1.71

2.625

1.89

V

V_{CCIO_HPS}

HPS I/O buffers (1.8 V) power supply

V

HPS I/O buffers (1.5 V) power supply

1.425

1.14

1.575

1.26

V

HPS I/O buffers (1.2 V) power supply

V

HPS reset and clock input pins (3.3 V) power supply

HPS reset and clock input pins (3.0 V) power supply

HPS reset and clock input pins (2.5 V) power supply

HPS reset and clock input pins (1.8 V) power supply

HPS PLL analog voltage regulator power supply

3.135

2.85

3.465

3.15

V

V_{CCRSTCLK_HPS}

2.375

1.71

2.625

1.89

V

V_{CCPLL_HPS}

2.375

2.625

V

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–6

Chapter 2: Device Datasheet for Arria V Devices

Electrical Characteristics

DC Characteristics

This section lists the supply current, I/O pin leakage current, input pin capacitance,

on-chip termination tolerance, and hot socketing specifications.

Supply Current

Standby current is the current drawn from the respective power rails used for power

budgeting. Use the Excel-based Early Power Estimator (EPE) to estimate supply

current for your design because these currents vary greatly with the resources you

use.

f

For more information about power estimation tools, refer to the PowerPlay Early Power

Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II

Handbook.

I/O Pin Leakage Current

Table 2–6 lists the Arria V I/O pin leakage current specifications.

Table 2–6. I/O Pin Leakage Current for Arria V Devices—Preliminary

Symbol

I_I

I_OZ

Description

Input pin

Tri-stated I/O pin

Conditions

V_I= 0 V to V_CCIOMAX

V_O= 0 V to V_CCIOMAX

Min

–30

Typ

—

Max

30

Unit

µA

—

30

µA

Bus Hold Specifications

Table 2–7 lists the Arria V device bus hold specifications.

Table 2–7. Bus Hold Parameters for Arria V Devices—Preliminary ⁽¹⁾(Part 1 of 2)

V_CCIO(V)

Parameter Symbol Conditions

1.2

1.5

1.8

2.5

3.0

3.3

Unit

Min Max

Min

Max

Min Max Min Max Min Max Min Max

Bus-hold,

low,

sustaining

current

V_IN> V_IL

(max.)

I_SUSL

I_SUSH

I_ODL

8

—

12

—

30

–30

—

50

–50

—

70

–70

—

70

-70

—

µA

Bus-hold,

high,

sustaining

current

V_IN< V_IH

(min.)

–8

—

–12

—

Bus-hold,

low,

overdrive

current

0V < V_IN<

V_CCIO

125

175

200

300

500

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Arria V Devices

2–7

Electrical Characteristics

Table 2–7. Bus Hold Parameters for Arria V Devices—Preliminary ⁽¹⁾(Part 2 of 2)

V

_CCIO(V)

Parameter Symbol Conditions

1.2

1.5

1.8

2.5

3.0

3.3

Unit

Min Max

Min

Max

Min Max Min Max Min Max Min Max

Bus-hold,

high,

overdrive

current

0V < V_IN<

V_CCIO

I_ODH

—

-125

0.9

—

-175

—

-200

—

-300

1.7

—

-500

2

—

-500 µA

Bus-hold

trip point

V_TRIP

—

0.3

0.375 1.125 0.68 1.07 0.7

0.8

2

V

Note to Table 2–7:

(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.

(OCT) Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically

performed at power up for I/Os connected to the calibration block. Table 2–8 lists the

Arria V OCT termination calibration accuracy specifications.

Table 2–8. OCT Calibration Accuracy Specifications for Arria V Devices—Preliminary ⁽¹⁾(Part 1 of 2)

Calibration Accuracy

Symbol

Description

Conditions (V)

Unit

%

C4

C5, I5

C6

Internal series termination

with calibration

(25- setting)

V

_CCIO= 3.0, 2.5, 1.8,

1.5, 1.2

25- R_S

15

Internal series termination

with calibration

(50- setting)

_CCIO= 3.0, 2.5, 1.8,

1.5, 1.2

50- R_S

15

%

Internal series termination

with calibration

(34- and 40- setting)

V_CCIO= 1.5, 1.35,

1.25, 1.2

34- and 40- R_S

%

Internal series termination

with calibration

(48-, 60-, and 80-

setting)

48-60-and

80- R_S

V_CCIO= 1.2

15

%

Internal parallel

termination with

calibration (50- setting)

V

_CCIO= 2.5, 1.8, 1.5,

1.2

50- R_T

–10 to +40 –10 to +40 –10 to +40

Internal parallel

termination with

calibration

(20-, 30-, 40-,

60-, and 120- setting)

20-, 30-,

40-,60-and

120- R_T

V_CCIO= 1.5, 1.35, 1.25 –10 to +40 –10 to +40 –10 to +40

%

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–8

Chapter 2: Device Datasheet for Arria V Devices

Electrical Characteristics

Table 2–8. OCT Calibration Accuracy Specifications for Arria V Devices—Preliminary ⁽¹⁾(Part 2 of 2)

Calibration Accuracy

Symbol

Description

Internal parallel

Conditions (V)

Unit

C4

C5, I5

C6

termination with

calibration

60- and 120-R_T

V_CCIO= 1.2

–10 to +40 –10 to +40 –10 to +40

%

(60- and 120- setting)

Internal left shift series

termination with

calibration

V_CCIO= 3.0, 2.5, 1.8,

1.5, 1.2

25- R_{S_left_shift}

15

%

(25- R_{S_left_shift}setting)

Note to Table 2–8:

(1) OCT calibration accuracy is valid at the time of calibration only.

Calibration accuracy for the calibrated on-chip series termination (R_SOCT) and

on-chip parallel termination (R_TOCT) are applicable at the moment of calibration.

When process, voltage, and temperature (PVT) conditions change after calibration,

the tolerance may change.

Table 2–9 lists the Arria V OCT without calibration resistance tolerance to PVT

changes.

Table 2–9. OCT Without Calibration Resistance Tolerance Specifications for Arria V Devices—Preliminary

Resistance Tolerance

Symbol

Description

Conditions (V)

V_CCIO= 3.0 and 2.5

V_CCIO= 1.8 and 1.5

V_CCIO= 1.2

Unit

%

C4

C5, I5

C6

Internal series termination

without calibration

(25- setting)

25- R_S

30

40

Internal series termination

without calibration

(25- setting)

25- R_S

50- R_S

30

35

30

40

50

40

50

40

%

Internal series termination

without calibration

(25- setting)

%

Internal series termination

without calibration (50-

setting)

V_CCIO= 3.0 and 2.5

V_CCIO= 1.8 and 1.5

V_CCIO= 1.2

%

Internal series termination

without calibration

(50- setting)

%

Internal series termination

without calibration

(50- setting)

50- R_S

35

25

50

%

Internal differential

termination (100- setting)

100- R_D

V

_CCIO= 2.5

TBD

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–9

Electrical Characteristics

OCT calibration is automatically performed at power up for OCT-enabled I/Os.

Table 2–10 lists OCT variation with temperature and voltage after power-up

calibration. Use Table 2–10 to determine the OCT variation after power-up calibration

and Equation 2–1 to determine the OCT variation without recalibration.

Equation 2–1. OCT Variation Without Recalibration—Preliminary ^{(1), (2), (3), (4), (5), (6)}

dR

dT

dR

dV







------

-------

 V

R_OCT= R

1 + 

 T

^SCAL

Notes to Equation 2–1:

(1) The R_OCTvalue calculated from Equation 2–1 shows the range of OCT resistance with the variation of temperature

and V_CCIO

.

(2) R_SCALis the OCT resistance value at power-up.

(3) T is the variation of temperature with respect to the temperature at power up.

(4) V is the variation of voltage with respect to the V_CCIOat power up.

(5) dR/dT is the percentage change of R_SCALwith temperature.

(6) dR/dV is the percentage change of R_SCALwith voltage.

Table 2–10 lists the OCT variation after the power-up calibration.

(1)

Table 2–10. OCT Variation after Power-Up Calibration for Arria V Devices—Preliminary

Symbol

Description

V_CCIO(V)

3.0

Value

0.0297

0.0344

0.0499

0.0744

0.1241

0.189

Unit

2.5

OCT variation of voltage without

recalibration

dR/dV

1.8

%/mV

%/°C

1.5

1.2

3.0

2.5

0.208

OCT variation of temperature without

recalibration

dR/dT

1.8

0.266

1.5

0.273

1.2

0.317

Note to Table 2–10:

(1) Valid for a V_CCIOrange of 5% and temperature range of 0° to 85°C.

Pin Capacitance

Table 2–11 lists the Arria V pin capacitance.

Table 2–11. Pin Capacitance for Arria V Devices

Symbol

C_IOTB

Description

Value

Unit

pF

Input capacitance on top/bottom I/O pins

Input capacitance on left/right I/O pins

5.5

C_IOLR

pF

C_OUTFB

Input capacitance on dual-purpose clock output/feedback pins

pF

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–10

Chapter 2: Device Datasheet for Arria V Devices

Electrical Characteristics

Hot Socketing

Table 2–12 lists the hot socketing specifications for Arria V devices.

Table 2–12. Hot Socketing Specifications for Arria V Devices—Preliminary

Symbol

I_{IOPIN (DC)}

I_{IOPIN (AC)}

Description

DC current per I/O pin

Maximum

300 A

(1)

AC current per I/O pin

8 mA

DC current per transceiver transmitter (TX)

I_{XCVR-TX (DC)}

100 mA

50 mA

I_{XCVR-RX (DC)}

DC current per transceiver receiver (RX) pin

Note to Table 2–12:

(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |I_IOPIN| = C dv/dt, in which C is the I/O pin

capacitance and dv/dt is the slew rate.

Internal Weak Pull-Up Resistor

Table 2–13 lists the weak pull-up resistor values for Arria V devices.

(1), (2)

Table 2–13. Internal Weak Pull-Up Resistor Values for Arria V Devices—Preliminary

Symbol

Description

Conditions (V) ⁽³⁾

Value ⁽⁴⁾Unit

V_CCIO= 3.3 5%

25

k

V_CCIO= 3.0 5%

V_CCIO= 2.5 5%

V_CCIO= 1.8 5%

V_CCIO= 1.5 5%

Value of the I/O pin pull-up resistor before and during

configuration, as well as user mode if you have enabled the

programmable pull-up resistor option.

R_PU

V

_CCIO= 1.35 5%

_CCIO= 1.25 5%

V_CCIO= 1.2 5%

Notes to Table 2–13:

(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins.

(2) The internal weak pull-down feature is only available for the JTAG TCKpin. The typical value for this internal weak pull-down resistor is

approximately 25 k

(3) Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO

.

(4) Valid with 10% tolerances to cover changes over PVT.

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–11

Electrical Characteristics

I/O Standard Specifications

Table 2–14 through Table 2–19 list the input voltage (V_IHand V_IL), output voltage

(V_OHand V_OL), and current drive characteristics (I_OHand I_OL) for various I/O

standards supported by Arria V devices. The I/O standards tables also list the Arria V

device family I/O standard specifications. The V_OLand V_OHvalues are valid at the

corresponding I_OHand I_OL, respectively.

For an explanation of terms used in Table 2–14 through Table 2–19, refer to “Glossary”

on page 2–48.

Table 2–14. Single-Ended I/O Standards for Arria V Devices—Preliminary

V_CCIO(V)

V_IL(V)

V_IH(V)

V_OL(V)

V_OH(V)

I_OL

I_OH

I/O Standard

(mA) (mA)

Min

Typ

Max

Min

Max

Min

Max

Min

3.3-V LVTTL

3.135

3.3

3.465 –0.3

0.8

1.7

3.6

0.45

2.4

4

2

–4

–2

3.3-V

LVCMOS

3.135

2.85

3.3

3

3.465 –0.3

0.8

1.7

3.6

0.2

0.4

0.2

V_CCIO– 0.2

2.4

3.0-V LVTTL

3.15

–0.3

2

–2

3.0-V

LVCMOS

3

V

_CCIO– 0.2

0.1

–0.1

V_CCIO

0.3

+

3.0-V PCI

2.85

3

3.15

—

0.3 x V_CCIO

0.5 x V_CCIO

0.1 x V_CCIO

0.9 x V_CCIO

1.5

–0.5

V_CCIO

0.3

+

3.0-V PCI-X

2.5 V

2.85

2.375

1.71

3

0.35 x V_CCIO0.5 x V_CCIO

0.1 x V_CCIO

0.4

0.9 x V_CCIO

2

1.5

1

–0.5

–1

2.5

1.8

2.625 –0.3

1.89 –0.3 0.35 x V_CCIO

1.575 –0.3 0.35 x V_CCIO

1.26 –0.3 0.35 x V_CCIO

0.7

1.7

3.6

0.65 x

V_CCIO

0.3

+

1.8 V

0.45

V_CCIO– 0.45

2

–2

0.65 x

V_CCIO

0.3

1.5 V

1.2 V

1.425

1.14

1.5

1.2

0.25 x V_CCIO0.75 x V_CCIO

2

–2

0.65 x

V_CCIO

0.3

Table 2–15. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Arria V Devices—Preliminary (Part 1

of 2)

V_CCIO(V)

Typ

V_REF(V)

Typ

V_TT(V)

Typ

I/O Standard

Min

Max

Min

Max

Min

Max

SSTL-2

Class I, II

2.375

2.5

1.8

2.625

0.49 x V_CCIO0.5 x V_CCIO0.51 x V_CCIO

0.833 0.9 0.969

V_REF– 0.04

V_REF

V_REF+ 0.04

SSTL-18

Class I, II

1.71

1.425

1.283

1.19

1.89

1.575

1.418

1.26

V_REF– 0.04

SSTL-15

Class I, II

1.5

0.49 x V_CCIO0.5 x V_CCIO0.51 x V_CCIO0.49 x V_CCIO

0.5 x V_CCIO0.51 x V_CCIO

SSTL 135

Class I, II

1.35

1.25

SSTL 125

Class I, II

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–12

Chapter 2: Device Datasheet for Arria V Devices

Electrical Characteristics

Table 2–15. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Arria V Devices—Preliminary (Part 2

of 2)

V

_CCIO(V)

Typ

V_REF(V)

Typ

V_TT(V)

Typ

I/O Standard

Min

Max

Min

Max

Min

Max

HSTL-18

Class I, II

1.71

1.8

1.5

1.89

0.85

0.9

0.95

—

V_CCIO/2

—

HSTL-15

Class I, II

1.425

1.575

0.68

0.75

0.9

—

HSTL-12

Class I, II

1.14

1.2

1.26

1.3

0.47 x V_CCIO0.5 x V_CCIO0.53 x V_CCIO

0.49 x V_CCIO0.5 x V_CCIO0.51 x V_CCIO

—

V_CCIO/2

—

HSUL-12

Table 2–16. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria V Devices—Preliminary (Part 1

of 2)

V_IL(DC)(V)

V_IH(DC)(V)

Min Max

V_REF

V_IL(AC)(V) V_IH(AC)(V)

Max Min

V_OL(V)

Max

V_OH(V)

Min

I/O Standard

I_ol(mA) I_oh(mA)

Min

Max

SSTL-2

Class I

V_REF

–0.15

+

V_CCIO

0.3

+

V_REF

0.31

–

–0.3

V_REF+ 0.31 V_TT– 0.608 V_TT+ 0.608

V_REF+ 0.31 V_TT– 0.81 V_TT+ 0.81

V_REF+ 0.25 V_TT– 0.603 V_TT+ 0.603

8.1

16.2

6.7

13.4

8

–8.1

–16.2

–6.7

–13.4

–8

0.15

SSTL-2

Class II

V_REF

–0.15

V_REF

0.15

+

V_CCIO

0.3

V_REF

0.31

–

–0.3

—

SSTL-18

Class I

V_REF

–0.125

V_REF

0.125

+

V_CCIO

0.3

V_REF

0.25

–

SSTL-18

Class II

V_REF

–0.125

V_REF

0.125

+

V_CCIO

0.3

V_REF

0.25

–

V_REF+ 0.25

0.28

0.2 x V_CCIO

TBD ⁽¹⁾

0.4

V_CCIO–0.28

0.8 x V_CCIO

TBD ⁽¹⁾

SSTL-15

Class I

V_REF

0.1

–

V_REF

0.1

+

V_REF

0.175

–

V_REF

0.175

+

—

SSTL-15

Class II

V_REF

0.1

V_REF

0.1

V_REF

0.175

–

V_REF+

0.175

—

16

–16

V_REF

0.09

V_REF

0.09

V_REF

0.16

–

SSTL 135

SSTL 125

—

V_REF+ 0.16

TBD ⁽¹⁾

8

TBD ⁽¹⁾

–8

V_REF

0.85

–

V_REF

0.85

+

V_REF

0.15

–

—

V_REF+ 0.15

V_REF+ 0.2

TBD ⁽¹⁾

HSTL-18

Class I

V_REF

–0.1

V_REF

0.1

+

V_REF

0.2

–

—

V_CCIO– 0.4

V_CCIO–0.4

HSTL-18

Class II

V_REF

0.1

–

V_REF

0.1

+

V_REF

0.2

–

—

0.4

16

–16

HSTL-15

Class I

V_REF

0.1

–

V_REF

0.1

V_REF

0.2

—

0.4

8

–8

HSTL-15

Class II

V_REF

0.1

V_REF

0.1

V_REF

0.2

—

0.4

16

–16

HSTL-12

Class I

V_REF

V_CCIO

+

V_REF

–0.15

V_REF+ 0.15 0.25 x V_CCIO0.75 x V_CCIO

8

–8

0.08

V_REF

0.08

V_REF

0.08

0.15

HSTL-12

Class II

–

+

V_CCIO

0.15

V_REF

–

16

–16

0.15

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Arria V Devices

2–13

Electrical Characteristics

Table 2–16. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria V Devices—Preliminary (Part 2

of 2)

V_IL(DC)(V)

Min Max

V_REF

V_IH(DC)(V)

Min Max

V_REF

V_IL(AC)(V) V_IH(AC)(V)

Max Min

V_OL(V)

Max

V_OH(V)

Min

I/O Standard

I_ol(mA) I_oh(mA)

–

+

V_REF

–

(1)

HSUL-12

—

V_REF+ 0.22 0.1 x V_CCIO

0.9 x V_CCIOTBD

TBD

0.13

0.22

Note to Table 2–16:

(1) Pending silicon characterization.

Table 2–17. Differential SSTL I/O Standards for Arria V Devices—Preliminary

V_CCIO(V)

Typ

V_SWING(DC)(V)

Min Max

V_X(AC)(V)

Typ

V_SWING(AC)(V)

V_OX(AC)(V)

Typ

I/O

Standard

Min

Max

Min

Max

Min

Max

V_CCIOV_CCIO/2 –

+ 0.6 0.15

V_CCIOV_CCIO/2 –

Min

Max

SSTL-2

Class I, II

V_CCIO

0.6

+

V_CCIO/2

– 0.2

V

_CCIO/2

V

_CCIO/2+

0.15

2.375 2.5 2.625 0.3

1.71 1.8 1.89 0.25

1.425 1.5 1.575 0.2

—

0.62

—

+ 0.2

SSTL-18

Class I, II

V_CCIO

0.6

+

V_CCIO/2

– 0.175

V_CCIO/2

+ 0.175

V_CCIO/2+

0.125

0.5

+ 0.6

0.125

SSTL-15

Class I, II

–0.2

—

–0.15

—

0.15

–0.35 0.35

—

V_CCIO/2

—

V_REF

– 0.135

V_REF

+

TBD

V_REF

–0.15

V_REF

+ 0.15

SSTL 135

SSTL 125

1.283 1.35 1.45

1.19 1.25 1.31

0.2

V_CCIO/2

(1)

0.135

TBD

(1)

TBD

—

TBD

(1)

Note to Table 2–17:

(1) Pending silicon characterization.

Table 2–18. Differential HSTL I/O Standards for Arria V Devices—Preliminary

V_CCIO(V)

Typ

V_DIF(DC)(V)

V_X(AC)(V)

Typ

V_CM(DC)(V)

Typ

V_DIF(AC)(V)

Min Max

I/O

Standard

Min

Max

Min

Max

Min

Max

Min

Max

HSTL-18

Class I, II

1.71

1.8

1.5

1.2

1.89

0.2

—

0.78

—

1.12

0.78

—

1.12

0.4

—

HSTL-15

Class I, II

1.425

1.14

1.575

1.26

—

0.68

—

0.9

—

0.68

0.9

0.4

0.3

—

HSTL-12

Class I, II

V_CCIO

+ 0.3

0.5 x

V_CCIO

0.4 x V 0.5 x V 0.6 x

V_CCIO

+ 0.48

0.16

CCIO

0.5 x

V_CCIO

+0.12

0.5 x V_CCIO0.5 x

– 0.12 V_CCIO

0.4 x V 0.5 x V 0.6 x

V_CCIO

HSUL-12

1.14

1.2

1.3

0.26 0.26

0.44

CCIO

(1)

Table 2–19. Differential I/O Standard Specifications for Arria V Devices—Preliminary

(Part 1 of 2)

(2)

V

_CCIO(V)

V_ID(mV)

V_ICM(DC)(V)

V_OD(V)

V_OCM(V)

Typ

I/O Standard

Min Typ Max Min Condition Max Min Max

Min Typ Max Min

Max

(3)

PCML

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–14

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

(1)

Table 2–19. Differential I/O Standard Specifications for Arria V Devices—Preliminary

(Part 2 of 2)

(2)

V_CCIO(V)

V_ID(mV)

V_ICM(DC)(V)

V_OD(V)

V_OCM(V)

Typ

I/O Standard

Min Typ Max Min Condition Max Min Max

Min Typ Max Min

Max

—

0.05

1.8 0.247

—

0.6 1.125 1.25 1.375

V_CM

1.25 V

=

2.5 V LVDS 2.375 2.5 2.625 100

RSDS (HIO) 2.375 2.5 2.625 100

1.05 1.55 0.247

V_CM

1.25 V

=

—

0.3

1.4

0.1

0.2 0.6

0.5

1.2

1.4

Mini-LVDS

2.375 2.5 2.625 200

(HIO)

—

600 0.4 1.325 0.25

0.6 1.8

—

0.6

—

1

1.2

—

1.4

—

LVPECL

2.375 2.5 2.625 300

—

Notes to Table 2–19:

(1) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 2–15.

(2) RL range: 90  RL  110 .

(3) Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and

reference clock I/O pin specifications, refer to Table 2–20 and Table 2–21.

Power Consumption

Altera offers two ways to estimate power consumption for a design—the Excel-based

Early Power Estimator (EPE) and the Quartus^®II PowerPlay Power Analyzer feature.

1

You typically use the interactive Excel-based EPE before designing the FPGA to get a

magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer

provides better quality estimates based on the specifics of the design after you

complete place-and-route. The PowerPlay Power Analyzer can apply a combination

of user-entered, simulation-derived, and estimated signal activities that, when

combined with detailed circuit models, yields very accurate power estimates.

f

For more information about power estimation tools, refer to the PowerPlay Early Power

Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II

Handbook.

Switching Characteristics

This section provides performance characteristics of Arria V core and periphery

blocks for commercial grade devices.

These characteristics can be designated as Preliminary or Final.

■

Preliminary characteristics are created using simulation results, process data, and

other known parameters. The title of these tables show the designation as

“Preliminary.”

Final numbers are based on actual silicon characterization and testing. The

numbers reflect the actual performance of the device under worst-case silicon

process, voltage, and junction temperature conditions. There are no preliminary

designations on finalized tables.

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Arria V Devices

2–15

Switching Characteristics

Transceiver Performance Specifications

This section describes transceiver performance specifications.

Table 2–20 and Table 2–21 list the Arria V transceiver specifications.

(1)

Table 2–20. Transceiver Specifications for Arria V GX Devices—Preliminary

(Part 1 of 3)

–4

–5

–6

Commercial

Speed Grade

Commercial/Industrial

Speed Grade

Commercial Speed

Grade

Symbol/

Description

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Reference Clock

Supported I/O

Standards

1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL ⁽²⁾, HCSL, and LVDS

Input frequency from

REFCLKinput pins

—

27

45

—

710

55

27

45

—

710

55

27

45

—

710

55

MHz

%

Duty cycle

Peak-to-peak

differential input voltage

200

2000

200

2000

200

2000

mV

Spread-spectrum

modulating clock

frequency

PCI Express^®

(PCIe^®)

30

—

33

30

—

33

30

—

33

kHz

—

0 to

Spread-spectrum

downspread

PCIe

—

–0.5%

On-chip termination

resistors

—

100



(3)

V_ICM(AC coupled)

1.1

1.1 ⁽³⁾

1.1

V

HCSL I/O

standard for the

PCIe reference

clock

V_ICM(DC coupled)

250

—

550

—

250

—

550

—

250

—

550

—

mV

2000

1%

2000

1%

2000

1%

R_REF

—



Transceiver Clocks

fixedclkclock

frequency

Avalon^®-Memory-

Mapped (Avalon-MM)

PHY management clock

frequency

PCIe

Receiver Detect

—

125

—

125

—

125

—

MHz

< 150

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–16

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

(1)

Table 2–20. Transceiver Specifications for Arria V GX Devices—Preliminary

(Part 2 of 3)

–4

–5

–6

Commercial

Speed Grade

Commercial/Industrial

Speed Grade

Commercial Speed

Grade

Symbol/

Description

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Receiver

Supported I/O

Standards

1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS

Data rate

—

611

—

6553

1.2

611

—

6553

1.2

611

—

3125

1.2

Mbps

V

Absolute V_MAXfor a

receiver pin

(4)

Absolute V_MINfor a

receiver pin

—

–0.4

—

–0.4

—

–0.4

—

V

Maximum peak-to-peak

differential input voltage

V_ID(diff p-p) before

1.6

device configuration

Maximum peak-to-peak

differential input voltage

V_ID(diff p-p) after

—

85

—

2.2

—

85

—

2.2

—

85

—

2.2

—

V

device configuration

Minimum differential

eye opening at the

receiver serial input

mV

(5)

pins

85- setting

100- setting

120- setting

150- setting

—

85

—

85

—

85

—



100

120

150

100

120

150

100

120

150

Differential on-chip

termination resistors

PCIe (Gen1 and

Gen2), GIGE,

XAUI, SDI,

Differential and

common mode return

loss

Compliant

—

CPRI, OBSAI

Programmable ppm

detector

—

62.5, 100, 125, 200, 250, 300, 500, and 1000

ppm

UI

(6)

Run Length

—

200

4

—

200

4

—

200

4

Programmable

equalization

dB

DC Gain Setting

= 0

—

0

3

—

0

3

—

0

3

—

dB

Programmable DC gain

DC Gain Setting

= 1

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Arria V Devices

2–17

Switching Characteristics

(1)

Table 2–20. Transceiver Specifications for Arria V GX Devices—Preliminary

(Part 3 of 3)

–5

–4

–6

Commercial

Speed Grade

Commercial/Industrial

Speed Grade

Commercial Speed

Grade

Symbol/

Description

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Transmitter

Supported I/O

Standards

1.5 V PCML

Data rate

V_OCM

—

611

—

6553

611

—

6553

611

—

3125

Mbps

mV



—

30

650

85

—

30

650

85

—

30

650

85

—

85- setting

100- setting

120- setting

150- setting

—

100

120

150

—

100

120

150

—

100

120

150

—



Differential on-chip

termination resistors

—



—



(7)

Rise time

160

ps

(7)

Fall time

—

ps

CMU PLL

Supported data range

—

611

—

6553

611

—

6553

611

—

3125

Mbps

Transceiver-FPGA Fabric Interface

Interface speed

—

25

—

187.50

163.84

25

—

163.84

25

—

156.25

MHz

(single-width mode)

Interface speed

—

(double-width mode)

Notes to Table 2–20:

(1) Speed grades shown in Table 2–20 refer to the Transceiver Speed Grade in the device ordering code. For more information about device ordering codes, refer

to the Overview for Arria V Device Family chapter.

(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.

(3) The reference clock common mode voltage is equal to the V_{CCR_GXB}power supply level.

(4) The device cannot tolerate prolonged operation at this absolute maximum.

(5) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the

Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.

(6) The rate match FIFO supports only up to 300 parts per million (ppm).

(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–18

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

(1)

Table 2–21. Transceiver Specifications for Arria V GT Devices—Preliminary

(Part 1 of 2)

–5

Industrial

Speed Grade

Symbol/

Conditions

Description

Unit

Min

Typ

Max

Reference Clock

1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL ⁽²⁾

HCSL, and LVDS

,

Supported I/O Standards

Input frequency from REFCLKinput pins

Duty cycle

—

27

45

—

710

55

MHz

%

Peak-to-peak differential input voltage

200

2000

mV

Spread-spectrum modulating clock

frequency

PCI Express^®(PCIe^®)

30

—

33

kHz

—

0 to

–0.5%

100

Spread-spectrum downspread

On-chip termination resistors

PCIe

—



(3)

V_ICM(AC coupled)

1.1

V

HCSL I/O standard for

the PCIe reference clock

V

_ICM(DC coupled)

250

—

550

—

mV

R_REF

—

2000 1%



Transceiver Clocks

PCIe

Receiver Detect

fixedclkclock frequency

—

125

—

MHz

Avalon-MM PHY management clock

frequency

< 150

Receiver

Supported I/O Standards

Data rate (6-Gbps Transceiver)

Data rate (10-Gbps transceiver)

1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS

—

611

6.376

—

9.8304

—

6375

10.3125

1.2

Mbps

Gbps

V

(4)

Absolute V_MAXfor a receiver pin

Absolute V_MINfor a receiver pin

–0.4

—

V

Maximum peak-to-peak differential input

voltage V_ID(diff p-p) before device

configuration

—

1.6

V

Maximum peak-to-peak differential input

voltage V_ID(diff p-p) after device

configuration

—

85

—

2.2

—

V

Minimum differential eye opening at the

mV

(5)

receiver serial input pins

85- setting

100- setting

120- setting

150- setting

85



100

120

150

Differential on-chip termination resistors

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–19

Switching Characteristics

(1)

Table 2–21. Transceiver Specifications for Arria V GT Devices—Preliminary

(Part 2 of 2)

–5

Industrial

Speed Grade

Symbol/

Conditions

Description

Unit

Min

Typ

Max

PCIe (Gen1 and Gen2),

GIGE, XAUI, SDI, CPRI,

OBSAI, SFI

Differential and common mode return loss

Compliant

—

62.5, 100, 125, 200, 250, 300, 500,

and 1000

(6)

Programmable ppm detector

—

ppm

Run Length

—

0

200

4

UI

dB

Programmable equalization

—

DC Gain Setting = 0

DC Gain Setting = 1

—

Programmable DC gain

3

Transmitter

Supported I/O Standards

Data rate (6-Gbps transceiver)

Data rate (10-Gbps transceiver)

V_OCM

1.5 V PCML

—

611

6.376

—

9.8304

650

85

6375

10.3125

—

Mbps

Gbps

mV



—

85- setting

100- setting

120- setting

150- setting

—

100

120

150

—



Differential on-chip termination resistors

—



—



(7)

Rise time

30

160

ps

(7)

Fall time

—

30

—

ps

CMU PLL

Supported data range

—

0.611

—

10.3125

Gbps

Transceiver-FPGA Fabric Interface

Interface speed (80-bit mode)

—

25

—

159.375

156.25

MHz

Interface speed

(single-width mode)

Interface speed (double-width mode)

159.375

Notes to Table 2–21:

(1) Speed grades shown in Table 2–21 refer to the Transceiver Speed Grade in the device ordering code. For more information about device

ordering codes, refer to the Overview for Arria V Device Family chapter.

(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.

(3) The reference clock common mode voltage is equal to the V_{CCR_GXB}power supply level.

(4) The device cannot tolerate prolonged operation at this absolute maximum.

(5) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you

enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.

(6) The rate match FIFO supports only up to 300 ppm.

(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–20

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

Table 2–22 and Table 2–23 list the transceiver block jitter specification for Arria V

devices.

Table 2–22. Transceiver Block Jitter Specification for Arria V GX Devices—Preliminary (Part 1 of 4)

–5

–4

–6

Commercial/

Commercial Speed

Grade

Commercial Speed

Grade

Symbol/

Description

Industrial Speed

Grade

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

(1)

CPRI Transmit Jitter Generation

E.6.HV, E.12.HV

—

0.279

0.35

0.14

0.17

—

0.279

0.35

0.14

0.17

—

0.279

0.35

0.14

0.17

UI

Pattern = CJPAT

Total Jitter

E.6.LV, E.12.LV, E.24.LV,

E.30.LV

Pattern = CJTPAT

E.6.HV, E.12.HV

Pattern = CJPAT

Deterministic

Jitter

E.6.LV, E.12.LV, E.24.LV,

E.30.LV

Pattern = CJTPAT

(1)

CPRI Receiver Jitter Tolerance

E.6.HV, E.12.HV

Pattern = CJPAT

E.6.HV, E.12.HV

Pattern = CJPAT

Total jitter

tolerance

> 0.66

> 0.4

> 0.66

> 0.4

> 0.66

> 0.4

UI

Deterministic

jitter tolerance

E.6.LV, E.12.LV, E.24.LV,

E.30.LV

Total jitter

tolerance

> 0.65

> 0.37

> 0.65

> 0.37

> 0.65

> 0.37

UI

Pattern = CJTPAT

E.6.LV, E.12.LV, E.24.LV,

E.30.LV

Deterministic

jitter tolerance

Pattern = CJTPAT

Combined

E.6.LV, E.12.LV, E.24.LV,

E.30.LV

deterministic

and random

jitter tolerance

> 0.55

UI

Pattern = CJTPAT

(2)

OBSAI Transmit Jitter Generation

Total jitter at

768 Mbps,

REFCLK = 153.6 MHz

—

0.35

0.17

—

0.35

0.17

—

0.35

0.17

UI

1536 Mbps,and

3072 Mbps

Pattern = CJPAT

Deterministic

jitter at

768 Mbps,

1536 Mbps,and

3072 Mbps

REFCLK = 153.6 MHz

Pattern = CJPAT

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

2–21

Unit

Table 2–22. Transceiver Block Jitter Specification for Arria V GX Devices—Preliminary (Part 2 of 4)

–5

–4

–6

Commercial/

Commercial Speed

Grade

Commercial Speed

Grade

Symbol/

Description

Industrial Speed

Grade

Conditions

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

(2)

OBSAI Receiver Jitter Tolerance

Deterministic

jitter tolerance

at 768 Mbps,

1536 Mbps, and

3072 Mbps

Pattern = CJPAT

> 0.37

UI

Combined

deterministic

and random

jitter tolerance

at 768 Mbps,

1536 Mbps,and

3072 Mbps

> 0.55

Jitter Frequency =

5.4 KHz

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

UI

Sinusoidal Jitter

tolerance at

768 Mbps

Pattern = CJPAT

Jitter Frequency =

460 MHz to 20 MHz

Pattern = CJPAT

Jitter Frequency =

10.9 KHz

Sinusoidal Jitter

tolerance at

1536 Mbps

Pattern = CJPAT

Jitter Frequency =

921.6 MHz to 20 MHz

Pattern = CJPAT

Jitter Frequency =

21.8 KHz

Sinusoidal Jitter

tolerance at

3072 Mbps

Pattern = CJPAT

Jitter Frequency =

1843.2 MHz to 20 MHz

Pattern = CJPAT

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–22

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

Table 2–22. Transceiver Block Jitter Specification for Arria V GX Devices—Preliminary (Part 3 of 4)

–5

–4

–6

Commercial/

Commercial Speed

Grade

Commercial Speed

Grade

Symbol/

Description

Industrial Speed

Grade

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

(3)

Serial RapidIO^®(SRIO) Transmit Jitter Generation

Data Rate = 1.25, 2.5,

3.125 Gbps

Deterministic

jitter

(peak-to-peak)

—

0.17

0.35

—

0.17

0.35

—

0.17

0.35

UI

Pattern = CJPAT

Data Rate = 1.25, 2.5,

3.125 Gbps

Total jitter

(peak-to-peak)

Pattern = CJPAT

(3)

SRIO Receiver Jitter Tolerance

Data Rate = 1.25, 2.5,

3.125 Gbps

Deterministic

jitter tolerance

(peak-to-peak)

> 0.37

> 0.55

> 0.37

> 0.55

> 0.37

> 0.55

UI

Pattern = CJPAT

Combined

Data Rate = 1.25, 2.5,

3.125 Gbps

deterministic

and random

jitter tolerance

(peak-to-peak)

Pattern = CJPAT

Jitter Frequency =

22.1 KHz Data Rate =

1.25, 2.5, 3.125 Gbps

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

UI

Pattern = CJPAT

Jitter Frequency =

1.875 MHz

Sinusoidal jitter

tolerance

Data Rate = 1.25, 2.5,

3.125 Gbps

(peak-to-peak)

Pattern = CJPAT

Jitter Frequency =

20 MHz

Data Rate = 1.25, 2.5,

3.125 Gbps

> 0.1

UI

Pattern = CJPAT

(4)

GIGE Transmit Jitter Generation

Deterministic

jitter

(peak-to-peak)

Pattern = CRPAT

—

0.14

—

0.14

—

0.14

UI

Total jitter

(peak-to-peak)

0.279

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

2–23

Unit

Table 2–22. Transceiver Block Jitter Specification for Arria V GX Devices—Preliminary (Part 4 of 4)

–5

–4

–6

Commercial/

Commercial Speed

Grade

Commercial Speed

Grade

Symbol/

Description

Industrial Speed

Grade

Conditions

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

(4)

GIGE Receiver Jitter Tolerance

Deterministic

jitter tolerance

(peak-to-peak)

Pattern = CJPAT

> 0.4

UI

Combined

deterministic

and random

jitter tolerance

(peak-to-peak)

> 0.66

(5)

HiGig Transmit Jitter Generation

Deterministic

jitter

(peak-to-peak)

Data Rate = 3.75 Gbps

Pattern = CJPAT

—

0.17

0.35

—

UI

Data Rate = 3.75 Gbps

Pattern = CJPAT

Total jitter

(peak-to-peak)

Notes to Table 2–22:

(1) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.

(2) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.

(3) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.

(4) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.

(5) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–24

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

Table 2–23. Transceiver Block Jitter Specification for Arria V GT Devices—Preliminary (Part 1 of 3)

–5

Symbol/

Description

Industrial Speed Grade

Conditions

Unit

Min

Typ

Max

SFI Transmit Jitter Generation ⁽¹⁾

Deterministic Jitter

Total Jitter

Data Rate = 9.8304, 10.3125 Gbps

—

0.1

UI

Pattern = PRBS31

0.28

(1)

SFI Receive Jitter Tolerance

99% Jitter Tolerance

Total Jitter

Data Rate = 9.8304, 10.3125 Gbps

Pattern = PRBS31

>0.42

>0.70

UI

CPRI Transmit Jitter Generation ⁽²⁾

E.6.HV, E.12.HV

—

0.279

0.35

0.14

0.17

—

Pattern = CJPAT

Total Jitter

E.6.LV, E.12.LV, E.24.LV, E.30.LV

Pattern = CJTPAT

E.6.HV, E.12.HV

Pattern = CJPAT

Deterministic Jitter

E.6.LV, E.12.LV, E.24.LV, E.30.LV

Pattern = CJTPAT

CPRI Receive Jitter Generation ⁽²⁾

E.6.HV, E.12.HV

Total jitter tolerance

> 0.66

> 0.4

> 0.66

> 0.4

Pattern = CJPAT

E.6.HV, E.12.HV

Deterministic jitter

tolerance

Pattern = CJPAT

E.6.LV, E.12.LV, E.24.LV, E.30.LV

Pattern = CJTPAT

Total jitter tolerance

> 0.65

> 0.37

> 0.55

> 0.65

> 0.37

> 0.55

E.6.LV, E.12.LV, E.24.LV, E.30.LV

Pattern = CJTPAT

Deterministic jitter

tolerance

E.6.LV, E.12.LV, E.24.LV, E.30.LV

Pattern = CJTPAT

Combined deterministic

and random jitter tolerance

(3)

OBSAI Transmit Jitter Generation

Total jitter at 768 Mbps,

1536 Mbps, and

3072 Mbps

REFCLK = 153.6MHz

—

0.35

0.17

—

Pattern = CJPAT

Deterministic jitter at

768 Mbps, 1536 Mbps,

and 3072 Mbps

REFCLK = 153.6MHz

Pattern = CJPAT

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–25

Switching Characteristics

Table 2–23. Transceiver Block Jitter Specification for Arria V GT Devices—Preliminary (Part 2 of 3)

–5

Symbol/

Description

Industrial Speed Grade

Conditions

Unit

Min

Typ

Max

(3)

OBSAI Receiver Jitter Tolerance

Deterministic jitter

tolerance at 768 Mbps,

1536 Mbps, and

3072 Mbps

Pattern = CJPAT

> 0.37

> 0.55

> 0.37

> 0.55

Combined deterministic

and random jitter tolerance

at 768 Mbps, 1536 Mbps,

and 3072 Mbps

Jitter Frequency = 5.4 KHz

Pattern = CJPAT

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

> 0.1

> 8.5

Sinusoidal Jitter tolerance

at 768 Mbps

Jitter Frequency = 460 MHz to 20 MHz

Pattern = CJPAT

Jitter Frequency = 10.9 KHz

Pattern = CJPAT

Sinusoidal Jitter tolerance

at 1536 Mbps

Jitter Frequency = 921.6 MHz to 20 MHz

Pattern = CJPAT

Jitter Frequency = 21.8 KHz

Pattern = CJPAT

Sinusoidal Jitter tolerance

at 3072 Mbps

Jitter Frequency = 1843.2 MHz to

20 MHz

> 0.1

Pattern = CJPAT

(4)

SRIO Transmit Jitter Generation

Data Rate = 1.25, 2.5, 3.125 Gbps

Deterministic jitter

(peak-to-peak)

—

0.17

0.35

UI

Pattern = CJPAT

Data Rate = 1.25, 2.5, 3.125 Gbps

Pattern = CJPAT

Total jitter (peak-to-peak)

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–26

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

Table 2–23. Transceiver Block Jitter Specification for Arria V GT Devices—Preliminary (Part 3 of 3)

–5

Symbol/

Description

Industrial Speed Grade

Conditions

Unit

Min

Typ

Max

(4)

SRIO Receiver Jitter Tolerance

Data Rate = 1.25, 2.5, 3.125 Gbps

Pattern = CJPAT

Deterministic jitter

tolerance (peak-to-peak)

> 0.37

> 0.55

UI

Combined deterministic

and random jitter tolerance

(peak-to-peak)

Data Rate = 1.25, 2.5, 3.125 Gbps

Pattern = CJPAT

Jitter Frequency = 22.1 KHz Data Rate =

1.25, 2.5, 3.125 Gbps

> 8.5

> 0.1

UI

Pattern = CJPAT

Jitter Frequency = 1.875 MHz

Data Rate = 1.25, 2.5, 3.125 Gbps

Pattern = CJPAT

Sinusoidal jitter tolerance

(peak-to-peak)

Jitter Frequency = 20 MHz

Data Rate = 1.25, 2.5, 3.125 Gbps

Pattern = CJPAT

> 0.1

UI

(5)

GIGE Transmit Jitter Generation

Deterministic jitter

(peak-to-peak)

Pattern = CRPAT

—

0.14

UI

Total jitter (peak-to-peak)

Pattern = CRPAT

0.279

(5)

GIGE Receiver Jitter Tolerance

Deterministic jitter

tolerance (peak-to-peak)

Pattern = CJPAT

> 0.4

UI

Combined deterministic

and random jitter tolerance Pattern = CJPAT

(peak-to-peak)

> 0.66

(6)

HiGig Transmit Jitter Generation

Data Rate = 3.75 Gbps

Deterministic jitter

(peak-to-peak)

—

0.17

0.35

UI

Pattern = CJPAT

Data Rate = 3.75 Gbps

Pattern = CJPAT

Total jitter (peak-to-peak)

Notes to Table 2–23:

(1) The jitter numbers for SFI are compliant to SFF-8431 Specification.

(2) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.

(3) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.

(4) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.

(5) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.

(6) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–27

Switching Characteristics

Core Performance Specifications

This section describes the clock tree, phase-locked loop (PLL), digital signal

processing (DSP), memory blocks and temperature sensing diode specifications.

Clock Tree Specifications

Table 2–24 lists the clock tree specifications for Arria V devices.

Table 2–24. Clock Tree Performance for Arria V Devices—Preliminary

Performance

–C4 Speed Grade

Unit

Symbol

–C5, I5 Speed Grade

–C6 Speed Grade

Global clock and Regional clock

Peripheral clock

625

450

625

400

525

350

MHz

PLL Specifications

Table 2–25 lists the Arria V PLL specifications when operating in both the commercial

junction temperature range (0° to 85°C) and the industrial junction temperature range

(–40° to 100°C).

(1)

Table 2–25. PLL Specifications for Arria V Devices—Preliminary

(Part 1 of 3)

Min

Symbol

Parameter

Typ

—

Max

Unit

MHz

%

(2)

Input clock frequency (–4 speed grade)

Input clock frequency (–5 speed grade)

Input clock frequency (–6 speed grade)

Integer input clock frequency to the PFD

Fractional input clock frequency to the PFD

PLL VCO operating range (–4 speed grade)

PLL VCO operating range (–5 speed grade)

PLL VCO operating range (–6 speed grade)

Input clock or external feedback clock input duty cycle

5

670

622

500

(2)

f_IN

5

f_INPFD

5

325

f_FINPFD

50

600

40

TBD ⁽¹⁾

1600

1400

1300

60

f_VCO

t_EINDUTY

Output frequency for internal global or regional clock

(–4 speed grade)

(3)

—

500

MHz

Output frequency for internal global or regional clock

(–5 speed grade)

(3)

f_OUT

500

Output frequency for internal global or regional clock

(–6 speed grade)

(3)

400

(3)

Output frequency for external clock output (–4 speed grade)

Output frequency for external clock output (–5 speed grade)

Output frequency for external clock output (–6 speed grade)

Duty cycle for external clock output (when set to 50%)

External feedback clock compensation time

—

45

—

50

—

670

MHz

%

(3)

f_{OUT_EXT}

622

(3)

500

t_OUTDUTY

55

10

t_FCOMP

ns

t_CONFIGPHASE

t_DYCONFIGCLK

Time required to reconfigure phase shift

TBD ⁽¹⁾

—

Dynamic Configuration Clock

100

MHz

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–28

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

(1)

Table 2–25. PLL Specifications for Arria V Devices—Preliminary

(Part 2 of 3)

Symbol

t_LOCK

t_DLOCK

Parameter

Min

Typ

Max

Unit

Time required to lock from end-of-device configuration or

—

1

ms

deassertion of areset

Time required to lock dynamically (after switchover or

reconfiguring any non-post-scale counters/delays)

—

1

ms

PLL closed-loop low bandwidth

—

10

—

0.3

1.5

4

—

MHz

f_CLBW

PLL closed-loop medium bandwidth

(8)

PLL closed-loop high bandwidth

—

MHz

t_{PLL_PSERR}

t_ARESET

Accuracy of PLL phase shift

—

50

ps

Minimum pulse width on the aresetsignal

Input clock cycle-to-cycle jitter (F_REF≥ 100 MHz)

Input clock cycle-to-cycle jitter (F_REF< 100 MHz)

Period jitter for dedicated clock output (F_OUT≥ 100 MHz)

Period jitter for dedicated clock output (F_OUT< 100 MHz)

—

ns

0.15

+750

UI (p-p)

ps (p-p)

mUI (p-p)

(4), (5)

t_INCCJ

(1)

TBD

(6)

t_{OUTPJ_DC}

(1)

Cycle-to-cycle jitter for dedicated clock output

(F_OUT≥ 100 MHz)

—

TBD

ps (p-p)

mUI (p-p)

ps (p-p)

(6)

t_{OUTCCJ_DC}

Cycle-to-cycle jitter for dedicated clock output

(F_OUT< 100 MHz)

(1)

Period Jitter for clock output on the regular I/O

(F_OUT≥ 100 MHz)

(6),

t_{OUTPJ_IO}

(9)

Period Jitter for clock output on the regular I/O

(F_OUT< 100 MHz)

mUI (p-p)

ps (p-p)

Cycle-to-cycle jitter for clock output on the regular I/O

(F_OUT≥ 100 MHz)

(6),

t_{OUTCCJ_IO}

(9)

Cycle-to-cycle jitter for clock output on the regular I/O

(F_OUT< 100 MHz)

—

mUI (p-p)

t_{OUTPJ_DC_F}

Period jitter for dedicated clock output in fractional mode

TBD ⁽¹⁾

—

Cycle-to-cycle jitter for dedicated clock output in fractional

mode

t_{OUTCCJ_DC_F}

t_{OUTPJ_IO_F}

t_{OUTCCJ_IO_F}

Period Jitter for clock output on the regular I/O in fractional

mode

—

TBD ⁽¹⁾

—

Cycle-to-cycle jitter for clock output on the regular I/O in

fractional mode

Period jitter for dedicated clock output in cascaded PLLs

(F_OUT≥100 MHz)

(1)

TBD

ps (p-p)

mUI (p-p)

%

t_{CASC_OUTPJ_DC}

(6), (7)

Period jitter for dedicated clock output in cascaded PLLs

(F_OUT< 100 MHz)

(1)

TBD

Frequency drift after PFDENA is disabled for a duration of

100 µs

t_DRIFT

10

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–29

Switching Characteristics

(1)

Table 2–25. PLL Specifications for Arria V Devices—Preliminary

(Part 3 of 3)

Min

Symbol

dK_BIT

k_VALUE

f_RES

Parameter

Bit number of Delta Sigma Modulator (DSM)

Numerator of Fraction

Typ

Max

—

TBD ⁽¹⁾

Unit

—

24

bits

—

TBD ⁽¹⁾8388608

Resolution of VCO frequency (f_INPFD=100 MHz)

—

5.96

—

Hz

Notes to Table 2–25:

(1) Pending silicon characterization.

(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O

standard.

(3) This specification is limited by the lower of the two: I/O f_MAXor F_OUTof the PLL.

(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.

(5) F_REFis fIN/N when N = 1.

(6) Peak-to-peak jitter with a probability level of 10^–12(14 sigma, 99.99999999974404 % confidence level). The output jitter specification applies to

the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different

measurement method and are available in Table 2–33 on page 2–35.

(7) The cascaded PLL specification is only applicable with the following conditions:

a. Upstream PLL: 0.59 MHz  Upstream PLL BW < 1 MHz

b. Downstream PLL: Downstream PLL BW > 2 MHz

(8) High bandwidth PLL settings are not supported in external feedback mode.

(9) External memory interface clock output jitter specifications use a different measurement method, which are available in Table 2–33 on page 2–35.

DSP Block Specifications

Table 2–26 lists the Arria V DSP block performance specifications.

Table 2–26. DSP Block Performance Specifications for Arria V Devices—Preliminary

Performance

–C4

Speed

Grade

–C5, I5

Speed

Grade

–C6

Speed

Grade

Mode

Unit

Modes using One DSP Block

Independent 9 x 9 Multiplication

370

310

370

310

250

310

220

200

220

MHz

Independent 18 x 19 Multiplication

Independent 18 x 18 Multiplication

Independent 27 x 27 Multiplication

Independent 18 x 25 Multiplication

Independent 20 x 24 Multiplication

Two 18 x 19 Multiplier Adder Mode

18 x 18 Multiplier Added Summed with 36-bit Input

Modes using Two DSP Blocks

Complex 18 x 19 multiplication

370

310

370

310

250

310

220

200

220

MHz

Two 27 x 27 Multiplier Adder

Four 18 x 19 Multiplier Adder

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–30

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

Memory Block Specifications

Table 2–27 lists the Arria V memory block specifications.

Table 2–27. Memory Block Performance Specifications for Arria V Devices—Preliminary ^{(1), (2)}

Resources Used

Performance

C5,I5

Memory

Mode

Unit

C4

C6

ALUTs

Memory

Speed Grade Speed Grade Speed Grade

Single port, all supported widths

0

1

500

450

400

MHz

Simple dual-port, all supported

widths

500

450

400

MLAB

Simple dual-port with read and

write at the same address

0

1

400

350

300

MHz

ROM, all supported width

—

0

—

1

500

400

450

350

400

285

MHz

Single-port, all supported widths

Simple dual-port, all supported

widths

0

1

400

315

400

350

275

350

285

240

285

MHz

Simple dual-port with the

read-during-write option set to

Old Data, all supported widths

M10K

Block

True dual port, all supported

widths

ROM, all supported widths

0

1

400

1,275

850

350

285

MHz

ps

Min Pulse Width (clock high time)

Min Pulse Width (clock low time)

—

1,360

1,060

1,445

1,175

ps

Notes to Table 2–27:

(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL

set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.

(2) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in f_MAX

.

Temperature Sensing Diode Specifications

Table 2–28 lists the specifications for the Arria V internal temperature sensing diode.

Table 2–28. Internal Temperature Sensing Diode Specifications for Arria V Devices—Preliminary

Offset

Temperature

Range

Conversion

Time

Minimum Resolution with no

Missing Codes

Accuracy Calibrated Sampling Rate

Option

Resolution

Frequency:

1 MHz

–40 to 100°C

8°C

No

< 100 ms

8 bits

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–31

Switching Characteristics

Periphery Performance

This section describes periphery performance and the high-speed I/O and external

memory interface.

I/O performance supports several system interfaces, such as the LVDS high-speed

I/O interface, external memory interface, and the PCI/PCI-X bus interface. GPIO

standards such as 3.3-, 2.5-, 1.8-, and 1.5-V LVTTL/LVCMOS are capable of a typical

167 MHz and 1.2 LVCMOS at 100 MHz interfacing frequency with a 10 pF load.

1

Actual achievable frequency depends on design- and system-specific factors. You

must perform HSPICE/IBIS simulations based on your specific design and system

setup to determine the maximum achievable frequency in your system.

High-Speed I/O Specification

Table 2–29 lists high-speed I/O timing for Arria V devices.

Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary ^{(1), (2), (3)}(Part 1 of 3)

–4 Speed Grade

Min Typ Max

–5 Speed Grade

Min Typ Max

–6 Speed Grade

Min Typ Max

Symbol

Conditions

Unit

f_{HSCLK_in}(input

clock

frequency)

True

Differential

I/O Standards

(5)

Clock boost factor W = 1 to 40

5

—

625

TBD

5

—

625

TBD

5

—

TBD

MHz

f_{HSCLK_in}(input

clock

frequency)

Single Ended

Clock boost factor W = 1 to 40

MHz

I/O Standards

(4)

f_{HSCLK_in}(input

clock

frequency)

Single Ended

Clock boost factor W = 1 to 40

5

—

5

—

5

—

MHz

I/O Standards

(3)

f_{HSCLK_OUT}

(output clock

frequency)

(6)

—

625

TBD

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–32

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary ^{(1), (2), (3)}(Part 2 of 3)

–4 Speed Grade

–5 Speed Grade

–6 Speed Grade

Symbol

Conditions

Unit

Min Typ

Max

Min Typ

Max

Min Typ

Max

Transmitter

(7)

True

SERDES factor J = 3 to 10

—

1250

—

1250

—

1050

Mbps

Differential

I/O Standards

- f_HSDR(data

rate)

SERDES factor J = 1 to 2, Uses

DDR Registers

(7)

Emulated

Differential

I/O Standards

with Three

External

(7)

SERDES factor J = 4 to 10

—

TBD

—

TBD

—

TBD

Mbps

Output

Resistor

Networks -

f_HSDR(data

(8)

rate)

Total Jitter for Data Rate,

600 Mbps - 1.25 Gbps

—

160

0.1

—

160

0.1

—

160

0.1

ps

UI

ps

t_{x Jitter}- True

Differential

I/O Standards

Total Jitter for Data Rate,

< 600 Mbps

t_{x Jitter}

-

Total Jitter for Data Rate,

600 Mbps – 1.25 Gbps

TBD

Emulated

Differential

I/O Standards

with Three

External

Total Jitter for Data Rate

< 600 Mbps

—

TBD

—

TBD

—

TBD

UI

Output

Resistor

Network

TX output clock duty cycle for both

True and Emulated Differential I/O

Standards

t_DUTY

45

—

50

—

55

45

—

50

—

55

45

—

50

—

55

%

ps

True Differential I/O Standards

200

250

200

250

200

300

Emulated Differential I/O

Standards with Three External

Output Resistor Networks

t_{RISE &}t_FALL

True Differential I/O Standards

—

150

300

—

150

300

—

150

300

ps

TCCS

Emulated Differential I/O

Standards

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–33

Switching Characteristics

Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary ^{(1), (2), (3)}(Part 3 of 3)

–4 Speed Grade

Min Typ Max

–5 Speed Grade

Min Typ Max

–6 Speed Grade

Symbol

Conditions

Unit

Min Typ

Max

Receiver

True

Differential

I/O Standards

- f_HSDRDPA

(data rate)

SERDES factor J = 3 to 10

—

1250

—

1250

—

1050

Mbps

(7)

(9)

(7)

(9)

(7)

(9)

(7)

—

Mbps

f_HSDR(data

SERDES factor J = 1 to 2, Uses

DDR Registers

rate)

DPA Mode

DPA run

length

—

10000

300

—

10000

300

—

10000

300

UI

Soft CDR mode

Soft-CDR

ppm tolerance

ppm

ps

Non DPA Mode

Sampling

Window

300

Notes to Table 2–29:

(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.

(2) When J = 1 or 2, bypass the SERDES block.

(3) This applies to LVDS source synchronous mode only.

(4) This applies to DPA and soft-CDR modes only.

(5) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.

(6) This is achieved by using the LVDS clock network.

(7) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that

you use. The I/O differential buffer and input register do not have a minimum toggle rate.

(8) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter

channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

(9) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin,

transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

Figure 2–1 shows the DPA lock time specifications with the DPA PLL calibration

option enabled.

Figure 2–1. DPA Lock Time Specification with DPA PLL Calibration Enabled

rx_reset

DPA Lock Time

rx_dpa_locked

256 data

transitions

96 slow

clock cycles

256 data

transitions

96 slow

clock cycles

256 data

transitions

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–34

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

Table 2–30 lists the DPA lock time specifications for Arria V devices.

(1), (2), (3)

Table 2–30. DPA Lock Time Specifications for Arria V Devices—Preliminary

Number of Data

Number of

Transitions in One

Standard

Training Pattern

Repetitions per 256

Maximum

Repetition of the

Training Pattern

(4)

Data Transitions

SPI-4

00000000001111111111

00001111

2

4

8

128

64

640 data transitions

Parallel Rapid I/O

10010000

10101010

32

Miscellaneous

01010101

32

Notes to Table 2–30:

(1) The DPA lock time is for one channel.

(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.

(3) The DPA lock time stated in this table applies to both commercial and industrial grades.

(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.

Figure 2–2 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for

a data rate equal to 1.25 Gbps.

Figure 2–2. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to 1.25 Gbps

LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification

25

8.5

0.35

0.1

F3

F2

F1

F4

Jitter Frequency (Hz)

Table 2–31 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a

data rate equal to 1.25 Gbps.

Table 2–31. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.25 Gbps—Preliminary

Jitter Frequency (Hz)

Sinusoidal Jitter (UI)

25.000

F1

F2

F3

F4

10,000

17,565

25.000

1,493,000

50,000,000

0.350

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Arria V Devices

2–35

Switching Characteristics

Figure 2–3 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for

a data rate less than 1.25 Gbps.

Figure 2–3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps

Sinusoidal Jitter Amplitude

20db/dec

0.1 UI

P-P

Frequency

20 MHz

baud/1667

DQS Logic Block and Memory Output Clock Jitter Specifications

Table 2–32 lists the DQS phase shift error for Arria V devices.

Table 2–32. DQS Phase Shift Error Specification for DLL-Delayed Clock (t_{DQS_PSERR}) for Arria V

Devices—Preliminary ^{(1), (2)}

Number of DQS Delay

Buffer

–C4

Speed Grade

–C5, I5

Speed Grade

–C6

Speed Grade

Unit

2

57

58

74

ps

Notes to Table 2–32:

(1) The numbers are preliminary pending silicon characterization.

(2) This error specification is the absolute maximum and minimum error. For example, skew on two DQS delay buffers

in a –4 speed grade is 58 ps or 29 ps.

Table 2–33 lists the memory output clock jitter specifications for Arria V devices.

(1)

Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary

(Part 1 of 2)

–6

–4

–5

Clock

Speed Grade

Parameter

Symbol

Unit

Network

Min

–50

Max

50

Min

–55

Max

55

Min

–55

Max

55

Clock period jitter

Regional

Global

t_JIT(per)

t_JIT(cc)

ps

Cycle-to-cycle period jitter

Duty cycle jitter

–100

–50

100

50

–110

–82.5

–165

110

82.5

165

–110

–82.5

–165

110

82.5

165

t_JIT(duty)

t_JIT(per)

t_JIT(cc)

Clock period jitter

–75

75

Cycle-to-cycle period jitter

Global

–150

150

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–36

Chapter 2: Device Datasheet for Arria V Devices

Switching Characteristics

(1)

Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary

(Part 2 of 2)

–6

–4

–5

Clock

Network

Speed Grade

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

Duty cycle jitter

Global

t_JIT(duty)

–75

75

–90

90

–90

90

ps

Note to Table 2–33:

(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.

OCT Calibration Block Specifications

Table 2–34 lists the OCT calibration block specifications for Arria V devices.

Table 2–34. OCT Calibration Block Specifications for Arria V Devices—Preliminary

Symbol

Description

Min

Typ

Max

Unit

OCTUSRCLK

Clock required by OCT calibration blocks

—

20

MHz

Number of OCTUSRCLK clock cycles required for

R_SOCT /R_TOCT calibration

T_OCTCAL

—

1000

32

—

Cycles

Number of OCTUSRCLK clock cycles required for OCT code

to shift out

T_OCTSHIFT

Time required between the dyn_term_ctrland oesignal

transitions in a bidirectional I/O buffer to dynamically switch

between R_SOCT and R_TOCT

T_{RS_RT}

—

2.5

—

ns

Figure 2–4 shows the T_{RS_RT}for dyn_term_ctrland oesignals.

Figure 2–4. Timing Diagram for dyn_term_ctrl and oe Signals

Tristate

RX

oe

RX

dyn_term_ctrl

TRS_RT

Duty Cycle Distortion (DCD) Specifications

Table 2–35 lists the worst-case DCD for Arria V devices.

Table 2–35. Worst-Case DCD on Arria V I/O Pins—Preliminary

–C5,I5 Speed

–C6 Speed

Grade

–C4 Speed Grade

Grade

Symbol

Unit

Min

Max

Min

Max

Min

45

Max

Output Duty Cycle

45

55

45

55

%

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–37

Configuration Specification

This section provides configuration specifications and timing for Arria V devices.

These characteristics can be designated as Preliminary or Final.

■

Preliminary characteristics are created using simulation results, process data, and

other known parameters. The title of these tables show the designation as

“Preliminary.”

Final numbers are based on actual silicon characterization and testing. The

numbers reflect the actual performance of the device under worst-case silicon

process, voltage, and junction temperature conditions. There are no designations

on finalized tables.

POR Specifications

Table 2–36 lists the specifications for fast and standard POR for Arria V devices.

Table 2–36. Fast and Standard POR Delay Specification for Arria V Devices ⁽¹⁾

POR Delay

Fast ⁽²⁾

Minimum (ms)

Maximum (ms)

4

12

Standard ⁽³⁾

100

300

Notes to Table 2–36:

(1) Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Arria V Devices”

table in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.

(2) When the PORSELsignal is high, the device is in fast POR delay.

(3) When the PORSELsignal is low, the device is in standard POR delay.

JTAG Configuration Timing

Table 2–37 lists the JTAG timing parameters and values for Arria V devices.

Table 2–37. JTAG Timing Parameters and Values for Arria V Devices—Preliminary

Symbol

Description

TCK clock period

Min

30

14

1

Max

—

Unit

ns

t_JCP

t_JCH

t_JCL

TCK clock high time

—

TCK clock low time

—

t_{JPSU (TDI)}

t_{JPSU (TMS)}

t_JPH

TDI JTAG port setup time

TMS JTAG port setup time

JTAG port hold time

—

3

—

5

—

(1)

t_JPCO

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

—

11

14

(1)

t_JPZX

t_JPXZ

Note to Table 2–37:

(1) A 1-ns adder is required for each V_CCIOvoltage step down from 3.0 V. For example, t_JPCO= 12 ns if V_CCIOof the TDO

I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–38

Chapter 2: Device Datasheet for Arria V Devices

Configuration Specification

FPP Configuration Timing

This section describes the fast passive parallel (FPP) configuration timing parameters

for Arria V devices.

DCLK-to-DATA[] Ratio (r) for FPP Configuration

FPP configuration requires a different DCLK-to-DATA[]ratio when you turn on

encryption or the compression feature.

Table 2–38 lists the DCLK-to-DATA[]ratio for each combination.

Table 2–38. DCLK-to-DATA[] Ratio for Arria V Devices ⁽¹⁾

Configuration Scheme

Encryption

Compression

DCLK-to-DATA[] ratio (r)

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

1

2

1

2

4

FPP (8-bit wide)

FPP (16-bit wide)

Note to Table 2–38:

(1) Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the DATA[]rate in

byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the DCLKfrequency

must be 2 times the DATA[]rate in Wps.

FPP Configuration Timing when DCLK to DATA[] = 1

Figure 2–5 shows the timing waveform for a FPP configuration when using a MAX^®II

device as an external host. This timing waveform shows timing when the DCLK-to-

DATA[]ratio is 1.

1

When you enable decompression or the design security feature, the DCLK-to-DATA[]

ratio varies for FPP x8 and FPP x16. For the respective DCLK-to-DATA[]ratio, refer to

Table 2–38.

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Arria V Devices

2–39

Configuration Specification

(1)

Figure 2–5. DCLK-to-DATA[] FPP Configuration Timing Waveform When the Ratio is 1

t_CF2ST1

t_CFG

t_CF2CK

nCONFIG

nSTATUS (2)

t_STATUS

(6)

t_CF2ST0

t_CLK

CONF_DONE (3)

t

_CHt_CL

t_CF2CD

t_ST2CK

(4)

DCLK

t_DH

Word 0 Word 1 Word 2 Word 3

Word n

DATA[15..0](5)

Word n-2 Word n-1

User Mode

t_DSU

High-Z

User I/O

(7)

INIT_DONE

t_CD2UM

Notes to Figure 2–5:

(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG

, nSTATUS, and CONF_DONEare at logic-high levels. When

nCONFIGis pulled low, a reconfiguration cycle begins.

(2) After power up, the Arria V device holds nSTATUSlow for the time of the POR delay.

(3) After power up, before and during configuration, CONF_DONEis low.

(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.

(5) For FPP x16, use DATA[15..0]. For FPP x8, use DATA[7..0]. DATA[15..0]are available as a user I/O pin after configuration. The state of this

pin depends on the dual-purpose pin settings.

(6) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONEis released high when the Arria V device

receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization and

enter user mode.

(7) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONE goes low.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–40

Chapter 2: Device Datasheet for Arria V Devices

Configuration Specification

Table 2–39 lists the timing parameters for Arria V devices for FPP configuration when

the DCLK-to-DATA[]ratio is 1.

(1)

Table 2–39. DCLK-to-DATA[] FPP Timing Parameters for Arria V Devices When the Ratio is 1—Preliminary

Symbol

t_CF2CD

t_CF2ST0

t_CFG

Parameter

nCONFIGlow to CONF_DONElow

nCONFIGlow to nSTATUSlow

Minimum

Maximum

600

Unit

ns

—

600

ns

nCONFIGlow pulse width

2

268

—

µs

(2)

nSTATUSlow pulse width

1506

t_STATUS

t_CF2ST1

t_CF2CK

t_ST2CK

t_DSU

(3)

nCONFIGhigh to nSTATUShigh

nCONFIGhigh to first rising edge on DCLK

nSTATUShigh to first rising edge of DCLK

1506

2

—

DATA[]setup time before rising edge on

DCLK

5.5

—

ns

DATA[]hold time after rising edge on DCLK

DCLKhigh time

0

—

ns

t_DH

0.45 x 1/f_MAX

t_CH

DCLKlow time

0.45 x 1/f_MAX

—

ns

t_CL

DCLKperiod

1/f_MAX

—

ns

t_CLK

f_MAX

t_R

DCLKfrequency (FPP x8/ x16)

Input rise time

—

125

40

MHz

ns

—

Input fall time

—

175

40

ns

t_F

(4)

CONF_DONEhigh to user mode

437

—

µs

t_CD2UM

t_CD2CU

t_CD2UMC

CONF_DONEhigh to CLKUSRenabled

4 × maximum DCLKperiod

—

t

_CD2CU+ (T_initx CLKUSR

CONF_DONEhigh to user mode with CLKUSR

option on

—

period)

Number of clock cycles required for device

initialization

T_init

17,408

Cycles

Notes to Table 2–39:

(1) Use these timing parameters when the DCLK-to-DATA[]ratio is 1. To find the DCLK-to-DATA[]ratio for your system, refer Table 2–38 on

page 2–38.

(2) You can obtain this value if you do not delay configuration by extending the nCONFIGor the nSTATUSlow pulse width.

(3) You can obtain this value if you do not delay configuration by externally holding the nSTATUSlow.

(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–41

Configuration Specification

FPP Configuration Timing when DCLK to DATA[] > 1

Figure 2–6 shows the timing waveform for a FPP configuration when using a MAX II

device or microprocessor as an external host. This waveform shows timing when the

DCLK-to-DATA[]ratio is more than 1.

(1), (2)

Figure 2–6. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1

t_CF2ST1

t_CFG

t_CF2CK

nCONFIG

nSTATUS (3)

t_STATUS

t_CF2ST0

CONF_DONE (4)

t

CL

t_CF2CD

(8)

t_ST2CK

t

CH

DCLK (6)

DATA[15..0] (8)

User I/O

(7)

(5)

1

2

1

2

r

1

2

r

t

CLK

n

Word 0

Word 1

Word (n-1) Word

User Mode

Word 3

t

t_DSU

DH

High-Z

(9)

INIT_DONE

t_CD2UM

Notes to Figure 2–6:

(1) To find the DCLK-to-DATA[]ratio for your system, refer Table 2–38 on page 2–38.

(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONEare at logic high levels.

When nCONFIGis pulled low, a reconfiguration cycle begins.

(3) After power up, the Arria V device holds nSTATUSlow for the time as specified by the POR delay.

(4) After power up, before and during configuration, CONF_DONEis low.

(5) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.

(6) “r” denotes the DCLK-to-DATA[]ratio. For the DCLK-to-DATA[]ratio based on the decompression and the design security feature enable

settings, refer to Table 2–38 on page 2–38.

(7) If needed, pause DCLKby holding it low. When DCLKrestarts, the external host must provide data on the DATA[15..0]pins prior to sending

the first DCLKrising edge.

(8) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONEis released high after the Arria V device

receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization

and enter user mode.

(9) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–42

Chapter 2: Device Datasheet for Arria V Devices

Configuration Specification

Table 2–40 lists the timing parameters for Arria V devices when the

DCLK-to-DATA[]ratio is more than 1.

Table 2–40. DCLK-to-DATA[] FPP Timing Parameters for Arria V Devices When the Ratio is >1—Preliminary ⁽¹⁾

Symbol

t_CF2CD

t_CF2ST0

t_CFG

Parameter

nCONFIGlow to CONF_DONElow

nCONFIGlow to nSTATUSlow

Minimum

Maximum

600

Unit

ns

—

600

ns

nCONFIGlow pulse width

2

268

—

µs

(2)

nSTATUSlow pulse width

1506

t_STATUS

t_CF2ST1

t_CF2CK

t_ST2CK

t_DSU

(3)

nCONFIGhigh to nSTATUShigh

nCONFIGhigh to first rising edge on DCLK

nSTATUShigh to first rising edge of DCLK

1506

2

—

DATA[]setup time before rising edge on

DCLK

5.5

—

ns

DATA[]hold time after rising edge on DCLK

DCLKhigh time

3 x 1/f_DCLK

—

ns

t_DH

0.45 x 1/f_MAX

t_CH

DCLKlow time

0.45 x 1/f_MAX

—

ns

t_CL

DCLKperiod

1/f_MAX

—

ns

t_CLK

f_MAX

t_R

DCLKfrequency (FPP x8/ x16)

Input rise time

—

125

40

MHz

ns

—

Input fall time

—

175

40

ns

t_F

(4)

CONF_DONEhigh to user mode

437

—

µs

t_CD2UM

t_CD2CU

t_CD2UMC

CONF_DONEhigh to CLKUSRenabled

4 × maximum DCLKperiod

—

t

_CD2CU+ (T_initx CLKUSR

CONF_DONEhigh to user mode with CLKUSR

option on

—

period)

Number of clock cycles required for device

initialization

T_init

17,408

Cycles

Notes to Table 2–40:

(1) Use these timing parameters when you use decompression and the design security features.

(2) This value can be obtained if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.

(3) This value can be obtained if you do not delay configuration by externally holding nSTATUSlow.

(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–43

Configuration Specification

AS Configuration Timing

Figure 2–7 shows the timing waveform for the active serial (AS) x1 mode and AS x4

mode configuration timing.

Figure 2–7. AS Configuration Timing

t

(1)

POR

nCONFIG

nSTATUS

CONF_DONE

nCSO

DCLK

t

CO

t

DH

Read Address

AS_DATA0/ASDO

AS_DATA1 (2)

t

SU

bit 1

bit 0

bit N - 1

bit N

t

(3)

CD2UM

INIT_DONE (4)

User I/O

User Mode

Notes to Figure 2–7:

(1) The AS scheme supports standard and fast POR delay (t_POR). For t_PORdelay information, refer to the “POR Delay Specification” section in the

Configuration, Design Security, and remote System Upgrades in Arria V Devices chapter.

(2) If you are using AS x4 mode, this signal represents the AS_DATA[3..0]and EPCQ sends in 4-bits of data for each DCLKcycle.

(3) The initialization clock can be from the internal oscillator or CLKUSRpin.

(4) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.

Table 2–41 lists the timing parameters for AS x1 and AS x4 configurations in Arria V

devices.

(1), (2)

Table 2–41. AS Timing Parameters for AS x1 and x4 Configurations in Arria V Devices—Preliminary

Symbol

t_CO

Parameter

Minimum

Maximum

Unit

µs

DCLK falling edge to the AS_DATA0

/

ASDOoutput

—

4

—

t_SU

Data setup time before the rising edge on DCLK

Data hold time after the rising edge on DCLK

CONF_DONEhigh to user mode

1.5

ns

t_H

0

175

—

ns

t_CD2UM

t_CD2CU

t_CD2UMC

437

—

µs

CONF_DONEhigh to CLKUSRenabled

4 x maximum DCLKperiod

—

t

_CD2CU+ (T_initx CLKUSR

CONF_DONEhigh to user mode with CLKUSR

—

option on

period)

Number of clock cycles required for device

initialization

T_init

17,408

Cycles

Notes to Table 2–41:

(1) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.

(2) The t_CF2CD, t_CF2ST0, t_CFG, t_STATUS, and t_CF2ST1timing parameters are identical to the timing parameters for PS mode listed in Table 2–43 on

page 2–45.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–44

Chapter 2: Device Datasheet for Arria V Devices

Configuration Specification

Table 2–42 lists the internal clock frequency specification for the AS configuration

scheme.

Table 2–42. DCLK Frequency Specification in the AS Configuration Scheme—Preliminary ^{(1), (2)}

Minimum

Typical

7.9

Maximum

12.5

Unit

MHz

5.3

10.6

21.3

15.7

31.4

62.9

25.0

50.0

42.6

100.0

Notes to Table 2–42:

(1) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source.

(2) The AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.

PS Configuration Timing

Figure 2–8 shows the timing waveform for a passive serial (PS) configuration when

using a MAX II device or microprocessor as an external host.

(1)

Figure 2–8. PS Configuration Timing Waveform

t_CF2ST1

t_CFG

t_CF2CK

nCONFIG

nSTATUS (2)

t_STATUS

t_CF2ST0

(6)

t_CLK

CONF_DONE (3)

t

_CHt_CL

t_CF2CD

t_ST2CK

(4)

(5)

DCLK

t_DH

Bit 2 Bit 3

Bit n

Bit 0 Bit 1

DATA0

t_DSU

High-Z

User I/O

User Mode

INIT_DONE (7)

t_CD2UM

Notes to Figure 2–8:

(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG

, nSTATUS, and CONF_DONEare at logic high levels. When

nCONFIGis pulled low, a reconfiguration cycle begins.

(2) After power up, the Arria V device holds nSTATUSlow for the time of the POR delay.

(3) After power up, before and during configuration, CONF_DONEis low.

(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.

(5) DATA0is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins

Option.

(6) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONEis released high after the Arria V device

receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization

and enter user mode.

(7) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–45

Configuration Specification

Table 2–43 lists the PS timing parameter for Arria V devices.

Table 2–43. PS Timing Parameters for Arria V Devices—Preliminary

Symbol

t_CF2CD

Parameter

nCONFIGlow to CONF_DONElow

nCONFIGlow to nSTATUSlow

Minimum

Maximum

600

Unit

ns

—

t_CF2ST0

600

ns

nCONFIGlow pulse width

nSTATUSlow pulse width

nCONFIGhigh to nSTATUShigh

nCONFIGhigh to first rising edge on DCLK

nSTATUShigh to first rising edge of DCLK

DATA[]setup time before rising edge on DCLK

DATA[]hold time after rising edge on DCLK

DCLKhigh time

2

—

µs

ns

t_CFG

(1)

268

1506

t_STATUS

t_CF2ST1

t_CF2CK

t_ST2CK

t_DSU

(2)

—

1506

—

2

5.5

—

0

—

ns

MHz

ns

µs

—

t_DH

0.45 x 1/f_MAX

—

t_CH

DCLKlow time

0.45 x 1/f_MAX

—

t_CL

DCLKperiod

1/f_MAX

—

t_CLK

DCLKfrequency

—

125

40

f_MAX

t_R

Input rise time

—

Input fall time

—

175

40

t_F

CONF_DONEhigh to user mode ⁽³⁾

CONF_DONEhigh to CLKUSRenabled

437

—

t_CD2UM

t_CD2CU

t_CD2UMC

4 x maximum DCLKperiod

t

_CD2CU+ (T_initx CLKUSR

CONF_DONEhigh to user mode with CLKUSRoption on

—

period)

Number of clock cycles required for device

initialization

T_init

17,408

Cycles

Notes to Table 2–43:

(1) You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.

(2) You can obtain this value if you do not delay configuration by externally holding nSTATUSlow.

(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–46

Chapter 2: Device Datasheet for Arria V Devices

Configuration Specification

Remote System Upgrades Circuitry Timing Specification

Table 2–44 lists the timing parameter specifications for the remote system upgrade

circuitry.

Table 2–44. Remote System Upgrade Circuitry Timing Specification

Parameter

Minimum

Maximum

Unit

(1)

(3)

—

40

MHz

t_{MAX_RU_CLK}

(2)

t_{RU_nCONFIG}

250

—

ns

t_{RU_nRSTIMER}

Notes to Table 2–44:

(1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE

megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification.

(2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the

minimum timing specification. For more information, refer to the “Remote System Upgrade State Machine”

section in the Device Interfaces and Integration Basics for Arria V Devices chapter.

(3) This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE megafunction high for the

minimum timing specification. For more information, refer to the “User Watchdog Timer” section in the Device

Interfaces and Integration Basics for Arria V Devices chapter.

User Watchdog Internal Oscillator Frequency Specification

Table 2–45 lists the frequency specifications for the user watchdog internal oscillator.

Table 2–45. User Watchdog Internal Oscillator Frequency Specifications—Preliminary

Minimum

Typical

Maximum

Unit

5.3

7.9

12.5

MHz

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Chapter 2: Device Datasheet for Arria V Devices

2–47

I/O Timing

Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the

Quartus II Timing Analyzer.

Excel-based I/O timing provides pin timing performance for each device density and

speed grade. The data is typically used prior to designing the FPGA to get an estimate

of the timing budget as part of the link timing analysis. The Quartus II Timing

Analyzer provides a more accurate and precise I/O timing data based on the specifics

of the design after you complete place-and-route.

f

You can download the Excel-based I/O Timing spreadsheet from the Arria V Devices

Literature webpage.

Programmable IOE Delay

Table 2–46 lists the Arria V IOE programmable delay settings.

Table 2–46. IOE Programmable Delay for Arria V Devices ⁽¹⁾

Fast Model

Slow Model

Available

Settings

Minimum

Offset

Parameter

Unit

Industrial

Commercial

TBD

C4

C5, I5

TBD

C6

TBD

ns

TBD

Note to Table 2–46:

(1) Pending the Quartus II software extraction.

Programmable Output Buffer Delay

Table 2–47 lists the delay chain settings that control the rising and falling edge delays

of the output buffer. The default delay is 0 ps.

(1), (2)

Table 2–47. Programmable Output Buffer Delay—Preliminary

Symbol

Parameter

Typical

0 (default)

50

Unit

ps

Rising and/or falling edge

delay

D_OUTBUF

100

ps

150

ps

Notes to Table 2–47:

(1) Pending the Quartus II software extraction.

(2) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay

Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the

Output Buffer Delay assignment.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–48

Chapter 2: Device Datasheet for Arria V Devices

Glossary

Table 2–48 lists the glossary for this chapter.

Table 2–48. Glossary Table (Part 1 of 4)

Letter

Subject

Definitions

A

B

C

—

Receiver Input Waveforms

Single-Ended Waveform

Positive Channel (p) = V

IH

V

ID

Negative Channel (n) = V

Ground

IL

V

CM

Differential Waveform

V

ID

p - n = 0 V

V

ID

Differential I/O

Standards

D

Transmitter Output Waveforms

Single-Ended Waveform

Positive Channel (p) = V

OH

V

OD

Negative Channel (n) = V

Ground

OL

V

CM

Differential Waveform

V

OD

p - n = 0 V

V

OD

E

F

—

f_HSCLK

Left/right PLL input clock frequency.

High-speed I/O block—Maximum/minimum LVDS data transfer rate

(f_HSDR= 1/TUI), non-DPA.

f_HSDR

High-speed I/O block—Maximum/minimum LVDS data transfer rate

(f_HSDRDPA= 1/TUI), DPA.

f_HSDRDPA

G

H

I

—

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Arria V Devices

2–49

Glossary

Table 2–48. Glossary Table (Part 2 of 4)

Letter

Subject

Definitions

High-speed I/O block—Deserialization factor (width of parallel data bus).

JTAG Timing Specifications:

J

TMS

TDI

t_JCP

J

JTAG Timing

Specifications

t_JCH

t _JCL

t_JPH

t_JPSU

TCK

TDO

t_JPXZ

t_JPZX

t_JPCO

K

L

M

N

O

—

(1)

Diagram of PLL Specifications

CLKOUT Pins

f_{OUT_EXT}

Switchover

4

CLK

f_IN

f_INPFD

N

GCLK

RCLK

Counters

C0..C17

f_VCO

VCO

f_OUT

PFD

CP

LF

Core Clock

PLL

Specifications

P

Delta Sigma

Modulator

Key

External Feedback

Reconfigurable in User Mode

Note:

(1) Core Clockcan only be fed by dedicated clock input pins or PLL outputs.

Q

R

—

R_L

Receiver differential input discrete resistor (external to the Arria V device).

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–50

Chapter 2: Device Datasheet for Arria V Devices

Glossary

Table 2–48. Glossary Table (Part 3 of 4)

Letter

Subject

Definitions

Timing Diagram—the period of time during which the data must be valid in order to capture

it correctly. The setup and hold times determine the ideal strobe position in the sampling

window, as shown:

Sampling

Bit Time

window (SW)

Sampling Window

(SW)

RSKM

0.5 x TCCS

The JEDEC standard for the SSTl and HSTL I/O defines both the AC and DC input signal

values. The AC values indicate the voltage levels at which the receiver must meet its timing

specifications. The DC values indicate the voltage levels at which the final logic state of the

receiver is unambiguously defined. After the receiver input has crossed the AC value, the

receiver changes to the new logic state.

The new logic state is then maintained as long as the input stays beyond the AC threshold.

This approach is intended to provide predictable receiver timing in the presence of input

waveform ringing, as shown:

S

Single-Ended Voltage Referenced I/O Standard

Single-ended

voltage

V_CCIO

referenced I/O

standard

V_OH

V_IH

(

)

AC

V_IH(DC)

V_REF

V_IL(DC)

V_IL(AC

)

V_OL

V_SS

t_C

High-speed receiver/transmitter input and output clock period.

The timing difference between the fastest and slowest output edges, including the t_CO

variation and clock skew, across channels driven by the same PLL. The clock is included in

the TCCS measurement (refer to the Timing Diagram figure under SW in this table).

TCCS (channel-

to-channel-skew)

High-speed I/O block—Duty cycle on high-speed transmitter output clock.

Timing Unit Interval (TUI)

t_DUTY

The timing budget allowed for skew, propagation delays, and the data sampling window.

T

(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)

t_FALL

Signal high-to-low transition time (80–20%)

Cycle-to-cycle jitter tolerance on the PLL clock input

Period jitter on the GPIO driven by a PLL

Period jitter on the dedicated clock output driven by a PLL

Signal low-to-high transition time (20–80%)

—

t_INCCJ

t_{OUTPJ_IO}

t_{OUTPJ_DC}

t_RISE

U

—

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

February 2012 Altera Corporation

Chapter 2: Device Datasheet for Arria V Devices

2–51

Document Revision History

Table 2–48. Glossary Table (Part 4 of 4)

Letter

Subject

V_CM(DC)

Definitions

DC Common mode input voltage.

V_ICM

Input Common mode voltage—The common mode of the differential signal at the receiver.

Input differential voltage swing—The difference in voltage between the positive and

complementary conductors of a differential transmission at the receiver.

V_ID

V_DIF(AC)

V_DIF(DC)

AC differential input voltage—Minimum AC input differential voltage required for switching.

DC differential input voltage— Minimum DC input differential voltage required for switching.

Voltage input high—The minimum positive voltage applied to the input which is accepted by

the device as a logic high.

V_IH

V_IH(AC)

V_IH(DC)

High-level AC input voltage

High-level DC input voltage

V

Voltage input low—The maximum positive voltage applied to the input which is accepted by

the device as a logic low.

V_IL

V_IL(AC)

V_IL(DC)

Low-level AC input voltage

Low-level DC input voltage

Output Common mode voltage—The common mode of the differential signal at the

transmitter.

V_OCM

V_OD

Output differential voltage swing—The difference in voltage between the positive and

complementary conductors of a differential transmission at the transmitter.

V_SWING

V_X

Differential input voltage

Input differential cross point voltage

Output differential cross point voltage

High-speed I/O block—Clock Boost Factor

V_OX

W

X,

Y,

Z

—

Document Revision History

Table 2–49 lists the revision history for this chapter.

Table 2–49. Document Revision History

Date

Version

1.3

Changes

■ Updated Table 2–1.

February 2012

December 2011

November 2011

August 2011

■ Updated Transceiver-FPGA Fabric Interface rows in Table 2–20.

■ Updated V_CCPdescription.

1.2

Updated Table 2–1, and Table 2–3.

■ Updated Table 2–1, Table 2–19, Table 2–26, and Table 2–36.

■ Added Table 2–5.

1.1

■ Added Figure 2–4.

1.0

Initial release.

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

2–52

Chapter 2: Device Datasheet for Arria V Devices

Document Revision History

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet

Additional Information

This chapter provides additional information about the document and Altera.

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the

following table.

Contact ⁽¹⁾

Technical support

Contact Method

Website

Email

Address

www.altera.com/support

www.altera.com/training

custrain@altera.com

Technical training

Product literature

Website

Email

www.altera.com/literature

nacomp@altera.com

Nontechnical support (general)

(software licensing)

Note to Table:

Email

authorization@altera.com

(1) You can also contact your local Altera sales office or sales representative.

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue

Meaning

Indicate command names, dialog box titles, dialog box options, and other GUI

labels. For example, Save As dialog box. For GUI elements, capitalization matches

the GUI.

Bold Type with Initial Capital

Letters

Indicates directory names, project names, disk drive names, file names, file name

extensions, software utility names, and GUI labels. For example, \qdesigns

directory, D: drive, and chiptrip.gdf file.

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

Indicates variables. For example, n + 1.

italic type

Variable names are enclosed in angle brackets (< >). For example, <file name> and

<project name>.pof file.

Indicate keyboard keys and menu names. For example, the Delete key and the

Options menu.

Initial Capital Letters

“Subheading Title”

Quotation marks indicate references to sections in a document and titles of

Quartus II Help topics. For example, “Typographic Conventions.”

February 2012 Altera Corporation

Arria V Device Handbook

Volume 1: Device Overview and Datasheet

Info–2

Additional Information

Typographic Conventions

Visual Cue

Meaning

Indicates signal, port, register, bit, block, and primitive names. For example, data1

tdi, and input. The suffix denotes an active-low signal. For example, resetn

Indicates command line commands and anything that must be typed exactly as it

appears. For example, c:\qdesigns\tutorial\chiptrip.gdf

,

n

.

Courier type

.

Also indicates sections of an actual file, such as a Report File, references to parts of

files (for example, the AHDL keyword SUBDESIGN), and logic function names (for

example, TRI).

r

An angled arrow instructs you to press the Enter key.

1., 2., 3., and

Numbered steps indicate a list of items when the sequence of the items is important,

such as the steps listed in a procedure.

a., b., c., and so on

■

Bullets indicate a list of items when the sequence of the items is not important.

The hand points to information that requires special attention.

1

h

A question mark directs you to a software help system with related information.

The feet direct you to another document or website with related information.

f

A caution calls attention to a condition or possible situation that can damage or

destroy the product or your work.

c

A warning calls attention to a condition or possible situation that can cause you

injury.

w

The envelope links to the Email Subscription Management Center page of the Altera

website, where you can sign up to receive update notifications for Altera documents.

Arria V Device Handbook

February 2012 Altera Corporation

Volume 1: Device Overview and Datasheet


型号：	5AGTFD3D427I4N
厂家：	ALTERA CORPORATION
描述：	Arria V Device Handbook 阿里亚V器件手册
文件：	总82页 (文件大小：1787K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5AGTFD3D427I4N [ALTERA]

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