ASM5I9352 [ALSC]
2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer; 2.5V或3.3V ， 200兆赫， 11输出零延迟缓冲器
| 型号： | ASM5I9352 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| 文件： | 总12页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2005
rev 0.2
ASM5I9352
2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer
Features
The ASM5I9352 features an LVCMOS reference clock
input and provides 11 outputs partitioned in 3 banks of 5, 4,
and 2 outputs. Bank A divides the VCO output by 4 or 6
while Bank B divides by 4 and 2 and Bank C divides by 2
and 4 per SEL(A:C) settings, see Table 2. These dividers
allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and
1:3. Each LVCMOS compatible output can drive 50Ω series
or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:22.
Output frequency range: 25MHz to 200MHz
Output frequency range: 16.67MHz to 200MHz
Input frequency range: 16.67MHz to 200MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
± 2% max Output duty cycle variation
11 Clock outputs: Drive up to 22 clock lines
LVCMOS reference clock input
125-pS max output-output skew
PLL bypass mode
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 16.67 MHz to 200 MHz.
For normal operation, the external feedback input, FB_IN,
is connected to one of the outputs. The internal VCO is
running at multiples of the input reference clock set by the
feedback divider, see Table 1.
Spread AwareTM
Output enable/disable
Pin compatible with MPC9352 and MPC952
Industrial temperature range: –40°C to +85°C
32-Pin 1.0mm TQFP & LQFP Packages
Functional Description
When PLL_EN# is HIGH, PLL is bypassed and the
reference clock directly feeds the output dividers. This
mode is fully static and the minimum input clock frequency
specification does not apply.
The ASM5I9352 is a low voltage high performance
200MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9352
rev 0.2
Block Diagram
PLL_EN#
+4/
VCO
200-500MHz
REFCLK
FB_IN
QA0
QA1
QA2
Phase
Detector
+2
LPF
VCO_SEL
SELA
QA3
QA4
+4/
+2
QB0
QB1
QB2
QB3
SELB
+2/
QC0
QC1
SELC
MR/OE#
Pin Configuration
28
25
32 31 30 29
27 26
VCO_SEL
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VSS
SELC
SELB
QB1
QB0
VDDQB
VDDQA
QA4
SELA
ASM5I9352
MR/OE#
REFCLK
AVSS
QA3
FB_IN
VSS
9
10 11 12 13 14 15 16
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
2 of 12
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9352
rev 0.2
Pin Configuration1
Pin
Name
I/O
Type
Description
6
REFCLK
I, PD
LVCMOS
Reference clock input.
Clock output bank A.
12, 14,
15, 18, 19
QA(0:4)
O
LVCMOS
22, 23,
26, 27
QB(0:3)
QC(0,1)
O
O
LVCMOS
LVCMOS
Clock output bank B.
Clock output bank C.
30, 31
Feedback clock input. Connect to an output for normal operation.
This input should be at the same voltage rail as input reference
clock. See Table 1.
8
FB_IN
I, PD
LVCMOS
1
5
VCO_SEL
MR/OE#
I, PD
I, PD
LVCMOS
LVCMOS
VCO divider select input. See Table 2.
Master reset/output enable/disable input. See Table 2.
PLL enable/disable input. See Table 2.
9
PLL_EN#
SEL(A:C)
VDDQA
VDDQB
VDDQC
AVDD
I, PD
I, PD
LVCMOS
LVCMOS
VDD
2, 3, 4
16, 20
21, 25
32
Frequency select input, Bank (A:C). See Table 2.
2.5V or 3.3V power supply for bank A output clocks2,3
.
2.5V or 3.3V power supply for bank B output clocks.2,3
2.5V or 3.3V power supply for bank C output clocks. 2,3
2.5V or 3.3V power supply for PLL. 2,3
Supply
Supply
Supply
Supply
Supply
VDD
VDD
10
VDD
11
VDD
VDD
2.5V or 3.3V power supply for core and inputs. 2,3
7
AVSS
Supply
Ground
Ground
Analog ground.
13, 17,
24, 28, 29
VSS
Supply
Common ground.
Note: 1. PD = Internal pull-down.
2.A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
supply pins.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
3 of 12
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9352
rev 0.2
Table 1: Frequency Table
Feedback
VCO_SEL
Input Frequency Range
(AVDD = 3.3V)
Input Frequency
Range (AVDD = 2.5V)
VCO
Output Divider
0
0
0
1
1
1
÷2
÷4
÷6
÷2
÷4
÷6
Input Clock * 2
Input Clock * 4
Input Clock * 6
Input Clock * 4
Input Clock * 8
Input Clock * 12
100 MHz to 200 MHz
50 MHz to 125 MHz
33.33 MHz to 83.33 MHz
50 MHz to 125 MHz
25 MHz to 62.5 MHz
16.67 MHz to 41.67 MHz
100 MHz to 200 MHz
50 MHz to 100 MHz
33.33 MHz to 66.67 MHz
50 MHz to 100 MHz
25 MHz to 50 MHz
16.67 MHz to 33.33 MHz
Table 2: Function Table
Control
Default
0
1
VCO_SEL
0
VCO
VCO ÷ 2
PLL enabled. The VCO output
connects to the output dividers
Bypass mode, PLL disabled. The input clock
connects to the output dividers
PLL_EN#
MR/OE#
0
Outputs disabled (three-state), VCO running
at its minimum frequency
0
Outputs enabled
SELA
SELB
SELC
0
0
0
QA = VCO÷4
QB = VCO ÷4
QC = VCO÷2
QA = VCO÷6
QB = VCO÷2
QC = VCO÷4
Absolute Maximum Ratings
Parameter
VDD
VDD
VIN
Description
Condition
Min
–0.3
2.375
–0.3
–0.3
Max
5.5
Unit
V
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
Functional
3.465
V
Relative to VSS
Relative to VSS
VDD+ 0.3
VDD+ 0.3
VDD ÷2
V
VOUT
VTT
DC Output Voltage
V
Output termination Voltage
Latch Up Immunity
V
LU
Functional
200
mA
mVp-p
°C
RPS
TS
Power Supply Ripple
Ripple Frequency < 100 kHz
Non Functional
Functional
150
+150
+85
155
42
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
–65
–40
TA
°C
TJ
Functional
°C
ØJC
ØJA
Functional
°C/W
°C/W
Volts
ppm
Functional
105
ESDH
FIT
2000
Manufacturing test
10
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
4 of 12
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9352
rev 0.2
DC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C)
Parameter
VIL
Description
Condition
Min
1.7
Typ
Max
0.7
Unit
V
Input Voltage, Low
LVCMOS
VIH
Input Voltage, High
LVCMOS
VDD+ 0.3
0.6
V
VOL
Output Voltage, Low1
Output Voltage, High1
Input Current, Low
Input Current, High2
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
IOL= 15 mA
IOH= –15 mA
VIL= VSS
V
VOH
IIL
1.8
V
–10
100
10
µA
µA
mA
mA
mA
pF
Ω
IIH
VIL= VDD
IDDA
IDDQ
IDD
AVDD only
5
3
All VDD pins except AVDD
5
170
4
CIN
ZOUT
17 – 20
Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated
transmission lines.
2.Inputs have pull-down resistors that affect the input current.
DC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)
Parameter
Description
Condition
Min
Typ
Max
0.8
Unit
V
VIL
VIH
Input Voltage, Low
LVCMOS
Input Voltage, High
LVCMOS
2.0
VDD + 0.3
0.55
V
IOL= 24 mA
IOL= 12 mA
IOH= –24 mA
VIL= VSS
VOL
Output Voltage, Low1
V
0.30
VOH
IIL
Output Voltage, High1
Input Current, Low
2.4
V
–10
100
10
µA
µA
mA
mA
mA
pF
Ω
IIH
Input Current, High2
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
VIL= VDD
IDDA
IDDQ
IDD
AVDD only
5
3
All VDD pins except AVDD
5
240
4
CIN
ZOUT
14 – 17
Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated
transmission lines.
2.Inputs have pull-down resistors that affect the input current.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
5 of 12
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9352
rev 0.2
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C) 1
Parameter
Description
Condition
Min
200
100
50
Typ
Max
400
Unit
fVCO
VCO Frequency
MHz
÷2 Feedback
200
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷12 Feedback
100
33.33
25
66.67
50
fin
Input Frequency
MHz
16.67
33.33
Bypass mode
(PLL_EN# = 1)
0
200
frefDC
tr, tf
Input Duty Cycle
25
75
1.0
%
TCLK Input Rise/FallTime
0.7V to 1.7V
÷2 Output
nS
100
50
200
100
66.67
50
÷4 Output
fMAX
Maximum Output Frequency
MHz
÷6 Output
33.33
25
÷8 Output
÷12 Output
fMAX< 100 MHz
fMAX > 100 MHz
0.6V to 1.8V
16.67
47
33.33
53
DC
Output Duty Cycle
%
44
56
tr, tf
t(φ)
Output Rise/Fall times
0.1
1.0
nS
pS
pS
Propagation Delay (static phase
offset)
TCLK to FB_IN, same VDD,
does not include jitter
-100
100
125
175
tsk(O)
Output-to-Output Skew
Skew within Bank
Banks at same voltage,
same frequency
tsk(B)
Bank-to-Bank Skew
pS
Banks at same voltage,
different frequency
225
tPLZ, HZ
tPZL, ZH
Output Disable Time
Output Enable Time
8
nS
nS
10
÷2 Feedback
2
1 - 1.5
0.6
÷4 Feedback
PLL Closed Loop Bandwidth (-
3dB)
BW
MHz
÷6 Feedback
÷8 Feedback
0.75
0.5
÷12 Feedback
Same frequency
Multiple frequencies
Same frequency
Multiple frequencies
VCO < 300 MHz
VCO > 300 MHz
100
300
100
150
tJIT(CC)
Cycle-to-Cycle Jitter
Period Jitter
pS
pS
tJIT(PER)
150
100
tJIT(φ)
I/O Phase Jitter
pS
tLOCK
Maximum PLL Lock Time
1
mS
Note:1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
6 of 12
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9352
rev 0.2
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)1
Parameter
Description
Condition
Min
200
100
50
Typ
Max
500
200
125
83.33
62.5
41.67
200
75
Unit
fVCO
VCO Frequency
MHz
÷2 Feedback
÷4 Feedback
÷6 Feedback
33.33
25
fin
Input Frequency
MHz
÷8 Feedback
÷12 Feedback
16.67
0
Bypass mode (PLL_EN# = 1)
frefDC
tr, tf
Input Duty Cycle
25
%
TCLK Input Rise/FallTime
0.8V to 2.0V
÷2 Output
1.0
nS
100
50
200
125
83.33
62.5
41.67
52
÷4 Output
fMAX
Maximum Output Frequency
MHz
÷6 Output
33.33
25
÷8 Output
÷12 Output
fMAX< 100 MHz
fMAX > 100 MHz
0.55V to 2.4V
16.67
48
DC
Output Duty Cycle
%
44
56
tr, tf
t(φ)
Output Rise/Fall times
0.1
1.0
nS
pS
pS
Propagation Delay
(static phase offset)
TCLK to FB_IN, same VDD,
does not include jitter
–100
200
125
175
tsk(O)
Output-to-Output Skew
Skew within each Bank
Banks at same voltage,
same frequency
tsk(B)
Bank-to-Bank Skew
Banks at same voltage,
different frequency
pS
235
Banks at different voltage
425
8
tPLZ, HZ
tPZL, ZH
Output Disable Time
Output Enable Time
nS
nS
10
÷2 Feedback
2
1 – 1.5
0.6
÷4 Feedback
PLL Closed Loop Bandwidth
(-3dB)
BW
MHz
÷6 Feedback
÷8 Feedback
0.75
0.5
÷12 Feedback
Same frequency
Multiple frequencies
Same frequency
Multiple frequencies
VCO < 300 MHz
VCO > 300 MHz
100
275
100
150
tJIT(CC)
Cycle-to-Cycle Jitter
Period Jitter
pS
pS
tJIT(PER)
150
100
tJIT(φ)
I/O Phase Jitter
pS
tLOCK
Maximum PLL Lock Time
1
mS
Note:1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
7 of 12
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I9352
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
VDD
LVCMOS_CLK
VDD/2
GND
VDD
FB_IN
VDD/2
GND
t(φ)
Figure 2. LVCMOS Propagation Delay t(φ), Static Phase Offset
VDD
LVCMOS_CLK
VDD/2
GND
tP
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (DC)
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(0)
Figure 4. Output-to-Output Skew , tsk(O)
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
8 of 12
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9352
rev 0.2
Package Diagram
32-lead TQFP Package
SECTION A-A
Dimensions
Millimeters
Symbol
Inches
Min
Max
Min
…
Max
1.2
A
A1
A2
D
….
0.0472
0.0059
0.0413
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0374
0.3465
0.2717
0.3465
0.2717
0.0177
0.05
0.95
8.8
0.15
1.05
9.2
D1
E
6.9
7.1
8.8
9.2
E1
L
6.9
7.1
0.45
0.75
L1
T
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0°
0.0079
0.0062
0.0177
0.0157
0.0079
7°
0.09
0.097
0.30
0.30
0.08
0°
0.2
0.157
0.45
0.40
0.2
T1
b
b1
R0
a
7°
e
0.031 BASE
0.8 BASE
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
9 of 12
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I9352
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Millimeters
Min
Max
Min
…
Max
1.6
A
A1
A2
D
….
0.0630
0.0059
0.0571
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0531
0.3465
0.2717
0.3465
0.2717
0.0177
0.05
1.35
8.8
0.15
1.45
9.2
D1
E
6.9
7.1
8.8
9.2
E1
L
6.9
7.1
0.45
0.75
L1
T
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0.0079
0.0062
0.0177
0.0157
0.0079
0.09
0.097
0.30
0.30
0.08
0.2
0.157
0.45
0.40
0.20
T1
b
b1
R0
e
0.031 BASE
0.8 BASE
a
0°
7°
0°
7°
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
10 of 12
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I9352
Ordering Information
Part Number
ASM5I9352-32-ET
ASM5I9352-32-LT
ASM5I9352G-32-ET
ASM5I9352G-32-LT
Marking
Package Type
Temperature
Industrial
ASM5I9352
32-pin TQFP
ASM5I9352
ASM5I9352G
ASM5I9352G
32-pin LQFP –Tape and Reel
32-pin TQFP, Green
Industrial
Industrial
32-pin LQFP –Tape and Reel, Green
Industrial
Device Ordering Information
A S M 5 I 9 3 5 2 F - 3 2 - L T
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
(-40C to +125C) (-40C to +85C)
I= Industrial
P or n/c = Commercial
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
11 of 12
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I9352
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5I9352
Document Version: 0.2
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
12 of 12
Notice: The information in this document is subject to change without notice.
相关型号：
ASM5I9352-32-ET
PLL Based Clock Driver, 9352 Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, 1 MM HEIGHT, TQFP-32
PULSECORE
ASM5I9352-32-LT
PLL Based Clock Driver, 9352 Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, 1 MM HEIGHT, LQFP-32
PULSECORE
ASM5I9352G-32-ET
PLL Based Clock Driver, 9352 Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, 1 MM HEIGHT, GREEN, TQFP-32
PULSECORE
ASM5I9352G-32-LT
PLL Based Clock Driver, 9352 Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, 1 MM HEIGHT, GREEN, LQFP-32
PULSECORE
©2020 ICPDF网 联系我们和版权申明