ASM5I961CG-32-ET [ALSC]
Low Voltage Zero Delay Buffer; 低压零延迟缓冲器
| 型号： | ASM5I961CG-32-ET |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Low Voltage Zero Delay Buffer |
| 文件： | 总15页 (文件大小：684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2005
rev 0.2
ASM5I961C
Low Voltage Zero Delay Buffer
Features
reference clock while the ASM5I961P offers an LVPECL
reference clock.
Fully Integrated PLL
Up to 200MHz I/O Frequency
LVCMOS Outputs
When pulled high the OE pin will force all of the outputs
(except QFB) into a high impedance state. Because the OE
pin does not affect the QFB output, down stream clocks
can be disabled without the internal PLL losing lock.
Outputs Disable in High Impedance
LVCMOS Reference Clock Options
LQFP and TQFP Packaging
±50pS Cycle–Cycle Jitter
150pS Output Skews
The ASM5I961C is fully 2.5V or 3.3V compatible and
requires no external loop filter components. All control
inputs accept LVCMOS compatible levels and the outputs
provide low impedance LVCMOS outputs capable of
driving terminated 50Ω transmission lines. For series
terminated lines the ASM5I961C can drive two lines per
output giving the device an effective fanout of 1:36. The
device is packaged in a 32 lead LQFP and TQFP
Packages.
Functional Description
The ASM5I961C is a 2.5V or 3.3V compatible, 1:18 PLL
based zero delay buffer. With output frequencies of up to
200MHz, output skews of 150pS the device meets the
needs of the most demanding clock tree applications.
The ASM5I961 is offered with two different input
configurations. The ASM5I961C offers an LVCMOS
Block Diagram
Q0
Q1
PLL
100-200 MHz
Ref
CCLK
FB_IN
0
1
50K
50K
Q2
Q3
50-100 MHz
FB
Q14
Q15
Q16
F_RANGE
50K
OE
50K
QFB
Figure 1. ASM5I961C Logic Diagram
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I961C
rev 0.2
Pin Configuration
20
17
19 18
24 23 22 21
Q5
Q4
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCC
Q12
Q13
Q14
GND
Q15
Q16
QFB
Q3
GND
Q2
ASM5I961C
Q1
Q0
VCC
1
2
3
4
5
6
7
8
Figure 2. ASM5I961C 32-Lead Package Pinout (Top View)
Table 1: Pin Configuration
Pin #
2
Pin Name
I/O
Input
Type
LVCMOS
Function
PLL reference clock signal
CCLK
PLL feedback signal input, connect to a
7
4
6
FB_IN
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
QFB output
F_RANGE
PLL frequency range select
Output enable/disable
OE
31,30,29,27,26,25,23,22,21,
19,18,17,15,14,13,11,10
Q0 - Q16
Output
LVCMOS
Clock outputs
PLL feedback signal output, connect to a
FB_IN
Negative power supply
9
QFB
GND
Output
Supply
LVCMOS
Ground
1,12,20,28
PLL positive power supply (analog power
supply). The ASM5I961C requires an
external RC filter for the analog power
supply pin VCCA. Please see applications
section for details.
Positive power supply for I/O and core
Not connected
5
VCCA
Supply
Supply
VCC
VCC
8,16,24,32
3
VCC
NC
Low Voltage Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
July 2005
ASM5I961C
rev 0.2
Table 2: FUNCTION TABLE
Control
Default
0
1
PLL high frequency range. ASM5I961C input
reference and output clock frequency range is
100 – 200MHz
PLL low frequency range. ASM5I961C input
reference and output clock frequency range is
50 – 100MHz
F_RANGE
0
0
Outputs enabled
Outputs disabled (high–impedance state)
OE
Table 3: ABSOLUTE MAXIMUM RATINGS1
Symbol
VCC
VIN
VOUT
IIN
Parameter
Min
–0.3
–0.3
–0.3
Max
3.6
VCC + 0.3
VCC + 0.3
±20
Unit
V
V
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
V
mA
mA
°C
IOUT
TS
±50
125
Storage Temperature Range
–40
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Table 4: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = -40°C to +85°C)
Symbol
VIH
VIL
VOH
VOL
ZOUT
IIN
Characteristic
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
Min
2.0
–0.3
2.4
Typ
Max
VCC + 0.3
0.8
Unit
V
V
V
V
Condition
LVCMOS
LVCMOS
IOH = –20mA1
IOL = 20mA1
0.55
20
±120
14
Ω
µA
pF
pF
mA
mA
V
CIN
4.0
8.0
2.0
CPD
ICCA
ICC
10
5.0
TBD
Per Output
VCCA Pin
All VCC Pins
VTT
VCC÷2
Note: 1. The ASM5I961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives up two 50Ω series terminated transmission lines.
Low Voltage Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
July 2005
ASM5I961C
rev 0.2
Table 5: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 40°C to +85°C)1
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
F_RANGE = 0
100
200
fref
Input Frequency
MHz
MHz
F_RANGE = 1
50
100
Maximum Output
Frequency
F_RANGE = 0
100
50
200
100
fmax
F_RANGE = 1
frefDC
tr, tf
Reference Input Duty Cycle
TCLK Input Rise/Fall Time
Propagation Delay
25
75
3.0
%
nS
0.8 to 2.0V
PLL locked
CCLK to FB_IN
–80
120
150
pS
pS
%
t(∅
)
(static phase offset)
tsk(O)
DCO
tr, tf
Output–to–Output Skew2
90
F_RANGE = 0
F_RANGE = 1
42
45
0.1
50
55
Output Duty Cycle
50
55
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter
Period Jitter
1.0
10
10
15
10
15
10
nS
nS
nS
pS
pS
nS
mS
0.55 to 2.4V
tPLZ HZ
,
tPZL,LZ
tJIT(CC)
tJIT(PER)
RMS (1σ)3
RMS (1σ)
RMS (1σ)
7.0
I/O Phase Jitter
tJIT(
)
∅
tlock
Maximum PLL Lock Time
Note: 1. AC characteristics apply for parallel output termination of 50ꢀ to VTT
.
2. See applications section for part–to–part skew calculation
3. See applications section for calculation for other confidence factors than 1σ
Low Voltage Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
July 2005
ASM5I961C
rev 0.2
Table 6: DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)
Symbol
VIH
VIL
VOH
VOL
ZOUT
IIN
Characteristic
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
Min
1.7
–0.3
1.8
Typ
Max
VCC + 0.3
0.7
Unit
V
V
V
V
Condition
LVCMOS
LVCMOS
IOH = –15mA1
IOL = 15mA1
0.6
26
±120
18
ꢀ
mA
pF
pF
mA
mA
V
CIN
4.0
8.0
2.0
CPD
ICCA
ICC
10
5.0
TBD
Per Output
VCCA Pin
All VCC Pins
VTT
VCC ÷2
Note: 1.The ASM5I961C is capable of driving 50ꢀ transmission lines on the incident edge. Each output drives one 50ꢀ parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives up two 50ꢀ series terminated transmission lines.
Table 7: AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = 40°C to +85°C)1
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
F_RANGE = 0
100
200
fref
Input Frequency
MHz
F_RANGE = 1
50
100
Maximum Output
Frequency
F_RANGE = 0
100
50
200
100
fmax
MHz
F_RANGE = 1
frefDC
tr, tf
Reference Input Duty Cycle
TCLK Input Rise/Fall Time
Propagation Delay
25
75
3.0
%
nS
0.7 to 1.7V
PLL locked
CCLK to FB_IN
–80
120
150
pS
pS
%
t(∅
)
(static phase offset)
tsk(O)
DCO
Output–to–Output Skew2
90
F_RANGE = 0
F_RANGE = 1
40
45
50
60
Output Duty Cycle
50
55
tr, tf
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter
Period Jitter
0.1
1.0
10
10
15
10
15
10
nS
nS
nS
pS
pS
nS
mS
0.6 to 1.8V
tPLZ,HZ
tPZL,LZ
tJIT(CC)
tJIT(PER)
RMS (1σ)3
RMS (1σ)
RMS (1σ)
7.0
I/O Phase Jitter
Maximum PLL Lock Time
tJIT(
)
∅
tlock
Note: 1 AC characteristics apply for parallel output termination of 50ꢀ to VTT
.
2 See applications section for part–to–part skew calculation
3 See applications section for calculation for other confidence factors than 1σ
Low Voltage Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
July 2005
ASM5I961C
rev 0.2
APPLICATIONS INFORMATION
Power Supply Filtering
Although the ASM5I961C has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related
problems in most designs.
The ASM5I961C is a mixed analog/digital product and as
such it exhibits some sensitivity that would not
necessarily be seen on a fully digital product. Analog
circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
The ASM5I961C provides separate power supplies for
the output buffers (VCC) and the phase–locked loop
(VCCA) of the device. The purpose of this design
technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as
an evaluation board this level of isolation is sufficient.
However, in a digital system environment where it is more
difficult to minimize noise on the power supplies a second
level of isolation may be required. The simplest form of
isolation is a power supply filter on the VCCA pin for the
ASM5I961C.
Driving Transmission Lines
The ASM5I961C clock driver was designed to drive high
speed signals in
a
terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 15ꢀ the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point–to–point distribution of
signals is the method of choice. In a point–to–point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50ꢀ
resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line
can be driven by each output of the ASM5I961C clock
driver. For the series terminated case however there is no
DC current draw, thus the outputs can drive multiple
series terminated lines. Figure 4. illustrates an output
driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the
fanout of the ASM5I961C clock driver is effectively
doubled due to its capability to drive multiple lines.
Figure 3. illustrates a typical power supply filter scheme.
The ASM5I961C is most susceptible to noise with
spectral content in the 10KHz to 10MHz range. Therefore
the filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is
the DC voltage drop that will be seen between the VCC
supply and the VCCA pin of the ASM5I961C. From the
data sheet the ICCA current (the current sourced through
the VCCA pin) is typically 2mA (5mA maximum), assuming
that a minimum of 2.375V (VCC = 3.3V or VCC = 2.5V)
must be maintained on the VCCA pin. The resistor RF
shown in Figure 3. must have a resistance of 270ꢀ
(VCC = 3.3V) or 5 to 15ꢀ (VCC = 2.5V) to meet the voltage
drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the
noise frequency crosses the series resonant point of an
individual capacitor it’s overall impedance begins to look
inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a
low impedance path to ground exists for frequencies well
above the bandwidth of the PLL.
ASM5I961C
OUTPUT BUFFER
Z0=50ꢀ
RS=36ꢀ
IN
IN
14ꢀ
OUTA
ASM5I961C
Z0=50ꢀ
Z0=50ꢀ
RS=36ꢀ
RS=36ꢀ
OUTPUT BUFFER
OUTB0
OUTB1
14ꢀ
Figure 4. Single versus Dual Transmission Lines
The waveform plots of Figure 5. show the simulation
results of an output driving a single line vs two lines. In
both cases the drive capability of the ASM5I961C output
buffer is more than sufficient to drive 50ꢀ transmission
lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43pS
exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used
exclusively to maintain the tight output–to–output skew of
the ASM5I961C. The output waveform in Figure 5. shows
Figure 3. Power Supply Filter
Low Voltage Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
July 2005
ASM5I961C
rev 0.2
a step in the waveform, this step is caused by the
impedance mismatch seen looking into the driver. The
parallel combination of the 36ꢀ series resistor plus the
output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
Using the ASM5I961C in zero-delay applications
Nested clock trees are typical applications for the
ASM5I961C. Designs using the ASM5I961C as LVCMOS
PLL fanout buffer with zero insertion delay will show
significantly lower clock skew than clock distributions
developed from CMOS fanout buffers. The external
feedback option of the ASM5I961C clock driver allows for
its use as a zero delay buffer. By using the QFB output as
a feedback to the PLL the propagation delay through the
device is virtually eliminated. The PLL aligns the
feedback clock output edge with the clock input reference
edge resulting a near zero delay through the device. The
maximum insertion delay of the device in zero-delay
applications is measured between the reference clock
input and any output. This effective delay consists of the
static phase offset, I/O jitter (phase or long-term jitter),
feedback path delay and the output-to-output skew error
relative to the feedback output.
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 36Ω || 36Ω
Ro = 14Ω
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.62V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
Calculation of part-to-part skew
The ASM5I961C zero delay buffer supports applications
where critical clock signal timing can be maintained
across several devices. If the reference clock inputs of
two or more ASM5I961C are connected together, the
maximum overall timing uncertainty from the common
CCLK input to any output is:
tSK(PP) = t(ϕ) + tSK(O) + tPD, LINE(FB) + tJIT( ) CF
ϕ
This maximum timing uncertainty consist of
4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 6. should be used. In
this case the series terminating resistors are reduced
such that when the parallel combination is added to the
output buffer impedance the line impedance is perfectly
matched.
ASM5I961C
Z0=50ꢀ
RS=22ꢀ
OUTPUT BUFFER
14ꢀ
IN
Z0=50ꢀ
RS=22ꢀ
Figure 7. ASM5I961C max. device-to-device skew
14Ω + 22Ω ║ 22Ω = 50Ω ║ 50Ω
25Ω = 25Ω
Due to the statistical nature of I/O jitter a rms value (1σ) is
specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
Figure 6. Optimized Dual Line Termination
Low Voltage Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
July 2005
ASM5I961C
rev 0.2
term reliability may decrease the maximum frequency
limit, depending on operating conditions such as clock
frequency, supply voltage, output loading, ambient
temperature, vertical convection and thermal conductivity
of package and board. This section describes the impact
of these parameters on the junction temperature and
gives a guideline to estimate the ASM5I961C die junction
temperature and the associated device reliability.
Table 8: Confidence Factor CF
Probability of clock edge within the
CF
distribution
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
Table 9: Die junction temperature and MTBF
Junction temperature (°C)
MTBF (Years)
100
110
120
130
20.4
9.1
4.2
2.0
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation
a I/O jitter confidence factor of 99.7% (± 3 σ) is assumed,
resulting in a worst case timing uncertainty from input to
any output of -275 pS to 315 pS relative to CCLK:
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM5I961C
needs to be controlled and the thermal impedance of the
board/package should be optimized. The power
dissipated in the ASM5I961C is represented in equation
1. Where ICCQ is the static current consumption of the
ASM5I961C, CPD is the power dissipation capacitance
per output, (M)ΣCL represents the external capacitive
output load, N is the number of active outputs (N is
always 27 in case of the ASM5I961C). The ASM5I961C
supports driving transmission lines to maintain high signal
integrity and tight timing parameters. Any transmission
line will hide the lumped capacitive load at the end of the
board trace, therefore, ΣCL is zero for controlled
transmission line systems and can be eliminated from
equation 1. Using parallel termination output termination
results in equation 2 for power dissipation. In equation 2,
P stands for the number of outputs with a parallel or
thevenin termination, VOL, IOL, VOH and IOH are a function
of the output termination technique and DCQ is the clock
signal duty cycle. If transmission lines are used ΣCL is
zero in equation 2 and can be eliminated. In general, the
use of controlled transmission line techniques eliminates
the impact of the lumped capacitive loads at the end lines
and greatly reduces the power dissipation of the device.
Equation 3 describes the die junction temperature TJ as a
function of the power consumption.
t
SK(PP) = [–80pS...120pS] + [–150pS...150pS] +
[(15pS _ –3)...(15pS _ 3)] + tPD
,
LINE(FB)
tSK(PP) = [–275pS...315pS] + tPD
,
LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure
8. “Max. I/O Jitter versus frequency” can be used for a
more precise timing performance analysis.
Figure 8. Max. I/O Jitter versus frequency
Power Consumption of the ASM5I961C and Thermal
Management
The ASM5I961C AC specification is guaranteed for the
entire operating frequency range up to 200MHz. The
ASM5I961C power consumption and the associated long-
Low Voltage Zero Delay Buffer
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July 2005
rev 0.2
ASM5I961C
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 9, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM5I961C in a
series terminated transmission line system.
TJ,MAX should be selected according to the MTBF system
requirements and Table 9. Rthja can be derived from Table
10. The Rthja represent data based on 1S2P boards, using
2S2P boards will result in a lower thermal impedance
than indicated below. If the calculated maximum
frequency is below 200MHz, it becomes the upper clock
speed limit for the given application conditions. The
following two derating charts describe the safe frequency
operation range for the ASM5I961C. The charts were
Table 10: Thermal package impedance of the 32
LQFP
calculated for
a
maximum tolerable die junction
temperature of 110°C, corresponding to an estimated
MTBF of 9.1 years, a supply voltage of 3.3V and series
terminated transmission line or capacitive loading.
Depending on a given set of these operating conditions
and the available device convection a decision on the
maximum operating frequency can be made. There are
no operating frequency limitations if a 2.5V power supply
or the system specifications allow for a MTBF of 4 years
(corresponding to a max. junction temperature of 120°C.
Convection, LFPM
Still air
Rthja (1P2S board), °C/W
80
70
61
57
56
55
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
Low Voltage Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I961C
Figure 10. Maximum ASM5I961C frequency,
Figure 9. Maximum ASM5I961C frequency, VCC = 3.3V,
MTBF 9.1 years, driving series terminated transmission
V
CC = 3.3V, MTBF 9.1 years,4pF load per line
Figure 11. TCLK ASM5I961C AC test reference for VCC = 3.3V and VCC =2.5V
Low Voltage Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I961C
Low Voltage Zero Delay Buffer
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July 2005
ASM5I961C
rev 0.2
Package Diagram
32-lead TQFP Package
SECTION A-A
Dimensions
Millimeters
Symbol
Inches
Min
Max
Min
…
Max
1.2
A
A1
A2
D
D1
E
….
0.0472
0.0059
0.0413
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0374
0.3465
0.2717
0.3465
0.2717
0.0177
0.05
0.95
8.8
0.15
1.05
9.2
6.9
7.1
8.8
9.2
E1
L
6.9
7.1
0.45
0.75
L1
T
T1
b
b1
R0
a
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0°
0.0079
0.0062
0.0177
0.0157
0.0079
7°
0.09
0.097
0.30
0.30
0.08
0°
0.2
0.157
0.45
0.40
0.2
7°
e
0.031 BASE
0.8 BASE
Low Voltage Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I961C
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Millimeters
Min
….
Max
Min
…
0.05
1.35
8.8
6.9
8.8
6.9
0.45
Max
1.6
0.15
1.45
9.2
7.1
9.2
7.1
0.75
A
A1
A2
D
D1
E
0.0630
0.0059
0.0571
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0531
0.3465
0.2717
0.3465
0.2717
0.0177
E1
L
L1
T
T1
b
b1
R0
e
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0.0079
0.0062
0.0177
0.0157
0.0079
0.09
0.097
0.30
0.30
0.08
0.2
0.157
0.45
0.40
0.20
0.031 BASE
0.8 BASE
a
0°
7°
0°
7°
Low Voltage Zero Delay Buffer
13 of 15
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I961C
rev 0.2
Ordering Information
Marking
ASM5I961C
ASM5I961C
ASM5I961CG
ASM5I961CG
Part Number
ASM5I961C-32-ET
ASM5I961C-32-LT
ASM5I961CG-32-ET
ASM5I961CG-32-LT
Package Type
32 pin TQFP
32 pin LQFP – Tape and Reel
32 pin TQFP, Green
32 pin LQFP – Tape and Reel, Green
Temperature
Industrial
Industrial
Industrial
Industrial
Device Ordering Information
A S M 5 I 9 6 1 C F - 3 2 - L T
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low Voltage Zero Delay Buffer
14 of 15
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I961C
Copyright © Alliance Semiconductor
Alliance Semiconductor Corporation
2575 Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
All Rights Reserved
Part Number: ASM5I961C
Document Version: 0.2
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
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Low Voltage Zero Delay Buffer
15 of 15
Notice: The information in this document is subject to change without notice.
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