ASM5I9351 [ALSC]
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer; 2.5V或3.3V ， 200 MHz时， 9路输出零延迟缓冲器
| 型号： | ASM5I9351 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| 文件： | 总13页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2005
rev 0.2
ASM5I9351
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Features
The ASM5I9351 features LVPECL and LVCMOS reference
clock inputs and provides 9 outputs partitioned in 4 banks
of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by
2 or 4 while the other banks divide by 4 or 8 per SEL(A:D)
settings, see Table.2. These dividers allow output to input
ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS
compatible output can drive 50Ω series or parallel
terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:18.
Output frequency range: 25 MHz to 200 MHz
Input frequency range: 25 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
± 2.5% max Output duty cycle variation
Nine Clock outputs: Drive up to 18 clock lines
Two reference clock inputs: LVPECL or LVCMOS
150-ps max output-output skew
Phase-locked loop (PLL) bypass mode
‘SpreadTrak’
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 25 MHz to 200 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to one of the outputs. The internal VCO is
running at multiples of the input reference clock set by the
feedback divider, see the Table 1.
Output enable/disable
Pin-compatible with MPC9351 and CY29351.
Industrial temperature range: –40°C to +85°C
32-pin 1.0mm TQFP & LQFP Package.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
Functional Description
The ASM5I9351 is a low voltage high performance
200MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9351
rev 0.2
Block Diagram
SELA
PLL_EN
REF_SEL
TCLK
PECL_CLK
VCO
200-500MHz
+2/
+4
Phase
Detector
QA
QB
LPF
FB_IN
SELB
+4/
+8
+4/
+8
QC0
QC1
SELC
OE#
+4/
+8
QD0
QD1
QD2
SELD
QD3
QD4
Pin Configuration
32 31 30 29 28 27 26 25
AVDD
FB_IN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QC0
VDDQC
QC1
SELA
SELB
VSS
ASM5I9351
SELC
QD0
SELD
VDDQD
QD1
AVSS
PECL_CLK
VSS
13 16
14 15
9
10 11 12
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
2 of 13
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I9351
Pin Configuration1
Pin #
Pin Name
I/O
Type
Description
8
PECL_CLK
PECL_CLK#
TCLK
I, PU
Analog
LVPECL reference clock input.
9
I, PU/PD Analog
LVPECL reference clock input. Weak pull-up to VDD/2.
LVCMOS/LVTTL reference clock input
Clock output bank A
30
28
26
22, 24
I, PD
O
LVCMOS
QA
LVCMOS
LVCMOS
LVCMOS
QB
O
Clock output bank B
QC(1:0)
O
Clock output bank C
12, 14, 16, 18,
20
QD(4:0)
O
LVCMOS
Clock output bank D
Feedback clock input. Connect to an output for normal
operation. This input should be at the same voltage rail as
input reference clock. See Table 1.
2
FB_IN
I, PD
LVCMOS
10
31
OE#
I, PD
I, PU
LVCMOS
LVCMOS
Output enable/disable input. See Table 2.
PLL enable/disable input. See Table 2.
PLL_EN
32
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
I, PD
I, PD
LVCMOS
LVCMOS
VDD
Reference select input. See Table 2.
3, 4, 5, 6
Frequency select input, Bank (A:D). See Table 2.
2.5V or 3.3V Power supply for bank B output clock2,3
2.5V or 3.3V Power supply for bank C output clocks2,3
2.5V or 3.3V Power supply for bank D output clocks2,3
2.5V or 3.3V Power supply for PLL2,3
27
Supply
Supply
Supply
Supply
23
VDD
15, 19
1
VDD
VDD
2.5V or 3.3V Power supply for core, inputs, and bank A
output clock2,3
11
VDD
Supply
VDD
7
AVSS
VSS
Supply
Supply
Ground
Ground
Analog ground
13, 17, 21, 25,
29
Common ground
Note: 1 PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
power supply pins.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
3 of 13
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9351
rev 0.2
Table 1: Frequency Table
Feedback Output
Divider
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
VCO
÷2
÷4
÷8
Input Clock * 2
Input Clock * 4
Input Clock * 8
100 MHz to 200 MHz
50 MHz to 125 MHz
25 MHz to 62.5 MHz
100 MHz to 190MHz
50 MHz to 95MHz
25 MHz to 47.5MHz
Table 2: Function Table
Control
Default
0
1
REF_SEL
0
PCLK
TCLK
Bypass mode, PLL disabled. The
input clock connects to the output
dividers
PLL enabled. The VCO output connects to
the output dividers
PLL_EN
1
Outputs disabled (three-state), VCO running
at its minimum frequency
OE#
0
Outputs enabled
SELA
SELB
SELC
SELD
0
0
0
0
÷2 (Bank A)
÷4 (Bank B)
÷4 (Bank C)
÷4 (Bank D)
÷ 4 (Bank A)
÷ 8 (Bank B)
÷ 8 (Bank C)
÷ 8 (Bank D)
Absolute Maximum Ratings
Parameter
VDD
VDD
VIN
Description
Condition
Min
–0.3
2.375
–0.3
–0.3
Max
5.5
Unit
V
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
Functional
3.465
V
Relative to VSS
Relative to VSS
VDD+ 0.3
VDD+ 0.3
VDD ÷2
V
VOUT
VTT
DC Output Voltage
V
Output termination Voltage
Latch Up Immunity
V
LU
Functional
200
mA
mVp-p
°C
RPS
TS
Power Supply Ripple
Ripple Frequency < 100 kHz
Non-functional
Functional
150
+150
+85
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
–65
–40
TA
°C
TJ
Functional
+150
°C
ØJC
ØJA
Functional
42
°C/W
°C/W
Volts
ppm
Functional
105
ESDH
FIT
2000
Manufacturing test
10
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
4 of 13
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9351
rev 0.2
DC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C)
Parameter
VIL
Description
Condition
Min
Typ
Max
Unit
Input Voltage, Low
LVCMOS
-
-
0.7
V
VIH
Input Voltage, High
LVCMOS
LVPECL
1.7
-
VDD+0.3
1000
V
Peak-Peak Input Voltage
250
mV
VPP
-
Common Mode Range1
Output Voltage, Low2
Output Voltage, High2
Input Current, Low3
Input Current, High3
PLL Supply Current
Quiescent Supply Current
LVPECL
1.0
V
V
VCMR
VOL
-
VDD– 0.6
IOL= 15mA
-
-
-
0.6
VOH
IIL
IOH= –15mA
1.8
-
-100
100
10
7
V
VIL= VSS
-
-
-
µA
µA
mA
mA
IIH
VIL= VDD
-
IDDA
IDDQ
AVDD only
-
5
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
-
-
-
180
210
4
-
IDD
Dynamic Supply Current
mA
-
-
CIN
Input Pin Capacitance
Output Impedance
-
-
pF
ZOUT
14
18
22
Ω
Note: 1 VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the
input swing is within the VPP (DC) specification.
2.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated
transmission lines.
3.Inputs have pull-up or pull-down resistors that affect the input current.
DC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)
Parameter
VIL
Description
Condition
Min
Typ
Max
Unit
Input Voltage, Low
LVCMOS
-
-
0.8
V
VIH
Input Voltage, High
LVCMOS
LVPECL
LVPECL
2.0
250
1.0
-
VDD+0.3
1000
V
mV
V
Peak-Peak Input Voltage
Common Mode Range1
VPP
-
VCMR
-
VDD– 0.6
IOL= 24 mA
-
-
0.55
VOL
Output Voltage, Low2
V
IOL= 12 mA
-
-
-
0.30
VOH
IIL
Output Voltage, High2
Input Current, Low3
Input Current, High3
PLL Supply Current
Quiescent Supply Current
IOH= –24 mA
2.4
-
–100
100
10
7
V
VIL= VSS
-
-
-
µA
µA
mA
mA
IIH
VIL= VDD
-
IDDA
IDDQ
AVDD only
-
5
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
-
-
-
270
300
4
-
IDD
Dynamic Supply Current
mA
-
-
CIN
Input Pin Capacitance
Output Impedance
-
-
pF
ZOUT
12
15
18
Ω
Note: 1 VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the
input swing is within the VPP (DC) specification.
2.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated
transmission lines.
3.Inputs have pull-up or pull-down resistors that affect the input current.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
5 of 13
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9351
rev 0.2
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C) 1
Parameter
Description
Condition
Min
Typ
Max
380
190
95
Unit
fVCO
VCO Frequency
200
-
MHz
÷2 Feedback
100
-
÷4 Feedback
50
-
fin
Input Frequency
MHz
÷8 Feedback
25
-
47.5
200
75
Bypass mode (PLL_EN = 0)
0
-
frefDC
VPP
Input Duty Cycle
25
-
%
mV
V
Peak-Peak Input Voltage
Common Mode Range2
TCLK Input Rise/FallTime
LVPECL
500
-
1000
VDD– 0.6
1.0
190
95
VCMR
tr, tf
LVPECL
1.2
-
0.7V to 1.7V
÷2 Output
-
-
nS
100
-
fMAX
Maximum Output Frequency
MHz
÷4 Output
50
-
÷8 Output
25
-
47.5
52.5
55
fMAX < 100 MHz
fMAX > 100 MHz
0.6V to 1.8V
TCLK to FB_IN
PCLK to FB_IN
47.5
-
DC
tr, tf
t(φ)
Output Duty Cycle
%
45
-
Output Rise/Fall times
0.1
-
1.0
100
100
150
10
nS
pS
–100
-
Propagation Delay
(static phase offset)
–100
-
tsk(O)
Output-to-Output Skew
Output Disable Time
Output Enable Time
-
-
-
-
-
-
-
-
-
-
-
-
-
pS
nS
nS
tPLZ, HZ
tPZL, ZH
-
-
10
÷2 Feedback
2.2
-
PLL Closed Loop Bandwidth
(–3dB)
BW
MHz
÷4 Feedback
0.85
-
÷8 Feedback
0.6
-
Same frequency
Multiple frequencies
Same frequency
Multiple frequencies
-
150
250
100
175
-
tJIT(CC)
Cycle-to-Cycle Jitter
Period Jitter
pS
pS
-
-
tJIT(PER)
-
175
-
tJIT(φ)
tLOCK
I/O Phase Jitter
pS
Maximum PLL Lock Time
1
mS
Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
6 of 13
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9351
rev 0.2
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)1
Parameter
Description
Condition
Min
200
100
50
Typ
Max
500
200
125
62.5
Unit
fVCO
VCO Frequency
-
-
-
-
MHz
÷2 Feedback
÷4 Feedback
÷8 Feedback
fin
Input Frequency
MHz
25
Bypass mode
(PLL_EN = 0)
0
-
200
frefDC
VPP
Input Duty Cycle
25
-
75
1000
VDD– 0.9
1.0
200
125
62.5
52.5
55
%
mV
V
Peak-Peak Input Voltage
Common Mode Range2
TCLK Input Rise/FallTime
LVPECL
500
-
VCMR
tr, tf
LVPECL
1.2
-
0.8V to 2.0V
-
-
nS
÷2 Output
100
-
fMAX
Maximum Output Frequency
MHz
÷4 Output
50
-
÷8 Output
25
-
fMAX < 100 MHz
fMAX > 100 MHz
0.8V to 2.4V
47.5
-
DC
tr, tf
t(φ)
Output Duty Cycle
%
45
-
Output Rise/Fall times
0.1
-
1.0
100
100
150
350
10
nS
pS
TCLK to FB_IN, same VDD
PCLK to FB_IN, same VDD
Banks at same voltage
Banks at different voltages
–100
-
Propagation Delay
(static phase offset)
–100
-
tsk(O)
Output-to-Output Skew
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pS
pS
nS
nS
tsk(B)
-
tPLZ, HZ
tPZL, ZH
-
-
10
÷2 Feedback
2.2
-
PLL Closed Loop Bandwidth
(–3dB)
BW
MHz
÷4 Feedback
0.85
-
÷8 Feedback
0.6
-
Same frequency
Multiple frequencies
Same frequency
Multiple frequencies
I/O same VDD
-
150
250
100
150
-
tJIT(CC)
Cycle-to-Cycle Jitter
Period Jitter
pS
pS
-
-
tJIT(PER)
-
175
-
tJIT(φ)
tLOCK
I/O Phase Jitter
pS
Maximum PLL Lock Time
1
mS
Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
7 of 13
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I9351
Zo = 50 ohm
RT = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm
Zo = 50 ohm
Differential
Pulse
Generator
Zo = 50 ohm
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 2. PECL_CLK AC Test Reference for VDD = 3.3V / 2.5V
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
8 of 13
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I9351
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
9 of 13
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9351
rev 0.2
Package Diagram
32-lead TQFP Package
SECTION A-A
Dimensions
Millimeters
Symbol
Inches
Min
Max
Min
…
Max
1.2
A
A1
A2
D
….
0.0472
0.0059
0.0413
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0374
0.3465
0.2717
0.3465
0.2717
0.0177
0.05
0.95
8.8
0.15
1.05
9.2
D1
E
6.9
7.1
8.8
9.2
E1
L
6.9
7.1
0.45
0.75
L1
T
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0°
0.0079
0.0062
0.0177
0.0157
0.0079
7°
0.09
0.097
0.30
0.30
0.08
0°
0.2
0.157
0.45
0.40
0.2
T1
b
b1
R0
a
7°
e
0.031 BASE
0.8 BASE
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
10 of 13
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I9351
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Millimeters
Min
Max
Min
…
Max
1.6
A
A1
A2
D
….
0.0630
0.0059
0.0571
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0531
0.3465
0.2717
0.3465
0.2717
0.0177
0.05
1.35
8.8
0.15
1.45
9.2
D1
E
6.9
7.1
8.8
9.2
E1
L
6.9
7.1
0.45
0.75
L1
T
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0.0079
0.0062
0.0177
0.0157
0.0079
0.09
0.097
0.30
0.30
0.08
0.2
0.157
0.45
0.40
0.20
T1
b
b1
R0
e
0.031 BASE
0.8 BASE
a
0°
7°
0°
7°
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
11 of 13
Notice: The information in this document is subject to change without notice.
July 2005
ASM5I9351
rev 0.2
Ordering Information
Part Number
ASM5I9351-32-ET
ASM5I9351-32-LT
ASM5I9351G-32-ET
ASM5I9351G-32-LT
Marking
Package Type
Temperature
Industrial
ASM5I9351
32-pin TQFP
ASM5I9351
ASM5I9351G
ASM5I9351G
32-pin LQFP –Tape and Reel
32-pin TQFP, Green
Industrial
Industrial
32-pin LQFP –Tape and Reel, Green
Industrial
Device Ordering Information
A S M 5 I 9 3 5 1 F - 3 2 - L T
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
(-40C to +125C) (-40C to +85C)
I= Industrial
P or n/c = Commercial
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
12 of 13
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
ASM5I9351
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5I9351
Document Version: 0.2
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
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including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
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All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
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components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
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2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
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ASM5I9352-32-ET
PLL Based Clock Driver, 9352 Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, 1 MM HEIGHT, TQFP-32
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