AS7C4098-12 [ALSC]
5V/3.3V 256K x 16 CMOS SRAM; 5V / 3.3V 256K ×16的CMOS SRAM
| 型号： | AS7C4098-12 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 5V/3.3V 256K x 16 CMOS SRAM |
| 文件： | 总10页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS7C4098
AS7C34098
January 2005
®
5V/3.3V 256K × 16 CMOS SRAM
Features
• AS7C4098 (5V version)
• Low power consumption: STANDBY
• AS7C34098 (3.3V version)
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4098)/max @ 12 ns
- 576 mW (AS7C34098)/max @ 10 ns
- 110 mW (AS7C4098)/max CMOS
- 72 mW (AS7C34098)/max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 100 mA
Logic block diagram
Pin arrangement for SOJ and TSOP 2
44-pin (400 mil) SOJ
TSOP2
A0
A1
A2
V
CC
A0
A1
A2
A3
A4
CE
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
A17
1024 × 256 × 16
A3
GND
2
A16
A4
3
A15
Array
(4,194,304)
A6
4
OE
A7
A8
5
UB
6
LB
A12
A13
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O1
7
I/O2
I/O3
I/O4
8
9
I/O1–I/O8
I/O9–I/O16
I/O
buffer
Control circuit
10
11
12
13
14
15
VCC
GND
I/O5
I/O6
I/O7
Column decoder
WE
I/O8
WE
A5
16
17
18
19
20
21
22
29
28
27
26
I/O9
NC
A14
A13
A12
A11
A10
UB
OE
LB
CE
A6
A7
25
24
23
A8
A9
Selection guide
–10
10
5
–12
–15
15
–20
Unit
ns
Maximum address access time
12
6
20
8
Maximum output enable access time
7
ns
AS7C4098
AS7C34098
AS7C4098
AS7C34098
–
250
130
20
220
110
20
180
100
20
mA
mA
mA
mA
Maximum operating current
160
–
Maximum CMOS standby current
20
20
20
20
1/13/05; v.1.9
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C4098
AS7C34098
®
Functional description
The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 262,144 words × 16 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5/6/7/8 ns are
AA RC WC
OE
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is High the device enters standby mode. The standard AS7C4098/AS7C34098 is guaranteed not to exceed 110/
72mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip
enable (CE). Data on the input pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To
avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or
write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to
be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V
(AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ and TSOP 2 packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
–0.50
–0.50
–0.50
–
Max
+7.0
+5.0
Unit
V
AS7C4098
AS7C34098
V
V
V
t1
t1
t2
D
Voltage on V relative to GND
CC
V
Voltage on any pin relative to GND
Power dissipation
V
+0.50
V
CC
P
T
1.5
W
Storage temperature
–65
–55
–
+150
+125
±20
°C
°C
mA
stg
bias
Ambient temperature with V applied
T
CC
DC current into outputs (low)
I
OUT
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
WE
X
OE
X
LB
X
X
H
L
UB
X
X
H
H
L
I/O1–I/O8
I/O9–I/O16
Mode
Standby (I , I
High Z
High Z
)
SB SB1
L
H
H
High Z
High Z
High Z
Output disable (I
)
CC
L
X
X
D
OUT
L
L
H
L
L
H
L
High Z
D
D
Read (I
)
CC
OUT
OUT
L
D
OUT
L
H
L
D
High Z
IN
X
H
L
High Z
D
D
Write (I
)
IN
IN
CC
L
D
IN
Key: X = Don’t care, L = Low, H = High.
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Alliance Semiconductor
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AS7C4098
AS7C34098
®
Recommended operating conditions
Parameter
Symbol
(12/15/20)
Min Typical
Max
5.5
Unit
V
AS7C4098
AS7C34098
AS7C34098
AS7C4098
AS7C34098
V
4.5
3.15
3.0
2.2
2.0
–0.5
0
5.0
3.3
3.3
–
CC
Supply voltage
Input voltage
V
(10)
3.6
V
CC
V
(12/15/20)
3.6
V
CC
V
V
V
V
+ 0.5
V
IH
CC
CC
–
+ 0.5
V
IH
1
V
–
0.8
V
IL
commercial
Ambient operating temperature
industrial
T
–
70
85
°C
°C
A
T
–40
–
A
1 VIL min = –1.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)1
–10
–12
–15
–20
Parameter Symbol
Test conditions
Min Max Min Max Min Max Min Max Unit
AS7C4098/
AS7C34098
Input leakage
current
V
= Max
CC
|I |
–
1
–
1
–
1
–
1
µA
LI
V
= GND to V
IN CC
V
= Max
CC
AS7C4098/
AS7C34098
Output leakage
current
CE = V or OE = V
IH IH
|I
|
–
1
–
1
–
1
–
1
µA
LO
or WE = V
IL
V
= GND to V
I/O
CC
Operating
power supply
current
V
= Max
AS7C4098
–
–
–
–
–
250
130
–
–
220
110
–
–
180 mA
100 mA
CC
I
Min cycle, 100% duty
CE = V , I = 0mA
CC
AS7C34098
160
IL OUT
AS7C4098
AS7C34098
AS7C4098
–
–
–
–
60
–
–
–
–
60
60
20
–
–
–
60
60
20
–
–
–
60 mA
60 mA
20 mA
V
= Max
CC
I
SB
CE = V , f = Max
IH
Standby power
supply current
V
= Max
CC
I
CE ≥ V – 0.2V, V ≥ V
SB1
CC IN CC
AS7C34098
–
20
–
20
–
20
–
20 mA
– 0.2V or V ≤ 0.2V, f = 0
IN
V
V
I
= 8 mA, V = Min
AS7C4098/
AS7C34098
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
OL
OL
CC
Output voltage
I
= –4 mA, V = Min
2.4
2.4
2.4
2.4
OH
OH
CC
Capacitance (f = 1MHz, T = 25° C, V = NOMINAL)2
a
CC
Signals
Parameter
Input capacitance
I/O capacitance
Symbol
Test conditions
= 0V
Max
Unit
C
A, CE, WE, OE, UB, LB
I/O
V
6
8
pF
pF
IN
IN
C
V
= V
= 0V
OUT
I/O
IN
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AS7C4098
AS7C34098
®
Read cycle (over the operating range)3,9
–10
–12
–15
–20
Parameter
Read cycle time
Symbol
Min Max Min Max Min Max Min Max Unit Notes
t
10
–
–
–
3
0
–
0
–
–
0
–
0
–
–
10
10
5
12
–
–
–
3
3
–
0
–
–
0
–
0
–
–
12
12
6
15
–
–
–
3
0
–
0
–
–
0
–
0
–
–
15
15
7
20
–
–
–
3
0
–
0
–
–
0
–
0
–
–
20
20
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
AA
Address access time
t
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in higfch Z
OE Low to output in low Z
OE High to output in high Z
LB, UB access time
t
ACE
t
OE
OH
t
–
–
–
–
5
t
–
–
–
–
4, 5
4, 5
4, 5
4, 5
CLZ
CHZ
t
5
6
7
9
t
–
–
–
–
OLZ
OHZ
t
5
6
7
9
t
5
6
7
8
BA
LB, UB Low to output in low Z
LB, UB High to output in high Z
Power up time
t
–
–
–
–
BLZ
BHZ
t
5
6
7
9
t
t
–
–
–
–
5
5
PU
PD
Power down time
10
12
15
20
Key to switching waveforms
Rising input
Falling input
tRC
Undefined/don’t care
Read waveform 1 (address controlled)6,7,9
Address
tAA
tOH
Previous data valid
tOH
DataOUT
Data valid
1/13/05; v.1.9
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AS7C4098
AS7C34098
®
Read waveform 2 (CE, OE, UB, LB controlled)6,8,9
tRC
Address
tAA
OE
tOHZ
tOE
tOH
tOLZ
CE
tACE
tLZ
tCHZ
LB, UB
tBA
tBHZ
tBLZ
DataOUT
Data valid
Write cycle (over the operating range)11
–10
–12
–15
–20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max Unit Note
t
t
t
10
7
–
–
–
–
–
–
–
–
–
–
5
–
–
12
8
–
–
–
–
–
–
–
–
15
10
10
0
–
–
–
–
–
–
–
–
–
–
7
–
–
20
12
12
0
–
–
–
–
–
–
–
–
–
–
9
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AW
Chip enable (CE) to write end
Address setup to write end
Address setup time
7
8
t
0
0
AS
Write pulse width (OE = High)
Write pulse width (OE = Low)
Write recovery time
t
t
7
8
10
15
0
12
20
0
WP1
WP2
10
0
12
0
t
WR
Address hold from end of write
Data valid to write end
t
0
0
0
0
AH
t
5
6
7
9
DW
Data hold time
t
0
0
–
6
–
–
0
0
4, 5
4, 5
4, 5
4, 5
DH
WZ
OW
Write enable to output in High-Z
Output active from write end
Byte enable Low to write end
t
0
0
0
0
t
3
3
3
3
t
7
8
10
12
BW
1/13/05; v.1.9
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AS7C4098
AS7C34098
®
Write waveform 1(WE controlled)10,11
tWC
tAH
tWR
Address
tCW
tBW
tAW
CE
LB, UB
tAS
tWP
WE
tDW
tDH
Data valid
DataIN
tWZ
tOW
DataOUT
Data undefined
High Z
Write waveform 2 (CE controlled)10,11
tWC
tAH
tWR
Address
tAS
tCW
CE
tAW
tBW
LB, UB
WE
tWP
tDW
tDH
Data valid
High Z
DataIN
DataOUT
tCLZ
High Z
tWZ
Data undefined
tOW
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AS7C4098
AS7C34098
®
Write waveform 3 10,11
tWC
tAH
tWR
Address
tAS
tCW
CE
tAW
tBW
LB, UB
WE
tWP
tDW
Data valid
tDH
DataIN
tWZ
DataOUT
Data undefined
High Z
High Z
AC test conditions
- Output load: see Figure B or Figure C.
168Ω
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Thevenin equivalent:
+5V
+1.728V (5V and 3.3V)
+3.3V
DOUT
DOUT
480
Ω
320
Ω
+3.0V
DOUT
350
90%
10%
90%
10%
255
Ω
C13
Ω
C13
GND
2 ns
GND
Figure B: 5V Output load
GND
Figure C: 3.3V Output load
Figure A: Input pulse
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
t
CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
1/13/05; v.1.9
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P. 7 of 10
AS7C4098
AS7C34098
®
Typical DC and AC characteristics12
Normalized supply current ICC, ISB
Normalized supply current ICC, ISB
vs. ambient temperature Ta
Normalized supply current ISB1
vs. supply voltage VCC
vs. ambient temperature Ta
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
625
25
ICC
VCC = VCC(NOMINAL)
ICC
5
1
ISB
ISB
0.2
0.04
MIN
NOMINAL
–55
–10
35
80
–55
–10
35
80
MAX
125
125
Supply voltage (V)
Ambient temperature (
°
C)
Ambient temperature (°C)
Normalized access time tAA
vs. supply voltage VCC
Normalized access time tAA
vs. ambient temperature Ta
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Ta = 25
°
C
VCC = VCC(NOMINAL)
VCC = VCC(NOMINAL)
Ta = 25° C
MIN
NOMINAL
–55
–10
35
80
0
25
50
75
MAX
125
100
Supply voltage (V)
Ambient temperature (°C)
Cycle frequency (MHz)
Output source current IOH
vs. output voltage VOH
Output sink current IOL
vs. output voltage VOL
Typical access time change ∆tAA
vs. output capacitive loading
140
120
100
80
140
120
100
80
35
30
25
20
15
10
5
VCC = VCC(NOMINAL)PL
VCC = VCC(NOMINAL)
VCC = VCC(NOMINAL)
Ta = 25
°
C
Ta = 25° C
60
60
40
40
20
20
0
0
0
0
0
0
250
500
750
VCC
VCC
1000
Output voltage (V)
Output voltage (V)
Capacitance (pF)
1/13/05; v.1.9
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AS7C4098
AS7C34098
®
Package dimensions
c
44 434241403938373635343332313029282726252423
44-pin TSOP 2
Min (mm) Max (mm)
A
1.2
He
e
44-pin TSOP 2
A
0.05
0.95
0.15
1.05
1
A
2
b
c
0.30
0.45
1 2 3 4 5 6 7 8 9 101112131415161718 19202122
d
0.21
0.12
d
e
18.31
10.06
11.68
18.52
10.26
11.94
H
e
l
A2
A
E
l
0.80 (typical)
0–5°
A1
0.40
0.60
b
E
D
e
44-pin SOJ 400 mils
E1
A
E2
44-pin SOJ
B
Min(mils) Max(mils)
A
A1
A2
B
0.128
0.025
0.105
0.026
0.015
0.007
1.120
0.148
-
Pin 1
A1
c
0.115
0.032
0.020
0.013
1.130
A2
b
E
Seating
Plane
b
c
D
E
0.370 NOM
E1
E2
e
0.395
0.435
0.405
0.445
0.050 NOM
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P. 9 of 10
AS7C4098
AS7C34098
®
Ordering Codes
Package
Version
10 ns
NA
12 ns
15 ns
20 ns
5V commercial
5V industrial
AS7C4098-12JC
AS7C4098-12JI
AS7C34098-12JC
AS7C34098-12JI
AS7C4098-12TC
AS7C4098-12TI
AS7C34098-12TC
AS7C34098-12TI
AS7C4098-15JC
AS7C4098-15JI
AS7C34098-15JC
AS7C34098-15JI
AS7C4098-15TC
AS7C4098-15TI
AS7C34098-15TC
AS7C34098-15TI
AS7C4098-20JC
AS7C4098-20JI
AS7C34098-20JC
AS7C34098-20JI
AS7C4098-20TC
AS7C4098-20TI
AS7C34098-20TC
AS7C34098-20TI
NA
SOJ
3.3V commercial AS7C34098-10JC
3.3V industrial
5V commercial
5V industrial
NA
NA
NA
TSOP 2
Note:
3.3V commercial AS7C34098-10TC
3.3V industrial NA
Add suffix “N” to the above part number for lead free devices, Ex. AS7C4098-12JCN
Part numbering system
AS7C
X
4098
–XX
J or T
X
N
Voltage:
Packages:
Temperature ranges:
Device Access
number time
SRAM prefix Blank: 5V CMOS
3: 3.3V CMOS
J: SOJ 400 mil C: Commercial, 0°C to 70°C Lead free device
T: TSOP 2 I: Industrial, –40°C to 85°C
1/13/05; v.1.9
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marks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under
development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or
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for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting sys-
tems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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