AS7C4098-15BC [ALSC]
Standard SRAM, 256KX16, 15ns, CMOS, PBGA48, 7 X 11 MM, CSP, FBGA-48;
| 型号： | AS7C4098-15BC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 256KX16, 15ns, CMOS, PBGA48, 7 X 11 MM, CSP, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS7C4098
AS7C34098
March 2002
®
5V/ 3.3V 256K × 16 CMOS SRAM
Features
• AS7C4098 (5V version)
• Low power consumption: STANDBY
• AS7C34098 (3.3V version)
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/ 12/ 15/ 20 ns address access time
- 5/ 6/ 7/ 8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4098)/ max @ 12 ns
- 468 mW (AS7C34098)/ max @ 12 ns
- 110 mW (AS7C4098)/ max CMOS
- 72 mW (AS7C34098)/ max CMOS
• Individual byte read/ write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/ O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
- 48-ball FBGA 7 x 11 mm
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement for SOJ and TSOP 2
44-pin (400 mil) SOJ
TSOP2
A0
A1
A2
VCC
A0
A1
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
A17
1024 × 256 × 16
A3
GND
2
A16
A4
A2
3
A15
Array
(4,194,304)
A6
A3
4
OE
A7
A8
A4
5
UB
CE
6
LB
A12
A13
I/ O16
I/ O15
I/ O14
I/ O13
GND
VCC
I/ O1
I/ O2
I/ O3
I/ O4
VCC
GND
I/ O5
I/ O6
I/ O7
7
8
9
I/ O1–I/ O8
I/ O
buffer
Control circuit
10
11
12
13
14
15
I/ O9–I/ O16
Column decoder
I/ O12
I/ O11
I/ O10
WE
I/ O8
WE
A5
16
17
18
19
20
21
22
29
28
27
26
25
24
23
I/ O9
NC
UB
OE
LB
A14
A13
A12
A11
A10
A6
A7
A8
A9
CE
Selection guide
–10
10
5
–12
–15
15
–20
Unit
ns
Maximum address access time
12
6
20
9
Maximum output enable access time
7
ns
AS7C4098
AS7C34098
AS7C4098
AS7C34098
–
250
130
20
220
110
20
180
100
20
mA
mA
mA
mA
Maximum operating current
160
–
Maximum CMOS standby current
20
20
20
20
5/ 23/ 02; v.1.8
Alliance Semiconductor
P. 1 of 12
Copyright © Alliance Semiconductor. All rights reserved.
AS7C4098
AS7C34098
®
Ball arrangement BGA
48-BGA Ball-Grid-Array Package
1
2
3
4
5
6
A
B
LB
OE A0 A1
A2
NC
I/ O9 UB A3 A4
CE I/ O1
C I/ O10 I/ O11 A5 A6 I/ O2 I/ O3
D
E
V
I/ O12 A17 A7 I/ O4 VCC
SS
VCC I/ O13 NC A16 I/ O5
V
SS
F I/ O15 I/ O14 A14 A15 I/ O6 I/ O7
G I/ O16 NC A12 A13 WE I/ O8
H
NC
A8
A9 A10 A11
NC
48-BGA Ball-Grid-Array Package -
Version 2 Alternative
1
2
3
4
5
6
A
B
C
D
E
LB
OE A0 A1
A2
NC
I/ O1 UB A3 A4
I/ O2 I/ O3 A5 A6 I/ O11 I/ O10
I/ O4 A17 A7 I/ O12 VCC
VCC I/ O5 NC A16 I/ O13
CE I/ O9
V
SS
V
SS
F
I/ O7 I/ O6 A14 A15 I/ O14 I/ O15
I/ O8 NC A12 A13 WE I/ O16
G
H
NC
A8
A9 A10 A11
NC
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Alliance Semiconductor
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AS7C4098
AS7C34098
®
Functional description
The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 262,144 words × 16 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/ 12/ 15/ 20 ns with output enable access times (tOE) of 5/ 6/ 7/ 8 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is High the device enters standby mode. The standard AS7C4098 is guaranteed not to exceed 110 mW power
consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/ O1–I/ O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/ O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip
drives I/ O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/ O1–I/ O8, and UB controls the higher bits, I/ O9–I/ O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V
(AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2, and 48 - CSP/ BGA packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
–0.50
–0.50
–0.50
–
Max
+7.0
Unit
V
AS7C4098
AS7C34098
V
t1
Voltage on VCC relative to GND
V
+5.0
V
t1
Voltage on any pin relative to GND
Power dissipation
V
VCC +0.50
1.5
V
t2
PD
W
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Tstg
–65
–55
–
+150
+125
±20
°C
°C
mA
Tbias
IOUT
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
WE
X
OE
X
LB
X
X
H
L
UB
X
X
H
H
L
I/ O1–I/ O8
I/ O9–I/ O16
Mode
High Z
High Z
Standby (ISB, ISB1)
H
H
High Z
High Z
Output disable (ICC)
L
X
X
DOUT
High Z
DOUT
High Z
DOUT
L
L
H
L
L
H
L
Read (ICC)
L
DOUT
L
H
L
D
High Z
IN
X
H
L
High Z
D
Write (ICC)
IN
L
D
D
IN
IN
Key: X = Don’t care, L = Low, H = High.
5/ 23/ 02; v.1.8
Alliance Semiconductor
P. 3 of 12
AS7C4098
AS7C34098
®
Recommended operating conditions
Parameter
Symbol
VCC (12/ 15/ 20)
CC (10)
CC (12/ 15/ 20)
Min Typical
Max
5.5
Unit
V
AS7C4098
AS7C34098
AS7C34098
AS7C4098
AS7C34098
4.5
3.15
3.0
5.0
3.3
3.3
–
Supply voltage
Input voltage
V
3.6
V
V
3.6
V
V
2.2
VCC + 0.5
VCC + 0.5
0.8
V
IH
V
2.0
–
V
IH
V
–0.51
–
V
IL
commercial
Ambient operating temperature
industrial
TA
TA
0
–
70
°C
°C
–40
–
85
1 V min = –3.0V for pulse width less than t / 2.
IL RC
ꢀ
DC operating characteristics (over the operating range)
–10
–12
–15
–20
Parameter Symbol
Test conditions
VCC = Max
IN = GND to VCC
VCC = Max
CE = VIH or OE = V
Min Max Min Max Min Max Min Max Unit
Input leakage
| ILI|
–
1
–
1
–
1
–
1
µA
current
V
Output leakage
current
IH
| ILO
|
–
1
–
1
–
1
–
1
µA
or WE = V
IL
VI/ O = GND to VCC
Operating
power supply
current
VCC = Max
Min cycle, 100% duty
AS7C4098
–
–
–
–
–
250
130
–
–
220
110
–
–
180 mA
100 mA
ICC
AS7C34098
160
CE = V , IOUT = 0mA
IL
AS7C4098
AS7C34098
AS7C4098
–
–
–
–
60
–
–
–
–
60
60
20
–
–
–
60
60
20
–
–
–
60 mA
60 mA
20 mA
VCC = Max
ISB
CE = V , f = Max
IH
Standby power
supply current
VCC = Max
ISB1
CE ≥ VCC – 0.2V, V ≥ VCC
IN
AS7C34098
–
20
–
20
–
20
–
20 mA
– 0.2V or V ≤ 0.2V, f = 0
IN
V
IOL = 8 mA, VCC = Min
IOH = –4 mA, VCC = Min
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
OL
Output voltage
V
2.4
2.4
2.4
2.4
OH
ꢁ
Capacitance (f = 1MHz, T = 25° C, V = NOMINAL)
a
CC
Parameter
Input capacitance
I/ O capacitance
Symbol
Signals
Test conditions
IN = 0V
IN = VOUT = 0V
Max
6
Unit
C
A, CE, WE, OE, UB, LB
I/ O
V
pF
pF
IN
C
V
8
I/ O
5/ 23/ 02; v.1.8
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AS7C4098
AS7C34098
®
ꢆꢃꢅ
Read cycle (over the operating range)
–10
–12
–15
–20
Parameter
Read cycle time
Symbol
tRC
Min
10
–
Max Min Max Min Max Min Max Unit Notes
–
10
10
5
12
–
–
–
3
3
–
0
–
–
0
–
0
–
–
12
12
6
15
–
–
–
3
0
–
0
–
–
0
–
0
–
–
15
15
7
20
–
–
–
3
0
–
0
–
–
0
–
0
–
–
20
20
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
tAA
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in higfch Z
OE Low to output in low Z
OE High to output in high Z
LB, UB access time
tACE
tOE
–
–
tOH
3
–
–
–
–
5
tCLZ
tCHZ
tOLZ
tOHZ
tBA
0
–
–
–
–
4, 5
4, 5
4, 5
4, 5
–
5
6
7
9
0
–
–
–
–
–
5
6
7
9
–
5
6
7
8
LB, UB Low to output in low Z
LB, UB High to output in high Z
Power up time
tBLZ
tBHZ
tPU
0
–
–
–
–
–
5
6
7
9
0
–
–
–
–
5
5
Power down time
tPD
–
10
12
15
20
Key to switching waveforms
Rising input
Falling input
Undefined/ don’t care
ꢂꢃꢄꢃꢅ
Read waveform 1 (address controlled)
t
RC
Address
t
AA
t
t
OH
OH
Data
Previous data valid
Data valid
OUT
5/ 23/ 02; v.1.8
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AS7C4098
AS7C34098
®
ꢂꢃꢇꢃꢅ
Read waveform 2 (CE, OE, UB, LB controlled)
t
RC
Address
t
AA
OE
CE
t
OHZ
t
OE
t
t
OH
OLZ
t
ACE
t
t
CHZ
LZ
LB, UB
t
t
BA
BHZ
t
BLZ
Data
Data valid
OUT
ꢀꢀ
Write cycle (over the operating range)
–10
–12
–15
–20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max Unit Note
tWC
tCW
tAW
tAS
10
7
–
–
–
–
–
–
–
–
–
–
5
–
–
12
8
–
–
–
–
–
–
–
–
15
10
10
0
–
–
–
–
–
–
–
–
–
–
7
–
–
20
12
12
0
–
–
–
–
–
–
–
–
–
–
9
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable (CE) to write end
Address setup to write end
Address setup time
7
8
0
0
Write pulse width (OE = High)
Write pulse width (OE = Low)
Write recovery time
tWP1
tWP2
tWR
tAH
7
8
10
15
0
12
20
0
10
0
12
0
Address hold from end of write
Data valid to write end
0
0
0
0
tDW
tDH
5
6
7
9
Data hold time
0
0
–
6
–
–
0
0
4, 5
4, 5
4, 5
4, 5
Write enable to output in High-Z
Output active from write end
Byte enable Low to write end
tWZ
tOW
tBW
0
0
0
0
3
3
3
3
7
8
10
12
5/ 23/ 02; v.1.8
Alliance Semiconductor
P. 6 of 12
AS7C4098
AS7C34098
®
ꢀꢈꢃꢀꢀ
Write waveform 1(WE controlled)
t
t
WC
t
AH
WR
t
Address
CW
CE
t
BW
LB, UB
t
AW
t
t
WP
AS
WE
t
t
DH
DW
Data valid
Data
IN
t
WZ
t
OW
Data
Data undefined
OUT
High Z
ꢀꢈꢃꢀꢀ
Write waveform 2 (CE controlled)
t
WC
t
AH
t
WR
Address
t
AS
t
CW
CE
t
AW
t
BW
LB, UB
WE
t
WP
t
t
DH
DW
Data valid
High Z
Data
IN
t
t
CLZ
WZ
t
OW
Data
Data undefined
OUT
High Z
5/ 23/ 02; v.1.8
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P. 7 of 12
AS7C4098
AS7C34098
®
ꢀꢈꢃꢀꢀ
Write waveform 3
t
t
WC
t
AH
t
WR
Address
CE
t
AS
CW
t
AW
t
BW
LB, UB
WE
t
WP
t
DW
Data valid
Data
IN
t
WZ
t
DH
Data
Data undefined
OUT
High Z
High Z
AC test conditions
- Output load: see Figure B or Figure C.
168
Ω
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Thevenin equivalent:
+5V
+1.728V (5V and 3.3V)
+3.3V
D
OUT
D
OUT
480
Ω
320
Ω
+3.0V
D
OUT
90%
10%
90%
10%
255
Ω
C(14)
GND
350
Ω
C(14)
GND
GND
2 ns
Figure A: Input pulse
Figure B: 5V Output load
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CE is required to meet I specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
CC CC SB
t
and t
are specified with C = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
CLZ
CHZ L
This parameter is guaranteed, but not tested.
WEis High for read cycle.
CEand OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
5/ 23/ 02; v.1.8
Alliance Semiconductor
P. 8 of 12
AS7C4098
AS7C34098
®
ꢀꢁꢉ
Typical DC and AC characteristics
Normalized supply current ICC, ISB
vs. supply voltage VCC
1.4
Normalized supply current I , I
Normalized supply current I
SB1
CC SB
vs. ambient temperature T
vs. ambient temperature T
a
a
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
625
25
I
V = V (NOMINAL)
CC CC
I
CC
CC
1.0
0.8
0.6
5
1
I
I
SB
SB
0.4
0.2
0.0
0.2
0.04
MIN
NOMINAL
–55
–10
35
80
–55
–10
35
80
MAX
125
125
Supply voltage (V)
Ambient temperature (
°
C)
Ambient temperature (°C)
Normalized access time t
Normalized access time t
Normalized supply current I
CC
AA
AA
a
vs. supply voltage V
vs. ambient temperature T
vs. cycle frequency 1/ t , 1/ t
RC WC
CC
1.5
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.3
1.2
1.1
1.0
0.9
0.8
T = 25
°
C
V = V (NOMINAL)
CC CC
V
= V (NOMINAL)
CC
a
CC
T = 25
°
C
a
MIN
NOMINAL
–55
–10
35
80
0
25
50
75
MAX
125
100
Supply voltage (V)
Ambient temperature (
°C)
Cycle frequency (MHz)
Output source current I
Output sink current I
Typical access time change
∆t
AA
OH
OL
vs. output voltage V
vs. output voltage V
OL
vs. output capacitive loading
OH
140
120
100
80
140
120
100
80
35
30
25
20
15
10
5
V
= V (NOMINAL)PL
V
= V (NOMINAL)
V = V (NOMINAL)
CC CC
CC
CC
CC
CC
T = 25
°
C
T = 25° C
a
a
60
60
40
40
20
20
0
0
0
0
0
0
250
500
750
V
V
1000
CC
CC
Output voltage (V)
Output voltage (V)
Capacitance (pF)
5/ 23/ 02; v.1.8
Alliance Semiconductor
P. 9 of 12
AS7C4098
AS7C34098
®
Package dimensions
c
44 434241403938373635343332313029282726252423
44-pin TSOP 2
Min (mm) Max (mm)
A
A1
A2
b
1.2
H
e
44-pin TSOP 2
e
0.05
0.95
0.25
1.05
0.45
1 2 3 4 5 6 7 8 9 101112131415161718 19202122
d
c
0.15 (typical)
d
18.28
10.06
11.56
18.54
10.26
11.96
e
He
E
l
A
2
A
0.80 (typical)
0–5
°
A
1
l
0.40
0.60
b
E
D
e
44-pin SOJ 400 mils
E1
A
E2
44-pin SOJ
B
Min(mils) Max(mils)
A
A1
A2
B
0.128
0.025
1.105
0.026
0.015
0.007
1.120
0.148
-
Pin 1
A1
c
1.115
0.032
0.020
0.013
1.130
A2
b
E2
Seating
Plane
b
c
D
E
0.370 NOM
E1
E2
e
0.395
0.435
0.405
0.445
0.050 NOM
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P. 10 of 12
AS7C4098
AS7C34098
®
48-ball FBGA
Ball # A1
Bottom View
Top View
Ball # A1 index
6
5
4
3
2
1
A
B
C
D
E
SRAM Die
C
C1
F
A
G
H
Elastomer
A
B
B1
Detail View
A
Side View
E2
D
E
E2
Y
E
Die
Die
E1
0.3/ Typ
Minimum Typical Maximum
A
–
6.90
–
0.75
7.00
3.75
11.00
5.25
0.35
–
–
7.10
–
Notes
B
B1
C
1. Bump counts: 48 (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
10.90
–
11.10
–
C1
D
4. All tolerance are ±0.050 unless otherwise specified.
5. Typ: typical.
0.30
–
0.40
1.20
–
E
6. Y is coplanarity: 0.08 (max).
E1
E2
Y
–
0.68
0.25
–
0.22
–
0.27
0.08
5/ 23/ 02; v.1.8
Alliance Semiconductor
P. 11 of 12
AS7C4098
AS7C34098
®
Ordering Codes
Package
Version
10 ns
NA
12 ns
15 ns
20 ns
5V commercial
5V industrial
AS7C4098-12JC
AS7C4098-12JI
AS7C4098-15JC
AS7C4098-15JI
AS7C4098-20JC
AS7C4098-20JI
NA
SOJ
3.3V commercial AS7C34098-10JC
AS7C34098-12JC
AS7C34098-12JI
AS7C4098-12TC
AS7C4098-12TI
AS7C34098-12TC
AS7C34098-12TI
AS7C4098-12BC
AS7C4098-12BI
AS7C34098-12BC
AS7C34098-12BI
AS7C4098-12B2C
AS7C4098-12B2I
AS7C34098-12B2C
AS7C34098-12B2I
AS7C34098-15JC
AS7C34098-15JI
AS7C4098-15TC
AS7C4098-15TI
AS7C34098-15TC
AS7C34098-15TI
AS7C4098-15BC
AS7C4098-15BI
AS7C34098-15BC
AS7C34098-15BI
AS7C4098-15B2C
AS7C4098-15B2I
AS7C34098-15B2C
AS7C34098-15B2I
AS7C34098-20JC
AS7C34098-20JI
AS7C4098-20TC
AS7C4098-20TI
AS7C34098-20TC
AS7C34098-20TI
AS7C4098-20BC
AS7C4098-20BI
AS7C34098-20BC
AS7C34098-20BI
AS7C4098-20B2C
AS7C4098-20B2I
AS7C34098-20B2C
AS7C34098-20B2I
3.3V industrial
5V commercial
5V industrial
NA
NA
NA
TSOP 2
BGA
3.3V commercial AS7C34098-10TC
3.3V industrial
5V commercial
5V industrial
NA
NA
NA
3.3V commercial AS7C34098-10BC
3.3V industrial
5V commercial
5V industrial
NA
NA
NA
BGA Ball
Arrange-
ment
3.3V commercial AS7C34098-10B2C
Version 2
3.3V industrial
NA
Part numbering system
AS7C
X
4098
–XX
J, T, or B
Packages:
J: SOJ 400 mil
T: TSOP 2
X
Voltage:
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
Device Access
number time
SRAM prefix Blank: 5V CMOS
3: 3.3V CMOS
B: 48-ball FBGA 7x11 mm
5/ 23/ 02; v.1.8
Alliance Semiconductor
P. 12 of 12
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