A8653_技术文档

A8652, A8653

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

FEATURES AND BENEFITS

DESCRIPTION

• Automotive AEC-Q100 qualified

• Cable and wiring drop compensation

The A8652/53 is a high output current synchronous buck

regulator that provides tight load regulation over a wiring

harnesswithouttheneedforremotesenselines.Thisremoteload

regulation is achieved with an integrated open-loop correction

scheme that, given a known wiring harness resistance, adjusts

the output voltage based on the measured load current and a

user-programmable gain, achieving ±2% accuracy at 500 mV

of correction. The Remote Load Regulation control includes a

115% regulated voltage clamp in conjunction with a dynamic

overvoltage protection, with OVPthreshold changing with the

correctionvoltage.TheA8652/53includesauser-configurable

load-sidecurrentlimittofoldbacktheoutputvoltageduringan

outputovercurrentcondition.TheA8652/53regulatesnominal

input voltages from 4 to 36 V and remains operational when

• Dynamic voltage correction with controller

• Integrated high-side and low-side switching MOSFETs

• Programmable load-side current limit

• Maximized duty cycle for low dropout operation

• Operating input voltage range: 4 V to 36 V

• UVLO STOP threshold is at 2.6 V_TYP

• Withstands surge voltages up to 40 V

• Continuous loading: 2.6 A for A8653; 1 A for A8652

• Adjustable switching frequency (f_SW): 100 kHz to

2.2 MHz

• Synchronization to external clock: 100 kHz to 2.2 MHz

• Frequency dithering for lower EMI signature

• External adjustable compensation network

• Stable with ceramic output capacitors

V

_INdrops as low as 2.6 V. When the input voltage approaches

the output voltage, the duty cycle is maximized to maintain

the output voltage.

Continued on next page...

The A8652/53 features include externally set soft-start time,

PACKAGES:

external compensation network, an EN input to enable V_OUT

a SYNC/FSETinput to synchronize or set the PWM switching

,

16-Pin eTSSOP (suffix LP) with exposed thermal pad

Continued on next page...

APPLICATIONS

• Automotive USB Power Ports

• Rear Seat Entertainment

• Navigation Systems

• Motorcycle Clusters

Not to scale

V_IN

BOOT

SW

VIN

C_IN

2 × 4.7 µF

C_BOOT

100 nF

L_O

GND

V_OUT

R_SEN

R_WIRE/2

V_LOAD

C_O

C_LOAD

R_GADJ

EN

R_WIRE/2

GADJ

ISEN+

SYNC/FSET

A8652/3

C_F

(optional)

R_F

(optional)

R_FSET

ISEN-

IADJ

SS

R_IADJ

C_SS

22 nF

COMP

FB

R_FB1

24.9 kΩ

R_PU

10 kΩ

R_Z

C_Z

C_P

POK

R_FB2

4.75 kΩ

Typical Application Diagram 1

A8652/53-DS, Rev.2

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

FEATURES AND BENEFITS (continued)

• Pre-bias startup compatible

• Power OK (POK) output

• Dynamic overvoltage protection, pulse-by-pulse current limit,

hiccup mode short-circuit, and thermal protections

• Open-circuit and adjacent pin short-circuit tolerant

• Short-to-ground tolerant at every pin

• USB3 charging capability: 2.6 A (A8653)

• USB2 capability: 1 A (A8652)

DESCRIPTION (continued)

frequency, and a Power OK output to indicate when V_OUTis within

regulationandthereisnoload-sidecurrentlimitcondition.Protection

features include V_INundervoltage lockout, pulse-by-pulse current

limit, hiccup mode short-circuit protection, dynamic overvoltage

protection, and thermal shutdown. The A8652/53 provides open-

circuited, adjacent pin short-circuit, and short-to-ground protection

at every pin to satisfy the most demanding automotive and non-

automotive applications.

TheA8652/53 device is available in a 16-pin eTSSOPpackage with

exposed pads for enhanced thermal dissipation. It is lead (Pb) free,

with 100% matte-tin lead frame plating. The maximum junction

temperature (T_J(max)) is 150ºC.

V_IN

BOOT

SW

VIN

C_IN

2 × 4.7 µF

C_BOOT

100 nF

GND

R_SEN

20 mΩ

R_WIRE/2

62.5 mΩ

L_O10 µH

V_OUT

V_LOAD

C_O

2 × 22 µF

C_LOAD

100 µF

R_IADJ

20 kΩ

R_WIRE/2

62.5 mΩ

EN

IADJ

SYNC/FSET

ISEN+

A8653

R_FSET

52.3 kΩ

C_F

(optional)

R_F

(optional)

ISEN-

GADJ

SS

R_GE

C_SS

22 nF

V_G

R_GADJ

20 kΩ

5 V

COMP

FB

R_FB1

24.9 kΩ

R_PU

10 kΩ

R_Z

C_Z

C_P

POK

R_FB2

4.75 kΩ

Typical Application Diagram 2 with Dynamic Voltage Correction Control at Pin GADJ

Selection Guide

Part Number

Packing

Package

A8652KLPTR-T

A8653KLPTR-T

4.4 mm × 5 mm, 1.2 mm nominal height

16-pin eTSSOP with exposed thermal pad

4000 pieces per 13-inch reel

Allegro MicroSystems, LLC

115 Northeast Cutoff

2

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

SPECIFICATIONS

Absolute Maximum Ratings¹

Characteristic

Symbol

Notes

Rating

–0.3 to 40

Unit

V

VIN, EN, SS

Continuous

_IN≤ 36 V, t < 50 ns

–0.3 to V_IN+ 0.3

–1 to V_IN+ 2

V_SW– 0.3 to

V

SW to GND ²

V_SW

V

Continuous

V

_SW+ 5.5

_SW– 0.3 to

_SW+ 7

BOOT Pin Above SW Pin

V_BOOT

V

< 1 ms

V

ISEN+ and ISEN– Pins

–0.3 to 6.5

–0.3 to 0.3

–0.3 to 5.5

150

V

ISEN+ to ISEN– Differential Voltage

All other pins

V

Maximum Junction Temperature

Storage Temperature Range

T_J(max)

T_stg

ºC

–55 to 150

¹Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of

the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability

²SW has internal clamp diodes to GND and VIN. Applications that forward bias these diodes should take care not to exceed the IC package power dissipation limits.

Thermal Characteristics

Characteristic

Symbol

Test Conditions³

Value

Unit

Package Thermal Resistance

R_θJA

LP Package, 4-layer PCB based on JEDEC standard

34

ºC/W

³Additional thermal information available on the Allegro website.

Allegro MicroSystems, LLC

115 Northeast Cutoff

3

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

PINOUT DIAGRAM AND TERMINAL LIST TABLE

16 BOOT

15 SW

EN

VIN

1

2

3

4

5

6

7

8

14 PGND

13 PGND

12 ISEN+

11 ISEN–

10 POK

SS

GADJ

FB

PAD

IADJ

SGND

COMP

9

SYNC/FSET

Package LP, 16-Pin eTSSOP Pinout Diagram

Terminal List Table

Symbol

Number

Function

Enable input. This pin is used to turn the converter on or off: set this pin high to turn the converter on or set this pin low to

turn the converter off. May be connected to VIN.

EN

1

Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. A high quality ceramic

capacitor should be placed very close to this pin.

VIN

SS

2

3

Soft-Start pin. Connect a capacitor, C_SS, from this pin to GND to set the soft-start time. This capacitor also determines

the hiccup period during overcurrent.

This pin is used to set the gain of the differential current sense amplifier with ISEN+/ISEN– pins. A resistor from this pin

to GND set the amplifier gain. Together with load sense resistor, it sets the desired voltage correction at the specified

load condition. Grounding GADJ disables Remote Load Regulation function.

GADJ

FB

4

5

Feedback (negative) input to the error amplifier. Connect a resistor divider from the converter output node (V_OUT) to this

pin to program the output voltage.

Active current limit adjust pin. A resistor from this pin to GND sets the current limit. When the load current exceeds this

limit, the output voltage will decrease at the predefined slope.

IADJ

SGND

6

7

Signal (quiet) GND.

Output of the error amplifier and compensation node for the control loop. Connect a series RC network from this pin to

GND for loop compensation.

COMP

8

SYNC/FSET

POK

9

Frequency setting and synchronization pin. A resistor, R_FSET, from this pin to GND sets the PWM switching frequency.

Power OK output signal. This pin is an open-drain output that transitions from low impedance to high impedance when

the output is within the final regulation voltage and no load side current limit exists.

10

Negative current-sensing pin to the internal current sense amplifier, connected to the load side of the external current

sensing resistor.

ISEN–

11

Positive current-sensing pin to the internal current sense amplifier, connected to the inductor side of the external current

sensing resistor.

ISEN+

PGND

SW

12

13, 14

115

16

Power GND.

The source of the high-side N-channel MOSFET. The output inductor (L_O) should be connected to this pin. L_Oshould be

placed as close as possible to this pin and connected with relatively wide traces.

BOOT

PAD

High-side gate drive boost input. Connect a 100 nF ceramic capacitor from BOOT to SW.

Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground

plane(s) of the PCB with at least 6 vias, directly in the pad.

–

Allegro MicroSystems, LLC

115 Northeast Cutoff

4

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

VIN

BOOT REG

VIN

VREF

Regulator

VREG

BOOT

UVLO

Current Sense

Amp

EN

Isen

TSD

OCP

500 nA

EN

OVP

Protection & Fault

SYNC/FSET

FB

OSC

Adj

SW

5 µs

CLK

80 mV

80 mΩ

55 mΩ

PWM

Control

Logic

PWM

COMP

VREG

Error Amp

PGND

Σ

COMP

Slope

Comp

Ramp

Offset

5 µA

20 µA

HICCUP

LOGIC

400 mV

2 kΩ

FAULT

SS

Sense

Amp

ISEN+

ISEN–

REF_ADJ

VREF

800 mV

POK

Adj

920 mV

UV

OV

GADJ

IADJ

SGND

Functional Block Diagram

Allegro MicroSystems, LLC

115 Northeast Cutoff

5

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

ELECTRICAL CHARACTERISTICS: Valid at 4 V ≤ V_IN≤ 36 V; T_A= 25ºC; • indicates speciﬁcations guaranteed

–40°C ≤ T_A= T_J≤ 150°C (unless noted otherwise).

Characteristics

INPUT VOLTAGE SPECIFICATIONS

Operating Input Voltage Range ²

UVLO Start Threshold

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

V_IN

●

4

–

36

3.7

2.9

–

V

V_UVLO(START)V_INrising

V_UVLO(STOP)V_INfalling

V_UVLO(HYS)

3.4

2.6

800

UVLO Stop Threshold

V

UVLO Hysteresis

mV

INPUT CURRENTS

Input Quiescent Current ¹

I_Q

V_EN= 5 V, V_FB= 1 V, no PWM switching

–

3

1

6.5

240

900

mA

µA

V_IN= 12 V, V_EN≤ 0.4 V, –40°C < T_A= T_J<

85°C

Input Sleep Supply Current ¹

VOLTAGE REGULATION

Feedback Voltage Accuracy ³

I_QSLEEP

V

_IN= 12 V, V_EN≤ 0.4 V, T_A= T_J= 125°C

40

V_FB= V_COMP, V_GADJ= 0 V, –40°C < T_A= T_J<

792

788

808

800

825

808

812

842

mV

125°C

V_FB

V

_FB= V_COMP, V_GADJ= 0 V

●

Feedback Voltage Accuracy with Cable

Compensation ³

V_FB= V_COMP, V_ISEN+– V_ISEN–= 25 mV,

V_OUT= 5 V, R_GADJ= 20 kΩ, R_IADJ= 20 kΩ

V_FB(ACC)

V_FB= V_COMP, V_ISEN+– V_ISEN–= 55 mV,

Error Amp Clamp Voltage ³

V_FB(CLAMP)

V_OUT

900

920

940

mV

V

_OUT=5 V, R_GADJ= 7.5 kΩ, R_IADJ= 20 kΩ

Output Voltage Setting Range ³

3.3

4.9

–

5.75

V

V_IN= 5.7 V, I_O= 2.6 A, f_SW= 500 kHz

●

–

A8653

A8652

V_IN= 7.3 V, I_O= 2.6 A, f_SW= 2 MHz

V_IN= 5.5 V, I_O= 1 A, f_SW= 500 kHz

V_IN= 6.8 V, I_O= 1 A, f_SW= 2 MHz

Output Dropout Voltage ³

V_O(PWM)

ERROR AMPLIFIER

Feedback Input Bias Current ¹

Open-Loop Voltage Gain

I_FB

–100

–

–8

–

nA

dB

A_VOL

V_COMP= 1.2 V

400 mV < V_FB

65

550

275

–

750

375

±75

950

475

–

Transconductance

gm_EA

I_EA

µA/V

µA

0 V < V_FB< 400 mV

V_COMP= 1.2 V

Output Current

INTERNAL MOSFET PARAMETERS

High-Side MOSFET On-Resistance ³

SW Node Rising Slew Rate

SW Leakage ¹

R_DSON(HS)

dV/dt

T_A= 25°C, I_DS= 100 mA

–

80

0.75

0

–

mΩ

V/ns

µA

12 V < V_IN< 16 V

I_SW(LEAK)

R_DSON(LS)

V_EN≤ 0.4 V, V_SW= 5 V, V_IN= 12 V, T_J= 25°C

T_A= 25°C, I_DS= 100 mA

–10

–

10

–

Low-Side MOSFET On-Resistance ³

55

mΩ

Continued on the next page…

Allegro MicroSystems, LLC

115 Northeast Cutoff

6

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

ELECTRICAL CHARACTERISTICS (continued): Valid at 4 V ≤ V_IN≤ 36 V; T_A= 25ºC; • indicates speciﬁcations guar-

anteed –40°C ≤ T_A= T_J≤ 150°C (unless noted otherwise).

Characteristics

OSCILLATOR

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

R_FSET= 261 kΩ

–

375

–

100

415

2000

±13

95

–

457

–

kHz

%

PWM Switching Frequency

f_SW

R

_FSET= 61.9 kΩ

_FSET= 10.5 kΩ

PWM Frequency Dithering

f_DITHER

t_ON(MIN)

t_OFF(MIN)

No dithering with FSET synchronization

V_IN= 12 V, I_OUT= 1 A

–

Minimum Controllable On-Time

Minimum Switch Off-Time

–

135

ns

V_IN= 12 V, I_OUT= 1 A

–

100

ns

FSET SYNCHRONIZATION TIMING

Synchronization Frequency Range

Synchronization Input Off-Time

Synchronization Input Rise Time³

Synchronization Input Fall Time³

Synchronization Rising Threshold

Synchronization Falling Threshold

CURRENT LOOP

f_{SW_MULT}

t_{SYNC_OFF}

t_r(SYNC)

100

0.2

–

2200

1.3

15

kHz

µs

ns

V

10

–

t_f(SYNC)

–

15

V_SYNC(HI)

V_SYNC(LO)

V_SYNCrising

V_SYNCfalling

–

2

0.5

–

0.7

V

A8653

A8652

A8653

A8652

A8653

A8652

A8653

A8652

●

3.3

1.5

2.4

0.9

2.5

1

4

1.8

3.2

1

4.62

2.1

4

A

I_{PK_LIM(MINON)}t_ON= t_ON(MIN)

Peak Inductor (Pulse-by-Pulse) Current

Limit

A

I_{PK_LIM(MINOFF)}t_ON= 1/f_SW– t_OFF(MIN), No Sync

1.5

3.3

1.4

–

A

3

A

R_IADJ= 20 kΩ, R_SEN= 20 mΩ,

V_OUT= 5 V

Load-Side Current Limit

I_{OUT_LIM}

1.2

6.3

3.2

0.056

0.24

1.3

0.035

0.15

0.8

A

–

A/V

A/µs

COMP to SW Current Gain

gm_POWER

–

R_FSET= 261 kΩ, 100 kHz

–

R_FSET= 61.9 kΩ, 415 kHz

R_FSET= 10.5 kΩ, 2 MHz

R_FSET= 261 kΩ, 100 kHz

R_FSET= 61.9 kΩ, 415 kHz

R_FSET= 10.5 kΩ, 2 MHz

A8653

A8652

0.09

–

0.43

–

Slope Compensation

S_E

–

0.07

–

0.23

–

Continued on the next page…

Allegro MicroSystems, LLC

115 Northeast Cutoff

7

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

ELECTRICAL CHARACTERISTICS (continued): Valid at 4 V ≤ V_IN≤ 36 V; T_A= 25ºC; • indicates speciﬁcations guar-

anteed –40°C ≤ T_A= T_J≤ 150°C (unless noted otherwise).

Characteristics

SOFT-START

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

SS FAULT/HICCUP Reset Voltage

SS Maximum Charge Voltage

SS Startup (Source) Current ¹

SS Hiccup (Sink) Current ¹

SS Pull-Down Resistance

V_SS(RST)

V_SS(MAX)

I_SS(SU)

V_SSfalling due to R_SS(FLT)

–

200

3.3

275

–

mV

V

HICCUP = FAULT = 0

HICCUP = 1

–30

1

–20

2.2

–10

5

µA

kΩ

–

I_SS(HIC)

R_SS(FLT)

FAULT = 1 or EN = 0

0 V < V_FB< 200 mV

200 mV < V_FB< 400 mV

400 mV < V_FB

–

2

–

f_SW/4

f_SW/2

f_SW

–

SS Switching Frequency

f_SS

–

HICCUP MODE

Hiccup OCP Enable Threshold

Hiccup, OCP Count

V_HIC(EN)

OCP_LIM

V_SSrising

–

2.3

240

64

7

–

V

V_SS> 2.3 V, OCP pulses

counts

Hiccup, BOOT Shorted Count

Hiccup, BOOT Open Count

POWER OK (POK) OUTPUT

POK Output Voltage

BOOT_UV

BOOT_OPEN

V_POK

I_POK= 4 mA

V_POK= 5 V

V_FBfalling

–

0.4

5

V

POK Leakage ¹

I_POK(LEAK)

V_POK(UV)

●

µA

mV

POK UV Threshold

715

–

740

10

760

–

POK UV Hysteresis

V_POK(UV,HYS)

V_FBrising, V_GADJ= 0 V

840

880

920

V

_FBrising, V_ISEN+– V_ISEN–= 25 mV,

865

–

905

1

950

–

mV

V

POK OV Threshold

POK OV Hysteresis

ISEN+ OV Threshold

V_POK(OV)

V_POK(OV,HYS)

V_ISEN(OV)

V_OUT= 5 V, R_GADJ= 20 kΩ, R_IADJ= 20 kΩ

V_FBrising, V_ISEN+– V_ISEN–= 55 mV,

V_OUT= 5 V, R_GADJ= 7.5 kΩ, R_IADJ= 20 kΩ

–

10

–

6

mV

V

I_SEN+rising, V_GADJ= 0 V

5.4

5.65

I_SEN+rising, V_ISEN+– V_ISEN–= 25 mV,

5.6

5.8

6.1

V

V_OUT= 5 V, R_GADJ= 20 kΩ, R_IADJ= 20 kΩ

I

_SEN+rising, V_ISEN+– V_ISEN–= 55 mV,

–

6.45

60

7

–

V

V_OUT= 5 V, R_GADJ= 7.5 kΩ, R_IADJ= 20 kΩ

ISEN+ OV Hysteresis

POK Delay

V_ISEN(OV,HYS)

t_d(POK)

mV

PWM

cycles

V_FBrising only

THERMAL PROTECTION

TSD Rising Threshold

TSD Hysteresis ³

PWM stops immediately and COMP is pulled

low and SS is reset

TSD

155

–

170

20

185

–

ºC

TSD_HYS

Continued on the next page…

Allegro MicroSystems, LLC

115 Northeast Cutoff

8

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

ELECTRICAL CHARACTERISTICS (continued): Valid at 4 V ≤ V_IN≤ 36 V; T_A= 25ºC; • indicates speciﬁcations guar-

anteed –40°C ≤ T_A= T_J≤ 150°C (unless noted otherwise).

Characteristics

EN INPUT THRESHOLDS

EN High Threshold

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

V_EN(H)

V_EN(L)

EN rising

EN falling

–

1.41

1.36

2

–

V

EN Low Threshold

0.7

PWM

cycles

EN Delay

t_d(EN)

EN transitioning low, V_OUT< 25%

–

60

–

EN Input Bias Current ¹

I_{EN_BIAS}

EN = 5 V

500

nA

¹For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin or node.

²Thermally limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow.

³Ensured by design and characterization, not production tested.

Allegro MicroSystems, LLC

115 Northeast Cutoff

9

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

TYPICAL PERFORMANCE CHARACTERISTICS

815

810

805

800

795

790

785

4.05

4.00

3.95

3.90

3.85

3.80

3.75

3.70

0

125

175

0

25

75

50

Temperature (ºC)

100

125

150

175

25

75

Temperature (ºC)

100

150

-50

-25

-50

-25

50

Pulse-by-Pulse Current Limit at t_ON(MIN)(I_{PK_LIM(MINON)}

)

Reference Voltage versus Temperature

versus Temperature

3.50

1.6

EN Rising Threshold

1.5

EN Falling Threshold

3.25

3.00

2.75

2.50

1.4

1.3

1.2

1.1

1.0

0.9

START, UVLOSTART

STOP, UVLOSTART

0

125

175

0

125

175

25

75

Temperature (ºC)

100

150

25

75

Temperature (ºC)

100

150

-50

-25

50

-50

-25

50

VIN UVLO START and STOP Thresholds versus

Temperature

EN Rising and Falling Thresholds versus Temperature

8.3

8.2

8.1

8.0

7.9

7.8

7.7

7.6

7.5

7.4

7.3

7.2

925

900

875

850

825

800

775

750

725

700

POK Overvoltage

POK Undervoltage

0

125

175

0

125

175

25

75

Temperature (ºC)

100

150

25

75

Temperature (ºC)

100

150

-50

-25

50

-50

-25

50

POK Overvoltage and Undervoltage Thresholds at FB

versus Temperature (POK OV test with V_GADJ= 0 V)

POK Delay Time versus Temperature

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Wide Input Voltage, Synchronous USB Buck Regulator

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A8652,

A8653

6.00

5.95

5.90

5.85

5.80

2.5

5.5

5.0

4.5

4.0

3.5

3.0

5.75

5.70

5.65

5.60

5.55

5.50

0

125

175

0

125

175

25

75

Temperature (ºC)

100

150

25

75

Temperature (ºC)

100

150

-50

-25

50

-50

-25

50

ISEN+ Overvoltage Thresholds versus Temperature

(test with V_GADJ= 0 V)

Quiescent Current I_Qversus Temperature

5.00

4.50

4.00

3.50

3.00

2.50

2.00

1.50

1.00

96

94

92

90

88

86

84

82

80

78

V_IN= 8 V

V_IN= 12 V

V_IN= 16 V

V_OUT

0.50

V_LOAD

0

0.5

1.0

1.5

2.0

2.5

3.0

0.00

Load (A)

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

V_IN(V)

Efﬁciency versus Output Current

Low V_INDropout Operation at 5 Ω Load

(Typical Design A in Table 3)

5.2 V

5.1 V

5.0 V

4.9 V

V_OUT

5.1 V

5.0 V

V_LOAD

4.9 V

25 mA/µs

I_OUT

1 A/div

I_OUT

C4

C2

100 µs/div

Transient Response 0 to 1 A Load Step

(Typical Design A in Table 3)

Transient Response 1 to 2 A Load Step

(Typical Design A in Table 3)

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FUNCTIONAL DESCRIPTION

over the operating temperature range. Connecting a resistor

from the FSET/SYNC pin to GND, as shown in the Applications

Overview

The A8652/53 is a synchronous PWM buck regulator that inte-

grates low R_DS(on)high-side and low-side N-channel MOSFETs.

It is designed to remain operational when input voltage falls as

low as 2.6 V. The A8652/53 employs peak current mode control

to provide superior line and load regulation, pulse-by-pulse cur-

rent limit, fast transient response and simple compensation. The

A8652/53 incorporates a Cable Drop Compensation (Remote

Load Regulation) function in its current mode control architec-

ture to adjust the output voltage according to the load current,

offsetting the voltage drop introduced by the wiring harness. The

reference voltage in the feedback loop is adjusted relative to the

voltage across the sensing resistor at the load side. When the

load current increases, it causes the reference voltage at the error

amplifier to increase and the output voltage to follow. The gain of

the voltage correction is configurable using the GADJ and IADJ

pins. Such features provide flexibility in setting the amount of

output voltage correction and the load current limit.

Schematic, sets the switching frequency. An FSET resistor with

±1% tolerance is recommended. A graph of switching frequency

versus FSET resistor value is shown in the Component Selection

section of this datasheet. The A8652/53 will suspend operation if

the FSET pin is shorted to GND or left open.

FSET/SYNC pin also can be used as a synchronization input that

accepts an external clock to switch the A8652/53 from 100 kHz

to 2.2 MHz and scales the slope compensation according to the

synchronization frequency. When being used as a synchroniza-

tion input, the applied clock pulses must satisfy the pulse width,

duty cycle, and rise/fall time requirements shown in the Electrical

Characteristics shown in this datasheet.

Remote Load Regulation Control and

Transconductance Error Amplifier

The Remote Load Regulation control in the A8652/53 provides

improved load regulation at the remote load by increasing the

voltage reference of the error amplifier to correct for the voltage

drop introduced by wiring harness to the load. The amount of

voltage correction is user-programmable with external configu-

ration resistors, allowing the A8652/53 to be applied to wiring

harnesses that have up to 750 mV IR drops at full load. The

Remote Load Regulation controller has a variety of protection

features, including a load-side current limit, a maximum regula-

tion voltage, and protection in the event of open pin or shorted

pin conditions.

The features of the A8652/53 include Remote Load Regula-

tion, an internal precision reference, an adjustable switching

frequency, a transconductance error amplifier, an enable input,

integrated top and bottom switching MOSFETs, adjustable soft-

start time, pre-bias startup, and a Power OK output. Protection

features of A8652/53 include V_INundervoltage lockout, pulse-by-

pulse overcurrent protection, BOOT overvoltage and undervolt-

age protection, hiccup mode short-circuit protection, dynamic

overvoltage protection, and thermal shutdown. In addition, the

A8652/53 provides open-circuit, adjacent pin short-circuit, and

pin-to-ground short-circuit protection.

The Remote Load Regulation voltage correction and protection

features interface with the error amplifier, which is a four-termi-

nal input device with three positive inputs and one negative input,

as shown in Figure 1. The negative input is simply connected to

the FB pin and is used to sense the feedback voltage for regula-

tion. The error amplifier performs an “analog OR” selection

between its positive inputs, operating according to the positive

input with the lowest potential. The three positive inputs are used

for soft-start, steady-state regulation, and the 15% maximum

regulation voltage. The error amplifier regulates to the soft-start

pin voltage minus 400 mV during startup, the sum of A8652/53

internal reference (VREF) and the Remote Load Regulation

correction (REF_ADJ) during normal operation, or the 920 mV

maximum.

Reference Voltage

The A8652/53 incorporates an internal precision reference that

allows output voltages as low as 0.8 V. The accuracy of the

internal reference is ±1% from –40°C to 125°C and ±1.5% across

from –40°C to 150°C when the Remote Load Regulation is dis-

abled. The output voltage of the regulator is programmed with a

resistor divider between V_OUTand the FB pin of the A8652/53.

Oscillator/Switching Frequency and

Synchronization

The PWM switching frequency of the A8652/53 is adjustable

from 100 kHz to 2.2 MHz and has an accuracy of about ±10%

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The gain of the current sense to the REF_ADJ (G_ADJ) signal is set

by the ratio of resistance to GND on the GADJ pin and the IADJ

400 mV

SS

pin in conjunction with R_sen

:

REF_ADJ

I_OUT

R_sen× R_IADJ

R_GADJ

(1)

G

=

ADJ

Error Amp

COMP

920 mV

This allows the user to calibrate the voltage correction to the IR

drop of the wiring harness, as shown in Figure 3. This calibra-

tion results in improved load regulation at the end of the wiring

harness.

REF_ADJ

VREF

Larger

800 mV

R_sen× R_IADJ/ R_GADJ

VOUT

FB

5.5 V

Figure 1: A8652/53 Error Ampliﬁer

5.0 V

Smaller

920 mV

R_sen× R_IADJ/ R_GADJ

Current

Sense

Amp

VREF

800 mV

ISEN+

ISEN-

GADJ

Error

Amp

Σ

IOUT

REF_ADJ

Gain Adj

0 A

1.0 A

R_GADJ

Figure 3: Voltage Correction Gain Adjustment

To configure the voltage correction gain, the load-side current

limit (I_{OUT_LIM}) must first be set by the following equation (also

referring to Table 1):

IADJ

R_IADJ

1200

R_IADJ

=

(2)

I_{OUT_LIM}

× Rsen

Figure 2: Remote Load Regulation Control

The voltage correction gain is based on R_WIRE, which is the sum

of the wiring harness supply and return resistive paths as detailed

in the typical application diagram. Given the gain of the FB pin

voltage divider (A_FB= V_OUT/V_FB), R_WIREand R_IADJthe desired

voltage correction gain is set by the following equation (referring

to Figure 4):

The amount of the voltage correction for the wiring harness is

generated by the Remote Load Regulation control circuit and

fed to the error amplifier via the REF_ADJ signal, as shown in

Figures 1 and 2. The Remote Load Regulation controller gener-

ates REF_ADJ according to the load current sensed by ISEN+

and ISEN– and the gain set by the configuration resistors. The

current sense resistor (R_sen) is connected on the load side between

the regulator output capacitor and the load terminal and can have

a value between 20 and 50 mΩ.

R_sen

R_WIRE

(3)

R_GADJ

=

× A_FB× R_IADJ

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For example, for a 5 V application with a 20 mΩ current sense

resistor and a 3 A load side current limit the IADJ configuration

resistor would be 20 kΩ. To correct for a 125 mV wire harness

drop at 1 A (R_WIRE=125 mΩ) given R_IADJ= 20 kΩ, the GADJ

configuration resistor should be 20 kΩ.

800

700

600

500

400

300

200

100

0

R_sen= 50 mΩ, R_IADJ= 20 kΩ (1.2 A)

R_sen= 50 mΩ, R_IADJ= 23.7 kΩ (1.0 A)

R_sen= 50 mΩ, R_IADJ= 30.1 kΩ (0.8 A)

Table 1: R_IADJResistor Selection vs. I_{OUT_LIM}

R_IADJ(kΩ)

15.8

16.9

17.4

17.8

18.2

18.7

19.1

19.6

20.0

20.5

21.0

21.5

22.1

22.6

23.2

23.7

24.3

26.7

30.1

34.8

40.2

R_sen= 20 mΩ

3.80

R_sen= 50 mΩ

1.52

3.55

1.42

3.45

1.38

3.37

1.35

3.30

1.32

0

20

30

R_GADJ(kΩ)

40

50

60

10

3.21

1.28

300

250

200

150

3.14

1.26

R_sen= 20 mΩ, R_IADJ= 20 kΩ (3.0 A)

3.06

1.22

R_sen= 20 mΩ, R_IADJ= 23.7 kΩ (2.5 A)

R_sen= 20 mΩ, R_IADJ= 30.1 kΩ (2.0 A)

3.00

1.20

2.93

1.17

2.86

1.14

2.79

1.12

2.71

1.09

2.65

1.06

100

50

0

2.59

1.03

2.53

1.01

2.47

0.99

2.25

0.90

0

20

30

R_GADJ(kΩ)

40

50

60

10

1.99

0.80

1.72

0.69

Figure 4: R_GADJSelection vs R_WIREfor Given R_sen, R_IADJ

1.49

0.60

This can be very useful, for instance when one “universal”

design is created for multiple platforms, where the expected wir-

ing resistance can vary widely. The design can use this method

in conjunction with the system controller such that the degree of

voltage correction can be set via software.

As will be discussed in further detail below, altering the GADJ

resistance with an external voltage proportionally adjusts the

voltage correction gain (Method 1, refer to Typical Application

Diagram 2). On the other hand, altering the IADJ resistance with

an external voltage proportionally adjusts the load-side current

limit, and inversely proportionally adjusts the voltage correction

gain (Method 2).

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The minimum and maximum voltage correction can be adjusted

with the ratio of R_GADJand R_{G_E}for a given controlling voltage

1.0 V

(V_G) range.

A8652/53

Similarly, as shown in Figure 7, Method 2 can inversely pro-

portionally adjust the voltage correction gain for a fixed GADJ

resistance, at the same time proportionally adjusts the load side

current limit (I_{OUT_LIM}) by applying the control voltage (V_I) to

ig

the IADJ pin. The equivalent resistance RIADJ at pin IADJ is:

1

GADJ

R_{I_eqv}

=

1

R_IADJ

V_I– 1

R_{I_E}

(6)

V_G

–

R_{G_E}

(

)

R_GADJ

Thus the voltage correction gain can be kept the same by apply-

ing a separate control voltage to the GADJ pin to keep the GADJ

and IADJ resistor ratio the same if only load-side current limit

needs to be adjusted.

Figure 5: Dynamic Voltage Correction Adjustment

at Pin GADJ

1.0 V

Figure 5 above illustrates how to adjust the amount of voltage

correction by controlling V_G. The equivalent resistance R_{G_eqv}at

pin GADJ with respect to GND now becomes:

A8652/53

1

R_{G_eqv}

=

1

R_GADJ

V_G– 1

R_{G_E}

(4)

–

(

)

ia

The voltage correction gain (G_ADJ) then varies linearly with the

applied V_Gfor given R_GADJand R_{G_E}. Normalizing this gain to

the case with only R_GADJconnecting to pin GADJ results in:

IADJ

V_I

R_{I_E}

R_GADJ

R_{G_E}

R_GADJ

R_{G_E}

–

G_norm= 1 +

(5)

V_G

R_IADJ

G_norm

Figure 7: Simultaneous Voltage Correction and Load-

Side Current Limit Adjustment at Pin IADJ

1 + R_GADJ/ R_{G_E}

If a fixed load-side current limit is desired it is simpler to use

GADJ pin to dynamically control the amount of voltage cor-

rection because of linear control and only altering the voltage

correction gain.

1

The GADJ and IADJ pins are designed for a resistance range

of 10 to 34 kΩ, and therefore the controlling voltage V_Gand V_I

must be limited as follows:

0

V_G(V)

1

ꢀ

10ꢀkΩꢀ<ꢀR_{G_eqv}ꢀ<ꢀ34ꢀkΩꢀ

ꢀ

(7)

0

and

Figure 6: Normalized Gain G_normvs. V_G

ꢀ

10ꢀkΩꢀ<ꢀR_{I_eqv}ꢀ<ꢀ34ꢀkΩꢀ

ꢀ

(8)

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In addition to the voltage correction circuitry, Figure 2 also

details the load-side current limit (I_{OUT_LIM}), which is config-

ured independently by the resistance to GND on the IADJ pin.

As shown by Figure 8 and 9, when the load current exceeds

I_{OUT_LIM}, POK is pulled low to flag the condition, and the output

voltage is decreased at the same rate as the voltage correction (set

by Rsen, R_GADJand R_IADJ) to protect against unstable behavior.

Figure 8 and 9 also details the operation of peak inductor current

limit (I_{PK_LIM}), which monitors the inductor current and will

enter into hiccup mode after 240 counts of exceeding I_{PK_LIM}for

robust protection and against the output voltage shorted to GND.

12 V

VIN

2.6 V – UVLO_fall

5.75 V

5.5 V

VOUT

5.0 V

I_{PK_LIM}

4.0 A

2.5 A

I_{OUT_LIM}

2.0 A

1 A

1.5 A

IOUT

0

SS

12 V

VIN

2.6 V – UVLO_fall

5.75 V

POK

VOUT

t

5.25 V

5.0 V

I_{PK_LIM}

4.0 A

Figure 9: Excessive Voltage Correction Gain

I_{OUT_LIM}

3.0 A

The Remote Load Regulation controller is also robust against

pin faults, such as adjacent pins shorting, shorting pins to GND,

or pin open faults. When a pin fault is detected, either the IADJ

or GADJ pin, the A8652/53 will default to the 800 mV refer-

ence, not applying any voltage correction to the output voltage.

Given this, the GADJ pin can be connected to GND to disable the

Remote Load Regulation function.

1 A

IOUT

0

SS

POK

t

Compensation Components

To stabilize the regulator, a series RC compensation network

(R_Zand C_Z) must be connected from the error amplifier output

(COMP pin) to GND as shown in the applications schematic. In

most instances, an additional low-value capacitor (C_P) should be

connected in parallel with the R_Z-C_Zcompensation network to

reduce the loop gain at very high frequencies. However, if the C_P

capacitor is too large, the phase margin of the converter may be

reduced. How to calculate R_Z, C_Zand C_Pis covered in the Com-

ponent Selection section of this datasheet. When selecting the

compensation components, the load decoupling capacitance and

the wiring resistance must be taken into consideration.

Figure 8: POK and Load-Side Current Limit Timing

In addition to current protection, the A8652/53 also includes a

115% (5.75 V) regulation voltage limit on the error amplifier.

This protection feature prevents the excessive output voltages

during fault conditions, and is therefore set above the operating

range of the Remote Load Regulation. However, if the voltage

correction gain is too high, the 115% voltage limit will impede

the Remote Load Regulation operation, as shown in Figure 9.

The VOUT waveform shows the operation point of the Remote

Load Regulation controller set by REF_ADJ, but as illustrated,

the 115% voltage regulation limit at the error amplifier clips the

output voltage to 5.75 V.

If a fault occurs or the regulator is disabled, the COMP pin is

pulled to GND via the approximately 1 kΩ internal resistor and

PWM switching is inhibited.

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Slope Compensation

Power MOSFETs

The A8652/53 incorporates internal slope compensation to allow

PWM duty cycles above 50% for a wide range of input/output

voltages, switching frequencies, and inductor values. As shown

in the functional block diagram, the slope compensation signal

is added to the sum of the current sense and PWM Ramp Offset.

The amount of slope compensation is scaled with the switching

frequency when programming the frequency with a resistor or

with an external clock.

The A8652/53 includes an 80 mΩ, high-side N-channel MOS-

FET capable of delivering up to 4 A typical. The A8652/53 also

includes a 55 mΩ, low-side N-channel MOSFET to provide

synchronous rectification.

When the A8652/53 is disabled via the EN input being low or a

Fault condition, the A8652/53 output stage is tri-stated by turning

off both the upper and lower MOSFETs.

The value of the output inductor should be chosen such that slope

compensation rate S_Eis between 0.5× and 1× the falling slope of

the inductor current (S_F).

Pulse-Width Modulation (PWM) Mode

The A8652/53 employs fixed-frequency, peak current mode

control to provide excellent load and line regulation, fast transient

response, and simple compensation.

Current Sense Amplifier

A high-speed comparator and control logic is included in

A8652/53. The inverting input of the PWM comparator is con-

nected to the output of the error amplifier. The non-inverting

input is connected to the sum of the current sense signal, the

slope compensation signal, and a DC PWM Ramp offset voltage

(V_PWM(OFFSET)).

The A8652/53 incorporates a high-bandwidth current sense

amplifier to monitor the current through the top MOSFET. This

current signal is used to regulate the peak current when the top

MOSFET is turned on. The current signal is also used by the

protection circuitry for the pulse-by-pulse current limit (I_{PK_LIM}

and hiccup mode short-circuit protection.

)

At the beginning of each PWM cycle, the CLK signal sets the

PWM flip-flop, the bottom MOSFET is turned off, the top MOS-

FET is turned on, and the inductor current increases. When the

voltage at the non-inverting of PWM comparator rises above the

error amplifier output COMP, the PWM flip-flop is reset and the

top MOSFET is turned off, the bottom MOSFET is turned on and

the inductor current decreases.

Low Dropout Operation and Undervoltage

Lockout

The Undervoltage Lockout behavior is described in the following

Protection Features section.

The A8652/53 is designed to allow operation when input volt-

age drops as low as 2.6 V, which is the UVLO STOP threshold.

When the input voltage falls towards the nominal output voltage,

the high-side switch can remain on for maximum on-time to keep

regulating the output. This is accomplished by decreasing the f_SW

switching frequency. In this way, the dropout from the input to

output voltage is minimized.

The PWM flip-flop is reset-dominant, so the error amplifier may

override the CLK signal in certain situations.

BOOT Regulator

The A8652/53 includes a regulator to charge its boot capacitor.

The voltage across the boot capacitor is typically 5 V. If the boot

capacitor is missing, the A8652/53 will detect a boot overvolt-

age. Similarly, if the boot capacitor is shorted, the A8652/53 will

detect a boot undervoltage. Also, the boot regulator has a current

limit to protect itself during a short-circuit condition.

Sleep Mode with Enable input

The A8652/53 provides a shutdown function via the EN pin.

When this pin is low, the A8652/53 is shut down and the

A8652/53 will enter a “sleep mode” where the internal control

circuits will be shut off and draw less current from VIN. If EN

goes high, the A8652/53 will turn on and provided there are no

fault conditions, soft-start will be initiated and V_OUTwill ramp to

its final voltage in a time set by the soft-start capacitor (C_SS). To

automatically enable the A8652/53, the EN pin may be connected

directly to VIN.

Soft-Start (Startup) and Inrush Current Control

The soft-start function controls the inrush current at startup. The

soft-start pin, SS, is connected to GND via a capacitor. When the

A8652/53 is enabled and all faults are cleared, the soft-start pin

will source the charging current I_SS(SU), and the voltage on the

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Wide Input Voltage, Synchronous USB Buck Regulator

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A8653

soft-start capacitor, C_SS, will ramp upward from 0 V. When the

voltage at the soft-start pin exceeds the Soft-Start COMP Release

Threshold (V_SS(RELEASE), typically 400 mV) the error amplifier

will ramp up its output voltage above the PWM Ramp Offset. At

that instant, the top and bottom MOSFETs will begin switching.

There is a small delay (t_d(SS)) between the moments of EN pin

transitioning high and the soft-start voltage reaching 400mV to

initiate PWM switching.

Pre-Biased Startup

If the output of the buck regulator is pre-biased at certain output

voltage level, the A8652/53 will modify the normal startup

routine to prevent discharging the output capacitors. As described

in the Soft-Start (Startup) and Inrush Current Control section,

the error amplifier usually becomes active when the voltage at

the soft-start pin exceeds 400 mV. If the output is pre-biased, the

voltage at the FB pin will be non-zero. The A8652/53 will not

start switching until the voltage at SS pin rises to approximately

V_FB+ 400 mV. From then on, the error amplifier becomes active,

the voltage at the COMP pin rises, PWM switching starts, and

V_OUTwill ramp upward from the pre-bias level.

Once the A8652/53 begins PWM switching, the error amplifier

will regulate the voltage at the FB pin to the soft-start pin voltage

minus approximately 400 mV. During the active portion of soft-

start, the voltage at the SS pin will rise from 400 mV to 1.2 V

(a difference of 800 mV), the voltage at the FB pin will rise from

0 V to 800 mV, and the regulator output voltage will rise from

0 V to the setpoint determined by the feedback resistor divider.

Power OK (POK) Output

The Power OK (POK) output is an open-drain output, so an

external pull-up resistor must be connected. POK remains high

when the voltage at the FB pin is within regulation and the load-

side current limit I_{out_LIM}is not triggered. The POK output is

pulled low under the conditions below:

During startup, the PWM switching frequency is reduced to 25%

of f_SWwhile V_FBis below 200 mV. If V_FBis above 200 mV but

below 400 mV, the switching frequency is 50% of f_SW. At the

same time, the transconductance of the error amplifier, gm_EA

,

is reduced to 1/2 of nominal value when V_FBis below 400 mV.

When V_FBis above 400 mV, the switching frequency will be

f_SWand the error amplifier gain will be the nominal value. The

reduced switching frequencies and error amplifier gain are neces-

sary to help improve output regulation and stability when V_OUT

is at very low voltage. When V_OUTis very low, the PWM control

loop requires on-time near the minimum controllable on-time and

extra low duty cycles that are not possible at the nominal switch-

ing frequency.

1. V_FB(RISING)< 92.5% of the reference voltage V_REF

2. V_FB(RISING)is larger than the sum of the adjusted reference

voltage (i.e. V_REF+ V_{REF_ADJ}or 920 mV, whichever is

lower) and 80 mV

3. Load current exceeds the load-side current limit I_{out_LIM}

4. EN is low for more than 32 PWM cycles

5. V_INUVLO event occurs

6. Thermal shutdown event occurs

When the voltage at the soft-start pin reaches approximately

1.2 V, the error amplifier will “switch over” and begin regulating

the voltage at the FB pin to the A8652/53 adjusted reference volt-

age. The voltage at the soft-start pin will continue to rise to the

internal LDO regulator output voltage.

Once the load-side current limit is triggered, POK will go low

even if the output voltage has not yet dropped due to the current

limit. If the A8652/53 is running and EN is kept low for more

than 32 PWM cycles, POK will fall low and remain low only as

long as the internal circuitry is able to enhance the open-drain

output device. Once V_INfully collapses, POK will return to the

high-impedance state. Hysteresis is included in POK comparators

to prevent chattering due to the ripple effects on comparators’

input terminals.

If the A8652/53 is disabled or a fault occurs, the internal fault

latch is set and the capacitor at the SS pin is discharged to ground

very quickly through a 2 kΩ pull-down resistor. The A8652/53

will clear the internal fault latch when the voltage at the SS pin

decays to approximately 200 mV. However, if the A8652/53

enters hiccup mode, the capacitor at the SS pin is slowly dis-

charged through a current sink, I_SS(HIC). Therefore, the soft-start

capacitor C_SSnot only controls the startup time but also the time

between soft-start attempts in hiccup mode.

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Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

PROTECTION FEATURES

The A8652/53 was designed to satisfy the most demanding

automotive and nonautomotive applications. In this section, a

description of each protection feature is described and Table 2

summarizes the protections and their operation.

Because of the addition of the slope compensation ramp to the

inductor current, the A8652/53 can deliver more current at lower

duty cycles than at higher duty cycles to activate pulse-by-pulse

overcurrent protection. Also the slope compensation is not a per-

fectly linear function of switching frequency, so the current limit

at lower switching frequency is larger compared with the limit at

higher switching frequency for a given duty cycle.

Undervoltage Lockout Protection (UVLO)

An Undervoltage Lockout (UVLO) comparator in the A8652/53

monitors the voltage at the VIN pin and keeps the regulator dis-

abled if the voltage is below the START threshold (V_UVLO(START)

Figure 10 shows the typical and worst case pulse-by-pulse current

limits versus duty cycles at 2 MHz, 550 kHz, and 100 kHz.

,

V_INrising) or the STOP threshold (V_UVLO(STOP), V_INfalling). The

UVLO comparator incorporates some hysteresis, V_UVLO(HYS), to

help reduce ON/OFF cycling of the regulator due to the resistive

or inductive drops in the VIN path during heavy loading or during

startup.

The exact current the buck regulators can support is heavily

dependent on duty cycle (V_IN, V_OUT), ambient temperature,

thermal resistance of the PCB, airflow, component selection, and

nearby heat sources.

Overcurrent Protection (OCP) and Hiccup

Mode

Pulse-by-Pulse Overcurrent Protection (OCP)

The A8652/53 monitors the current in the upper MOSFET, and

if this current exceeds the pulse-by-pulse overcurrent threshold

(I_{PK_LIM}), then the upper MOSFET is turned off. Normal PWM

operation resumes on the next clock pulse from the oscillator. The

A8652/53 includes leading-edge blanking to prevent falsely trig-

gering the pulse-by-pulse current limit when the upper MOSFET

is turned on.

An OCP counter and hiccup mode circuit protect the buck regula-

tor when the output of the regulator is shorted to ground or when

the load current is too high. When the voltage at the SS pin is

below the Hiccup OCP Threshold, the hiccup mode counter is

disabled. Two conditions must be met for the OCP counter to be

enabled and begin counting:

1. V_SS> V_HIC(EN)(2.3 V) and

4.6

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0

2. V_COMPclamped at its maximum voltage (OCL = 1)

As long as these two conditions are met, the OCP counter

remains enabled and will count pulses from the overcurrent

comparator. If the COMP voltage decreases (OCL = 0) the OCP

counter is cleared. If the OCP counter reaches OCP_LIMcounts

(240), a hiccup latch is set and the COMP pin is quickly pulled

down by a relatively low resistance (1 kΩ).

The hiccup latch also enables a small current sink connected to

the SS pin (I_SS(HIC)). This causes the voltage at the soft start pin

to slowly ramp downward. When the voltage at the soft-start pin

decays to a low-enough level (V_SS(RST), 200 mV_TYP), the hiccup

latch is cleared and the small current sink turned off. At that

instant, the SS pin will begin to source current (I_SS(SU)) and the

voltage at the SS pin will ramp upward. This marks the begin-

ning of a new, normal soft-start cycle as described earlier. When

the voltage at the soft-start pin exceeds the error amp voltage

by approximately 400 mV, the error amp will force the voltage

at the COMP pin to quickly slew upward and PWM switching

will resume. If the short circuit at the regulator’s output remains,

MAX_550 kHz

2.8

TYP_550 kHz

MIN_550 kHz

MAX_100 kHz

TYP_100 kHz

MIN_100 kHz

MAX_2 MHz

TYP_2 MHz

MIN_2 MHZ

2.6

2.4

2.2

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

Duty Cycle (%)

Figure 10: Pulse-by-Pulse Current Limit vs. Duty Cycle

at 100 kHz (long dashed lines), 550 kHz (solid lines) and 2 MHz (short

dashed lines)

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Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

another hiccup cycle will occur. Hiccups will repeat until the

short circuit is removed or the converter is disabled. If the short

circuit is removed, the A8652/53 will soft-start normally and the

output voltage will automatically recover to the desired level.

FB

OV

5 µs

80 mV

Thus Hiccup mode is a very effective protection for the overload

condition. It can avoid false trigger for a short-term overload. On

the other hand, for the extended overload, the average power dis-

sipation during Hiccup operation is very low to keep the control-

ler cool and enhance the reliability.

800 mV

VREF

920 mV

Note that OCP is the only fault that results in Hiccup mode being

ignored while V_SS< 2.3 V.

REF_ADJ

BOOT Capacitor Protection

Figure 11: Dynamic Overvoltage Protection

The A8652/53 monitors the voltage across the BOOT capaci-

tor to detect if the capacitor is missing or short-circuited. If the

BOOT capacitor is missing, the regulator will enter Hiccup mode

after 7 PWM cycles. If the BOOT capacitor is short-circuited, the

regulator will enter Hiccup mode after 64 PWM cycles.

USB buck application), the OVP threshold will be 5.5 V; when

the output voltage reaches the 115% regulation limit, the OVP

threshold will reach the maximum value of 6.25 V.

When the voltage at the FB pin exceeds the overvoltage threshold

(V_POK(OV)), A8652/53 will stop PWM switching, i.e. both high

and side switches will be turned off, and POK will be pulled low.

In most cases, the error amplifier will be able to maintain regula-

tion since the synchronous output stage has excellent sink and

source capability. However the error amplifier and its regulation

voltage clamp are not effective when the FB pin is disconnected

or when the output is shorted to the input supply. When the FB

pin is disconnected from the feedback resistor divider, a tiny

internal current source will force the voltage at the FB pin to rise

above V_POK(OV)and disable the regulator, preventing the load

from being significantly overvoltage. If a higher external volt-

age is accidently shorted to the A8652/53’s output, V_FBwill rise

above the overvoltage threshold, triggering an OVP event and

thus protecting the low-side switch. In either case, if the condi-

tions causing the overvoltage are corrected, the regulator will

automatically recover.

For a BOOT fault, Hiccup mode will operate virtually the same

as described previously for an output short-circuit fault (OCP),

with SS ramping up and down as a timer to initiate repeated

soft-start attempts. BOOT faults are nonlatched condition, so the

A8652/53 will automatically recover when the fault is corrected.

Dynamic Overvoltage Protection (OVP)

In addition to the error amp regulation voltage clamp

(V_EA(CLAMP)) at 115%, the A8652/53 includes a dynamic

overvoltage protection feature where the overvoltage threshold

changes with the correction voltage. As shown in Figure 11

below, the A8652/53 also includes an overvoltage comparator

that monitors the FB pin and the sum of the adjusted reference

voltage (i.e. V_REF+ V_{REF_ADJ}or 920 mV, whichever is lower)

and 80 mV. In this way, the overvoltage threshold will dynami-

cally change with the amount of the correction voltage and the

threshold is always 0.5 V above the output voltage. For example,

OVP threshold is 5.5 V when V_OUT= 5 V at I_OUT= 0 A; the OVP

threshold will be 5.75 V when V_OUT= 5.25 V at I_OUT= 1 A; if

V_OUT= 5.75 V at certain load, the OVP threshold will become

6.25 V. When the Remote Load Regulation function is disabled

due to some reason (e.g., IADJ or GADJ pin fault or general non-

To provide additional protection when the battery is shorted to

the load terminal, a 40 V Schottky diode (D) can be inserted after

sensing resistor R_sento block the high voltage entering into IC,

and a Zener diode is placed at FB pin, as shown in Figure 12. The

test result was shown in Figure 12b when Battery = 36 V was

shorted to V_OUT

.

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Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

R_sen

20 mΩ

R_WIRE/2

62.5 mΩ

L_O10 µH

Thermal Shutdown (TSD)

V_OUT

V_LOAD

The A8652/53 monitors its junction temperature and will stop

PWM switching and pull POK low if it becomes too hot. Also, to

prepare for a restart, the SS and COMP pins will be pulled low

until V_SS< V_SS(RST). TSD is a non-latched fault so the A8652/53

will automatically recover if the junction temperature decreases

by approximately 20°C.

C_O

2 × 22 µF

C_LOAD

100 µF

D

R_WIRE/2

62.5 mΩ

ISEN+

ISEN-

R_FB1

Pin-to-Ground and Pin-to-Pin Short Protec-

tions

FB

R_FB2

5.1 V

The A8652/53 was designed to satisfy the most demanding

automotive and nonautomotive applications. For example, the

A8652/53 was carefully designed “up front” to withstand a short

circuit to ground at each pin without suffering damage.

Figure 12a: Protection Circuitry for

Load Short-to-Battery

FB

In addition, care was taken when defining the A8652/53’s pinouts

to optimize protection against pin-to-pin adjacent short-circuits.

For example, logic pins and high-voltage pins were separated as

much as possible. Inevitably, some low-voltage pins were located

adjacent to high-voltage pins. In these instances, the low-voltage

pins were designed to withstand increased voltages, with clamps

and/or series input resistance, to prevent damage to the A8652/53.

VOUT

POK

Figure 12b: Test Results when Battery = 36 V is

Shorted to V_OUT

Ch1: V_OUT(10 V/div); Ch2: V_FB(2 V/div);

Ch4: V_POK(5 V/div); 50 ms/div

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Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

Table 2: Summary of A8652/53 Fault Modes and Operation

During Fault Count, before Hiccup

Dropout

Foldback

BOOT

Charging

Fault Mode

Fault Cases

V_SS

POK

LATCH RESET

High-Side

Switch

Low-Side

Switch

V_COMP

1. Excessive I_OUT

2. V_OUTShorted

Overcurrent to GND

Clamped to

Hiccup, after 240 achieve I_LIM, and

Positive

CCM

according to

COMP

CCM

according to

COMP

Depends on

Auto,

remove

short

f

_SW/4 or f_SW/2

Not

affected

V_OUTand

No

faults of OCL

pulled low only by

hiccup

based on V_FB

Protection

3. SW Soft Short

To GND

ISEN

CCM

according to

COMP

CCM

according to

COMP

Load-Side

Current Limit

Pulled Low

immediately

Not

affected

Excessive I_OUT

Not affected

No

Auto

Negative

Overcurrent Negative I_OUT

Protection

1. Excessive

Dropout

Foldback

Reset

Depends on

V_OUTand

ISEN

Auto,

remove

short

Hiccup, after 1

fault of LSOC

Pulled low only by

hiccup

Forced off

Immediately

Forced off

Immediately

Not

affected

2. Inductor Short

No

(option

avail

One Shot

Diode

Emulation

Dropout

Foldback

Reset

Depends on

Auto,

remove

short

SW Hard

Short to GND

SW to GND hard

Short

Hiccup at the

end of blankOn

Pulled low only by

hiccup

Forced off

Immediately

Not

affected

V_OUTand

ISEN

able)

Pulled Low

Immediately &

latched until V_SSlatched until V_SS

< V_SS(RST)

Pulled Low

Immediately &

Dropout

Foldback

Reset

Auto,

Cool

Down

Thermal

Shutdown

Forced off

Immediately

Forced off

Immediately

Pulled Low

Immediately

Die is too hot

Off

No

–

< V_SS(RST)

Boot

Capacitor

Greater than

7 V

Dropout

Foldback

Disabled by

Hiccup

CCM

according to

COMP

CCM

according to

COMP

Depends on

BOOT capacitor

Open

Hiccup, after 7

latched faults

Pulled low by

hiccup

Off for rest

of period

V

_OUTand

ISEN

–

Dropout

Foldback

Disabled by

Hiccup

Boot

Capacitor On

Fault

CCM

according to

COMP

CCM

according to

COMP

Depends on

Off only

during

hiccup

Auto,

replace

capacitor

BOOT Capacitor

Open

Hiccup, after 7

latched faults

Pulled low by

hiccup

V

_OUTand

ISEN

No

Boot

Capacitor

Overcurrent

Depends on

BOOT to GND

Short

Pulsed at

minOff

Off until

fault clears

Not affected

V

_OUTand

ISEN

–

Boot

Capacitor

Low Voltage

Depends on

V_OUTand

ISEN

Normal Low V_IN

Operation

Active during

minOff period

On

Boot

Capacitor

Undervoltage

Dropout

Foldback

Reset

Depends on

BOOT Capacitor

Short

Forced Off

Immediately

Active during

minOff period

V_OUTand

ISEN

Low-Side

Switch

Undervoltage

Dropout

Foldback

Reset

Depends on

V_OUTand

ISEN

Forced Off

Immediately

Forced Off

Immediately

Not

affected

Low V_IN

Pulled Low

Immediately &

latched until V_SSlatched until V_SS

< V_SS(RST)

Pulled Low

Immediately &

Dropout

Foldback

Reset

V_REG

Undervoltage

Forced Off

Immediately

Forced Off

Immediately

Pulled Low

Immediately

Off

No

Auto

< V_SS(RST)

Pulled Low

Immediately &

latched until V_SSlatched until V_SS

< V_SS(RST)< V_SS(RST)

Pulled Low

Immediately &

One Shot

Diode

Emulation

Dropout

Foldback

Reset

Depends on

V_OUTand

ISEN

V_IN

Forced Off

Immediately

Low V_IN

Undervoltage

Continued on next page...

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Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

Table 2: Summary of A8652/53 Fault Modes and Operation (continued)

During Fault Count, before Hiccup

Dropout

Foldback

BOOT

Charging

Fault Mode

Fault Cases

V_SS

POK

LATCH RESET

High-Side

Switch

Low-Side

Switch

V_COMP

Not

affected,

(off only

for boot

capacitor

faults)

Hiccup Delay

(after fault

count is

Discharged with

One Shot

Diode

Emulation

Dropout

Foldback

Reset

Depends on

Pulled Low until

V_SS< V_SS(RST)

Forced Off at

Start of Period

Hiccup

I_SS(HIC)until V_SS

V_OUTand

–

< V_SS(RST)

ISEN

reached)

(sleep opt

available)

Hiccup

Restart or

Startup (after

CCM after

Released

from 0 V, then

CCM after

V_COMP

>

Dropout

Foldback

Reset

Depends on

Charged with

I_SS(SU)

Not

affected

Startup Hiccup

V_COMP> 400

400 mV

(pulsed at

minOff)

V_OUTand

–

V_SSreturns to

responds to V_SS

↑

mV

ISEN

V_SS(RST)

)

Auto,

V_FBto

normal

range

1. V_OUTto VIN

Short

2. FB pin Open

One Shot

Diode

Emulation

Dropout

Foldback

Reset

FB

Forced Off

Immediately

Pulled Low

Immediately

Not affected

Off

No

Overvoltage

1. V_OUTto VIN

short

Overvoltage 2. FB to GND

short

Auto,

V_FBto

normal

range

One Shot

Diode

Emulation

Dropout

Foldback

Reset

ISENP

Forced Off

Immediately

Pulled Low

Immediately

Not affected

Auto,

V_FBto

normal

range

CCM

according to

COMP

CCM

according to

COMP

FB

Pulled Low

Immediately

Not

affected

Startup

Not affected

Undervoltage

Feedback

Less Than

400 mV

CCM

according to

COMP

Not

affected

Startup

Not affected

f_SW/2

Pulled Low

–

Feedback

Less Than

200 mV

CCM

according to

COMP

Startup V_OUTto

GND Short

f_SWalready

at 1/4

Not

affected

f_SW/4

1.FSET to GND

short

2.FSET pulled

Pulled Low

Immediately &

latched until V_SSlatched until V_SS

< V_SS(RST)

Pulled Low

Immediately &

One Shot

Diode

Emulation

Depends on

V_OUTand

ISEN

FSET

Forced Off

Immediately

Not affected

Off

–

Resistor Fault high

3.Low R

< V_SS(RST)

Not affected

4.High R

GADJ or

IADJ Resistor

Fault

ADJ to GND short

ADJ pulled high

Low R High R

CCM

according to

COMP

CCM

according to

COMP

Depends on

Not

affected

Not affected

V

_OUTand

ISEN

–

Clamped to

Zener voltage

internally

CCM

according to

COMP

CCM

according to

COMP

Depends on

SS shorted

to VIN

Not

affected

SS to VIN short

SS to GND short

V

_OUTand

ISEN

CCM

according to

COMP

CCM

according to

COMP

Depends on

SS shorted to

GND

Loop response

only

Not

affected

At GND

V

_OUTand

ISEN

COMP

shorted to

GND

CCM

according to

COMP

CCM

according to

COMP

Depends on

COMP to GND

short

Not

affected

Not affected

At GND

V

_OUTand

ISEN

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Wide Input Voltage, Synchronous USB Buck Regulator

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A8652,

A8653

DESIGN AND COMPONENT SELECTION

2.0 × 10³

Setting the Output Voltage

1.8 × 10³

The output voltage of the regulator is determined by connecting

a resistor divider from the output node (V_OUT) to the FB pin as

shown in Figure 13. There are tradeoffs when choosing the value

of the feedback resistors. If the series combination (R_FB1+ R_FB2

is too low, then the light load efficiency of the regulator will be

reduced. To maximize the efficiency, it is best to choose higher

values of resistors. On the other hand, if the parallel combination

(R_FB1//R_FB2) is too high, then the regulator may be susceptible to

noise coupling onto the FB pin. 1% resistors are recommended to

maintain the output voltage accuracy.

1.6 × 10³

1.4 × 10³

1.2 × 10³

1 × 10³

800

)

600

400

C_FB

200

FB Pin

VOUT

0

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160

R_FB1

R_FSET(kΩ)

R_FB2

Figure 14: PWM Switching Frequency versus R_FSET

the FSET resistor, R_FSET(x-axis).

For a desired switching frequency (f_SW), the FSET resistor can be

calculated using equation 11, where f_SWis in kHz and R_FSETis in

kΩ.

Figure 13: Connecting a Feedback Divider to

Set the Output Voltage

The feedback resistors must satisfy the ratio shown in equation

26000

f_SW

below to produce a desired output voltage, V_OUT

.

– 2.2

R_FSET

=

(11)

R_FB1

R_FB2

V_OUT

– 1

=

(9)

0.8 V

When the PWM switching frequency is chosen, the designer

should be aware of the minimum controllable on-time, t_ON(MIN)

of the A8652/53. If the system’s required on-time is less than

the minimum controllable on-time, pulse skipping will occur

and the output voltage will have increased ripple or oscilla-

tions. The PWM switching frequency should be calculated using

equation 12, where V_OUTis the output voltage, t_ON(MIN)is the

minimum controllable on-time of the A8652/53 (See EC table),

and V_IN(MAX)is the maximum required operational input voltage

(not the peak surge voltage).

,

A phase lead capacitor (C_FB) can be connected in parallel with

R_FB1to increase the phase and gain margins. It adds a zero and

pole to the compensation network and boosts the loop phase

at the crossover frequency. In general, C_FBshould be less than

25 pF. If C_FBis too large, it will have no effect.

If C_FBis used, C_FBcan be calculated from equation 10:

1

C_FB=

(10)

2πR_FB1f_c

V_OUT

t_ON(MIN)× V_IN(MAX)

f_SW

<

(12)

where f_cis crossover frequency.

If the A8652/53 synchronization function is employed, the base

switching frequency should be chosen such that pulse skipping

will not occur at the maximum synchronized switching frequency

according to equation 12 (i.e. 1.5 × f_SWis less than the result

from equation 12).

PWM Switching Frequency (f_SW, R_FSET

)

The PWM switching frequency is set by connecting a resistor

from the FSET pin to ground. Figure 14 is a graph showing the

relationship between the typical switching frequency (y-axis) and

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Wide Input Voltage, Synchronous USB Buck Regulator

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A8652,

A8653

S_E× D

f_SW

V_OUT× (1 – D)

Output Inductor (L_O)

(16a) for

A8653

I_OUT(DC)≤ 4.62 –

I_OUT(DC)≤ 2.1 –

–

2 × f_SW× L_O

For a peak current mode regulator, it is common knowledge that

without adequate slope compensation, the system will become

unstable when the duty cycle is near or above 50%. However,

the slope compensation in the A8652/53 is a fixed value (S_E).

Therefore, it is important to calculate an inductor value so the

falling slope of the inductor current (S_F) will work well with the

A8652/53 slope compensation. Equations 13 and 14 can be used

to calculate a range of values for the output inductor based on

the well-known approach of providing slope compensation that

matches 50% to 100% of the down slope of the inductor current.

In equation 13, use the slope compensation (S_E), which is a func-

tion of switching frequency according to equation 14.

S_E× D

f_SW

V_OUT× (1 – D)

2 × f_SW× L_O

(16b) for

A8652

After an inductor is chosen, it should be tested during output

short-circuit conditions. The inductor current should be moni-

tored using a current probe. A good design should ensure neither

the inductor nor the regulator are damaged when the output is

shorted to ground at maximum input voltage and the highest

expected ambient temperature.

Output Capacitors

The output capacitors filter the output voltage to provide an

acceptable level of ripple voltage and they store energy to help

maintain voltage regulation during a load transient. The voltage

rating of the output capacitors must support the output voltage

with sufficient design margin. The output voltage ripple (ΔV_OUT

V_OUT

S_E

(13)

≤ L_O≤

2 × S_E

S_E= 0.0445 × f_SW²+ 0.5612 × f_SW

S_E= 0.0237 × f_SW²+ 0.3529 × f_SW

(14a for

A8653)

)

(14b for

A8652)

is a function of the output capacitors parameters: C_O, ESR_CO

,

ESL_CO

.

V_IN– V_OUT

L_O

DI_L

S_Eis in A/µs, f_SWis in MHz, and L_Owill be in µH.

(17)

DV_OUT= DI_L× ESR_CO

+

× ESL_CO+

8f_SWC_O

If equations 13 or 14 yield an inductor value that is not a standard

value, then the next highest available value should be used. The

final inductor value should allow for 10%-20% of initial toler-

ance and 20%-30% of inductor saturation.

The type of output capacitors will determine which terms of

equation 17 are dominant.

For ceramic output capacitors, the ESR_COand ESL_COare virtu-

ally zero, so the output voltage ripple will be dominated by the

third term of equation 17.

The saturation current of the inductor should be higher than the

peak current capability of the A8652/53. Ideally, for output short-

circuit conditions, the inductor should not saturate at the highest

pulse-by-pulse current limit at minimum duty cycle. This may be

too costly. At the very least, the inductor should not saturate at

the peak operating current according to equation 15. In equa-

tion 15, V_IN(MAX)is the maximum continuous input voltage.

DI_L

(18)

DV_OUT

=

8f_SWC_O

To reduce the voltage ripple of a design using ceramic output

capacitors, simply increase the total capacitance, reduce the

inductor current ripple (i.e. increase the inductor value), or

increase the switching frequency.

S_E× V_OUT

(15a) for

A8653

I_PEAK= 4.62 –

I_PEAK= 2.1 –

1.15 × f_SW× V_IN(MAX)

S_E× V_OUT

1.15 × f_SW× V_IN(MAX)

For electrolytic output capacitors, the value of capacitance will be

relatively high, so the third term in equation 17 will be very small

and the output voltage ripple will be determined primarily by the

first two terms of equation 17.

(15b) for

A8652

Subtracting half of the inductor ripple current from equation 15

gives an interesting equation to predict the typical DC load capa-

bility of the regulator at a given duty cycle (D),

V_IN– V_OUT

(19)

DV_OUT= DI_L× ESR_CO

+

× ESL_CO

L_O

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0.55

To reduce the voltage ripple of a design using electrolytic output

capacitors, simply decrease the equivalent ESR_COand ESL_CO

by using a high(er) quality capacitor, or add more capacitors in

parallel, or reduce the inductor current ripple (i.e. increase the

inductor value).

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

The ESR of some electrolytic capacitors can be quite high so

Allegro recommends choosing a quality capacitor for which the

ESR or the total impedance is clearly documented in the data-

sheet. Also, the ESR of electrolytic capacitors usually increases

significantly at cold ambients, as much as 10×, which increases

the output voltage ripple and in most cases reduces the stability

of the system.

60

Duty Cycle (%)

0

10

20

30

40

70

80

90 100

50

The transient response of the regulator depends on the quantity

and type of output capacitors. In general, minimizing the ESR of

the output capacitance will result in a better transient response.

The ESR can be minimized by simply adding more capacitors in

parallel or by using higher quality capacitors. At the instant of a

fast load transient (di/dt), the output voltage will change by the

amount:

Figure 15: Input Capacitor Ripple vs. Duty Cycle

VIN pin UVLO circuitry (V_UVLO(HYS), nominally 800 mV for the

A8652/53) at maximum loading and minimum input voltage.

The input capacitors must deliver the RMS current according to:

(21)

I_RMS= I_OD × (1 – D)

di

(20)

ESL_CO

DV_OUT= DI_LOAD× ESR_CO

+

where the duty cycle D is D ≈ V_OUT/ V_IN. Figure 15 shows the

normalized input capacitor RMS current versus duty cycle. To

use this graph, simply find the operational duty cycle (D) on the

x-axis and determine the input/output current multiplier on the

y-axis. For example, at a 20% duty cycle, the input/output current

multiplier is 0.40. Therefore, if the regulator is delivering 2.6 A of

steady-state load current, the input capacitor(s) must support 0.40

dt

After the load transient occurs, the output voltage will deviate

from its nominal value for a short time. This time will depend

on the system bandwidth, the output inductor value, and output

capacitance. Eventually, the error amplifier will bring the output

voltage back to its nominal value.

× 2.6 A or 1.04 A_RMS

.

The speed at which the error amplifier will bring the output

voltage back to its setpoint mainly depends on the closed-loop

bandwidth of the system. A higher bandwidth usually results in

a shorter time to return to the nominal voltage. However, with

a higher bandwidth system, it may be more difficult to obtain

acceptable gain and phase margins. Selection of the compensa-

tion components (R_Z, C_Z, C_P) are discussed in more detail in the

Compensation Components section of this datasheet.

The input capacitor(s) must limit the voltage deviations at the

VIN pin to something significantly less than the A8652/53 UVLO

hysteresis during maximum load and minimum input voltage.

The minimum input capacitance can be calculated as follows:

I_OUT× D × (1 – D)

0.85 × f_SW× ΔV_IN(MIN)

(22)

C_IN≥

where ΔV_IN(MIN)is chosen to be much less than the hysteresis

of the VIN UVLO comparator (ΔV_IN(MIN)≤ 150 mV is recom-

mended), and f_SWis the nominal PWM frequency.

Input Capacitors

Three factors should be considered when choosing the input

capacitors. First, they must be chosen to support the maximum

expected input surge voltage with adequate design margin.

Second, the capacitor RMS current rating must be higher than

the expected RMS input current to the regulator. Third, they must

have enough capacitance and a low enough ESR to limit the input

voltage dV/dt to something much less than the hysteresis of the

The D × (1 – D) term in equation 20 has an absolute maximum

value of 0.25 at 50% duty cycle. So, for example, a very con-

servative design based on I_OUT= 2.6 A, f_SW= 85% of 425 kHz,

D × (1 – D) = 0.25, and ΔV_IN= 150 mV,

2.6 A × 0.25

C_IN≥

= 12 µF

361 kHz × 150 mV

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A good design should consider the DC bias effect on a ceramic

capacitor: as the applied voltage approaches the rated value, the

capacitance value decreases. This effect is very pronounced with

the Y5V and Z5U temperature characteristic devices (as much as

90% reduction) so these types should be avoided. The X5R and

X7R type capacitors should be the primary choices due to their

stability versus both DC bias and temperature.

To avoid prematurely triggering Hiccup mode, the soft-start

capacitor (C_SS) should be calculated according to equation below,

Output

Capacitor

Current (I_CO)

I_LIM

}

I_LOAD

For all ceramic capacitors, the DC bias effect is even more

pronounced on smaller case sizes, so a good design will use the

largest affordable case size (i.e. 1206 or 1210). Also, it is advis-

able to select input capacitors with plenty of design margin in

the voltage rating to accommodate the worst-case transient input

voltage (such as a load dump as high as 40 V for automotive

applications).

t_SS

Bootstrap Capacitor

A bootstrap capacitor must be connected between the BOOT and

SW pins to provide the floating gate drive to the high-side MOS-

FET. Usually, 100 nF is an adequate value. This capacitor should

be a high-quality ceramic capacitor, such as an X5R or X7R, with

a voltage rating of at least 16 V.

Figure 16: Output Current (I_CO) During Startup

I_SS(SU)× V_OUT× C_O

(24)

C_SS≥

0.8 V × I_CO

where V_OUTis the output voltage, C_Ois the output capacitance,

I_COis the amount of current allowed to charge the output capaci-

tance during soft-start (recommend 0.1 A < I_CO< 0.3 A). Higher

values of I_COresult in faster soft-start times. Howewer, lower

values of I_COensure that Hiccup mode is not falsely triggered.

Allegro recommends starting the design with an I_COof 0.1 A and

increasing it only if the soft-start time is too slow. If a nonstan-

dard capacitor value for C_SSis calculated, the next larger value

should be used.

Soft-Start and Hiccup Mode Timing (C_SS)

The soft-start time of the A8652/53 is determined by the value of

the capacitance at the soft-start pin (C_SS).

When the A8652/53 is enabled, the voltage at the soft-start pin

will start from 0 V and will be charged by the soft-start current

(I_SS(SU)). However, PWM switching will not begin instantly

because the voltage at the soft-start pin must rise above 400 mV.

The soft-start delay (t_d(SS)) can be calculated using equation

below,

The output voltage ramp time (t_SS) can be calculated by using

either of the following methods:

400 mV

SS(SU)

C_OUT

I_CO

C_SS

(23)

t_d(SS)= C_SS×

( _I)

t_SS= V_OUT

×

or 0.8 V ×

(25)

I_SS(SU)

If the A8652/53 is starting with a very heavy load, a very fast

When the A8652/53 is in hiccup mode, the soft-start capaci-

soft-start time may cause the regulator to exceed the pulse-by-

pulse overcurrent threshold. This occurs because the sum of the

full load current, the inductor ripple current, and the additional

current required to charge the output capacitors,

tor is used as a timing capacitor and sets the hiccup period. The

soft-start pin charges the soft-start capacitor with I_SS(SU)during

a startup attempt and discharges the same capacitor with I_SS(HIC)

between startup attempts. Because the ratio of I_SS(SU)/I_SS(HIC)is

approximately 4:1, the time between hiccups will be about four

times as long as the startup time. Therefore, the effective duty

cycle will be very low and the junction temperature will be kept

low.

I_CO= C_O× V_OUT/ t_SS

is higher than the pulse-by-pulse current threshold, as shown in

Figure 16. This phenomena is more pronounced when using high-

value electrolytic type output capacitors.

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Remote Load Regulation Control Components Compensation Components (R_Z, C_Z, C_P)

To compensate the voltage drop across the wiring harness, the

To compensate the system, it is important to understand where

wire resistance R_WIREmust be know as a priori. The current sense the buck power stage, load resistance, and output capacitance

resistor R_sen,which is connected in series with the load after the

output capacitor C_O, is recommended to have a value between

20 and 50 mΩ, considering the tradeoff between measurement

accuracy and power dissipation.

form their poles and zeroes in frequency. Also, it is important

to understand that the (Type II) compensated error amplifier

introduces a zero and two more poles and where these should be

placed to maximize system stability, provide a high bandwidth,

and optimize the transient response.

When the load side current limit I_{OUT_LIM}is set, the resistor

R_IADJat pin IADJ can be calculated from the equation below:

First, consider the power stage of the A8652/53, the output

capacitors, and the load resistance. This circuitry is commonly

referred as the “control to output” transfer function. The low fre-

quency gain of this section depends on the COMP to SW current

gain (gm_POWER), and the value of the load resistor (R_L). The DC

gain (G_{CO(0 HZ)}) of the control-to-output is

1,200

R_IADJ

=

I_{OUT_LIM}× R_sen

The needed amount of voltage correction should be equal to the

voltage drop across the wiring harness:

R_IADJ

G_CO(0ꢀHz)= gm_POWERꢀ×ꢀR_Lꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ(26)

I_OUT× R_WIRE= I_OUT× R_sen×

× A_FB

R_GADJ

The control to output transfer function has a pole (f_P1) formed by

the output capacitance (C_OUT) and load resistance (R_L) at

Thus for given R_sen, R_IADJ, R_WIRE, the resistance R_GADJat pin

GADJ can be determined from the equation above:

1

f_P1=

(27)

2π × R_L× C_OUT

R_sen× R_IADJ

R_GADJ

=

× A_FB

R_WIRE

The control to output transfer function also has a zero (f_Z1)

formed by the output capacitance (C_OUT) and its associated ESR

Where A_FB= V_OUT/ V_FBis the gain of the FB pin voltage

divider.

1

f_Z1=

(28)

2π × ESR × C_OUT

If the dynamic voltage correction adjustment at pin GADJ is

desired (refer to Figure 5), then R_GADJin the equation above

should be replaced with the equivalent resistance R_{G_eqv}at pin

GADJ:

For a design with very low ESR type output capacitors (i.e.

ceramic or OSCON output capacitors), the ESR zero, f_Z1, is

usually at a very high frequency, so it can be ignored. On the

other hand, if the ESR zero falls below or near the 0 dB crossover

frequency of the system (as is the case with electrolytic output

capacitors), then it should be cancelled by the pole formed by the

C_Pcapacitor and the R_Zresistor (discussed and identified later as

f_P3).

1

V_G– 1

R_{G_E}

R_{G_eqv}

=

–

(

)

R_GADJ

Similarly the equivalent resistance R_IADJat pin IADJ can be

calculated below if an external voltage V_Iis applied at pin IADJ

as shown in Figure 7:

Next, consider the feedback resistor divider, (R_FB1and R_FB2), the

error amplifier (gm_EA), and its compensation network R_Z/C_Z/C_P.

It greatly simplifies the transfer function derivation if R_O>> R_Z,

and C_Z>> C_P(where R_Ois the error amplifier output imped-

ance). In most cases, R_O> 2 MΩ, 1 kΩ < R_Z< 100 kΩ, 220 pF <

C_Z< 47 nF, and C_P< 50 pF, so the following equations are very

accurate.

1

V_I– 1

R_{I_E}

R_{I_eqv}

=

–

(

)

R_IADJ

The GADJ and IADJ pins are designed for a resistance range

of 10 to 34 kΩ, and therefore the controlling voltage V_Gand V_I

must be limited as follows:

The low frequency gain of the control section (G_{C(0 Hz)}) is formed

by the feedback resistor divider and the error amplifier. It can be

calculated using equation 29:

10ꢀkΩꢀ<ꢀR_{G_eqv}ꢀ<ꢀ34ꢀkΩ

and,

10ꢀkΩꢀ<ꢀR_{I_eqv}ꢀ<ꢀ34ꢀkΩ

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R_FB2

R_{FB1 +}R_FB2

V_FB

A Generalized Tuning Procedure

G_{C(0 Hz)}

=

× gm_EA× R_O

1. Choose the system bandwidth, f_C, the frequency at which the

magnitude of the gain will cross 0 dB. Recommended values

× gm_EA× R_O

(29)

V_OUT

for f_Cbased on the PWM switching frequency are f_SW/20

< f_C< f_SW/7.5. A higher value of f_Cwill generally provide

a better transient response while a lower value of f_Cwill be

easier to obtain higher gain and phase margins.

V_FB

× A_VOL

V_OUT

where

2. Calculate the R_Zresistor value to set the desired system

bandwidth (f_C),

V_OUTis the output voltage,

V_OUT

V_FB

2 × π × C_OUT

V_FBis the reference voltage (0.8 V),

R_Z= f_C×

×

(33)

gm_POWER× gm_EA

gm_EAis the error amplifier transconductance (750 µA/V),

and

3. Determine the frequency of the pole (f_P1) formed by C_OUT

and R_Lby using equation 27 (repeated here).

R_Ois the error amplifier output impedance (A_VOL/gm_EA

)

1

f_P1=

The transfer function of the Type-II compensated error amplifier

has a (very) low frequency pole (f_P2) dominated by the output

error amplifier’s output impedance R_Oand the C_Zcompensation

capacitor,

2π × R_L× C_OUT

4. Calculate a range of values for the C_Zcapacitor,

4

1

< C_Z<

(34)

2 × π × R_Z× f_c

2 × π × R_Z× 1.5 × f_P1

1

f_P2=

(30)

2π × R_O× C_Z

To maximize system stability (i.e. have the most gain mar-

gin), use a higher value of C_Z. To optimize transient recovery

time at the expense of some phase margin, use a lower value

of C_Z.

The transfer function of the Type-II error amplifier also has a

low frequency zero (f_Z2) dominated by the R_Zresistor and the C_Z

capacitor.

5. Calculate the frequency of the ESR zero (f_Z1) formed by the

1

f_Z2=

(31)

output capacitor(s) by using equation 28 (repeated here).

2π × R_Z× C_Z

1

f_Z1=

Lastly, the transfer function of the Type-II compensated error

2π × ESR × C_OUT

amplifier has a (very) high frequency pole (f_P3) dominated by the

R_Zresistor and the C_Pcapacitor

A. If f_Z1is at least 1 decade higher than the target crossover

frequency (f_C), then f_Z1can be ignored. This is usually

the case for a design using ceramic output capacitors. Use

equation 32 to calculate the value of C_Pby setting f_P3to

either 5 × f_Cor f_SW/2, whichever is higher.

1

f_P3=

(32)

2π × R_Z× C_P

Placing f_Z2just above f_P1will result in excellent phase margin,

but relatively slow transient recovery time.

B. On the other hand, if f_Z1is near or below the target

crossover frequency (f_C) then use equation 32 to calculate

the value of C_Pby setting f_P3equal to f_Z1. This is usually

the case for a design using high ESR electrolytic output

capacitors.

The magnitude and phase of the entire system are simply the sum

of the error amplifier response and the control-to-output response.

Referring to Typical Application Diagram 1 on page 1, several

typical designs are provided in Table 3 with V_LOAD= 5 V.

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Table 3: Recommended Components Values for Several Typical Designs

Design

f_SW

R_FSET

L_O

C_O

R_Z+ C_Z// C_P

R_sen

R_GADJ

R_IADJ

A8653 (set I_{OUT_LIM}= 2.75 A, R_WIRE= 125 mΩ)

A

B

C

500 kHz

1 MHz

2 MHz

52.3 kΩ

23.7 kΩ

10.5 kΩ

10 µH (74437368100)

6.8 µH (74437368068)

44 µF

32 µF

14 kΩ + 2.7 nF//33 pF

37.4 kΩ + 1.8 nF//4.7 pF

20 mΩ

20.0 kΩ

A8652 (set I_{OUT_LIM}= 1.2 A, R_WIRE= 200 mΩ)

D

E

500 kHz

2 MHz

52.3 kΩ

10.5 kΩ

33 µH (74437368330)

10 µH (74437368100)

20 µF

14 kΩ + 2.7 nF//33pF

50 mΩ

31.6 kΩ

20.0 kΩ

24.3 kΩ + 2.2 nF//4.7 pF

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POWER DISSIPATION AND THERMAL CALCULATIONS

The power dissipated in the A8652/53 is the sum of the power

Similarly, the conduction losses dissipated by the low-side MOS-

dissipated from the V_INsupply current (P_IN), the power dissipated FET while it is conducting can be calculated by the following

due to the switching of the high-side power MOSFET (P_SW1), the equation:

power dissipated due to the RMS current being conducted by the

high-side MOSFET (P_COND1) and low-side MOSFET (P_COND2),

and the power dissipated by both gate drivers (P_DRIVER).

V_OUT

DI_L²

( ) ( )

P_COND2= I²_RMS,FET× R_DS(ON)LS

=

× I²

× R_DS(ON)LS

1 –

+

OUT

V_IN

12

(38)

The power dissipated from the V_INsupply current can be calcu-

lated using equation 35,

where

I_OUTis the regulator output current,

ΔI_Lis the peak-to-peak inductor ripple current,

P_IN= V_IN× I_Qꢀ+ꢀ(V_IN– V_GS)ꢀ×ꢀ(Q_G1+ Q_G2ꢀ)ꢀ×ꢀf_SWꢀꢀꢀꢀꢀꢀꢀꢀ(35)

where

R_DS(ON)HSis the on-resistance of the high-side MOSFET,

R_DS(ON)LSis the on-resistance of the low-side MOSFET

V_INis the input voltage,

I_Qis the input quiesent current drawn by the A8652/53 (see

EC table),

The R_DS(ON)of the both MOSFETs have some initial tolerance

plus an increase from self-heating and elevated ambient tempera-

tures. A conservative design should accomodate an R_DS(ON)with

at least a 15% initial tolerance plus 0.39%/°C increase due to

temperature.

V_GSis the MOSFET gate drive voltage (typically 5 V),

Q_G1and Q_G2is the internal high-side and low-side MOSFET

gate charges (approximately 5.8 nC and 10.4 nC, respec-

tively), and

The power dissipated from the low-side MOSFET body diode

during the non-overlap time can be calculated as follows:

f_SWis the PWM switching frequency.

The power dissipated by the high-side MOSFET during PWM

switching can be calculated using equation 36,

P_NO= V_SD× I_OUTꢀ×ꢀ2ꢀ×ꢀt_NOꢀ×ꢀf_SWꢀꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ(39)

where

V_IN× I_OUT× (t_r+ t_f) × f_SW

(36)

P_SW1

=

V_SDis the source-to-drain voltage of the low-side MOSFET

(typically 0.60 V), and

2

where

V_INis the input voltage,

t_NOis the non-overlap time (15 ns(typ))

The sum of the power dissipated by the internal gate driver can be

calculated using equation 40,

I_OUTis the regulator output current,

f_SWis the PWM switching frequency, and

P_DRIVERꢀ=ꢀ(Q_G1+ Q_G2)ꢀ×ꢀV_GSꢀ×ꢀf_SWꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ(40)

where

t_rand t_fare the rise and fall times measured at the SW node.

The exact rise and fall times at the SW node will depend on the

external components and PCB layout, so each design should be

measured at full load. Approximate values for both t_rand t_frange

from 10 to 20 ns.

V_GSis the gate drive voltage (typically 5 V),

Q_G1and Q_G2is the gate charges to drive high-side and

low-side MOSFETs to V_GS= 5 V (about 5.8 nC and 10.4 nC

respectively), and

The power dissipated by the high-side MOSFET while it is con-

ducting can be calculated using equation 37,

f_SWis the PWM switching frequency.

DI_L²

(_V) ( )

Finally, the total power dissipated by the A8652/53 (P_TOTAL) is

the sum of the previous equations,

V_OUT

P_COND1= I²_RMS,FET× R_DS(ON)HS

=

×

I²

× R_DS(ON)HS

+

OUT

12

IN

(37)

P_TOTAL= P_IN+ P_SW1+ P_COND1+ P_COND2+ P_NO+ P_DRIVERꢀ(41)

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The average junction temperature can be calculated with the

equation below,

efficiently heat can be transferred from the PCB to the ambi-

ent air. It is critical that the thermal pad on the bottom of the IC

should be connected to at least one ground plane using multiple

vias.

T_J= P_TOTALꢀ×ꢀR_θJA+ T_A

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ(42)

where

As with any regulator, there are limits to the amount of heat that

can be dissipated before risking thermal shutdown. There are

tradeoffs between ambient operating temperature, input voltage,

output voltage, output current, switching frequency, PCB thermal

resistance, airflow, and other nearby heat sources. Even a small

amount of airflow will reduce the junction temperature consider-

ably.

P_TOTALis the total power dissipated from equation 40,

R_θJAis the junction-to-ambient thermal resistance (34°C/W

on a 4-layer PCB), and

T_Ais the ambient temperature.

The maximum junction temperature will be dependent on how

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PCB COMPONENT PLACEMENT AND ROUTING

A good PCB layout is critical for the A8652/53 to provide clean,

stable output voltages. Follow these guidelines to ensure a good

PCB layout. Figure 17 shows a typical buck converter schematic

with the critical power paths/loops. Figure 18 shows an example

PCB component placement and routing with the same critical

power paths/loops from the schematic.

trace 3 in Figure 17 and 18. The SW node voltage transitions

from 0 V to V_INand with a high dv/dt rate. This node is the

root cause of many noise issues. It is suggested to minimize

the SW copper area to minimize the coupling capacitance

between SW node and other noise-sensitive nodes. However,

the SW node area cannot be too small in order to conduct

high current. A ground copper area can be placed beneath

the SW node to provide additional shielding. Also, keep low

level analog signals (like FB, COMP) away from the SW

polygon.

1. The current sensing traces from ISEN+ and ISEN– are most

sensitive to noise. A Kelvin connection is strongly recom-

mended for the low ohmic current sensing resistor. The loop

formed by ISEN+ and ISEN– traces should be minimal. The

loop should be away from the noisy switching areas and can

be placed on the bottom layer of PCB where it is away from

the high di/dt and dv/dt areas. This critical loop is shown as

trace 1 in Figure 17 and 18.

7. Place the feedback resistor divider (R_FB1and R_FB2) very

close to the FB pin. Make the ground side of R_FB2as close as

possible to the A8652/53.

8. Place the compensation components (R_Z, C_Z, and C_P) as

close as possible to the COMP pin. Also make the ground

side of C_Zand C_Pas close as possible to the A8652/53.

2. Place the ceramic input capacitors as close as possible to the

VIN pin and GND pins to make the loop area minimal, and

the traces of the input capacitors to VIN pin should be short

and wide to minimize the inductance. This critical loop is

shown as trace 2 in Figure 17 and 18. The larger input capaci-

tor can be located further away from VIN pin. The input

capacitors and A8652/53 IC should be on the same side of the

board with traces on the same layer.

9. Place the FSET resistor as close as possible to the SYNC/

FSET pin. Place the soft-start capacitor C_SSas close as pos-

sible to the SS pin.

10. The output voltage sense trace (from V_OUTto R_FB1) should

be connected as close as possible to the load to obtain the

best load regulation.

3. The loop from the input supply and capacitors, through the

high-side MOSFET, into the load via the output inductor, and

back to ground should be minimized with relatively wide

traces.

11. Place the bootstrap capacitor (C_BOOT) near the BOOT pin and

keep the routing from this capacitor to the SW polygon as

short as possible.

12. When connecting the input and output ceramic capacitors,

use multiple vias to GND and place the vias as close as possi-

ble to the pads of the components. Do not use thermal reliefs

around the pads for the input and output ceramic capacitors.

4. When the high-side MOSFET is off, free-wheeling cur-

rent ﬂows from ground, through the synchronous low-side

MOSFET, into the load via the output inductor, and back to

ground. This loop should be minimized and have relatively

wide traces, shown as trace 4 in Figure 17 and 18.

13. To minimize PCB losses and improve system efﬁciency, the

input and output traces should be as wide as possible and be

duplicated on multiple layers, if possible.

5. Place the output capacitors relatively close to the output

inductor (L_O) and the A8652/53. Ideally, the output capaci-

tors, output inductor and the controller IC A8652/53 should

be on the same layer. Connect the output inductor and the

output capacitors with a fairly wide trace. The output capaci-

tors must use a ground plane to make a very low-inductance

connection to the GND.

14. The thermal pad under the A8652/53 IC should be connected

to the GND plane (preferably on the top and bottom layer)

with as many vias as possible. Allegro recommends vias

with an approximately 0.25 to 0.30 mm hole and a 0.13 and

0.18 mm ring.

15. EMI/EMC issues are always a concern. Allegro recommends

having locations for an RC snubber from SW to ground. The

resistor should be 0805 or 1206 size.

6. Place the output inductor (L_O) as close as possible to the SW

pin with short and wide traces. This critical trace is shown as

Allegro MicroSystems, LLC

115 Northeast Cutoff

33

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

2

VIN

ISEN-

1

R_FB1

ISEN+

1

C_IN

FB

L_O

R_sen

V_OUT

Load

SW

3

SS

VREG

SYNC/FSET

COMP

C_O

4

C_SS

C_P

R_FSET

R_Z

C_Z

SGND

PGND

R_FB2

2

Figure 17: Typical Synchronous Buck Regulator with Current Sensing Resistor for Remote Load Regulation

A single-point ground is recommended, which could be the exposed thermal pad under the IC.

Figure 18a: Example PCB Component Placement and Routing, Top Layer

Allegro MicroSystems, LLC

115 Northeast Cutoff

34

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

Figure 18b: Example PCB Component Placement and Routing, Bottom Layer

Allegro MicroSystems, LLC

115 Northeast Cutoff

35

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

PACKAGE OUTLINE DRAWING

For Reference Only – Not for Tooling Use

(Reference MO-153 ABT)

Dimensions in millimeters. NOT TO SCALE

Dimensions exclusive of mold ﬂash, gate burrs, and dambar protrusions

Exact case and lead conﬁguration at supplier discretion within limits shown

0.65

0.45

8º

0º

16

5.00 0.10

16

0.20

0.09

1.70

B

4.40 0.10

3 NOM

6.40 0.20

3.00

6.10

A

0.60 0.15

1.00 REF

1

2

3 NOM

1

2

0.25 BSC

Branded Face

SEATING PLANE

GAUGE PLANE

3.00

C

16X

PCB Layout Reference View

C

0.10

C

SEATING

PLANE

0.30

0.19

1.20 MAX

0.65 BSC

NNNNNNN

YYWW

0.15

0.00

LLLL

A

B

C

Terminal #1 mark area

Exposed thermal pad (bottom surface); dimensions may vary with device

1

D

Standard Branding Reference View

N = Device part number

Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances; when

mounting on a multilayer PCB, thermal vias at the exposed thermal pad land

can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

= Supplier emblem

Y = Last two digits of year of manufacture

W= Week of manufacture

L = Characters 5-8 of lot number

D

Branding scale and appearance at supplier discretion

Figure 19: Package LP, 16-Pin eTSSOP with Exposed Thermal Pad

Allegro MicroSystems, LLC

115 Northeast Cutoff

36

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

Revision Table

Number

Date

Description

–

1

February 6, 2015

March 2, 2016

Initial Release

Corrected Output Voltage Accuracy symbol (page 6), Synchronization Input Rise and Fall Time units and

Threshold symbols (page 7), SS Maximum Charge Voltage (page 8), and miscellaneous editorial changes.

2

April 7, 2016

Test specifications changed.

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, LLC

115 Northeast Cutoff

37

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com


型号：	A8653
厂家：	ALLEGRO MICROSYSTEMS
描述：	Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation
文件：	总37页 (文件大小：1320K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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