A8450 [ALLEGRO]
Automotive Multioutput Voltage Regulator; 汽车多输出稳压器
| 型号： | A8450 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Automotive Multioutput Voltage Regulator |
| 文件： | 总15页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A8450
Automotive Multioutput Voltage Regulator
The A8450 is a multioutput power supply intended for automotive
applications. The A8450 operates from a wide input supply range and
is designed to satisfy the requirements of high ambient temperature
environments.
Package LB 24-pin SOIC
Four regulated voltage outputs provide multiple options. The 3.3 V
regulator and the 1.2 to 3.3 V adjustable regulator can be used to power
microcontroller or DSP cores, or for I/O, sensing, and A-to-D conver-
sion. Two 5 V outputs, one digital and the other analog, feature output
tracking within 0.5% of each other over the operating temperature
range. In addition, the analog regulator is protected against short-to-
battery conditions. All four regulators feature foldback current limit
protection.
The device can be enabled or disabled using two input pins. The
high voltage input, on the ENBAT pin, allows enable/disable using an
engine ignition or battery switch signal. The logic-level input, on the
ENB pin, allows enable/disable by microcontroller or DSP signals.
When disabled, the A8450 draws less than 10 µA of current. A POR
(power-on-reset) block monitors the supply voltages and provides a
reset signal, with an adjustable delay, for microcontroller or DSP resets.
A separate fault pin signals TSD (thermal shutdown), 5 V analog short-
to-supply, and 5 V analog or digital undervoltage.
Buck
Converter
VBB
CP2
1
2
24 LX
23 ENBAT
22 V33
Charge
Pump
CP1
3
VCP
V33BD
CL33
4
21
20
19
18
17
16
15
VREG11
GND
5
Soft
Start
3.3 V
Lin Reg
Control
GND
6
GND
GND
7
5 V
Dig/Anlg
Lin Reg
ENB
VREG
V5D
8
CPOR
CLADJ
VADJBD
FB
9
10
11
12
NFAULT
1.2 V to
3.3 V
Lin Reg
Control
14 NPOR
13
5 V Reg
Track
Control
V5A
The A8450 is supplied in a 24-pin SOIC package (part number
suffix LB) with fused power ground pins for enhanced thermal perfor-
mance. This provides an RθJA of 35°C/W on a 4-layer board (see chart
on p.4).
Approximate Scale 1:1
FEATURES
ꢀ6 V to 45 V input range
ꢀdc-to-dc buck converter with 5.7 V output
ꢀOvercurrent protection with foldback, and undervoltage lockout (UVLO)
ꢀDual 5 V outputs
ABSOLUTE MAXIMUM RATINGS
– Digital 5 V ±2%, 200 mA
– Analog 5 V, 200 mA
– Short-to-supply protection on analog regulator
– Analog to digital regulator output tracking <0.5%, throughout
operating temperature range
ꢀ3.3 V linear regulator, with foldback current limit
ꢀAdjustable 1.2 V to 3.3 V linear regulator, adjustable foldback current limit
ꢀIgnition switch enable; Sleep mode
Load Supply Voltage, VBB ..................................45 V
Analog Output, Pin V5A........................–1 V to 45 V
Logic Input Signal
Pin ENBAT .................................–0.3 V to 45 V
Pin ENB .....................................–0.3 V to 6.5 V
Pin LX.................................................... –2 V to VBB
Operating Temperature Range
Ambient Temperature, TA............ –40°C to 135°C
Junction Temperature, TJ(MAX).....................150°C
Storage Temperature, TS .................... –55°C to 150°C
ꢀ100% duty cycle operation for low input voltages
ꢀPower OK output
ꢀ–40°C to 135°C ambient operating temperature range
Use the following complete part number when ordering:
Part Number
Package
Description
A8450KLB
24-pin, SOIC
Webbed Leadframe
A8450KLB-DS, Rev. 1
A8450
Automotive Multioutput Voltage Regulator
Functional Block Diagram
D2
VIN
L1
C8
D1
C7
CIN
COUT
High
Voltage
Switch
LX
CP1
CP2
VCP
VBB
VREG
R3
CL33
VREG11
Buck Converter with
Switching Regulator
V33BD
V33
3.3 V Linear
Regulator Control
Q1
C10
Charge Pump
Soft Start
CPOK
VREG
VBB
C3
R4
ENBAT
ENB
High V
Protection
VREF
Internal
Reference
CLADJ
1.2 V to 3.3 V
Adjustable Linear
Regulator Control
VADJBD
FB
Q2
VADJ
C4
R1
R2
NPOR
VREG
V5D
5 V Digital Linear
Regulator
VUVLOREG
VUVLOADJ
VUVLO33
C1
5V Analog
CPOR
C9
Adjustable
Delay
Linear Regulator
and V5D to V5A
Tracking Control
Current
Limiting
POR Block
V5A
NFAULT
GND
C2
TSD Warning
Short-to-Supply
Protection
V5A Short to Supply
UVLO V5D, V5A
Fault
ID
Characteristics
Representative Device
C1, C2, C3, C4
COUT
CIN
1 µF, 25 V ceramic X7R
100 µF, 35 V low-ESR electrolytic
47 µF, 63 V electrolytic
UHC1V101M, Nichicon
0.1 µF, 50 V ceramic X7R (for 14 V applications), or
0.1 µF, 100 V ceramic X7R (for 42 V applications)
0.22 µF, 10 V X7R
C7, C8
C10
D1, D2
L1
1 A, 40 V Schottky (for 14 V applications)
100 µH, 1.2 A
EKO4, Sanken
D03316HT, Coilcraft
MPSW06
Q1, Q2 pass transistors npn transistor, hFE > 50
A8450KLB-DS, Rev. 1
Allegro MicroSystems, Inc.
2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
ELECTRICAL CHARACTERISTICS at TA = –40ºC to 135°C, VBB = 6 to 45 V, VENB = 5 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min. Typ. Max. Units
Enabled mode: VENBAT or VENB = HIGH,
IOUT = 0 mA: VBB = 14 V
–
6
10
mA
Enabled mode: VENBAT or VENB = HIGH,
Supply Quiescent Current
IBB
–
–
10
–
15
10
mA
µA
V
I
OUT = 0 mA; VBB = 6 V
Disabled mode: VENBAT and VENB = LOW
ILOAD = 550 mA = ILOADV5D + ILOADV5A + ILOADV33
+ ILOADVADJ; VBB > 6.5 V
5.50
–
5.80
Regulated Output Voltage
VREG
Dropout: 6 V ≤ VBB < 6.5 V
TJ = 25°C
5.00
–
–
5.80
500
750
1.8
V
415
650
1.2
mΩ
mΩ
A
Buck Switch On-Resistance
Buck Switch Current Limit
RDSON
IDSLIM
tOFF
tSS
TJ = 135°C
–
1.0
dc-to-dc Fixed Off-Time
VBB = 14 V
VBB = 14 V
–
5
4.75
10
–
µs
Soft Start Time
15
ms
Logic Inputs
HIGH input level
2.7
–0.3
–
–
–
–
–
–
–
–
–
–
45
0.8
300
70
V
V
ENBAT Logic Input Voltage
ENBAT Input Current
VENBAT
LOW input level
HIGH input level, VENBAT = 45 V
HIGH input level, VENBAT = 14 V
LOW input level, VENBAT = 0.8 V
HIGH input level
µA
µA
µA
V
IENBAT
–
–1
2.7
–0.3
–
10
6.5
0.8
50
ENB Logic Input Voltage
ENB Input Current
VENB
IENB
LOW input level
V
HIGH input level, VENB ≥ 2.7 V
LOW input level, VENB ≤ 0.8 V
µA
µA
–1
10
Linear Regulator Outputs*
V5D Output Voltage
V5A Output Voltage
VOUTV5D 1 mA ≤ ILOADV5D ≤ 200 mA
VOUTV5A 1 mA ≤ ILOADV5A ≤ 200 mA
VOUTV33
4.9
4.9
5.0
5.0
5.1
5.1
V
V
V
V33 Output Voltage
3.234 3.300 3.366
50 mA ≤ ILOADV5A, ILOADV5D ≤ 200mA;
BB > 6.5 V
V5A to V5D Tracking
VTRACK
–25
–
25
mV
V
V5D Current Limit
V5A Current Limit
IOUTV5DLIM
IOUTV5ALIM
200
200
300
300
–
–
mA
mA
Base Drive Output Current
Feedback Voltage
IBD
VFB
IFB
1 V ≤ VOUTVADJ, VOUTV33 ≤ 4 V
5.0
10.0 16.0
1.20 1.24
mA
V
1.16
Feedback Input Bias Current
–400 –100 100
nA
Continued on next page
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A8450KLB-DS, Rev. 1
A8450
Automotive Multioutput Voltage Regulator
ELECTRICAL CHARACTERISTICS (continued) at TA = –40ºC to 135°C, VBB = 6 to 45 V, VENB = 5 V, unless
otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
mV
Protection
Fault asserted;
NFAULT, INPOR = 1 mA
NFAULT, NPOR Output Voltage
VERRON
–
–
400
I
NFAULT, NPOR Leakage Current
POR Delay
IERROFF
tPOR
VNFAULT, VNPOR = 5 V
C9 = 0.47 µF
–
65
–
1
135
3.10
3.05
–
µA
ms
V
100
2.95
2.90
80
V33 rising
2.80
2.75
–
V33 Undervoltage Threshold
V33 Hysteresis
VUVLOV33
VHYSV33
VUVLOV5
VHYSV5
V33 falling
V
mV
V
VREG rising
VREG falling
4.36
4.24
–
4.50
4.38
125
1.07
1.02
70
4.75
4.63
–
V5A, V5D Undervoltage Threshold
V5A, V5D Hysteresis
V
mV
V
VFB rising
VFB falling
At FB pin
1.02
0.97
–
1.12
1.07
–
VADJ Undervoltage Threshold
VUVLOVADJ
V
VADJ Hysteresis
VHYSVADJ
VOC
VUVLOVREG
TJTW
mV
mV
V
VADJ, V33 Overcurrent Threshold
VREG Undervoltage Threshold
Thermal Warning Threshold
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
175
4.94
–
200
5.15
160
175
15
225
5.36
–
TJ rising
°C
°C
°C
TJTSD
TJ rising
–
–
THYSTSD
Recovery period = TJTSD – TJTW
–
–
*Linear regulator output specifications are only valid when VREG is in regulation (VBB ≥ 6.5).
Power Dissipation Versus Ambient Temperature
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4-Layer PCB*
(RθJA = 35 ºC/W)
20
40
60
Ambient Temperature (°C)
*In still air; mounted on PCB based on JEDEC high-conductance standard PCB
80
100
120
140
160
(JESD51-7; High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages); data on other PCB types is provided on the Allegro Web site.
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
Timing Diagrams
VREG
VHYSV33
VOUTV33
VUVLOV33
VHYSVADJ
VOUTVADJ
VUVLOVADJ
tPOR
VNPOR
tPOR
A B
Slope of V
and V
from A to B determined by I and output capacitor (C3, C4).
LOAD
OUTV33
OUTVADJ
Figure 1a. NPOR fault due to undervoltage lockout on the V33 or FB pins
VBB
VREG
VUVLOVREG
VOUTV33
VUVLOV33
VREG Monitor
VOUTVADJ
VENBAT
VENB
VNPOR
tPOR
tPOR
POR event initiates
V33 can sustain regulation with normal load by bulk capacitor (COUT) on V
.
REG
Figure 1b. Power-off using VBB
+7 V
VCP
VBB > 6 V
VREG
VREG = 1.8 V
VOUTV5A/V5D
VUVLO(33)
VOUTV33
VOUTVADJ
VNPOR
VENBAT
VENB
ENBAT signals power-on
Charge pump ramping
Charge pump OK flag set
tSS
exceeded; VADJ enabled
tPOR
V
UVLOV33
ENB signals power-off
A
B
Slope of V
REG
(which controls V
, V
, and V ) from A to B determined by I
OUTVADJ
and COUT.
LOAD
OUTV33
OUTV5A/V5D
Figure 1c. Power-on using ENBAT, followed by power-off using ENB
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
Load Transients Diagrams
VIN = 12 V; ILOAD = 100 mA; TA = 25°C; ac-coupled; C1, C2, C3 and C4 = 1 µF
ILOAD
3.3 V Regulator
90%
10%
tRISE
t (0.2 µs/Div.)
t (50 µs/Div.)
V5D Regulator
Adjustable Regulator, at 1.8 V*
t (50 µs/Div.)
t (50 µs/Div.)
*For the adjustable regulator, the transient load response
is improved as the voltage is reduced. This is due to the
V5A Regulator
ability of the regulator to provide more base drive (V
)
ADJBD
because of more available voltage. When the adjustable
regulator approaches 3.3 V, its transient load response is
equivalent to the response of the V33 regulator.
For all regulators, load transients can be improved by
increasing the output capacitance (C1, C2, C3, and C4).
In order to keep ESR down it is best to use ceramic type
capacitors. However, large values in ceramic type capacitors
are either not available or very expensive. If larger values are
needed, above 22 µF, electrolytic capacitors with low ESR
ratings can be used. Performance can be improved further
by adding a 1 µF ceramic in parallel with the electrolytic.
t (50 µs/Div.)
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
Functional Description
Buck Converter with Switching Regulator. A cur-
tOFF by VBB
rent-mode, variable frequency buck dc-to-dc converter and
switching regulator are integrated in the A8450, as shown in
figure 2. This feature allows the device to efficiently handle
power over a wide range of input supply levels. The dc-to-dc
converter outputs 5.7 V typical, and has an overcurrent limit
of 1.2 A typical.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.75 µs
12 V
The converter employs a soft-start feature. This ramps the
converter output voltage and limits the maximum demand on
VREG by controlling the inrush current required at power-on
to charge the external capacitor, COUT, and any dc load.
2.05 µs
11 V
0.58 µs
6.02 V
An internal charge pump provides gate drive for the
N-channel MOSFET buck switch. A 100% duty cycle is
implemented when using low VBB input voltages.
5
7
9
11
13
15
VBB (V)
At VBB lower than 12 V, off-time, tOFF, is reduced, as shown
in figure 3. This reduction keeps the switching frequency,
fPWM, within a reasonable range and lowers the ripple cur-
rent. Lowering the ripple current at low VBB levels prevents
degradation of linear regulator headroom due to VREG ripple
voltage.
Figure 3. When VBB falls below 12 V, tOFF decreases
L1
100 µH
5VLinear Regulators. Two 5 V medium-power linear regula-
torsareprovided.Theselow-dropoutregulatorsfeaturefoldback
current limiting for short-to-supply protection. When a direct
VBB
COUT
100 µF
D1
LX
Buck Converter
Buck Switch
tOFF
VCP
Switching
Regulator
Control
IDEMAND
ENB
Clock
Counter
IPEAK
1.2 A Limit
Soft Start
Ramp
Generation
Compensation
Error
Bandgap
1.22 V
Clamp
VREG
Figure 2. Buck converter with switching regulator
Allegro MicroSystems, Inc.
7
115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
short is applied to the regulator output, either V5A or V5D, tors from a short-to-ground condition.The current limit setting,
the current folds back to 0 V at 50 mA, as shown in figure 4a. ICL (mA), is calculated using the formula
The voltage recovers to its regulated output when the short is
removed.
ICL = VOC ⁄ RRCL
The V5A and V5D regulators track each other during power- whereRCL(Ω)isthecurrent-limitingresistorcorrespondingto
on, and when the device is enabled and ramped up out of that regulator (R3 for the 3.3 V regulator, and R4 for the adjust-
disabled mode, the regulators will start to track when VREG ableregulator).WhenICLisexceeded,themaximumloadcurrent
reaches approximately 1.8 V. These regulators are guaranteed through that regulator is folded back to 40% of ICL ±10%, as
to track to within 0.5% of each other under normal operating shown in figure 4b. If current limiting is not needed, the CL33
conditions.
and CLADJ pins should be shorted to the VREG pin.
Disabled Mode. When the two input signal pins, ENBAT
and ENB, are pulled low, the A8450 enters disabled mode.
This is a sleep mode, in which all internal circuitry is dis-
abled in order to draw a minimal current from VBB. When
either of these pins is pulled high, the device is enabled.
When emerging from disabled mode, the buck converter
switching regulator does not operate until the charge pump
has stabilized (≈300 µs).
3.3 V and Adjustable Linear Regulators. Two additional
linear regulators, one that outputs at 3.3 V, and another that has
a 1.2 V to 3.3 V adjustable output, can be implemented using
external npn pass transistors. The output voltage of the adjust-
able regulator, VOUTVADJ (V), is set by the values of the output
resistors, R1 and R2 (Ω). It can be calculated as
VOUTVADJ = VFB (1+R1 ⁄ R2)
where VFB (V) is the voltage on the feedback pin, FB.
Enabled Mode. When one or both of the signal input
pins, ENBAT and ENB, are in the high state, the A8450 is
enabled.
Additional pins, CL33 and CLADJ, are provided for setting
currentlimits.Theseareusedtoprotecttheexternalpasstransis-
5V Regulators Overcurrent Foldback
3.3 V and Adjustable Regulators Overcurrent Foldback
6
6
5
4
3
2
5
0.4
I
10ꢀ
I
CL
CL
4
3
2
1
0
V
and V
OUTV33
OUTVADJ(max)
I
and I
OUTV5ALIM
OUTV5DLIM
V
OUTVADJ(min)
1
0
200
250
300
0
50
100
150
1600
0
1600
IOUT (mA)
IOUT (mA)
Figure 4a. Linear foldback to 50 mA. Foldback occurs at the
typical current limit for the 5 V regulator.
Figure 4b. Linear foldback to a percentage of ICL. Foldback
occurs at the current limit setting for the regulator.
Allegro MicroSystems, Inc.
8
115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
ENBAT is an edge-triggered enable (logic 1 ≥ 2.7 V), which
on either regulator, VOC , is exceeded. It also occurs if
the VREG voltage falls below VREGMON, due to current
is used to enable the A8450 in response to a high-voltage
signal, such as from an automobile ignition or battery switch.
In this capacity, ENBAT is used only as a momentary switch
to wake up the device. If there is no need for a high-voltage
signal, ENBAT can be pulled low continuously.
exceeding IDSLIM
.
• Both input signal pins, ENB and ENBAT, are pulled low.
This immediately pulls the NPOR pin low, indicating that
the device is beginning a power-off sequence. In addition,
the buck converter switching regulator is disabled, and
the VREG supply begins to ramp down. The rate at which
VREG decays is dependent on the total current draw, ILOAD
and value of the output capacitors (C1, C2, C3, and C4).
ENB is used to initiate the reset of the device. If ENBAT is
pulled low, ENB acts as a single reset control.
,
Diagnostics. An open drain output, through the NFAULT
pin, is pulled low to signal to a DSP or microcontroller any of
the following fault conditions:
• VREG drops below its UVLO threshold, VUVLOVREG
.
• During any normal power-on, VOUTVADJ falls below
VUVLOVADJ, triggering a POR.
• V5A, the 5 V analog regulator output, is shorted to supply
• Either or both of the V5A and the V5D regulator outputs
are below their UVLO threshold, VUVLOV5
An open drain output, through the NPOR pin, is provided to
signal a POR event to the DSP or microcontroller. The reset
occurs after an adjustable delay, tPOR, set by an external capaci-
tor, C9, connected to the CPOR pin. The value of tPOR (ms) is
calculated using the following formula
• Device junction temperature, TJ, exceeds the Thermal
Warning threshold, TJTW
Charge Pump. The charge pump generates a voltage above
VBB in order to provide adequate gate drive for the N-channel
buck switch.A0.1µFceramicmonolithiccapacitor,C7,should
be connected between the VCP pin and the VBB pin, to act as
a reservoir to run the buck converter switching regulator.
tPOR = 2.13 105
C
CPOR
× ×
where CCPOR (µF) is the value of the C9 capacitor.
VCP is internally monitored to ensure that the charge pump is
disabled in the case of a fault condition. In addition, a 0.1 µF
ceramicmonolithiccapacitor,C8,shouldbeconnectedbetween
CP1 and CP2.
A POR can be forced without a significant drop in the supply
voltage, VREG, by pulsing low both the ENB and the ENBAT
pins. However, pulse duration should be short enough so that
VREG does not drop significantly.
Power On Reset Delay. The POR block monitors the sup-
ply voltages and provides a signal that can be used to reset a
DSP or microcontroller. A POR event is triggered by any of
the following conditions:
Thermal Shutdown. When the device junction temperature,
TJ, is sensed to be at TJTSD (≈15°C higher than the thermal
warningtemperature,TJTW), afaultisindicatedattheNFAULT
pin. At the same time, a thermal shutdown circuit disables the
buck converter, protecting the A8450 from damage.
• Either V33 or VADJ is pulled below its UVLO threshold,
VUVLOV33 or VUVLOVADJ. This occurs if the current limit
Allegro MicroSystems, Inc.
9
115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
Application Information
Component Selection
VL1OFF = 5.8 + 0.8 + (0.550 0.400) = 6.821 V
×
Output Inductor (L1). This inductor must be rated to handle
the total load current, ILOAD. In addition, the value chosen
must keep the ripple current to a reasonable level. A typical
selection is a power inductor rated at 100 µH and 1.3 A.
IRIPPLE(max) = 6.821 4.75 ⁄ 100 = 0.324 A
×
VL1ON =14 – (0.550 0.750) – (0.550 0.400)
×
×
– 5.8 = 7.56 V
tON
= 0.324 100 ⁄ 7.56 = 4.3 µs
×
The worse case ripple current, IRIPPLE(max) (mA), can be
calculated as
fPWM = 1/(4.3 + 4.75) = 111 kHz
IRIPPLE(max) = VL1OFF
t
⁄ LL1
OFF
×
In the case of a shorted output, the buck converter could
reach its internal current limit, IDSLIM, of 1.2 A typical. To
ensure safe operation, the ISAT rating for the selected induc-
tor should be greater than 1.4 A. However, if the external
current limit resistors, R3 and R4, selected for the 3.3 V and
adjustable (1.2 V to 3.3 V) regulators, are rated such that the
total inductor current, ILOAD, could never reach that inter-
nal current limit, then an inductor can be selected that has
an ISAT rating closer to the calculated output current of the
device, ILOAD, plus the maximum ripple current, IRIPPLE(max)
where LL1 (µH) is the inductance for the selected component,
and VL1OFF is the voltage (V) through the inductor when the
A8450 is in the quiescent state
VL1OFF = VREG(max) + VD1 + (ILOAD R )
×
L1
where VD1 (V) is the voltage drop on diode D1, ILOAD (mA)
is the total load current, and RL1 is the specified dc resistence
(Ω) for the selected inductor at its rated temperature.
.
The frequency, fPWM (Hz), of the switching regulator in the
buck converter can then be estimated by
Higher inductor values can be chosen to lower IRIPPLE. This
may be an option if it is desired to increase the total maxi-
mum current that is drawn from the switching regulator. The
fPWM = 1/(tON + tOFF
where tON (µs) is calculated as
tON = IRIPPLE(max)
)
maximum total current available, ILOAD (mA), is calculated as
ILOAD = IDSLIM – (IRIPPLE(max) ⁄ 2)
L
⁄ VL1ON
×
L1
Catch Diode (D1). The Schottky catch diode should be
and VL1ON (V) as
VL1ON =VBB –(ILOAD
rated to handle 1.2 times the maximum load current, ILOAD
because the duty cycle at low input voltages, VBB, can be
,
R
)
×
DSON(max)
very close to 100%. The voltage rating should be higher than
the maximum input voltage, VBB(max), expected during any
operating condition.
– (ILOAD R )–V
×
L1
REG(max)
Example
Given a typical application with VBB = 14 V, tOFF = 4.75 µs,
and ILOAD = 550 mA. (Note that the value for tOFF is con-
stant for VBB > 12 V, as shown in figure 3.)
VREG Output Capacitor (COUT). Voltage ripple in the
VREG output is the main consideration when selecting the
VREG output capacitor, COUT. The peak-to-peak output
voltage ripple, VRIPPLE(p-p) (mV), is calculated as
Given also a 100 µH power inductor rated at 400 mΩ for
125ºC. (Note that temperature ratings for inductors may
include self-heating effects. If a 125ºC rating includes a self-
heating temperature rise of 20ºC at maximum current, then
the actual ambient temperature, TA, cannot exceed 105ºC.)
VRIPPLE(p-p) = IRIPPLE ESR
×
COUT
with ESR in ohms. It is recommended that the maximum
level of VRIPPLE(p-p) be less than 200 mV.
Allegro MicroSystems, Inc.
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115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
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A8450
Automotive Multioutput Voltage Regulator
For electrolytic output capacitors, a low-ESR type is recom-
mended, with a minimum voltage rating of 10 V. However,
because ESR decreases with voltage, the most cost-effective
choice may be a capacitor with a higher voltage rating.
For a typical application where VREG = 5.8 V, VOUT
2.5 V, and ILOAD = 190 mA
=
P = (5.8 – 2.5) 190 = 627 mW
×
D
Adjusting Pass Transistor Power Dissipation
Regulator Output Capacitors (C3 and C4). The output
capacitors used with the 3.3 V regulator (C3) and the 1.2 V
to 3.3 V adjustable regulator (C4), should be 1 µF or greater
X7R (5% tolerance) ceramic or equivalent capacitors, with
a maximum capacitance change of ±15% over a temperature
range of –55ºC to 125ºC.
Transistors are manufactured in a wide variety of pack-
age types, and the thermal dissipation efficiencies of the
packages can vary greatly. In general, increasing thermal
efficiency can also increase cost substantially. Selecting the
package to closely match operating conditions is important to
optimizing application design and cost.
The ESR of these capacitors does not affect the outputs of
the corresponding regulators. If a greater capacitance is used,
the regulators have improved ripple rejection at frequencies
greater than 100 kHz.
Even when using a thermally-enhanced package, it remains
difficult to provide high current to a load at high ambient
operating temperatures. Depending on the load requirements,
using drop resistors, as shown in figure 5, may be necessary
to protect the pass transistor from overheating.
Pass Transistors (Q1 and Q2). The pass transistors
used to implement the 3.3V regulator and the 1.2V to 3.3V
adjustable regulator must ensure the following:
The output current-limiting resistors, RCL (corresponding
to R3 and R4), will drop between 175 mV and 225 mV at
the highest current output, ILOAD. Assuming no additional
resistance, the voltage dropped, VDROP (mV), on each pass
• Stable operation. The cutoff frequency for the control
loops of the regulators is 100 kHz. Transistors must be
selected that have gain bandwidth product, fT (kHz), and
beta, hFE (A), ratings such that
fT ⁄ hFE > 100 kHz
VREG
• Adequate base drive. It is acceptable to use a lower level
of current gain, hFE, for lower total load currents, ILOAD
.
RCL
The lower limit for ILOAD is limited by the minimum base
current for the A8450, IBD(min), and the minimum hFE of
the pass transistor, such that
CL33
ILOAD = IBD(min)
h
FE(min)
×
ILOAD
A8450
Note that hFE is dependant on operating temperature.
Lower temperatures decrease hFE, affecting the current
capacity of the transistor.
V33BD
VDROP
VCE
• Packaged for sufficient power dissipation. In order to
ensure appropriate thermal handling, the design of the ap-
plication must take into consideration the thermal charac-
teristics of the PCB where the A8450 and pass transistors
are mounted, the ambient temperature, and the power
dissipation characteristics of the transistor packages. In
general, the power dissipation, PD (mW), is estimated by
VOUTV33
V33
Figure 5. Placement of drop resistors for thermal protection; example
shown is for the 3.3 V regulator.
PD = (VREG – VOUT
)
I
LOAD
×
Allegro MicroSystems, Inc.
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115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
transistor is
Assume that VREG(max) = 5.8 V and VOUT(max) = 3.3 V.
Assume also that TA = 125°C, and VCE = 1V (as specified for
the MPSW06 npn transistor, beta = 300 at 125˚C).
VDROP = VREG – VRCL – VOUT
This can be substituted into the power dissipation formula
PD = VDROP
In order to determine the resistance values for the current-
limiting and drop resistors, VRCL and VDROP can be expressed
in terms of ILOAD(lim)
I
×
LOAD
Given a typical application where VREG = 5.8 V, VRCL
=
VRCL = (ILOAD(lim)
R
)
CL
0.175 V, VOUT = 3.3 V, and ILOAD = 350 mA, then PD is
approximately 814 mW.
×
×
VRDROP = (ILOAD(lim)
R
)
RDROP
PD can be used to estimate the minimum required operating
temperature rating for the transistor. The ability of a package
to dissipate heat is approximated by the thermal resistance
from the die (junction) to the ambient environment, RθJA
(°C/W). This includes the significant effect of dissipa-
tion through the package leads and the PCB on which the
transistor is mounted, and the state of the ambient air. The
typical rating for a DPAK package is 32˚C/W. The expected
Assume a typical ILOAD = 350 mA. However, under normal
operating conditions, the current limit set by RCL would
be higher than the expected normal current, so assume
ILOAD(lim) = 0.400 A and RCL = 44 Ω. Substituting to deter-
mine VRCL
VRCL = 0.400 0.44 = 0.176 V
×
We can now solve for RRDROP and then VDROP
self-induced temperature rise in the package, ∆T (°C), given
J
PD = 0.814 W, is approximated as
VREG – VRCL – (ILOAD
R
RDROP) – VCE ≥ VOUT
×
∆TJ = PD
RθJA= 26°C
×
5.8 – 0.176 – (0.4
RRDROP) – 1 ≥ 3.30 V
×
In automotive applications, where under-the-hood ambient
temperatures can exceed 125˚C, the pass transistor would
have to be rated to provide the required beta at ≥151°C, plus
a safe operating margin.
therefore
and
RRDROP ≥ 3.31 Ω
VRDROP = 0.4 3.31 = 1.3 V
For a selected transistor, VCE can change depending on cur-
rent, temperature, and transistor beta. Typically, transistors
are rated at a minimum beta at a defined VCE. However, VCE
should be calculated with some margin so there is always
enough headroom to drive the device at the desired load.
×
Using four 0.25 W resistors valued at 14.7 Ω in parallel will
drop 1.3 volts.
Using the drop resistors as calculated above, the power dis-
sipation in the transistor, PD (W) is reduced to
To provide an operating margin, or if a lower-value RCL is
required, voltage drop resistors, RDROP, can be added to
the circuit, between the RCL and the transistor (figure 5). It
is also important to consider tolerances in resistance values
and VREG. The level of VREG(min) is 5.6 V, at which level PD
is reduced, but also the voltage available for VCE is reduced.
Calculating maximum and minimum voltage drops is useful
in determining the values of the drop resistors.
PD = ILOAD(lim) (VREG – VRCL – VRDROP – VOUT
)
×
= 0.400 (5.8 – 0.176 – 1.3 – 3.3) = 0.410 W
×
and
∆TJ = PD
RθJA= 13°C
×
The power dissipated in the transistor is significantly
The required drop resistor value, RRDROP, can be determined
in terms of the voltage drops across each component of the
circuit, as shown in the following formula
reduced. A transistor in a power package with an RθJA of
32˚C/W at 400 mA (a 50 mA margin) undergoes a tempera-
ture rise of 13˚C with the drop resistors, as opposed to a
similar transistor at 350 mA rising 26˚C without drop resis-
tors. At high output currents, properly selected drop resistors
can protect the external pass transitor from overheating.
VDROP ≥ VOUT
where
VDROP = VREG – VRCL – VRDROP – VCE
Allegro MicroSystems, Inc.
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115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
P
D(lim), the relationship can be assumed to be linear through-
A8450 Power Dissipation. The A8450 is designed to
operate in applications with high ambient temperatures. The
total power dissipated in the device must be considered in
conjunction with the thermal dissipation capabilities of the
PCB where the A8450 is mounted, as well as the capabilities
of the device package itself.
out the practical TJ operating range (see test conditions for
RDSON in the Electrical Characteristics table).
DC (duty cycle) is a function of VBB and VREG. This can be
calculated precisely as
DC = VREG(off) ⁄ (VREG(on) + VREG(off)
A rough estimate for DC is
DC = (VREG + VLX) ⁄ VBB
)
The ability of a package to dissipate heat is approximated by
the thermal resistance from the die (junction) to the ambi-
ent environment, RθJA (°C/W). This includes the significant
effect of dissipation through the package leads and the PCB
on which the package is mounted, and the temperature of the
ambient air. Test results for this 24-lead SOIC are approxi-
mately 35 °C/W when mounted on a high-thermally conduc-
tive PCB (based on the JEDEC standard PCB, having four
layers with buried copper areas).
IV33BD(max) is the maximum current drawn on the V33BD
pin. It is dependent on IOUTV33 and the hFE of the pass tran-
sistor.
IADJBD(max) is the maximum current drawn on the VADJBD
pin. It is dependent on IOUTVADJ and the hFE of the pass
transistor.
The total power that can be applied to the device, PD(lim)
(W), is affected by the maximum allowable device junction
temperature, TJ(max) (°C), RθJA, and the ambient air tempera-
ture, TA (°C), as shown in the following formula
Overcurrent Protection
The current supplied by the 3.3 V and the 1.2 to 3.3 V adjust-
able regulators is limited to ICL. Current above ICL is folded
back linearly, as shown in figure 4b. In the case of a shorted
load, the collector current is reduced to 40% of ICL ±10%,
to ensure protection of the pass transistors. After the short is
removed, the voltage recovers to its regulated level.
PD(lim) = (TJ(max) – TA) ⁄ RθJA
PD(lim) can be estimated based on several parameters, using
the following formula
PD(lim) = PD(Ibias) + PD(V5A) + PD(V5D) + PD(buckdc)
+ PD(buckac) + PD(BD)
The maximum power dissipated in the transistor during a
shorted load condition is:
where
PD(Ibias) = VBB
I
BB
PD ≈ (VREG – VOUT
)
(0.4
I )
×
× × CL
PD(V5A) = (VREG – 5 V)
I
LOAD(V5A)
where VOUT = 0 V.
Low Input Voltage Operation
×
×
PD(V5D) = (VREG – 5 V)
I
LOAD(V5D)
2
PD(buckdc)= ILOAD
R
DC
×
×
DSON(TJmax)
When the charge pump has ramped enough to enhance
the buck switch, the buck converter switching regulator is
enabled. This occurs at VBB ≈ 5.7 V. At that point, the duty
cycle, DC, of the A8450 can be forced to 100% until VIN is
high enough to allow the switch to begin operating normally.
The point at which normal switching begins is dependent
on ambient temperature, TA. Increases in TA cause RDSON to
increase. Other significant factors are ILOAD, VREG, the ESR
of the output inductor (L1), and the forward biasing voltage
for the output Schottky diode (D1).
PD(buckac)= ILOAD [V (5 ns ⁄ 14 V)
V
]
0.5f
PWM
×
× ×
BB
BB
PD(BD) = IV33BD(max) (VREG – 4V)+IVADJBD(max)
×
(VREG–VADJ – 0.7V)
×
and
ILOAD = ILOAD(V33) +ILOAD(VADJ) +ILOAD(V5D) +ILOAD(V5A)
RDSON is a function of TJ. For the purposes of estimating
Allegro MicroSystems, Inc.
13
115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
regulator, if either or both are not needed, the corresponding
external components are not used. In addition, if the 3.3 V
Regulator Bypass
Some applications may not require the use of all four regula-
tors provided in the A8450. For the regulators that are not
used, the corresponding external components are not needed.
regulator is not used, CL33 and V33 are not connected. If the
adjustable regulator is not used, CLADJ and FB are not con-
nected. However, to ensure stability of the A8450, the base
drive pin, V33BD or VADJBD, of any unused regulator must
be shorted to VREG.
If either or both of the two 5 V regulators are not required by
the application, bypass an unused regulator by not connect-
ing its output terminal, V5D or V5A. Also, the corresponding
output capacitor, C1 or C2, is not used.
For the 3.3 V regulator and the 1.2 V to 3.3 V adjustable
Pin List Table
Name
VBB
CP2
Description
Number
Supply input
1
Charge pump capacitor, positive side
Charge pump capacitor, negative side
2
3
CP1
Charge pump output used to drive N-channel buck converter
transistor
VCP
4
VREG11
GND
Internal reference
5
Power ground
6
GND
Power ground
7
ENB
Logic control
8
CPOR
CLADJ
VADJBD
FB
Connection for POR adjustment
Current limit for adjustable regulator
Base drive for adjustable regulator pass transistor
Feedback for adjustable regulator
5 V analog regulator output
Power on Reset logic output
Diagnostic output; open drain; low during fault condition
5 V digital regulator output
dc-to-dc converter supply output
Power ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V5A
NPOR
NFAULT
V5D
VREG
GND
GND
Power ground
CL33
V33BD
V33
Current limit for 3.3 V regulator
Base drive for 3.3 V regulator pass transistor
3.3 V regulator output
ENBAT
LX
High voltage logic control
Buck converter switching regulator output
Allegro MicroSystems, Inc.
14
115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
24-Pin SOIC
15.40 BSC
8º
0º
24
19 18
0.33
0.20
7.50 BSC
10.30 BSC
1.27
0.40
1
2
6
7
0.51
0.31
2.65
2.35
0.64 BSC
1.27 BSC
0.30
0.10
Dimensions in millimeters
Conform to JEDEC MS-013AD
Actual dimensions may vary at vendor discretion
Leads 6, 7, 18, and 19 are internally fused ground leads, for enhanced thermal
dissipation. Exact external appearance subject to vendor discretion.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required
to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned
to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for
its use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright©2004 AllegroMicrosystems, Inc.
Allegro MicroSystems, Inc.
15
115 Northeast Cutoff, Box 15036
A8450KLB-DS, Rev. 1
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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