A8450KLBTR [ALLEGRO]
Fixed/Adjustable Positive Standard Regulator, 3 Output, 3.23V1 Min, 1.2V2 Min, 3.366V1 Max, 3.3V2 Max, PDSO24, MS-013AD, SOIC-24;
| 型号： | A8450KLBTR |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Fixed/Adjustable Positive Standard Regulator, 3 Output, 3.23V1 Min, 1.2V2 Min, 3.366V1 Max, 3.3V2 Max, PDSO24, MS-013AD, SOIC-24 光电二极管 输出元件 调节器 |
| 文件： | 总17页 (文件大小：576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A8450
Automotive Multioutput Voltage Regulator
Features and Benefits
▪ 6 V to 45 V input range
Description
The A8450 is a multioutput power supply intended for
▪ DC-to-DC buck converter with 5.7 V output
▪ Overcurrent protection with foldback, and undervoltage
lockout (UVLO)
automotive applications. The A8450 operates from a wide
input supply range and is designed to satisfy the requirements
of high ambient temperature environments.
▪ Dual 5 V outputs
Four regulated voltage outputs provide multiple options. The
3.3 Vregulator and the 1.2 to 3.3Vadjustable regulator can be
usedtopowermicrocontrollerorDSPcores,orforI/O,sensing,
and A-to-D conversion. Two 5 V outputs, one digital and the
other analog, feature output tracking within 0.5% of each other
over the operating temperature range. In addition, the analog
regulator is protected against short-to-battery conditions. All
four regulators feature foldback current limit protection.
▫ Digital 5 V ±2%, 200 mA
▫ Analog 5 V, 200 mA
▫ Short-to-supply protection on analog regulator
▫ Analog to digital regulator output tracking <0.5%
throughout operating temperature range
Continued on the next page…
The device can be enabled or disabled using two input pins.
The high voltage input, on the ENBAT pin, allows enable/
disable using an engine ignition or battery switch signal. The
logic-level input, on the ENB pin, allows enable/disable by
microcontroller or DSP signals.
Package: 24 pin SOIC (suffix LB)
When disabled, the A8450 draws less than 10 μA of current.
A POR (power-on-reset) block monitors the supply voltages
and provides a reset signal, with an adjustable delay, for
Continued on the next page…
Not to scale
Typical Application
H.V.
L1
D1
COUT
VIN D2
LX
ENBAT
V33
VBB
C8
C7
CIN
CP2
CP1
Q1
C3
R3
V33BD
CL33
GND
VCP
VREG11
GND
C10
A8450
GND
GND
VREG
V5D
ENB
CPOR
CLADJ
VADJBD
FB
C1
C2
C9
NFAULT
NPOR
V5A
Q2
R1
R4
VADJ
R2
C4
A8450-DS, Rev. 8
A8450
Automotive Multioutput Voltage Regulator
Features and Benefits (continued)
Description (continued)
microcontroller or DSP resets. A separate fault pin signals TSD
▪ 3.3 V linear regulator, with foldback current limit
▪ Adjustable 1.2 V to 3.3 V linear regulator, adjustable foldback
current limit
▪ Ignition switch enable; Sleep mode
▪ 100% duty cycle operation for low input voltages
▪ Power OK output
(thermal shutdown), 5 V analog short-to-supply, and 5 V analog or
digital undervoltage.
The A8450 is supplied in a 24-pin SOIC-W package (part number
suffix LB) with internally-fused power ground pins for enhanced
thermal performance. This provides an RθJA of 35°C/W on a 4-layer
board (see chart on p. 5). The lead (Pb) free version has 100% matte
tin leadframe plating.
▪ –40°C to 135°C ambient operating temperature range
Selection Guide
Part Number
Pb-free
Yes
Packing
Terminals
24
Package
SOIC-W surface mount, internally
fused power ground pins (6-7, 18-19)
A8450KLBTR-T
1000 pieces per 13-in. reel
Absolute Maximum Ratings
Parameter
Load Supply Voltage
Analog Output
Symbol
Conditions
Rating
– 40
Units
V
VBB
V5A
VBB pin
V5A pin
–1 to 45
–0.3 to 45
–0.3 to 6.5
–2 to VBB
–40 to 135
150
V
VENBAT
VENB
VLX
ENBAT pin input
ENB pin input
LX pin
V
Logic Input Signal
V
LX Voltage
V
Operating Temperature Range
Junction Temperature
Storage Temperature Range
TA
K range
°C
°C
°C
TJ(max)
Tstg
–55 to 150
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
Functional Block Diagram
D2
VIN
L1
C8
D1
C7
CIN
COUT
High
Voltage
Switch
LX
CP1
CP2
VCP
VBB
VREG
R3
CL33
VREG11
Buck Converter with
Switching Regulator
V33BD
V33
3.3 V Linear
Regulator Control
Q1
C10
Charge Pump
Soft Start
VBB
CPOK
VREG
C3
R4
ENBAT
ENB
High V
Protection
VREF
Internal
Reference
CLADJ
1.2 V to 3.3 V
Adjustable Linear
Regulator Control
VADJBD
FB
Q2
VADJ
C4
R1
R2
NPOR
VREG
V5D
5 V Digital Linear
Regulator
VUVLOREG
VUVLOADJ
VUVLO33
C1
5V Analog
CPOR
C9
Adjustable
Delay
Linear Regulator
and V5D to V5A
Tracking Control
Current
Limiting
POR Block
V5A
NFAULT
GND
C2
TSD Warning
Short-to-Supply
Protection
V5A Short to Supply
UVLO V5D, V5A
Fault
ID
Characteristics
1 μF, 25 V ceramic X7R
100 μF, 35 V low-ESR electrolytic
47 μF, 63 V electrolytic
Representative Device
UHC1V101M, Nichicon
C1, C2, C3, C4
COUT
CIN
0.1 μF, 50 V ceramic X7R (for 14 V applications), or
0.1 μF, 100 V ceramic X7R (for 42 V applications)
0.22 μF, 10 V X7R
C7, C8
C10
D1, D2
L1
1 A, 40 V Schottky (for 14 V applications)
100 μH, 1.2 A
EKO4, Sanken
D03316HT, Coilcraft
MPSW06
Q1, Q2 pass transistors npn transistor, hFE > 50
Allegro MicroSystems, LLC
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
ELECTRICAL CHARACTERISTICS at TA = –40ºC to 135°C, VBB = 6 to 45 V, VENB = 5 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min. Typ. Max. Units
Enabled mode: VENBAT or VENB = HIGH,
IOUT = 0 mA: VBB = 14 V
–
6
10
mA
Enabled mode: VENBAT or VENB = HIGH,
Supply Quiescent Current
IBB
–
–
10
–
15
10
mA
μA
V
I
OUT = 0 mA; VBB = 6 V
Disabled mode: VENBAT and VENB = LOW
ILOAD = 550 mA = ILOADV5D + ILOADV5A + ILOADV33
+ ILOADVADJ; VBB > 6.5 V
5.50
–
5.80
Regulated Output Voltage
VREG
Dropout: 6 V ≤ VBB < 6.5 V
TJ = 25°C
5.00
–
–
5.80
500
750
2.2
V
415
650
1.2
mΩ
mΩ
A
Buck Switch On-Resistance
Buck Switch Current Limit
RDSON
IDSLIM
tOFF
tSS
TJ = 135°C
–
1.0
DC-to-DC Fixed Off-Time
VBB = 14 V
VBB = 14 V
–
5
4.75
10
–
μs
Soft Start Time
15
ms
Logic Inputs
HIGH input level
2.7
–0.3
–
–
–
–
–
–
–
–
–
–
45
0.8
300
70
V
V
ENBAT Logic Input Voltage
ENBAT Input Current
VENBAT
LOW input level
HIGH input level, VENBAT = 45 V
HIGH input level, VENBAT = 14 V
LOW input level, VENBAT = 0.8 V
HIGH input level
μA
μA
μA
V
IENBAT
–
–1
2.7
–0.3
–
10
6.5
0.8
50
ENB Logic Input Voltage
ENB Input Current
VENB
IENB
LOW input level
V
HIGH input level, VENB ≥ 2.7 V
LOW input level, VENB ≤ 0.8 V
μA
μA
–1
10
Linear Regulator Outputs*
V5D Output Voltage
V5A Output Voltage
VOUTV5D 1 mA ≤ ILOADV5D ≤ 200 mA
VOUTV5A 1 mA ≤ ILOADV5A ≤ 200 mA
VOUTV33
4.9
4.9
5.0
5.0
5.1
5.1
V
V
V
V33 Output Voltage
3.234 3.300 3.366
50 mA ≤ ILOADV5A, ILOADV5D ≤ 200mA;
BB > 6.5 V
V5A to V5D Tracking
VTRACK
–25
–
25
mV
V
V5D Current Limit
V5A Current Limit
IOUTV5DLIM
IOUTV5ALIM
200
200
300
300
–
–
mA
mA
Base Drive Output Current
Feedback Voltage
IBD
VFB
IFB
1 V ≤ VOUTVADJ, VOUTV33 ≤ 4 V
5.0
10.0 16.0
1.20 1.24
mA
V
1.16
Feedback Input Bias Current
–400 –100 100
nA
Continued on next page
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
ELECTRICAL CHARACTERISTICS (continued) at TA = –40ºC to 135°C, VBB = 6 to 45 V, VENB = 5 V, unless
otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
mV
Protection
Fault asserted;
NFAULT, INPOR = 1 mA
NFAULT, NPOR Output Voltage
VERRON
–
–
400
I
NFAULT, NPOR Leakage Current
POR Delay
IERROFF
tPOR
VNFAULT, VNPOR = 5 V
C9 = 0.47 μF
V33 rising
–
65
–
1
135
3.10
3.05
–
μA
ms
V
100
2.95
2.90
80
2.80
2.75
–
V33 Undervoltage Threshold
V33 Hysteresis
VUVLOV33
VHYSV33
VUVLOV5
VHYSV5
V33 falling
V
mV
V
V5A, V5D rising
V5A, V5D falling
4.36
4.24
–
4.50
4.38
125
1.07
1.02
70
4.75
4.63
–
V5A, V5D Undervoltage Threshold
V5A, V5D Hysteresis
V
mV
V
VFB rising
VFB falling
At FB pin
1.02
0.97
–
1.12
1.07
–
VADJ Undervoltage Threshold
VUVLOVADJ
V
VADJ Hysteresis
VHYSVADJ
VOC
VUVLOVREG
TJTW
mV
mV
V
VADJ, V33 Overcurrent Threshold
VREG Undervoltage Threshold
Thermal Warning Threshold
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
175
4.94
–
200
5.15
160
175
15
225
5.36
–
TJ rising
°C
°C
°C
TJTSD
TJ rising
–
–
THYSTSD
Recovery period = TJTSD – TJTW
–
–
*Linear regulator output specifications are only valid when VREG is in regulation (VBB ≥ 6.5).
Power Dissipation Versus Ambient Temperature
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4-Layer PCB*
(RθJA = 35 ºC/W)
20
40
60
Ambient Temperature (°C)
*In still air; mounted on PCB based on JEDEC high-conductance standard PCB
80
100
120
140
160
(JESD51-7; High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages); data on other PCB types is provided on the Allegro Web site.
Allegro MicroSystems, LLC
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
Timing Diagrams
VREG
VHYSV33
VOUTV33
VUVLOV33
VHYSVADJ
VOUTVADJ
VUVLOVADJ
tPOR
VNPOR
tPOR
A B
Slope of V
and V
from A to B determined by I
and output capacitor (C3, C4).
OUTV33
OUTVADJ
LOAD
Figure 1a. NPOR fault due to undervoltage lockout on the V33 or FB pins
VBB
VREG
VUVLOVREG
VOUTV33
VUVLOV33
VREG Monitor
VOUTVADJ
VENBAT
VENB
VNPOR
tPOR
tPOR
POR event initiates
V33 can sustain regulation with normal load by bulk capacitor (COUT) on V
.
REG
Figure 1b. Power-off using VBB
+7 V
VCP
VBB > 6 V
VREG
VREG = 1.8 V
VOUTV5A/V5D
VUVLO(33)
VOUTV33
VOUTVADJ
VNPOR
VENBAT
VENB
ENBAT signals power-on
Charge pump ramping
tSS
exceeded; VADJ enabled
tPOR
Charge pump OK flag set
V
UVLOV33
ENB signals power-off
A
B
Slope of V
(which controls V
, V
OUTV33
, and V
) from A to B determined by I and COUT.
REG
OUTVADJ
LOAD
OUTV5A/V5D
Figure 1c. Power-on using ENBAT, followed by power-off using ENB
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115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
Load Transients Diagrams
VIN = 12 V; ILOAD = 100 mA; TA = 25°C; ac-coupled; C1, C2, C3 and C4 = 1 μF
ILOAD
3.3 V Regulator
90%
10%
tRISE
t (0.2 μs/Div.)
t (50 μs/Div.)
V5D Regulator
Adjustable Regulator, at 1.8 V*
t (50 μs/Div.)
t (50 μs/Div.)
*For the adjustable regulator, the transient load response
is improved as the voltage is reduced. This is due to the
V5A Regulator
ability of the regulator to provide more base drive (V
)
ADJBD
because of more available voltage. When the adjustable
regulator approaches 3.3 V, its transient load response is
equivalent to the response of the V33 regulator.
For all regulators, load transients can be improved by
increasing the output capacitance (C1, C2, C3, and C4).
In order to keep ESR down it is best to use ceramic type
capacitors. However, large values in ceramic type capacitors
are either not available or very expensive. If larger values are
needed, above 22 μF, electrolytic capacitors with low ESR
ratings can be used. Performance can be improved further
by adding a 1 μF ceramic in parallel with the electrolytic.
t (50 μs/Div.)
Allegro MicroSystems, LLC
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
Functional Description
Buck Converter with Switching Regulator. A current-
mode, variable frequency buck DC-to-DC converter and switch-
ing regulator are integrated in the A8450, as shown in figure 2.
This feature allows the device to efficiently handle power over a
wide range of input supply levels. The DC-to-DC converter out-
puts 5.7 V typical, and has an overcurrent limit of 1.2 A typical.
tOFF by VBB
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.75 μs
12 V
The converter employs a soft-start feature. This ramps the con-
verter output voltage and limits the maximum demand on VREG
by controlling the inrush current required at power-on to charge
the external capacitor, COUT, and any DC load.
2.05 μs
0.58 μs
6.02 V
11 V
An internal charge pump provides gate drive for the
N-channel MOSFET buck switch. A 100% duty cycle is imple-
mented when using low VBB input voltages.
5
7
9
11
13
15
At VBB lower than 12 V, off-time, tOFF, is reduced, as shown in
VBB (V)
figure 3. This reduction keeps the switching frequency, fPWM
,
within a reasonable range and lowers the ripple current. Lowering
the ripple current at low VBB levels prevents degradation of linear
regulator headroom due to VREG ripple voltage.
Figure 3. When VBB falls below 12 V, tOFF decreases
5VLinear Regulators. Two 5 V medium-power linear regulators
are provided. These low-dropout regulators feature foldback current
limitingforshort-to-groundprotection.Whenadirectshortisapplied
to the regulator output, either V5A or V5D, the current folds back
L1
100 μH
COUT
D1
100 μF
LX
VBB
Buck Converter
Buck Switch
tOFF
VCP
Switching
Regulator
Control
IDEMAND
IPEAK
ENB
Clock
Counter
1.2 A Limit
Soft Start
Ramp
Compensation
Generation
Error
Bandgap
1.22 V
Clamp
VREG
Figure 2. Buck converter with switching regulator
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115 Northeast Cutoff
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A8450
Automotive Multioutput Voltage Regulator
to 0 V at 50 mA, as shown in figure 4a. The voltage recovers to its where RCL (Ω) is the current-limiting resistor corresponding to
regulated output when the short is removed. that regulator (R3 for the 3.3 V regulator, and R4 for the adjustable
TheV5AandV5D regulators track each other during power-on, and regulator).WhenICLisexceeded,themaximumloadcurrentthrough
when the device is enabled and ramped up out of disabled mode, that regulator is folded back to 40% of ICL ±10%, as shown in figure
the regulators will start to track when VREG reaches approximately 4b. If current limiting is not needed, the CL33 and CLADJ pins
1.8 V. These regulators are guaranteed to track to within 0.5% of should be shorted to the VREG pin.
each other under normal operating conditions.
Disabled Mode. When the two input signal pins, ENBAT and
ENB, are pulled low, the A8450 enters disabled mode. This is a
sleep mode, in which all internal circuitry is disabled in order to
draw a minimal current from VBB. When either of these pins is
pulled high, the device is enabled. When emerging from disabled
mode, the buck converter switching regulator does not operate
until the charge pump has stabilized (≈300 μs).
3.3 V and Adjustable Linear Regulators. Two additional
linear regulators, one that outputs at 3.3 V, and another that has a
1.2 V to 3.3 V adjustable output, can be implemented using external
npn pass transistors. The output voltage of the adjustable regulator,
VOUTVADJ (V), is set by the values of the output resistors, R1 and
R2 (Ω). It can be calculated as
Enabled Mode. When one or both of the signal input pins,
ENBAT and ENB, are in the high state, the A8450 is enabled.
ENBAT is an edge-triggered enable (logic 1 ≥ 2.7 V), which is
used to enable the A8450 in response to a high-voltage signal,
such as from an automobile ignition or battery switch. In this
capacity, ENBAT is used only as a momentary switch to wake up
the device. If there is no need for a high-voltage signal, ENBAT
can be pulled low continuously.
VOUTVADJ = VFB (1+R1 ⁄ R2)
where VFB (V) is the voltage on the feedback pin, FB.
Additional pins, CL33 and CLADJ, are provided for setting cur-
rent limits. These are used to protect the external pass transis-
tors from a short-to-ground condition. The current limit setting,
ICL (mA), is calculated using the formula
ICL = VOC ⁄ RRCL
ENB is used to initiate the reset of the device. If ENBAT is pulled
5V Regulators Overcurrent Foldback
3.3 V and Adjustable Regulators Overcurrent Foldback
6
6
5
4
3
2
5
0.4
I
±10%
I
CL
CL
4
3
2
1
0
V
and V
OUTV33
OUTVADJ(max)
I
and I
OUTV5ALIM
OUTV5DLIM
V
OUTVADJ(min)
1
0
200
250
300
0
50
100
150
1600
0
1600
IOUT (mA)
IOUT (mA)
Figure 4a. Linear foldback to 50 mA. Foldback occurs at the typical
current limit for the 5 V regulator.
Figure 4b. Linear foldback to a percentage of ICL. Foldback occurs at
the current limit setting for the regulator.
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A8450
Automotive Multioutput Voltage Regulator
low, ENB acts as a single reset control.
converter switching regulator is disabled, and the VREG supply
begins to ramp down. The rate at which VREG decays is depen-
Diagnostics. An open drain output, through the NFAULT pin, is
pulled low to signal to a DSP or microcontroller any of the follow-
ing fault conditions:
dent on the total current draw, ILOAD, and value of the output
capacitors (C1, C2, C3, and C4).
• V5A, the 5 V analog regulator output, is shorted to supply
• VREG drops below its UVLO threshold, VUVLOVREG
.
• Either or both of the V5A and the V5D regulator outputs are
below their UVLO threshold, VUVLOV5
• During any normal power-on, VOUTVADJ falls below
VUVLOVADJ, triggering a POR.
• Device junction temperature, TJ, exceeds the Thermal Warning
threshold, TJTW
An open drain output, through the NPOR pin, is provided to signal a
ChargePump. ThechargepumpgeneratesavoltageaboveVBB in POR event to the DSP or microcontroller. The reset occurs after an
order to provide adequate gate drive for the N-channel buck switch.
A 0.1 μF ceramic monolithic capacitor, C7, should be connected
between the VCP pin and the VBB pin, to act as a reservoir to run
the buck converter switching regulator.
adjustable delay, tPOR, set by an external capacitor, C9, connected
to the CPOR pin. The value of tPOR (ms) is calculated using the
following formula
V
CPisinternallymonitoredtoensurethatthechargepumpisdisabled
tPOR = 2.13 105
C
CPOR
× ×
in the case of a fault condition. In addition, a 0.1 μF ceramic mono-
lithic capacitor, C8, should be connected between CP1 and CP2.
Power On Reset Delay. The POR block monitors the supply
voltages and provides a signal that can be used to reset a DSP or
microcontroller. A POR event is triggered by any of the following
conditions:
• Either V33 or VADJ is pulled below its UVLO threshold,
VUVLOV33 or VUVLOVADJ. This occurs if the current limit on either
regulator, VOC , is exceeded. It also occurs if the VREG voltage
where CCPOR (μF) is the value of the C9 capacitor.
A POR can be forced without a significant drop in the supply volt-
age, VREG, by pulsing low both the ENB and the ENBAT pins.
However, pulse duration should be short enough so that VREG does
not drop significantly.
Thermal Shutdown. When the device junction temperature, TJ,
is sensed to be at TJTSD (≈15°C higher than the thermal warning
temperature, TJTW), a fault is indicated at the NFAULT pin. At the
same time, a thermal shutdown circuit disables the buck converter,
protecting the A8450 from damage.
falls below VREGMON, due to current exceeding IDSLIM
.
• Both input signal pins, ENB and ENBAT, are pulled low.
This immediately pulls the NPOR pin low, indicating that the
device is beginning a power-off sequence. In addition, the buck
Allegro MicroSystems, LLC
115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
A8450
Automotive Multioutput Voltage Regulator
Application Information
Component Selection
VL1OFF = 5.8 + 0.8 + (0.550 0.400) = 6.821 V
×
IRIPPLE(max) = 6.821 4.75 ⁄ 100 = 0.324 A
Output Inductor (L1). This inductor must be rated to handle the
total load current, ILOAD. In addition, the value chosen must keep
the ripple current to a reasonable level. A typical selection is a
power inductor rated at 100 μH and 1.3 A.
×
VL1ON =14 – (0.550 0.750) – (0.550 0.400)
×
×
– 5.8 = 7.56 V
tON
= 0.324 100 ⁄ 7.56 = 4.3 μs
×
The worse case ripple current, IRIPPLE(max) (mA), can be calcu-
lated as
fPWM = 1/(4.3 + 4.75) = 111 kHz
IRIPPLE(max) = VL1OFF
t
⁄ LL1
OFF
In the case of a shorted output, the buck converter could reach
its internal current limit, IDSLIM, of 1.2 A typical. To ensure safe
operation, the ISAT rating for the selected inductor should be
greater than 1.4 A. However, if the external current limit resistors,
R3 and R4, selected for the 3.3 V and adjustable (1.2 V to 3.3 V)
×
where LL1 (μH) is the inductance for the selected component, and
VL1OFF is the voltage (V) through the inductor when the A8450 is
in the quiescent state
VL1OFF = VREG(max) + VD1 + (ILOAD R )
regulators, are rated such that the total inductor current, ILOAD,
×
L1
could never reach that internal current limit, then an inductor can
be selected that has an ISAT rating closer to the calculated output
current of the device, ILOAD, plus the maximum ripple current,
where VD1 (V) is the voltage drop on diode D1, ILOAD (mA) is
the total load current, and RL1 is the specified DC resistence (Ω)
for the selected inductor at its rated temperature.
IRIPPLE(max)
.
The frequency, fPWM (Hz), of the switching regulator in the buck
converter can then be estimated by
Higher inductor values can be chosen to lower IRIPPLE. This may
be an option if it is desired to increase the total maximum current
that is drawn from the switching regulator. The maximum total
current available, ILOAD (mA), is calculated as
fPWM = 1/(tON + tOFF
where tON (μs) is calculated as
tON = IRIPPLE(max)
)
ILOAD = IDSLIM – (IRIPPLE(max) ⁄ 2)
L
⁄ VL1ON
×
L1
Catch Diode (D1). The Schottky catch diode should be rated to
handle 1.2 times the maximum load current, ILOAD, because the
duty cycle at low input voltages, VBB, can be very close to 100%.
The voltage rating should be higher than the maximum input
voltage, VBB(max), expected during any operating condition.
and VL1ON (V) as
VL1ON =VBB –(ILOAD
R
)
×
DSON(max)
– (ILOAD R )–V
×
L1
REG(max)
Example
VREG Output Capacitor (COUT). Voltage ripple in the
VREG output is the main consideration when selecting the
VREG output capacitor, COUT. The peak-to-peak output voltage
ripple, VRIPPLE(p-p) (mV), is calculated as
Given a typical application with VBB = 14 V, tOFF = 4.75 μs, and
ILOAD = 550 mA. (Note that the value for tOFF is constant for VBB
> 12 V, as shown in figure 3.)
Given also a 100 μH power inductor rated at 400 mΩ for 125ºC.
(Note that temperature ratings for inductors may include self-
heating effects. If a 125ºC rating includes a self-heating tempera-
ture rise of 20ºC at maximum current, then the actual ambient
temperature, TA, cannot exceed 105ºC.)
VRIPPLE(p-p) = IRIPPLE ESR
×
COUT
with ESR in ohms. It is recommended that the maximum level of
VRIPPLE(p-p) be less than 200 mV.
For electrolytic output capacitors, a low-ESR type is recom-
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A8450
Automotive Multioutput Voltage Regulator
mended, with a minimum voltage rating of 10 V. However,
because ESR decreases with voltage, the most cost-effective
choice may be a capacitor with a higher voltage rating.
Adjusting Pass Transistor Power Dissipation
Transistors are manufactured in a wide variety of package types,
and the thermal dissipation efficiencies of the packages can vary
greatly. In general, increasing thermal efficiency can also increase
cost substantially. Selecting the package to closely match operat-
ing conditions is important to optimizing application design and
cost.
Regulator Output Capacitors (C3 and C4). The output
capacitors used with the 3.3 V regulator (C3) and the 1.2 V to 3.3
V adjustable regulator (C4), should be 1 μF or greater X7R (5%
tolerance) ceramic or equivalent capacitors, with a maximum
capacitance change of ±15% over a temperature range of –55ºC
to 125ºC.
Even when using a thermally-enhanced package, it remains dif-
ficult to provide high current to a load at high ambient operating
temperatures. Depending on the load requirements, using drop
resistors, as shown in figure 5, may be necessary to protect the
pass transistor from overheating.
The ESR of these capacitors does not affect the outputs of the
corresponding regulators. If a greater capacitance is used, the
regulators have improved ripple rejection at frequencies greater
than 100 kHz.
The output current-limiting resistors, RCL (corresponding to R3
and R4), will drop between 175 mV and 225 mV at the highest
current output, ILOAD. Assuming no additional resistance, the
voltage dropped, VDROP (mV), on each pass transistor is
Pass Transistors (Q1 and Q2). The pass transistors used to
implement the 3.3V regulator and the 1.2V to 3.3V adjustable
regulator must ensure the following:
VDROP = VREG – VRCL – VOUT
• Stable operation. The cutoff frequency for the control loops of
the regulators is 100 kHz. Transistors must be selected that have
gain bandwidth product, fT (kHz), and beta, hFE (A), ratings
such that
This can be substituted into the power dissipation formula
PD = VDROP
I
LOAD
×
fT ⁄ hFE > 100 kHz
Given a typical application where VREG = 5.8 V, VRCL = 0.175 V,
VOUT = 3.3 V, and ILOAD = 350 mA, then PD is approximately
814 mW.
• Adequate base drive. It is acceptable to use a lower level of
current gain, hFE, for lower total load currents, ILOAD. The lower
limit for ILOAD is limited by the minimum base current for the
A8450, IBD(min), and the minimum hFE of the pass transistor,
such that
VREG
ILOAD = IBD(min)
h
FE(min)
×
RCL
CL33
Note that hFE is dependant on operating temperature. Lower
temperatures decrease hFE, affecting the current capacity of the
transistor.
ILOAD
A8450
• Packaged for sufficient power dissipation. In order to ensure
appropriate thermal handling, the design of the application must
take into consideration the thermal characteristics of the PCB
where the A8450 and pass transistors are mounted, the ambient
temperature, and the power dissipation characteristics of the
transistor packages. In general, the power dissipation, PD (mW),
is estimated by
V33BD
VDROP
VCE
VOUTV33
V33
PD = (VREG – VOUT
)
I
LOAD
×
For a typical application where VREG = 5.8 V, VOUT = 2.5 V,
and ILOAD = 190 mA
Figure 5. Placement of drop resistors for thermal protection; example
shown is for the 3.3 V regulator.
P = (5.8 – 2.5) 190 = 627 mW
×
D
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A8450
Automotive Multioutput Voltage Regulator
PD can be used to estimate the minimum required operating
temperature rating for the transistor. The ability of a package to
dissipate heat is approximated by the thermal resistance from
the die (junction) to the ambient environment, RθJA (°C/W). This
includes the significant effect of dissipation through the package
leads and the PCB on which the transistor is mounted, and the
state of the ambient air. The typical rating for a DPAK package is
32˚C/W. The expected self-induced temperature rise in the pack-
Assume a typical ILOAD = 350 mA. However, under normal oper-
ating conditions, the current limit set by RCL would be higher
than the expected normal current, so assume ILOAD(lim) = 0.400 A
and RCL = 44 Ω. Substituting to determine VRCL
VRCL = 0.400 0.44 = 0.176 V
×
We can now solve for RRDROP and then VDROP
age, ∆T (°C), given PD = 0.814 W, is approximated as
VREG – VRCL – (ILOAD
R
RDROP) – VCE ≥ VOUT
×
J
∆TJ = PD
RθJA= 26°C
×
5.8 – 0.176 – (0.4
RRDROP) – 1 ≥ 3.30 V
×
therefore
and
In automotive applications, where under-the-hood ambient tem-
peratures can exceed 125˚C, the pass transistor would have to be
rated to provide the required beta at ≥151°C, plus a safe operat-
ing margin.
RRDROP ≥ 3.31 Ω
VRDROP = 0.4 3.31 = 1.3 V
×
For a selected transistor, VCE can change depending on current,
temperature, and transistor beta. Typically, transistors are rated
at a minimum beta at a defined VCE. However, VCE should be
calculated with some margin so there is always enough headroom
to drive the device at the desired load.
Using four 0.25 W resistors valued at 14.7 ꢀ in parallel will drop
1.3 volts.
Using the drop resistors as calculated above, the power dissipa-
tion in the transistor, PD (W) is reduced to
To provide an operating margin, or if a lower-value RCL is
required, voltage drop resistors, RDROP, can be added to the
circuit, between the RCL and the transistor (figure 5). It is also
PD = ILOAD(lim) (VREG – VRCL – VRDROP – VOUT
)
×
= 0.400 (5.8 – 0.176 – 1.3 – 3.3) = 0.410 W
×
important to consider tolerances in resistance values and VREG
.
and
The level of VREG(min) is 5.6 V, at which level PD is reduced, but
also the voltage available for VCE is reduced. Calculating maxi-
mum and minimum voltage drops is useful in determining the
values of the drop resistors.
∆TJ = PD
RθJA= 13°C
×
The power dissipated in the transistor is significantly reduced. A
transistor in a power package with an RθJA of 32˚C/W at 400 mA
(a 50 mA margin) undergoes a temperature rise of 13˚C with the
drop resistors, as opposed to a similar transistor at 350 mA rising
26˚C without drop resistors. At high output currents, properly
selected drop resistors can protect the external pass transitor from
overheating.
The required drop resistor value, RRDROP, can be determined in
terms of the voltage drops across each component of the circuit,
as shown in the following formula
VDROP ≥ VOUT
where
VDROP = VREG – VRCL – VRDROP – VCE
A8450 Power Dissipation. The A8450 is designed to operate
in applications with high ambient temperatures. The total power
dissipated in the device must be considered in conjunction with
the thermal dissipation capabilities of the PCB where the A8450
is mounted, as well as the capabilities of the device package
itself.
Assume that VREG(max) = 5.8 V and VOUT(max) = 3.3 V. Assume
also that TA = 125°C, and VCE = 1V (as specified for the
MPSW06 npn transistor, beta = 300 at 125˚C).
In order to determine the resistance values for the current-limiting
and drop resistors, VRCL and VDROP can be expressed in terms of
ILOAD(lim)
The ability of a package to dissipate heat is approximated by
the thermal resistance from the die (junction) to the ambient
environment, RθJA (°C/W). This includes the significant effect
of dissipation through the package leads and the PCB on which
the package is mounted, and the temperature of the ambient air.
VRCL = (ILOAD(lim)
R
)
×
CL
VRDROP = (ILOAD(lim)
R
)
×
RDROP
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A8450
Automotive Multioutput Voltage Regulator
Test results for this 24-lead SOIC are approximately 35 °C/W
when mounted on a high-thermally conductive PCB (based on
the JEDEC standard PCB, having four layers with buried copper
areas).
It is dependent on IOUTVADJ and the hFE of the pass transistor.
Overcurrent Protection
The current supplied by the 3.3 V and the 1.2 to 3.3 V adjust-
able regulators is limited to ICL. Current above ICL is folded back
linearly, as shown in figure 4b. In the case of a shorted load,
the collector current is reduced to 40% of ICL ±10%, to ensure
protection of the pass transistors. After the short is removed, the
voltage recovers to its regulated level.
The total power that can be applied to the device, PD(lim) (W), is
affected by the maximum allowable device junction temperature,
TJ(max) (°C), RθJA, and the ambient air temperature, TA (°C), as
shown in the following formula
PD(lim) = (TJ(max) – TA) ⁄ RθJA
The maximum power dissipated in the transistor during a shorted
load condition is:
PD(lim) can be estimated based on several parameters, using the
following formula
PD(lim) = PD(Ibias) + PD(V5A) + PD(V5D) + PD(buckdc)
+ PD(buckac) + PD(BD)
PD ≈ (VREG – VOUT
)
(0.4
I )
× × CL
where VOUT = 0 V.
Low Input Voltage Operation
where
PD(Ibias) = VBB
I
BB
×
When the charge pump has ramped enough to enhance the buck
switch, the buck converter switching regulator is enabled. This
occurs at VBB ≈ 5.7 V. At that point, the duty cycle, DC, of the
A8450 can be forced to 100% until VIN is high enough to allow
the switch to begin operating normally. The point at which nor-
mal switching begins is dependent on ambient temperature, TA.
Increases in TA cause RDSON to increase. Other significant factors
are ILOAD, VREG, the ESR of the output inductor (L1), and the
forward biasing voltage for the output Schottky diode (D1).
PD(V5A) = (VREG – 5 V)
I
LOAD(V5A)
×
×
PD(V5D) = (VREG – 5 V)
I
LOAD(V5D)
2
PD(buckdc)= ILOAD
R
DC
×
×
DSON(TJmax)
PD(buckac)= ILOAD [V (5 ns ⁄ 14 V)
V
]
0.5f
PWM
×
× ×
BB
BB
PD(BD) = IV33BD(max) (VREG – 4V)+IVADJBD(max)
×
(VREG–VADJ – 0.7V)
×
and
Regulator Bypass
ILOAD = ILOAD(V33) +ILOAD(VADJ) +ILOAD(V5D) +ILOAD(V5A)
Some applications may not require the use of all four regulators
provided in the A8450. For the regulators that are not used, the
corresponding external components are not needed.
RDSON is a function of TJ. For the purposes of estimating PD(lim)
the relationship can be assumed to be linear throughout the
practical TJ operating range (see test conditions for RDSON in the
Electrical Characteristics table).
,
If either or both of the two 5 V regulators are not required by the
application, bypass an unused regulator by not connecting its
output terminal, V5D or V5A. Also, the corresponding output
capacitor, C1 or C2, is not used.
DC (duty cycle) is a function of VBB and VREG. This can be
calculated precisely as
DC = VREG(off) ⁄ (VREG(on) + VREG(off)
A rough estimate for DC is
DC = (VREG + VLX) ⁄ VBB
)
For the 3.3 V regulator and the 1.2 V to 3.3 V adjustable regula-
tor, if either or both are not needed, the corresponding external
components are not used. In addition, if the 3.3 V regulator is not
used, CL33 and V33 are not connected. If the adjustable regula-
tor is not used, CLADJ and FB are not connected. However, to
ensure stability of the A8450, the base drive pin, V33BD or VAD-
JBD, of any unused regulator must be shorted to VREG.
IV33BD(max) is the maximum current drawn on the V33BD pin. It
is dependent on IOUTV33 and the hFE of the pass transistor.
IADJBD(max) is the maximum current drawn on the VADJBD pin.
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A8450
Automotive Multioutput Voltage Regulator
Pin-Out Diagram
Buck
Converter
VBB
CP2
1
2
3
4
5
6
7
8
9
24 LX
23 ENBAT
22 V33
Charge
Pump
CP1
VCP
V33BD
CL33
GND
21
20
19
18
VREG11
GND
3.3 V
Soft
Start Lin Reg
Control
GND
GND
5 V
Dig/Anlg
Lin Reg
ENB
VREG
V5D
17
16
15
14
13
CPOR
CLADJ 10
NFAULT
NPOR
V5A
1.2 V to
3.3 V
Lin Reg
Control
11
12
VADJBD
FB
5 V Reg
Track
Control
Terminal List Table
Name
Description
Number
VBB
CP2
CP1
Supply input
1
2
3
Charge pump capacitor, positive side
Charge pump capacitor, negative side
Charge pump output used to drive N-channel buck converter
transistor
VCP
4
VREG11
GND
Internal reference
5
Power ground
6
GND
Power ground
7
ENB
Logic control
8
CPOR
CLADJ
VADJBD
FB
Connection for POR adjustment
Current limit for adjustable regulator
Base drive for adjustable regulator pass transistor
Feedback for adjustable regulator
5 V analog regulator output
Power on Reset logic output
Diagnostic output; open drain; low during fault condition
5 V digital regulator output
DC-to-DC converter supply output
Power ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V5A
NPOR
NFAULT
V5D
VREG
GND
GND
Power ground
CL33
V33BD
V33
Current limit for 3.3 V regulator
Base drive for 3.3 V regulator pass transistor
3.3 V regulator output
ENBAT
LX
High voltage logic control
Buck converter switching regulator output
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A8450
Automotive Multioutput Voltage Regulator
Package LB, 24-Pin SOICW
15.40±0.20
4° ±4
24
24
+0.07
–0.06
2.20
0.27
10.30±0.33
7.50±0.10
9.60
A
2
+0.44
–0.43
0.84
0.25
1
1
2
0.65
1.27
PCB Layout Reference View
B
24X
C
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.10
C
0.41 ±0.10
1.27
2.65 MAX
0.20 ±0.10
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
A
B
Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Leads 6 and 7, and 18 and 19 are internally fused ground leads, for enhanced
thermal dissipation.
Allegro MicroSystems, LLC
115 Northeast Cutoff
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A8450
Automotive Multioutput Voltage Regulator
Revision History
Revision
Revision Date
Description of Revision
Rev. 8
January 30, 2012 Update product availability
Copyright ©2004-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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