A6276SLWTR-T [ALLEGRO]
16-BIT SERIAL-INPUT, CONSTANT CURRENT LATCHED LED DRIV ER; 16位串行输入，恒流锁存LED DRIV ER
| 型号： | A6276SLWTR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | 16-BIT SERIAL-INPUT, CONSTANT CURRENT LATCHED LED DRIV ER |
| 文件： | 总14页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6276
16-BIT SERIAL-INPUT, CONSTANT-
CURRENT LATCHED LED DRIVER
The A6276 is specifically designed for LED-display applications.
Each BiCMOS device includes a 16-bit CMOS shift register, accom-
panying data latches, and 16 npn constant-current sink drivers. Except
for package style and allowable package power dissipation, the device
options are identical.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V logic supply, typical serial
data-input rates are up to 20 MHz. The LED drive current is deter-
mined by the user’s selection of a single resistor. A CMOS serial data
output permits cascade connections in applications requiring additional
drive lines. For inter-digit blanking, all output drivers can be disabled
with an ENABLE input high. Similar 8-bit devices are available as the
A6275EA and A6275ELW.
Three package styles are provided: through-hole DIP (suffix A),
surface-mount SOIC (suffix LW) and TSSOP with exposed thermal pad
(suffix LP). Under normal applications, a copper lead frame and low
logic-power dissipation allow the dual in-line package to sink maxi-
mum rated current through all outputs continuously over the operating
temperature range (90 mA, 0.75 V drop, +85°C).
A6276ELW
LOGIC
S UPPLY
V
GR OUND
1
2
3
4
24
23
22
21
20
DD
S E R IAL
DATA IN
I
O
R
E XT
R E GULATOR
S E R IAL
DATA OUT
CLOCK
CK
L
LATCH
E NABLE
OUTPUT
E NABLE
OE
R E GIS TE R
LATCHE S
OUT
0
OUT
15
5
6
19 OUT
OUT
14
1
18
17
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
7
8
2
3
4
5
6
7
13
12
11
10
9
9
16 OUT
15 OUT
14 OUT
13 OUT
10
11
12
8
Dwg. PP-029-11
Note that three packages offered are electrically
identical and share a common terminal number as-
signment.
FEATURES
■ To 90 mA Constant-Current Outputs
■ Under-Voltage Lockout
■ Low-Power CMOS Logic and Latches
■ High Data Input Rate
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD ....................... 7.0 V
Output Voltage Range,
VO ............................. -0.5 V to +17 V
Output Current, IO ........................ 90 mA
Ground Current, IGND .............. 1475 mA
Input Voltage Range,
VI .................... -0.4 V to VDD + 0.4 V
Package Power Dissipation,
PD ..................................... See Graph
Operating Temperature Range,
■ Functional Replacement for TB62706BN/BF
Selection Guide
Ambient
Temperature (°C)
–40 to 85
Part Number Pb-free*
Package
Packing
A6276EA-T
A6276ELP-T
Yes
Yes
Yes
Yes
Yes
Yes
Yes
24-pin DIP
24-pin TSSOP
15 per tube
62 per tube
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–20 to 85
–20 to 85
A6276ELPTR-T
A6276ELW-T
A6276ELWTR-T
A6276SLW-T
A6276SLWTR-T
24-pin TSSOP 4000 per reel
24-pin SOICW 31 per tube
24-pin SOICW 1000 per reel
24-pin SOICW 31 per tube
24-pin SOICW 1000 per reel
TA ............................. -40°C to +85°C
Storage Temperature Range,
*Pb-based variants are being phased out of the product line. The variants cited in this
footnote are in production but have been determined to be NOT FOR NEW DESIGN.
This classification indicates that sale of this device is currently restricted to existing
customer applications. The variants should not be purchased for new design applica-
tions because obsolescence in the near future is probable. Samples are no longer
available. Status change: May 1, 2006. These variants include:A6276EA, A6276ELW,
A6276ELWTR, A6276SA, A6276SLW, and A6276SLWTR.
TS ........................... -55°C to +150°C
Caution: These CMOS devices have input static
protection (Class 2) but are still susceptible
to damage if exposed to extremely high static
electrical charges.
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
4.0
3.5
24-PIN TSSOP*, RθJA = 32°C/W
3.0
2.5
2.0
1.5
1.0
0.5
0
24-PIN DIP, RθJA = 50°C/W
24-LEAD SOIC, RθJA = 85°C/W
25
50
75
100
125
150
°
AMBIENT TEMPERATURE IN
C
*Mounted on single-layer, two-sided PCB, with 3.8 in2 copper each side;
additional information on Allegro Web site
FUNCTIONAL BLOCK DIAGRAM
V
DD
LOGIC
UVLO
SUPPLY
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
LATCH
ENABLE
OUTPUT ENABLE
(ACTIVE LOW)
GROUND
MOS
BIPOLAR
R
I
EXT
O
REGULATOR
OUT OUT OUT
OUT
N
0
1
2
Dwg. FP-013-3
115 Northeast Cutoff, Box 15036
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, 2003 Allegro MicroSystems, Inc.
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
V
DD
V
DD
IN
IN
Dwg. EP-010-11
Dwg. EP-010-12
OUTPUT ENABLE (active low)
LATCH ENABLE
V
V
DD
DD
OUT
IN
Dwg. EP-063-6
Dwg. EP-010-13
CLOCK and SERIAL DATA IN
SERIAL DATA OUT
TRUTH TABLE
Serial
Data Clock
Input Input I
Shift Register Contents
Serial Latch
Data Enable
Output Input
Latch Contents
Output
Enable
Input
Output Contents
... I
I
I
...
I
I
I
I
I
...
I
I
I
I
I
I
N-1 N
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
...
...
...
...
...
R
R
R
X
R
R
R
R
X
1
1
2
2
2
3
N-2 N-1
N-1
N-1
N
R
N-2 N-1
X
R
X
R
1
N-1
N-1
N
N
X
L
R
R
R
...
...
...
R
R
1
2
3
N-1
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
P
P
... P
... H
P
H
1
2
3
N
1
2
3
N-1
N
1
2
3
N-1
N
X
H
H H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
3
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Limits
Characteristic
Symbol
VDD
Test Conditions
Operating
Min.
4.5
Typ. Max. Unit
Supply Voltage Range
Under-Voltage Lockout
5.0
–
5.5
4.0
V
V
VDD(UV)
IO
VDD = 0 → 5 V
3.4
Output Current
VCE = 0.7 V, REXT = 250 Ω
VCE = 0.7 V, REXT = 470 Ω
64.2
34.1
75.5
40.0
86.8
45.9
mA
mA
(any single output)
Output Current Matching
(difference between any
∆IO
0.4 V ≤ VCE(A) = VCE(B) ≤ 0.7 V:
REXT = 250 Ω
–
–
±1.5
±1.5
±6.0
±6.0
%
%
two outputs at same VCE
)
REXT = 470 Ω
Output Leakage Current
Logic Input Voltage
ICEX
VIH
VIL
VOH = 15 V
–
0.7VDD
GND
–
1.0
–
5.0
VDD
0.3VDD
0.4
–
µA
V
–
V
SERIAL DATA OUT
Voltage
VOL
VOH
RI
IOL = 500 µA
–
V
IOH = -500 µA
4.6
150
100
–
–
V
Input Resistance
Supply Current
ENABLE Input, Pull Up
LATCH Input, Pull Down
REXT = open, VOE = 5 V
REXT = 470 Ω, VOE = 5 V
REXT = 250 Ω, VOE = 5 V
REXT = 470 Ω, VOE = 0 V
REXT = 250 Ω, VOE = 0 V
300
200
0.8
6.0
11
13
22
600
400
1.4
8.0
15
kΩ
kΩ
mA
mA
mA
mA
mA
IDD(OFF)
3.5
6.5
7.0
10
IDD(ON)
20
32
Typical Data is at VDD = 5 V and is for design information only.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.
Limits
Characteristic
Symbol
Test Conditions
CLOCK-OUTn
Min.
–
Typ. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay Time
tpHL
350
350
350
40
1000
1000
1000
–
LATCH-OUTn
–
ENABLE-OUTn
–
CLOCK-SERIAL DATA OUT
CLOCK-OUTn
–
Propagation Delay Time
tpLH
–
300
300
300
40
1000
1000
1000
–
LATCH-OUTn
–
ENABLE-OUTn
–
CLOCK-SERIAL DATA OUT
90% to 10% voltage
10% to 90% voltage
–
Output Fall Time
Output Rise Time
tf
tr
150
150
350
300
1000
600
RECOMMENDED OPERATING CONDITIONS
Characteristic
Supply Voltage
Output Voltage
Output Current
Symbol
VDD
VO
Conditions
Min.
Typ. Max.
Unit
V
4.5
5.0
1.0
–
5.5
4.0
–
V
IO
Continuous, any one output
SERIAL DATA OUT
–
90
mA
mA
mA
V
IOH
–
–
–
-1.0
IOL
SERIAL DATA OUT
–
1.0
Logic Input Voltage
Clock Frequency
VIH
0.7VDD
-0.3
–
–
VDD + 0.3
0.3VDD
10
VIL
–
V
fCK
Cascade operation
–
MHz
www.allegromicro.com
5
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
B
CLOCK
A
SERIAL
DATA IN
DATA
50%
t
p
SERIAL
DATA OUT
50%
DATA
D
E
LATCH
ENABLE
50%
OUTPUT
ENABLE
LOW = ALL OUTPUTS ENABLED
t
p
HIGH = OUTPUT OFF
50%
DATA
OUT
N
A. Data Active Time Before Clock Pulse
LOW = OUTPUT ON
Dwg. WP-029-1
(Data Set-Up Time), tsu(D) ............................. 50 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................. 20 ns
C. Clock Pulse Width, tw(CK) .................................. 50 ns
D. Time Between Clock Activation
HIGH = ALL OUTPUTS DISABLED (BLANKED)
and Latch Enable, tsu(L) ............................... 100 ns
E. Latch Enable Pulse Width, tw(L) ...................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................... 4.5 μs
50%
OUTPUT
ENABLE
t
F
pLH
t
t
r
f
90%
NOTE: Timing is representative of a 10 MHz clock. Sig-
nificantly higher speeds are attainable.
50%
10%
OUT
N
DATA
t
pHL
Max. Clock Transition Time, tr or tf ....................... 10 μs
Dwg. WP-030-1A
Serial data present at the input is transferred to the shift
register on the logic 0-to-logic 1 transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data in-
formation towards the SERIAL DATA OUTPUT. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches continue to accept new data as
long as the LATCH ENABLE is held high. Applications where
the latches are bypassed (LATCH ENABLE tied high) will
require that the OUTPUT ENABLE input be high during serial
data entry.
When the OUTPUT ENABLE input is high, the output sink
drivers are disabled (OFF). The information stored in the latches
is not affected by the OUTPUT ENABLE input. With the OUT-
PUT ENABLE input low, the outputs are controlled by the state
of their respective latches.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
A6276EA A6276ELW
100
80
100
VCE = 1 V
VCE = 0.7 V
CE = 1 V
V
80
VCE = 2 V
VCE = 3 V
VCE = 2 V
60
60
VCE = 3 V
VCE = 4 V
VCE = 4 V
40
40
T
A
= +25°C
T
A
= +25°C
V
DD = 5 V
V
DD = 5 V
20
0
20
0
RθJA = 75°C/W
RθJA = 50°C/W
0
20
40
60
80
100
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-6
Dwg. GP-062-11
100
80
100
V
CE = 1 V
V
CE = 0.7 V
80
60
40
V
CE = 2 V
V
CE = 1 V
VCE = 3 V
V
CE = 2 V
60
V
CE = 3 V
VCE = 4 V
40
VCE = 4 V
T
V
A
= +50°C
T
V
A
= +50°C
DD = 5 V
20
0
DD = 5 V
20
0
R
θ
JA = 50°C/W
RθJA = 75°C/W
0
20
40
60
80
100
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-10
Dwg. GP-062-7
www.allegromicro.com
7
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6276EA A6276ELW
100
100
80
VCE = 0.4 V
V
CE = 0.7 V
VCE = 1 V
80
VCE = 0.7 V
VCE = 1 V
VCE = 2 V
60
60
VCE = 2 V
VCE = 3 V
VCE = 3 V
40
40
VCE = 4 V
VCE = 4 V
T
V
A
= +85°C
T
V
A
= +85°C
DD = 5 V
20
0
DD = 5 V
20
0
RθJA = 75°C/W
RθJA = 50°C/W
0
20
40
60
80
100
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-8
Dwg. GP-062-9
TYPICAL CHARACTERISTICS
60
40
20
TA = +25°C
REXT = 500 Ω
0
0
2.0
0.5
1.0
1.5
VCE IN VOLTS
Dwg. GP-063
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6276ELP
100
VCE = 1 V
80
VCE = 2 V
VCE = 3 V
60
VCE = 4 V
40
T
A
= +25ı°C
VDD = 5 V
20
RˇθJA = 40°ıC/W
0
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
100
VCE = 1 V
80
VCE = 2 V
VCE = 3 V
60
VCE = 4 V
40
TA
= +50ı°C
VDD = 5 V
20
RˇθJA = 40ı°C/W
0
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
9
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
TERMINAL DESCRIPTION
Terminal No.
Terminal Name
GND
Function
1
2
Reference terminal for control logic.
Serial-data input to the shift-register.
SERIAL DATA IN
CLOCK
3
Clock input terminal for data shift on rising edge.
Data strobe input terminal; serial data is latched with high-level input.
The 16 current-sinking output terminals.
4
LATCH ENABLE
OUT0-15
5-20
21
OUTPUT ENABLE
When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
22
23
SERIAL DATA OUT
REXT
CMOS serial-data output to the following shift-register.
An external resistor at this terminal establishes the output current for all sink
drivers.
24
SUPPLY
(VDD) The logic supply voltage (typically 5 V).
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
10
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
Applications Information
The load current per bit (IO) is set by the external resistor
(REXT) as shown in the figure below.
diode (VZ), or a series string of diodes (approximately
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
provide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
White
Blue
Green
Yellow
Amber
Red
3.5 – 4.0 V
3.0 – 4.0 V
1.8 – 2.2 V
2.0 – 2.1 V
1.9 – 2.65 V
1.6 – 2.25 V
1.2 – 1.5 V
Infrared
Pattern Layout. This device has a common logic-
ground and power-ground terminal. If ground pattern lay-
out contains large common-mode resistance, and the volt-
age between the system ground and the LATCH ENABLE
or CLOCK terminals exceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
Package Power Dissipation (PD). The maximum al-
lowable package power dissipation is determined as
PD(max) = (150 - TA)/RθJA
.
The actual package power dissipation is
PD(act) = DC • (VCE • IO • 16) + (VDD • IDD) ,
where DC is the duty cycle.
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage re-
ducer (VDROP) should be used.
Load Supply Voltage (VLED). These devices are de-
signed to operate with driver voltage drops (VCE) of
0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is recom-
mended to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
VDROP = VLED - VF - VCE
with VDROP = Io • RDROP for a single driver, or a Zener
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
11
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
A6276EA
Dimensions in Inches
(controlling dimensions)
0.014
0.008
24
13
0.430
MAX
0.300
BSC
0.280
0.240
1
12
0.100
BSC
0.070
0.045
0.005
MIN
1.280
1.230
0.210
MAX
0.015
MIN
0.150
0.115
0.022
0.014
Dwg. MA-001-24 in
Dimensions in Millimeters
(for reference only)
0.355
0.204
24
13
10.92
MAX
7.11
6.10
7.62
BSC
1
6
7
12
2.54
BSC
1.77
1.15
0.13
MIN
32.51
31.24
5.33
MAX
0.39
MIN
3.81
2.93
0.558
0.356
Dwg. MA-001-24 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 15 devices.
www.allegromicro.com
12
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
A6276ELW
Dimensions in Inches
(for reference only)
24
13
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
BSC
0° TO 8°
0.6141
0.5985
0.0926
0.1043
Dwg. MA-008-24A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
24
13
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
15.60
15.20
2.65
2.35
Dwg. MA-008-24A mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
13
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
A6276ELP
7.9 .311
7.7 .303
8º
0º
A
24
B
0.20 .008
0.09 .004
4.5 .177
4.3 .169
B
0.75 .030
0.45 .018
3
.118
NOM
6.6 .260
6.2 .244
A
2
1
REF
.039
1
4.32 .170
NOM
0.25 .010
C
SEATING PLANE
GAUGE PLANE
24X
SEATING
PLANE
0.10 [.004]
C
0.30 .012
0.19 .007
0.65 .026
24X
1.20 .047
MAX
0.10 [.004] M
C
A
B
0.15 .006
0.00 .000
0.45 .018
NOM
0.65 .026
NOM
2
NOM
.079
24
Preliminary dimensions, for reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
5.8 .228
NOM
A
B
C
Terminal #1 mark area
3
NOM
.118
C
Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling
0.40 .016
REF
Reference land pattern layout (reference IPC7351
TSOP65P640-24M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
1
2
4.32 .170
NOM
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