A6277SLW-T [ALLEGRO]
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| 型号： | A6277SLW-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | 暂无描述 驱动器 输入元件 |
| 文件： | 总12页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6277
8-BIT SERIAL-INPUT, CONSTANT-
CURRENT LATCHED LED DRIVER
PRELIMINARY INFORMATION
(Subject to change without notice)
July 20, 2000
The A6277x is specifically designed for LED-display applications.
Each BiCMOS device includes an 8-bit CMOS shift register, accompa-
nying data latches, and eight npn constant-current sink drivers. Two
package styles and two operating temperature ranges are available.
A6277ELW
LOGIC
GROUND
LOGIC
SUPPLY
V
1
2
3
4
5
6
20
19
18
17
DD
SERIAL
DATA IN
I
O
R
EXT
REGULATOR
SERIAL
DATA OUT
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V logic supply, typical serial
data-input rates are up to 20 MHz. The LED drive current is deter-
mined by the user’s selection of a single resistor. A CMOS serial data
output permits cascade connections in applications requiring additional
drive lines. For inter-digit blanking, all output drivers can be disabled
with an ENABLE input high. In addition, a HIGH/LOW function
enables full selected current with the application of a logic low, or 50%
selected current with the application of a logic high.
CK
L
CLOCK
1
2
LATCH
ENABLE
SERIAL
DATA OUT
FF
HIGH/LOW
(CURRENT)
OUTPUT
ENABLE
OE 16
POWER
GROUND
POWER
GROUND
15
SUB
SUB
REGISTER
LATCHES
14
OUT
7
OUT
0
7
8
13 OUT
OUT
1
6
12
OUT
2
OUT
9
5
4
11 OUT
OUT
3
10
The first character of the part number suffix determines the device
operating temperature range. Suffix ‘E–’ is for -40°C to +85°C, and
suffix ‘S–’ is -20°C to +85°C. Two package styles are provided for
through-hole DIP (suffix ‘–A’) or surface-mount SOIC (suffix ‘–LW’)
applications. The copper lead frame and low logic-power dissipation
allow the dual in-line package to sink 122 mA through all outputs
continuously over the operating temperature range (1.0 V drop,
+85°C).
Dwg. PP-029-17A
Note that the A6277EA (DIP) and the A6277ELW
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD ...................... 7.0 V
Output Voltage Range,
VO ............................ -0.5 V to +24 V
Output Current, IO ....................... 150 mA
FEATURES
I To 150 mA Constant-Current Outputs
I 24 V Outputs
Input Voltage Range,
VI .................... -0.4 V to VDD + 0.4 V
I Under-Voltage Lockout
Package Power Dissipation,
I Low-Power CMOS Logic and Latches
I High Data Input Rate
PD ..................................... See Graph
Operating Temperature Range, TA
Suffix ‘S-’ ................ -20°C to +85°C
I Similar to Toshiba TD62715FN
I High/Low Output Current Function
Suffix ‘E-’ ................ -40°C to +85°C
Storage Temperature Range,
TS ........................... -55°C to +150°C
Caution: These CMOS devices have input
static protection (Class 2) but are still suscep-
tible to damage if exposed to extremely high
static electrical charges.
Always order by complete part number, e.g., A6277EA .
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
2.5
SUFFIX 'A', R
= 55°C/W
θJA
2.0
1.5
1.0
0.5
0
SUFFIX 'LW', R
= 70°C/W
θJA
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GP-018-1
FUNCTIONAL BLOCK DIAGRAM
V
DD
LOGIC
UVLO
SUPPLY
CLOCK
SERIAL
DATA IN
SERIAL DATA
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
FF
OUT
2
SERIAL DATA
LATCH
ENABLE
OUT
1
OUTPUT ENABLE
(ACTIVE LOW)
LOGIC
GROUND
MOS
BIPOLAR
HIGH/LOW
(CURRENT)
POWER
GROUND
R
EXT
I
POWER
GROUND
O
REGULATOR
SUB
OUT OUT OUT
OUT
N
Dwg. FP-013-7
0
1
2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
2
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
V
V
DD
DD
IN
IN
Dwg. EP-010-7
Dwg. EP-010-6
OUTPUT ENABLE (active low)
LATCH ENABLE and HIGH/LOW
V
V
DD
DD
OUT
IN
Dwg. EP-063-1
Dwg. EP-010-5
CLOCK and SERIAL DATA IN
SERIAL DATA OUT
TRUTH TABLE
Serial
Data Clock
Input Input
Shift Register Contents
Serial Latch
Data EnableEnable
Output Input
Latch Contents
Output
Input
Output Contents
...
I
I
I
...
I
I
I
I
I
...
I
I
I
I
I
I
I
N-1 N
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
...
...
...
...
...
R
R
R
X
R
R
R
1
1
2
2
2
3
N-2 N-1
N-1
N-1
R
N-2 N-1
X
R
X
R
R
1
N-1
N-1
N
N
N
X
X
L
R
R
R
...
...
...
R
R
1
2
3
N-1
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
P
P
... P
... H
P
H
1
2
3
N
1
2
3
N-1
N
1
2
3
N-1
N
X
H
H H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
3
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VH/L = VDD = 5 V (unless otherwise noted).
Limits
Characteristic
Symbol
VDD
Test Conditions
Operating
Min.
4.5
3.4
100
34
Typ. Max. Unit
Supply Voltage Range
Under-Voltage Lockout
5.0
–
5.5
4.0
140
48
V
V
VDD(UV)
IO
VDD = 0 to 5 V
Output Current
VCE = 1.0 V, REXT = 160 Ω
VCE = 0.4 V, REXT = 470 Ω
120
42
mA
mA
(any single output)
Output Current Matching
(difference between any
∆IO
0.4 V ≤ VCE(A) = VCE(B) ≤ 1.0 V:
REXT = 160 Ω
–
–
1.5
1.5
6.0
6.0
%
%
two outputs at same VCE
)
REXT = 470 Ω
Output Leakage Current
Logic Input Voltage
ICEX
VIH
VIL
VOH = 20 V
–
0.7VDD
–
1.0
–
5.0
–
µA
V
–
0.3VDD
0.4
–
V
SERIAL DATA OUT Voltage
(SDO1 & SDO2)
VOL
VOH
RI
IOL = 1.0 mA
–
–
V
IOH = -1.0 mA
4.6
150
100
–
–
V
Input Resistance
Supply Current
ENABLE input, pull up
LATCH & HIGH/LOW inputs, pull down
REXT = open, VOE = 5 V
REXT = 470 Ω, VOE = 5 V
REXT = 160 Ω, VOE = 5 V
REXT = 470 Ω, VOE = 0 V
REXT = 160 Ω, VOE = 0 V
300
270
0.8
6.5
17
10
27
600
400
1.6
9.5
22
kΩ
kΩ
mA
mA
mA
mA
mA
IDD(OFF)
3.5
14
IDD(ON)
5.0
20
15
40
Typical Data is at VDD = 5 V and is for design information only.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.
Limits
Characteristic
Symbol
Test Conditions
CLOCK-OUTn
Min.
–
Typ. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay Time
tpHL
350
350
350
80
1000
1000
1000
110
LATCH-OUTn
–
ENABLE-OUTn
–
CLOCK-SERIAL DATA OUT1
CLOCK-OUTn
–
Propagation Delay Time
tpLH
–
300
400
380
80
1000
1000
1000
110
LATCH-OUTn
–
ENABLE-OUTn
–
CLOCK-SERIAL DATA OUT2
90% to 10% voltage
10% to 90% voltage
–
Output Fall Time
Output Rise Time
tf
tr
150
150
250
250
1000
600
RECOMMENDED OPERATING CONDITIONS
Characteristic
Supply Voltage
Output Voltage
Output Current
Symbol
VDD
VO
Conditions
Min.
Typ. Max.
Unit
V
4.5
5.0
1.0
–
5.5
4.0
–
V
IO
Continuous, any one output
SERIAL DATA OUT
–
150
-1.0
1.0
mA
mA
mA
V
IOH
–
–
IOL
SERIAL DATA OUT
–
–
Logic Input Voltage
Clock Frequency
VIH
0.7VDD
–
–
VIL
–
–
–
0.3VDD
10
V
fCK
Cascade operation
–
MHz
www.allegromicro.com
5
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
B
CLOCK
A
SERIAL
DATA IN
DATA
50%
t
p
SERIAL
50%
DATA
DATA
DATA OUT.
1
t
p
SERIAL
50%
E
DATA OUT.
2
D
LATCH
ENABLE
50%
OUTPUT
ENABLE
LOW = ALL OUTPUTS ENABLED
t
p
HIGH = OUTPUT OFF
50%
DATA
LOW = OUTPUT ON
Dwg. WP-029-3
OUT
N
HIGH = ALL OUTPUTS DISABLED (BLANKED)
50%
OUTPUT
ENABLE
t
F
dis(BQ)
t
t
t
r
en(BQ)
f
90%
OUT
N
DATA
10%
Dwg. WP-030-1
A. Data Active Time Before Clock Pulse
Information present at any register is transferred to the
(Data Set-Up Time), tsu(D) .......................................... 60 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 20 ns
C. Clock Pulse Width, tw(CK) ............................................... 50 ns
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches will continue to accept new
data as long as the LATCH ENABLE is held high. Applica-
tions where the latches are bypassed (LATCH ENABLE tied
high) will require that the OUTPUT ENABLE input be high
during serial data entry.
D. Time Between Clock Activation
and Latch Enable, tsu(L) ............................................ 100 ns
E. Latch Enable Pulse Width, tw(L) ................................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs
NOTE – Timing is representative of a 10 MHz clock.
Significantly higher speeds are attainable.
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
— Max. Clock Transition Time, tr or tf .............................. 10 µs
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
A6277xA
A6277xLW
V
CE = 1 V
V
CE = 1 V
140
120
100
140
120
100
VCE = 2 V
V
CE = 2 V
V
CE = 3 V
VCE = 3 V
VCE = 4 V
80
60
40
80
60
40
VCE = 4 V
T
V
A
= +25°C
T
V
A
= +25°C
DD = 5 V
DD = 5 V
RθJA = 55°C/W
RθJA = 70°C/W
20
0
20
0
0
20
40
60
80
100
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-17
Dwg. GP-062-16
V
CE = 1 V
140
120
100
140
120
100
VCE = 1 V
VCE = 2 V
VCE = 2 V
V
CE = 3 V
VCE = 3 V
80
60
40
80
60
40
VCE = 4 V
VCE = 4 V
T
V
A
= +50°C
T
V
A
= +50°C
DD = 5 V
DD = 5 V
Rθ
JA = 55°C/W
Rθ
JA = 70°C/W
20
0
20
0
0
20
40
60
80
100
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-15
Dwg. GP-062-14
www.allegromicro.com
7
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6277xA A6277xLW
V
CE = 0.7 V
140
120
100
140
120
100
V
CE = 0.7 V
V
CE = 1 V
V
CE = 1 V
VCE = 2 V
V
CE = 2 V
VCE = 3 V
80
60
40
80
60
40
V
CE = 3 V
VCE = 4 V
VCE = 4 V
T
V
A
= +85°C
T
V
A
= +85°C
DD = 5 V
DD = 5 V
RθJA = 55°C/W
RθJA = 70°C/W
20
0
20
0
0
20
40
60
80
100
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
DUTY CYCLE IN PER CENT
Dwg. GP-062-13
Dwg. GP-062-12
TYPICAL CHARACTERISTICS
60
40
20
T = +25°C
A
REXT = 470 Ω
0
0
2.0
0.5
1.0
1.5
VCE IN VOLTS
Dwg. GP-063-1
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
TERMINAL DESCRIPTION
Terminal No.
Terminal Name
LOGIC GROUND
SERIAL DATA IN
CLOCK
Function
1
2
3
4
5
Reference terminal for control logic.
Serial-data input to the shift-register.
Clock input terminal for data shift on rising edge.
LATCH ENABLE
Data strobe input terminal; serial data is latched with high-level input.
HIGH/LOW
(CURRENT)
Logic low for 100% of programmed current level;
logic high for 50% of programmed current level.
6
7-14
15
POWER GROUND
OUT0-7
Ground.
The eight current-sinking output terminals.
Ground.
POWER GROUND
OUTPUT ENABLE
16
When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
17
18
SERIAL OUT2
SERIAL OUT1
CMOS serial-data output (on clock falling edge).
CMOS serial-data output (on clock rising edge)
to the following shift-registers.
19
20
REXT
An external resistor at this terminal establishes the output current for all sink
drivers.
LOGIC SUPPLY
(VDD) The logic supply voltage. Typically 5 V.
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
9
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
Applications Information
The load current per bit (IO) is set by the external resistor
(REXT) as shown in the figure below.
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
provide supply voltages as low as 3.3 V.
140
VCE = 0.7 V
120
100
80
60
40
20
0
For reference, typical LED forward voltages are:
Blue
3.0 – 4.0 V
1.8 – 2.2 V
2.0 – 2.1 V
1.9 – 2.65 V
1.6 – 2.25 V
1.2 – 1.5 V
Green
Yellow
Amber
Red
Infrared
Pattern Layout. This device has separate logic-ground
and power-ground terminals. If ground pattern layout
contains large common-mode resistance, and the voltage
between the system ground and the LATCH ENABLE or
CLOCK terminals exceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
5 k
2 k
CURRENT-CONTROL RESISTANCE, REXT IN OHMS
3 k
100
200
300
500
700
1 k
Dwg. GP-061-1
Package Power Dissipation (PD). The maximum allow-
able package power dissipation is determined as
PD(max) = (150 - TA)/RθJA
.
The actual package power dissipation is
PD(act) = dc(VCE • IO • 8) + (VDD • IDD).
V
LED
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage
reducer (VDROP) should be used.
V
DROP
Load Supply Voltage (VLED). These devices are de-
signed to operate with driver voltage drops (VCE) of 0.4 V
to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is recom-
mended to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
V
F
V
CE
Dwg. EP-064
VDROP = VLED - VF - VCE
with VDROP = Io • RDROP for a single driver, or a Zener
diode (VZ), or a series string of diodes (approximately
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
A6277EA
Dimensions in Inches
(controlling dimensions)
0.014
0.008
20
11
0.430
MAX
0.280
0.240
0.300
BSC
1
10
0.100
0.070
0.045
0.005
BSC
MIN
1.060
0.980
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
0.355
0.204
20
11
10.92
MAX
7.11
6.10
7.62
BSC
1
10
2.54
1.77
1.15
0.13
BSC
MIN
26.92
24.89
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-20 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative
3. Lead thickness is measured at seating plane or below.
www.allegromicro.com
11
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
A6277ELW
Dimensions in Inches
(for reference only)
20
11
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
BSC
0° TO 8°
0.5118
0.4961
0.0926
0.1043
Dwg. MA-008-20 in
0.0040 MIN.
20
Dimensions in Millimeters
(controlling dimensions)
11
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
13.00
12.60
2.65
2.35
Dwg. MA-008-20 mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
12
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