A3977KLPTR [ALLEGRO]
Stepper Motor Controller, 2.5A, NMOS, PDSO28, EXPOSED PAD, TSSOP-28;
| 型号： | A3977KLPTR |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Stepper Motor Controller, 2.5A, NMOS, PDSO28, EXPOSED PAD, TSSOP-28 电动机控制 光电二极管 |
| 文件： | 总17页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A3977
Microstepping DMOS Driver with Translator
FEATURES AND BENEFITS
DESCRIPTION
• ±2.5 A, 35 V output rating
The A3977 is a complete microstepping motor driver, with
built-in translator. It is designed to operate bipolar stepper
motors in full-, half-, quarter-, and eighth-step modes, with
outputdrivecapabilityof35Vand±2.5A.TheA3977includes
afixedoff-timecurrentregulatorthathastheabilitytooperatein
slow-,fast-,ormixed-decaymodes.Thiscurrent-decaycontrol
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
• Low RDS(on) outputs, 0.28 Ω source, 0.22 Ω sink typical
• Automatic current decay mode detection/selection
• 3.0 to 5.5 V logic supply voltage range
• Mixed, fast, and slow current decay modes
• Home output
• Synchronous rectification for low power dissipation
• Internal UVLO and thermal shutdown circuitry
• Crossover-current protection
The translator is the key to the easy implementation of the
A3977.SimplyinputtingonepulseontheSTEPinputdrivesthe
motor one step (two logic inputs determine if it is a full-, half-,
quarter-, or eighth-step). There are no phase-sequence tables,
high-frequencycontrollines,orcomplexinterfacestoprogram.
The A3977 interface is an ideal fit for applications where a
complex microprocessor is unavailable or over-burdened.
Package: 28-pin TSSOP (suffix LP) with
Exposed Thermal Pad
Internalsynchronous-rectificationcontrolcircuitryisprovided
to improve power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis,undervoltagelockout(UVLO)andcrossover-current
protection. Special power-up sequencing is not required.
The A3977 is supplied in a thin (<1.2 mm), 28-pin TSSOP
with an exposed thermal pad (suffix LP). The A3977 is a lead
(Pb) free, with 100% matte tin leadframe plating.
Not to scale
Pin-out Diagram
A3977-DS, Rev. 12
A3977
Microstepping DMOS Driver with Translator
SPECIFICATIONS
Selection Guide
Ambient Temperature, TA
Part Number
Packing
Package
(°C)
A3977SLPTR-T
4000 per reel
28-pin TSSOP
–20 to 85
Absolute Maximum Ratings
Characteristic
Symbol
VBB
Notes
Rating
Units
Load Supply Voltage
35
V
V
V
V
V
V
Logic Supply Voltage
VDD
7.0
–0.3 to VDD+ 0.3
–1.0 to VDD+ 1
VDD
Pulsed, tw > 30 ns
Pulsed, tw < 30 ns
Logic Input Voltage Range
VIN
Reference Voltage
Sense Voltage (DC)
VREF
VSENSE
0.5
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions,
do not exceed the specified current rating or a junction
temperature of 150°C.
Output Current
IOUT
±2.5
A
Range K
Range S
–40 to 125
–20 to 85
150
ºC
ºC
ºC
ºC
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
TJ(max)
T
stg
–55 to 150
Thermal Characteristics
Characteristic
Symbol
Test Conditions*
Value
Units
Package Thermal Resistance
RθJA
Package LP, on 4-layer PCB based on JEDEC standard
28
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
VREG
CP2
CP1
LOGIC
LOAD
SUPPLY
VCP
SUPPLY
2 V
UVLO
AND
CHARGE
PUMP
REGULATOR
BANDGAP
VDD
FAULT
REF.
VBB1
SUPPLY
REF
RC1
DMOS H BRIDGE
DAC
SENSE1
VCP
+
-
OUT1A
OUT1B
PWM LATCH
BLANKING
MIXED DECAY
PWM TIMER
4
STEP
DIR
SENSE1
VBB2
RESET
MS1
DMOS H BRIDGE
MS2
HOME
SLEEP
OUT2A
OUT2B
SR
ENABLE
VPFD
PWM TIMER
PFD
PWM LATCH
BLANKING
4
MIXED DECAY
RC2
+
-
SENSE2
DAC
Dwg. FP-050-2
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Pin-out Diagram and Terminal List Table
LP Package, 28-Pin TSSOP Pin-out Digram
Terminal List Table
Terminal
Number
Terminal
Number
Terminal Name
Terminal Description
Terminal Name
Terminal Description
GND
SENSE1
HOME
DIR
–
1
2
3
4
–
5
Analog and Power Ground
Sense Resistor for Bridge 1
Logic Output
VBB2, the Load Supply for
Bridge 2
LOAD SUPPLY2
15
SR
RESET
OUT2B
NC
16
17
18
–
Logic Input
Logic Input
Logic Input
DMOS H Bridge 2 Output B
No (internal) Connection
Logic Input
OUT1A
NC
DMOS H Bridge 1 Output A
No (internal) Connection
Mixed Decay Setting
STEP
VREG
PGND
GND
19
20
21*
–
PFD
Regulator Decoupling
Power Ground
Analog Input for Fixed Offtime
– Bridge 1
RC1
6
GND
AGND
REF
–
7*
8
Analog and Power Ground
Analog Ground
Analog and Power Ground
Reservoir Capacitor
Charge Pump Capacitor
Charge Pump Capacitor
No (internal) Connection
DMOS H Bridge 1 Output B
Logic Input
VCP
22
23
24
–
Gm Reference Input
CP1
Analog Input for Fixed Offtime
– Bridge 2
CP2
RC2
9
NC
LOGIC SUPPLYNC
10
–
VDD, the Logic Supply Voltage
No (internal) Connection
DMOS H Bridge 2 Output A
Logic Input
OUT1B
ENABLE
SLEEP
25
26
27
NC
OUT2A
MS2
11
12
13
14
–
Logic Input
VBB1, the Load Supply for
Bridge 1
LOAD SUPPLY1
28
MS1
Logic Input
*AGND and PGND on the TSSOP package must be connected together exter-
nally.
SENSE2
GND
Sense Resistor for Bridge 2
Analog and Power Ground
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Maximum Power Dissipation, P
D(max)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
H
i
g
(
h
R
-
K
2
θ
J
P
A
=
C
B
8
º
C
/
W
)
(
R
θ
J
A
=
3
2
º
C
/
W
)
20
40
60
80
100
120
140
160
Temperature (°C)
Table 1: Microstep Resolution Truth Table
MS1
L
MS2
L
Resolution
Full Step (2 Phase)
Half Step
H
L
L
H
Quarter Step
Eighth Step
H
H
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted)
Characteristic
Output Drivers
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Operating
8.0
0
–
–
35
35
V
V
Load Supply Voltage Range
Output Leakage Current
Output On Resistance
VBB
During sleep mode
VOUT = VBB
–
<1.0
<1.0
0.28
0.22
–
20
µA
µA
Ω
IDSS
VOUT = 0 V
–
-20
0.335
0.265
1.4
Source driver, IOUT
=
-2.5 A
–
RDS(on)
Sink driver, IOUT = 2.5 A
Source diode, IF = -2.5 A
Sink diode, IF = 2.5 A
fPWM < 50 kHz
–
Ω
–
V
Body Diode Forward Voltage
VF
–
–
1.4
V
–
–
8.0
mA
mA
µA
Motor Supply Current
IBB
Operating, outputs disabled
Sleep mode
–
–
6.0
–
–
20
Control Logic
Logic Supply Voltage Range
VDD
VIN(1)
VIN(0)
IIN(1)
Operating
3.0
5.0
–
5.5
V
V
0.7VDD
–
0.3VDD
20
Logic Input Voltage
–
-20
-20
500*
0.7VDD
–
–
V
VIN = 0.7VDD
VIN = 0.3VDD
<1.0
<1.0
–
µA
µA
kHz
V
Logic Input Current
IIN(0)
20
Maximum STEP Frequency
HOME Output Voltage
fSTEP
VOH
–
IOH = -200 µA
–
–
VOL
IOL = 200 µA
–
0.3VDD
1200
46
V
Blank Time
tBLANK
toff
Rt = 56 kΩ, Ct = 680 pF
Rt = 56 kΩ, Ct = 680 pF
700
30
–
950
38
ns
µs
V
Fixed Off Time
PFDH
PFDL
0.6V
–
DD
Mixed Decay Trip Point
–
0.21V
–
V
DD
Ref. Input Voltage Range
Reference Input Current
V
Operating
0
–
0
–
–
–
V
V
REF
DD
I
–
±3.0
±10
±5.0
±5.0
800
–
µA
%
REF
V
V
V
= 2 V, Phase Current = 38.27%
= 2 V, Phase Current = 70.71%
= 2 V, Phase Current = 100.00%
–
REF
REF
REF
Gain (G ) Error (note 3)
m
E
–
%
G
–
%
Crossover Dead Time
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
t
SR enabled
100
–
475
165
15
2.7
0.10
–
ns
°C
°C
V
DT
T
J
∆T
–
–
J
V
Increasing V
2.45
0.05
–
2.95
–
UVLO
∆V
DD
V
UVLO
f
< 50 kHz
12
mA
mA
µA
PWM
Logic Supply Current
I
Outputs off
Sleep mode
–
–
10
DD
–
–
20
* Operation at a step frequency greater than the specified minimum value is possible but not warranteed.
NOTES:
1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. E = ([V
/8] – V
)/(V
/8)
G
REF
SENSE
REF
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
FUNCTIONAL DESCRIPTION
Step Input (STEP)
Device Operation
The A3977 is a complete microstepping motor driver with built
in translator for easy operation with minimal control lines. It
is designed to operate bipolar stepper motors in full-, half-,
quarter- and eighth-step modes. The current in each of the two
output full-bridges, all N-channel DMOS, is regulated with fixed
off-time pulse-width modulated (PWM) control circuitry. The
full-bridge current at each step is set by the value of an external
current sense resistor (RS), a reference voltage (VREF), and the
DACs output voltage controlled by the output of the translator.
A low-to-high transition on the STEP input sequences the transla-
tor and advances the motor one increment. The translator controls
the input to the DACs and the direction of current flow in each
winding. The size of the increment is determined by the state of
inputs MS1 and MS2 (see table 1).
Microstep Select (MS1 and MS2)
Input terminals MS1 and MS2 select the microstepping format per
table 1. Changes to these inputs do not take effect until the STEP
command (see figure).
At power up, or reset, the translator sets the DACs and phase
current polarity to initial home state (see figures for home-state
conditions), and sets the current regulator for both phases to
mixed-decay mode. When a step command signal occurs on the
STEP input the translator automatically sequences the DACs to
the next level (see table 2 for the current level sequence and cur-
rent polarity). The microstep resolution is set by inputs MS1 and
MS2 as shown in table 1. If the new DAC output level is lower
than the previous level the decay mode for that full-bridge will
be set by the PFD input (fast, slow, or mixed decay). If the new
DAC level is higher or equal to the previous level then the decay
mode for that full-bridge will be slow decay. This automatic
current-decay selection will improve microstepping performance
by reducing the distortion of the current waveform due to the
motor BEMF.
Direction Input (DIR)
The state of the DIRECTION input will determine the direction
of rotation of the motor.
Internal PWM Current Control
Each full-bridge is controlled by a fixed off-time PWM current-
control circuit that limits the load current to a desired value
(ITRIP). Initially, a diagonal pair of source and sink DMOS
outputs are enabled and current flows through the motor winding
and RS. When the voltage across the current-sense resistor equals
the DAC output voltage, the current-sense comparator resets the
PWM latch, which turns off the source driver (slow-decay mode)
or the sink and source drivers (fast- or mixed-decay modes).
The maximum value of current limiting is set by the selection
of RS and the voltage at the VREF input with a transconductance
function approximated by:
Reset Input (RESET)
The RESET input (active low) sets the translator to a predefined
home state (see figures for home state conditions) and turns off
all of the DMOS outputs. The HOME output goes low and all
STEP inputs are ignored until the RESET input goes high.
ITRIPmax = VREF/8RS
The DAC output reduces the VREF output to the current-sense
comparator in precise steps (see table 2 for % ITRIPmax at each
step).
Home Output (HOME)
The HOME output is a logic output indicator of the initial state of
the translator. At power up the translator is reset to the home state
(see figures for home state conditions).
I
TRIP = (% ITRIPmax/100) x ITRIPmax
It is critical to ensure that the maximum rating (0.5 V) on the
SENSE terminal is not exceeded. For full-step mode, VREF can
be applied up to the maximum rating of VDD, because the peak
sense value is 0.707 x VREF/8. In all other modes VREF should not
exceed 4 V.
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Fixed Off-Time
Shutdown
The internal PWM current-control circuitry uses a one shot to
control the time the drivers remain off. The one shot off-time,
toff, is determined by the selection of an external resistor (RT) and
capacitor (CT) connected from the RC timing terminal to ground.
The off-time, over a range of values of CT = 470 pF to 1500 pF
and RT = 12 kΩ to 100 kΩ is approximated by:
In the event of a fault (excessive junction temperature, or low
voltage on VCP) the outputs of the device are disabled until the
fault condition is removed. At power up, and in the event of
low VDD, the undervoltage lockout (UVLO) circuit disables the
drivers and resets the translator to the HOME state.
Sleep Mode (SLEEP)
t
off = RTCT
An active-low control input used to minimize power consump-
tion when not in use. This disables much of the internal circuitry
including the output DMOS, regulator, and charge pump. A logic
high allows normal operation and startup of the device in the
home position. When coming out of sleep mode, wait
1 ms before issuing a STEP command to allow the charge pump
(gate drive) to stabilize.
RC Blanking
In addition to the fixed off-time of the PWM control circuit, the
CT component sets the comparator blanking time. This function
blanks the output of the current-sense comparator when the
outputs are switched by the internal current-control circuitry.
The comparator output is blanked to prevent false over-current
detection due to reverse recovery currents of the clamp diodes,
and/or switching transients related to the capacitance of the load.
The blank time tBLANK can be approximated by:
Percent Fast Decay Input (PFD)
When a STEP input signal commands a lower output current
from the previous step, it switches the output current decay to
either slow-, fast-, or mixed-decay depending on the voltage level
at the PFD input. If the voltage at the PFD input is greater than
0.6 VDD then slow-decay mode is selected. If the voltage on the
PFD input is less than 0.21 VDD then fast-decay mode is selected.
Mixed decay is between these two levels. This terminal should be
decoupled with a 0.1 µF capacitor.
t
BLANK = 1400CT
Charge Pump. (CP1 and CP2)
The charge pump is used to generate a gate supply greater than
VBB to drive the source-side DMOS gates. A 0.22 µF ceramic
capacitor should be connected between CP1 and CP2 for pumping
purposes. A 0.22 µF ceramic capacitor is required between VCP
and VBB to act as a reservoir to operate the high-side DMOS
devices.
Mixed Decay Operation
If the voltage on the PFD input is between 0.6VDD and 0.21VDD
the bridge will operate in mixed-decay mode depending on the
step sequence (see figures). As the trip point is reached, the
device will go into fast-decay mode until the voltage on the RC
terminal decays to the voltage applied to the PFD terminal. The
time that the device operates in fast decay is approximated by:
,
VREG
This internally generated voltage is used to operate the sink-side
DMOS outputs. The VREG terminal should be decoupled with a
0.22 µF capacitor to ground. VREG is internally monitored and
in the case of a fault condition, the outputs of the device are
disabled.
t
FD = RTCTIn (0.6VDD/VPFD)
After this fast decay portion, tFD, the device will switch to slow-
decay mode for the remainder of the fixed off-time period.
Enable Input (ENABLE)
This active-low input enables all of the DMOS outputs. When
logic high the outputs are disabled. Inputs to the translator (STEP,
DIRECTION, MS1, MS2) are all active independent of the
ENABLE input state.
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Synchronous Rectification
Active Mode
When a PWM off-cycle is triggered by an internal fixed off-time
cycle, load current will recirculate according to the decay mode
selected by the control logic. The A3977 synchronous rectifica-
tion feature will turn on the appropriate MOSFETs during the
current decay and effectively short out the body diodes with the
low RDS(on) driver. This will reduce power dissipation signifi-
cantly and eliminate the need for external Schottky diodes for
most applications.
When the SR input is logic low, active mode is enabled and
synchronous rectification will occur. This mode prevents reversal
of the load current by turning off synchronous rectification when
a zero current level is detected. This prevents the motor winding
from conducting in the reverse direction.
Disabled Mode
When the SR input is logic high, synchronous rectification is
disabled. This mode is typically used when external diodes are
required to transfer power dissipation from the A3977 package to
the external diodes.
The synchronous rectification can be set in either active mode or
disabled mode.
A. Minimum Command Active Time Before Step Pulse (Data Set-Up Time)
B. Minimum Command Active Time After Step Pulse (Data Hold Time)
C. Minimum STEP Pulse Width
D. Minimum STEP Low Time
E. Maximum Wake-Up Time
200 ns
200 ns
1.0 µs
1.0 µs
1.0 ms
Figure 1: Timing Requirements
(TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground)
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
APPLICATIONS INFORMATION
Current Sensing
Layout.
The printed wiring board should use a heavy ground plane.
To minimize inaccuracies caused by ground-trace IR drops in
sensing the output current level, the current-sense resistor (RS)
should have an independent ground return to the star ground of
the device. This path should be as short as possible. For low-
value sense resistors the IR drops in the printed wiring board
For optimum electrical and thermal performance, the driver
should be soldered directly onto the board.
The load supply terminal, VBB, should be decoupled with an
electrolytic capacitor (>47 µF is recommended) placed as close to sense resistor’s traces can be significant and should be taken
the device as possible.
into account. The use of sockets should be avoided as they can
introduce variation in RS due to their contact resistance.
To avoid problems due to capacitive coupling of the high dv/dt
switching transients, route the bridge-output traces away from the Allegro MicroSystems recommends a value of RS given by
sensitive logic-input traces. Always drive the logic inputs with a
RS = 0.5/ITRIPmax
low source impedance to increase noise immunity.
Thermal Protection
Grounding
Circuitry turns off all drivers when the junction temperature
reaches 165°C, typically. It is intended only to protect the device
from failures due to excessive junction temperatures and should
not imply that output short circuits are permitted. Thermal
shutdown has a hysteresis of approximately 15°C.
A star ground system located close to the driver is recommended.
The 44-lead PLCC has the analog ground and the power ground
internally bonded to the power tabs of the package (leads 44, 1, 2,
11 – 13, 22 – 24, and 33 – 35).
On the 28-lead TSSOP package, the analog ground (lead 7) and
the power ground (lead 21) must be connected together exter-
nally. The copper ground plane located under the exposed thermal
pad is typically used as the star ground.
Allegro MicroSystems, LLC
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Table 2: Step Sequencing (DIR = H)
Phase 1 Current
[%Itripmax]
Phase 2 Current
[%Itripmax]
Step Angle
(º)
Full Step #
Half Step #
Quarter Step #
Eighth Step #
1
1
1
100.00
98.08
92.39
83.15
70.71*
55.56
38.27
19.51
0.00
0.00
19.51
38.27
55.56
70.71*
83.15
92.39
98.08
100.00
98.08
92.39
83.15
70.71
55.56
38.27
19.51
0.00
0
2
11.25
22.50
33.75
45*
2
3*
4
3
4
1*
2*
3
4
5
6
7
8
5*
6
56.25
67
7
8
78.75
90
5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-19.51
-38.27
-55.56
-70.71
-83.15
-92.39
-98.08
-100.00
-98.08
-92.39
-83.15
-70.71
-55.56
-38.27
-19.51
0.00
101.25
112.50
123.75
135
6
2
3
4
7
146.25
157.50
168.75
180
8
9
-19.51
-38.27
-55.56
-70.71
-83.15
-92.39
-98.08
-100.00
-98.08
-92.39
-83.15
-70.71
-55.56
-38.27
-19.51
191.25
202.50
213.75
225
10
11
12
13
14
15
16
236.25
247.50
258.75
270
19.51
38.27
55.56
70.71
83.15
92.39
98.08
281.25
292.50
303.75
315
326.25
337.50
348.75
*Home state; HOME output low.
Allegro MicroSystems, LLC
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Figure 2: Full-Step Operation
MS1 = MS2 = L, DIR = H
The vector addition of the output currents at any step is 100%.
Allegro MicroSystems, LLC
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Figure 3: Half-Step Operation
MS1 = H, MS2 = L, DIR = H
The mixed-decay mode is controlled by the percent fast decay
voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD
then slow-decay mode is selected. If the voltage on the PFD input is
less than 0.21VDD then fast-decay mode is selected. Mixed decay is
between these two levels.
Allegro MicroSystems, LLC
115 Northeast Cutoff
13
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Figure 4: Quarter-Step Operation
MS1 = L, MS2 = H, DIR = H
The mixed-decay mode is controlled by the percent fast decay
voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD
then slow-decay mode is selected. If the voltage on the PFD input is
less than 0.21VDD then fast-decay mode is selected. Mixed decay is
between these two levels.
Allegro MicroSystems, LLC
115 Northeast Cutoff
14
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Figure 5: 8 Microstep/Step Operation
MS1 = MS2 = H, DIR = H
The mixed-decay mode is controlled by the percent fast decay
voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD
then slow-decay mode is selected. If the voltage on the PFD input is
less than 0.21VDD then fast-decay mode is selected. Mixed decay is
between these two levels.
Allegro MicroSystems, LLC
115 Northeast Cutoff
15
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
CUSTOMER PACKAGE DRAWINGS
For Reference Only – Not for Tooling Use
(Reference MO-153 AET)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
9.70 0.10
5.08 NOM
8º
0º
28
0.20
0.09
B
4.40 0.10 6.40 0.20
3 NOM
A
2
1.00 REF
0.60 0.15
1
Branded Face
0.25 BSC
C
28X
SEATING PLANE
GAUGE PLANE
1.20 MAX
0.10
C
SEATING
PLANE
0.30
0.19
0.65 BSC
0.15
0.00
0.65
0.45
28
1.65
A
B
C
Terminal #1 mark area
Exposed thermal pad (bottom surface)
3.00
6.10
Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
1
2
5.00
C
PCB Layout Reference View
Figure 6: LP Package, 28-pin TSSOP
Allegro MicroSystems, LLC
115 Northeast Cutoff
16
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3977
Microstepping DMOS Driver with Translator
Revision History
Revision No.
Revision Date
April 23, 2013
Description of Revision
Update product selection and applications component recommendations
Removed ED package, Revised Table 2 title, reformatted document
11
12
October 30, 2014
Copyright ©2002-2014, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Al-
legro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
17
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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