A3977SED [ALLEGRO]
MICROSTEPPING DMOS DRIVER WITH TRANSLATOR; 微DMOS驱动器与翻译
| 型号： | A3977SED |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | MICROSTEPPING DMOS DRIVER WITH TRANSLATOR |
| 文件： | 总18页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
The A3977xED and A3977xLP are complete microstepping motor drivers
with built-in translator. They are designed to operate bipolar stepper motors in
full-, half-, quarter-, and eighth-step modes, with output drive capability of 35
V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has
the ability to operate in slow-, fast-, or mixed-decay modes. This current-
decay control scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
A3977xED
(PLCC)
4
3
2
1
41
6
5
44
43
BB1
42
40
V
NC
NC
NC
7
39
38
37
36
35
34
33
32
31
30
29
CP
CP
2
8
The translator is the key to the easy implementation of the A3977. By
simply inputting one pulse on the STEP input the motor will take one step
(full, half, quarter, or eighth depending on two logic inputs). There are no
phase-sequence tables, high-frequency control lines, or complex interfaces to
program. The A3977 interface is an ideal fit for applications where a complex
µP is unavailable or over-burdened.
PWM
TIMER
PFD
1
9
RC
1
10
11
12
13
14
15
16
17
VCP
GND
GND
GND
REF
GND
GND
GND
REG
VREG
÷8
Internal synchronous-rectification control circuitry is provided to improve
power dissipation during PWM operation.
RC
2
STEP
NC
LOGIC
SUPPLY
VDD
NC
NC
Internal circuit protection includes thermal shutdown with hysteresis,
under-voltage lockout (UVLO) and crossover-current protection. Special
power-up sequencing is not required.
V
BB2
18
21
22
23
19
20
24
25
26
27
28
Dwg. PP-075-1
The A3977 is supplied in a choice of two power packages, a 44-pin
plastic PLCC with copper batwing tabs (suffix ED), and a thin (<1.2 mm), 28-
pin TSSOP with an exposed thermal pad (suffix LP). The SLP package is
available in a lead-free version (100% matte tin leadframe).
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
FEATURES
■ ±2.5 A, 35 V Output Rating
Load Supply Voltage, VBB ............. 35 V
*
Output Current, IOUT .................. ±2.5 A
Logic Supply Voltage, VDD ........... 7.0 V
Logic Input Voltage Range, VIN
■ Low rDS(on) Outputs, 0.45 Ω Source, 0.36 Ω Sink Typical
■ Automatic Current Decay Mode Detection/Selection
■ 3.0 V to 5.5 V Logic Supply Voltage Range
■ Mixed, Fast, and Slow Current Decay Modes
■ Home Output
■ Synchronous Rectification for Low Power Dissipation
■ Internal UVLO and Thermal Shutdown Circuitry
■ Crossover-Current Protection
(tw >30 ns)..... -0.3 V to VDD + 0.3 V
(tw <30 ns)........... -1 V to VDD + 1 V
Sense Voltage, VSENSE ................. 0.5 V
Reference Voltage, VREF ................ VDD
Package Power Dissipation,
PD................................. See page 3
Operating Temperature Range, TA
(A3977Kx)............ -40°C to +125°C
(A3977Sx).............. -20°C to +85°C
Junction Temperature, TJ ......... +150°C
Storage Temperature Range,
Always order by complete part number:
Part Number
Package
TS ......................... -55°C to +150°C
A3977KED
A3977KLP
A3977SED
A3977SED-T
A3977SLP
A3977SLP-T
44-pin PLCC
* Output current rating may be limited by
duty cycle, ambient temperature, and heat
sinking. Under any set of conditions, do not
exceed the specified current rating or a
junction temperature of 150°C.
28-pin TSSOP
44-pin PLCC
44-pin PLCC; Lead-free
28-pin TSSOP
28-pin TSSOP; Lead-free
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
FUNCTIONAL BLOCK DIAGRAM
VREG
CP2
CP1
LOGIC
SUPPLY
LOAD
SUPPLY
V
CP
2 V
UVLO
AND
FAULT
CHARGE
PUMP
REGULATOR
BANDGAP
V
DD
REF.
SUPPLY
VBB1
REF
DMOS H BRIDGE
DAC
SENSE1
VCP
+
-
OUT1A
OUT1B
RC1
PWM LATCH
BLANKING
MIXED DECAY
PWM TIMER
4
STEP
DIR
SENSE
1
RESET
MS
1
2
DMOS H BRIDGE
MS
VBB2
HOME
SLEEP
SR
OUT2A
OUT2B
VPFD
ENABLE
PWM TIMER
PFD
PWM LATCH
BLANKING
MIXED DECAY
RC2
+
-
SENSE
2
DAC
Dwg. FP-050-2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2002, 2003 Allegro MicroSystems, Inc.
2
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
A3977xLP
(TSSOP)
5.0
LOAD
SUPPLY
SENSE
1
1
VBB1
28
27
1
SUFFIX '–LP', RθJA = 28°C/W*
HOME
DIR
SLEEP
2
3
4.0
26 ENABLE
OUT1B
OUT1A
4
25
24 CP
SUFFIX '–ED', RθJA = 32°C/W†
3.0
PFD
2
1
5
6
SUFFIX '–LP',
RC
1
CP
23
22
21
RθJA = 33°C/W†
AGND
REF
VCP
7
8
2.0
1.0
0
PGND
÷8
V
REG
RC
2
9
REG
20
19
LOGIC
SUPPLY
10
VDD
STEP
SUFFIX 'S–'
OUT2A 11
18 OUT2B
SUFFIX 'K–'
MS
2
1
12
13
RESET
16 SR
17
MS
25
50
75
100
125
150
°
AMBIENT TEMPERATURE IN C
LOAD
SUPPLY
SENSE
2
14
15
VBB2
2
Dwg. GP-018-2A
Dwg. PP-075
Package Thermal Resistance, RθJA
A3977xLP ......................... 28°C/W*
A3977xED ........................ 32°C/W†
A3977xLP ......................... 33°C/W†
*
Measured on JEDEC standard “High-K” four-layer board.
† Measured on typical two-sided PCB with three square inches
(1935 mm2) copper ground area.
Table 1. Microstep Resolution Truth Table
MS1
L
H
MS2
L
L
Resolution
Full step (2 phase)
Half step
L
H
H
H
Quarter step
Eighth step
www.allegromicro.com
3
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise
noted)
Limits
Characteristic
Symbol Test Conditions
Min.
Typ.
Max.
Units
Output Drivers
Load Supply Voltage Range
VBB
Operating
8.0
0
–
–
35
35
V
V
During sleep mode
VOUT = VBB
Output Leakage Current
Output On Resistance
Body Diode Forward Voltage
Motor Supply Current
IDSS
–
<1.0
<1.0
0.45
0.36
–
20
µA
µA
Ω
VOUT = 0 V
–
-20
0.57
0.43
1.4
1.4
8.0
6.0
20
rDS(on) Source driver, IOUT
=
-
2.5 A
–
Sink driver, IOUT = 2.5 A
Source diode, IF = -2.5 A
Sink diode, IF = 2.5 A
fPWM < 50 kHz
–
Ω
VF
–
V
–
–
V
IBB
–
–
mA
mA
µA
Operating, outputs disabled
Sleep mode
–
–
–
–
Control Logic
Logic Supply Voltage Range
Logic Input Voltage
VDD
VIN(1)
VIN(0)
IIN(1)
IIN(0)
fSTEP
VOH
Operating
3.0
0.7VDD
–
5.0
–
5.5
–
V
V
–
0.3VDD
20
V
Logic Input Current
VIN = 0.7VDD
VIN = 0.3VDD
-20
<1.0
<1.0
–
µA
µA
kHz
V
-20
20
Maximum STEP Frequency
HOME Output Voltage
500*
0.7VDD
–
–
IOH = -200 µA
IOL = 200 µA
–
–
VOL
–
0.3VDD
1200
46
V
Blank Time
tBLANK Rt = 56 kΩ, Ct = 680 pF
700
30
950
38
ns
µs
Fixed Off Time
toff
Rt = 56 kΩ, Ct = 680 pF
continued next page …
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
3977
MICROSTEPPPING DMOS DRIVER
WITH TRANSLATOR
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise
noted)
Limits
Characteristic
Control Logic (cont’d)
Mixed Decay Trip Point
Symbol
Test Conditions
Min.
Typ.
Max.
Units
PFDH
PFDL
–
–
0.6V
–
–
V
V
DD
0.21V
DD
Ref. Input Voltage Range
Reference Input Current
V
Operating
0
–
0
–
–
–
V
V
REF
REF
DD
I
–
±3.0
±10
±5.0
±5.0
800
–
µA
%
Gain (G ) Error
E
V
V
V
= 2 V, Phase Current = 38.27%
= 2 V, Phase Current = 70.71%
= 2 V, Phase Current = 100.00%
–
m
G
REF
REF
REF
–
%
(note 3)
–
%
Crossover Dead Time
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
t
SR enabled
100
–
475
165
15
2.7
0.10
–
ns
°C
°C
V
DT
T
J
∆T
–
–
J
V
Increasing V
2.45
0.05
–
2.95
–
UVLO
DD
∆V
V
UVLO
Logic Supply Current
I
f
< 50 kHz
12
mA
mA
µA
DD
PWM
Outputs off
Sleep mode
–
–
10
–
–
20
* Operation at a step frequency greater than the specified minimum value is possible but not warranteed.
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. EG = ([VREF/8] – VSENSE)/(VREF/8)
www.allegromicro.com
5
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
Functional Description
Device Operation. The A3977 is a complete
Step Input (STEP). A low-to-high transition on the
STEP input sequences the translator and advances the
motor one increment. The translator controls the input to
the DACs and the direction of current flow in each wind-
ing. The size of the increment is determined by the state
of inputs MS1 and MS2 (see table 1).
microstepping motor driver with built in translator for
easy operation with minimal control lines. It is designed
to operate bipolar stepper motors in full-, half-, quarter-
and eighth-step modes. The current in each of the two
output H-bridges, all n-channel DMOS, is regulated with
fixed off time pulse-width modulated (PWM) control
circuitry. The H-bridge current at each step is set by the
value of an external current sense resistor (RS), a reference
voltage (VREF), and the DAC’s output voltage controlled
by the output of the translator.
Microstep Select (MS1 and MS2). Input terminals
MS1 and MS2 select the microstepping format per
table 1. Changes to these inputs do not take effect until
the STEP command (see figure).
Direction Input (DIR). The state of the DIRECTION
input will determine the direction of rotation of the motor.
At power up, or reset, the translator sets the DACs and
phase current polarity to initial home state (see figures for
home-state conditions), and sets the current regulator for
both phases to mixed-decay mode. When a step command
signal occurs on the STEP input the translator automati-
cally sequences the DACs to the next level (see table 2 for
the current level sequence and current polarity). The
microstep resolution is set by inputs MS1 and MS2 as
shown in table 1. If the new DAC output level is lower
than the previous level the decay mode for that H-bridge
will be set by the PFD input (fast, slow or mixed decay).
If the new DAC level is higher or equal to the previous
level then the decay mode for that H-bridge will be slow
decay. This automatic current-decay selection will
improve microstepping performance by reducing the
distortion of the current waveform due to the motor
BEMF.
Internal PWM Current Control. Each H-bridge is
controlled by a fixed off time PWM current-control circuit
that limits the load current to a desired value (ITRIP).
Initially, a diagonal pair of source and sink DMOS outputs
are enabled and current flows through the motor winding
and RS. When the voltage across the current-sense resistor
equals the DAC output voltage, the current-sense com-
parator resets the PWM latch, which turns off the source
driver (slow-decay mode) or the sink and source drivers
(fast- or mixed-decay modes).
The maximum value of current limiting is set by the
selection of RS and the voltage at the VREF input with a
transconductance function approximated by:
ITRIPmax = VREF/8RS
The DAC output reduces the VREF output to the
current-sense comparator in precise steps (see table 2 for
% ITRIPmax at each step).
Reset Input (RESET). The RESET input (active low)
sets the translator to a predefined home state (see figures
for home state conditions) and turns off all of the DMOS
outputs. The HOME output goes low and all STEP inputs
are ignored until the RESET input goes high.
ITRIP = (% ITRIPmax/100) x ITRIPmax
It is critical to ensure that the maximum rating (0.5 V)
on the SENSE terminal is not exceeded. For full-step
mode, VREF can be applied up to the maximum rating of
VDD, because the peak sense value is 0.707 x VREF/8. In
all other modes VREF should not exceed 4 V.
Home Output (HOME). The HOME output is a logic
output indicator of the initial state of the translator. At
power up the translator is reset to the home state (see
figures for home state conditions).
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
Functional Description (cont’d)
Shutdown. In the event of a fault (excessive junction
temperature, or low voltage on VCP) the outputs of the
device are disabled until the fault condition is removed.
At power up, and in the event of low VDD, the under-
voltage lockout (UVLO) circuit disables the drivers and
resets the translator to the HOME state.
Fixed Off-Time. The internal PWM current-control
circuitry uses a one shot to control the time the driver(s)
remain(s) off. The one shot off-time, toff, is determined by
the selection of an external resistor (RT) and capacitor
(CT) connected from the RC timing terminal to ground.
The off time, over a range of values of CT = 470 pF to
1500 pF and RT = 12 kΩ to 100 kΩ is approximated by:
Sleep Mode (SLEEP). An active-low control input
used to minimize power consumption when not in use.
This disables much of the internal circuitry including the
output DMOS, regulator, and charge pump. A logic high
allows normal operation and startup of the device in the
home position. When coming out of sleep mode, wait
1 ms before issuing a STEP command to allow the charge
pump (gate drive) to stabilize.
toff = RTCT
RC Blanking. In addition to the fixed off time of the
PWM control circuit, the CT component sets the compara-
tor blanking time. This function blanks the output of the
current-sense comparator when the outputs are switched
by the internal current-control circuitry. The comparator
output is blanked to prevent false over-current detection
due to reverse recovery currents of the clamp diodes, and/
or switching transients related to the capacitance of the
load. The blank time tBLANK can be approximated by:
Percent Fast Decay Input (PFD). When a STEP
input signal commands a lower output current from the
previous step, it switches the output current decay to either
slow-, fast-, or mixed-decay depending on the voltage
level at the PFD input. If the voltage at the PFD input is
greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between
these two levels. This terminal should be decoupled with
a 0.1 µF capacitor.
tBLANK = 1400CT
Charge Pump. (CP1 and CP2). The charge pump is
used to generate a gate supply greater than VBB to drive
the source-side DMOS gates. A 0.22 µF ceramic capaci-
tor should be connected between CP1 and CP2 for pump-
ing purposes. A 0.22 µF ceramic capacitor is required
between VCP and VBB to act as a reservoir to operate the
high-side DMOS devices.
Mixed Decay Operation. If the voltage on the PFD
input is between 0.6VDD and 0.21VDD, the bridge will
VREG. This internally generated voltage is used to operate operate in mixed-decay mode depending on the step
the sink-side DMOS outputs. The VREG terminal should
be decoupled with a 0.22 µF capacitor to ground. VREG is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
sequence (see figures). As the trip point is reached, the
device will go into fast-decay mode until the voltage on
the RC terminal decays to the voltage applied to the PFD
terminal. The time that the device operates in fast decay is
approximated by:
Enable Input (ENABLE). This active-low input
enables all of the DMOS outputs. When logic high the
outputs are disabled. Inputs to the translator (STEP,
DIRECTION, MS1, MS2) are all active independent of the
ENABLE input state.
tFD = RTCTIn (0.6VDD/VPFD
)
After this fast decay portion, tFD, the device will
switch to slow-decay mode for the remainder of the fixed
off-time period.
www.allegromicro.com
7
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
Functional Description (cont’d)
Synchronous Rectification. When a PWM off cycle
is triggered by an internal fixed off-time cycle, load
current will recirculate according to the decay mode
selected by the control logic. The A3977 synchronous
rectification feature will turn on the appropriate
MOSFETs during the current decay and effectively short
out the body diodes with the low rDS(on) driver. This will
reduce power dissipation significantly and eliminate the
need for external Schottky diodes for most applications.
Active Mode. When the SR input is logic low, active
mode is enabled and synchronous rectification will occur.
This mode prevents reversal of the load current by turning
off synchronous rectification when a zero current level is
detected. This prevents the motor winding from conduct-
ing in the reverse direction.
Disabled Mode. When the SR input is logic high,
synchronous rectification is disabled. This mode is
typically used when external diodes are required to
transfer power dissipation from the A3977 package to the
external diodes.
The synchronous rectification can be set in either
active mode or disabled mode.
Timing Requirements
(TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground)
STEP
50%
C
D
B
A
MS1/MS2/
DIR/RESET
E
SLEEP
Dwg. WP-042
A. Minimum Command Active Time
Before Step Pulse (Data Set-Up Time)..... 200 ns
B. Minimum Command Active Time
After Step Pulse (Data Hold Time)............ 200 ns
C. Minimum STEP Pulse Width ...................... 1.0 µs
D. Minimum STEP Low Time ......................... 1.0 µs
E. Maximum Wake-Up Time ......................... 1.0 ms
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
Applications Information
Layout.
The printed wiring board should use a heavy ground
plane.
For optimum electrical and thermal performance, the
Current Sensing. To minimize inaccuracies caused by
ground-trace IR drops in sensing the output current level,
the current-sense resistor (RS) should have an independent
ground return to the star ground of the device. This path
should be as short as possible. For low-value sense
resistors the IR drops in the printed wiring board sense
resistor’s traces can be significant and should be taken
into account. The use of sockets should be avoided as
they can introduce variation in RS due to their contact
resistance.
driver should be soldered directly onto the board.
The load supply terminal, VBB, should be decoupled
with an electrolytic capacitor (>47 µF is recommended)
placed as close to the device as possible.
To avoid problems due to capacitive coupling of the
high dv/dt switching transients, route the bridge-output
traces away from the sensitive logic-input traces. Always
drive the logic inputs with a low source impedance to
increase noise immunity.
Allegro MicroSystems recommends a value of RS
given by
RS = 0.5/ITRIPmax
Thermal Protection. Circuitry turns off all drivers
when the junction temperature reaches 165°C, typically.
It is intended only to protect the device from failures due
to excessive junction temperatures and should not imply
that output short circuits are permitted. Thermal shut-
down has a hysteresis of approximately 15°C.
Grounding. A star ground system located close to the
driver is recommended.
The 44-lead PLCC has the analog ground and the
power ground internally bonded to the power tabs of the
package (leads 44, 1, 2, 11 – 13, 22 – 24, and 33 – 35).
On the 28-lead TSSOP package, the analog ground
(lead 7) and the power ground (lead 21) must be con-
nected together externally. The copper ground plane
located under the exposed thermal pad is typically used as
the star ground.
www.allegromicro.com
9
3977
MICROSTEPPPING DMOS DRIVER
WITH TRANSLATOR
Table 2. Step Sequencing
Home State = 45º Step Angle, DIR = H
Phase 1 Current Phase 2 Current
Step Angle
(º)
Full Step Half Step
¼ Step
⅛ Step
(%Itripmax)
(%)
(%Itripmax)
(%)
1
1
1
100.00
98.08
0.00
19.51
0.0
11.3
2
2
3
3
92.39
38.27
22.5
4
83.15
55.56
33.8
1
2
3
4
2
3
4
5
6
7
8
5
70.71
70.71
45.0
6
55.56
83.15
56.3
4
7
38.27
92.39
67.5
8
19.51
98.08
78.8
5
9
0.00
100.00
98.08
90.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–98.08
–100.00
–98.08
–92.39
–83.15
–70.71
–55.56
–38.27
–19.51
0.00
101.3
112.5
123.8
135.0
146.3
157.5
168.8
180.0
191.3
202.5
213.8
225.0
236.3
247.5
258.8
270.0
281.3
292.5
303.8
315.0
326.3
337.5
348.8
6
92.39
83.15
7
70.71
55.56
8
38.27
19.51
9
0.00
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–98.08
–100.00
–98.08
–92.39
–83.15
–70.71
–55.56
–38.27
–19.51
10
11
12
13
14
15
16
19.51
38.27
55.56
70.71
83.15
92.39
98.08
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
Full-Step Operation
MS1 = MS2 = L, DIR = H
STEP
INPUT
HOME
OUTPUT
SLOW
DECAY
70.7%
PHASE 1
CURRENT
–70.7%
SLOW
DECAY
70.7%
PHASE 2
CURRENT
–70.7%
Dwg. WK-004-15
The vector addition of the output currents at any step is
100%.
www.allegromicro.com
11
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
Half-Step Operation
MS1 = H, MS2 = L, DIR = H
STEP
INPUT
HOME
OUTPUT
100%
70.7%
PHASE 1
CURRENT
–70.7%
–100%
100%
70.7%
PHASE 2
CURRENT
–70.7%
–100%
Dwg. WK-004-14
The mixed-decay mode is controlled by the percent fast
decay voltage (VPFD). If the voltage at the PFD input is
greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between
these two levels.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
12
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
Quarter-Step Operation
MS1 = L, MS2 = H, DIR = H
STEP
INPUT
HOME
OUTPUT
SLOW
MIXED
MIXED
SLOW
DECAY
DECAY
DECAY
DECAY
100%
70.7%
38.3%
PHASE 1
CURRENT
–38.3%
–70.7%
–100%
MIXED
SLOW
SLOW
MIXED
DECAY
DECAY
DECAY
DECAY
100%
70.7%
38.3%
PHASE 2
CURRENT
–38.3%
–70.7%
–100%
Dwg. WK-004-13
The mixed-decay mode is controlled by the percent fast
decay voltage (VPFD). If the voltage at the PFD input is
greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between
these two levels.
www.allegromicro.com
13
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
8 Microstep/Step Operation
MS1 = MS2 = H, DIR = H
STEP
INPUT
HOME
OUTPUT
SLOW
MIXED
MIXED
SLOW
DECAY
DECAY
DECAY
DECAY
100%
70.7%
38.3%
PHASE 1
CURRENT
–38.3%
–70.7%
–100%
MIXED
SLOW
SLOW
MIXED
DECAY
DECAY
DECAY
DECAY
100%
70.7%
38.3%
PHASE 2
CURRENT
–38.3%
–70.7%
–100%
Dwg. WK-004-12
The mixed-decay mode is controlled by the percent fast
decay voltage (VPFD). If the voltage at the PFD input is
greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between
these two levels.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
14
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
Terminal List
Terminal
Name
GND
SENSE1
HOME
DIR
A3977xLP
(TSSOP)
–
A3977xED
(PLCC)
44, 1, 2
Terminal Description
Analog and power ground
Sense resistor for bridge 1
Logic output
1
2
3
3
4
5
Logic Input
OUT1A
NC
PFD
DMOS H bridge 1 output A
No (internal) connection
Mixed decay setting
4
–
5
6
7, 8
9
RC1
GND
AGND
REF
Analog Input for fixed offtime – bridge 1
Analog and power ground
Analog ground
6
–
7*
8
10
11, 12, 13
–
14
Gm reference input
RC2
Analog input for fixed offtime – bridge 2
9
15
LOGIC SUPPLY VDD, the logic supply voltage
10
–
16
17
18
19
20
21
NC
OUT2A
MS2
No (internal) connection
DMOS H bridge 2 output A
Logic input
11
12
13
14
–
MS1
Logic input
SENSE2
GND
Sense resistor for bridge 2
Analog and power ground
22, 23, 24
LOAD SUPPLY2 VBB2, the load supply for bridge 2
15
16
17
18
–
19
20
21*
–
22
23
24
–
25
26
27
28
25
26
27
28
29, 30
31
SR
Logic input
RESET
OUT2B
NC
STEP
VREG
PGND
GND
VCP
CP1
CP2
NC
Logic input
DMOS H bridge 2 output B
No (internal) connection
Logic input
Regulator decoupling
Power ground
Analog and power ground
Reservoir capacitor
Charge pump capacitor
Charge pump capacitor
No (internal) connection
DMOS H bridge 1 output B
Logic input
32
–
33, 34, 35
36
37
38
39
40
41
42
43
OUT1B
ENABLE
SLEEP
Logic input
LOAD SUPPLY1 VBB1, the load supply for bridge 1
* AGND and PGND on the TSSOP package must be connected together externally.
www.allegromicro.com
15
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
A3977xED
18
28
29
0.032
0.026
17
0.319
0.291
0.695
0.685
0.021
0.013
Dimensions in Inches
(controlling dimensions)
0.656
0.650
INDEX AREA
0.319
0.291
0.050
BSC
39
7
44
1
2
40
6
0.020
0.656
0.650
MIN
0.695
0.685
0.180
0.165
Dwg. MA-005-44A in
28
18
29
0.812
0.661
17
8.10
7.39
17.65
17.40
0.533
0.331
Dimensions in Millimeters
16.662
16.510
(for reference only)
INDEX AREA
8.10
7.39
1.27
BSC
39
7
44
1
2
40
6
16.662
16.510
0.51
MIN
4.57
4.20
17.65
17.40
Dwg. MA-005-44A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Webbed lead frame. Terminals 1, 2, 11, 12, 13, 22, 23, 24, 33, 34, 35, and 44 are internally one piece.
4. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
16
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
A3977xLP
0.197
28
15
0.0394
REF
0.118
0.177
0.169
0.0098
BSC
INDEX
AREA
GAUGE PLANE
SEATING PLANE
0.030
0.018
0° TO 8°
0.012
0.0075
1
2
0.026
3
Dimensions in Inches
BSC
0.386
0.378
(for reference only)
0.260
0.244
0.0079
0.0035
0.0472
MAX
0.0059
0.00
EXPOSED
THERMAL PAD
Dwg. MA-008-30A in
5.0
28
15
1.00
REF
3.0
4.50
4.30
0.25
BSC
INDEX
AREA
GAUGE PLANE
SEATING PLANE
0.75
0.45
0° TO 8°
0.30
0.19
1
2
0.65
3
BSC
9.80
9.60
Dimensions in Millimeters
(controlling dimensions)
6.60
6.20
0.20
0.09
1.20
MAX
0.15
0.00
EXPOSED
THERMAL PAD
Dwg. MA-008-30A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 49 devices or add “TR” to part number for tape and reel.
www.allegromicro.com
17
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
18
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