A3935 [ALLEGRO]
3-Phase Power MOSFET Controller for Automotive Applications; 3相电源MOSFET控制器为汽车应用
| 型号： | A3935 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | 3-Phase Power MOSFET Controller for Automotive Applications |
| 文件： | 总13页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A3935
3-Phase Power MOSFET Controller for Automotive Applications
Features and Benefits
Description
▪ Drives wide range of N-channel MOSFETs in 3-phase bridges
▪ PFM boost converter for use with low-voltage battery supplies
▪ Internal LDO regulator for gate-driver supply
▪ Bootstrap circuits for high-side gate drivers
▪ Current monitor output
TheA3935isdesignedspecificallyforautomotiveapplications
thatrequirehigh-powermotors.Eachprovidessixhigh-current
gatedriveoutputscapableofdrivingawiderangeofN-channel
power MOSFETs.
Arequirement of automotive systems is steady operation over
a varying battery input range. The A3935 integrates a pulse-
frequency modulated boost converter to create a constant
supply voltage for driving the external MOSFETs. Bootstrap
capacitors are utilized to provide the above battery supply
voltage required for N-channel FETs.
▪ Adjustable battery overvoltage detection
▪ Diagnostic outputs
▪ Motor lead short-to-battery, short-to-ground, and bridge-
open protection
▪ Undervoltage protection
▪ –40°C to 150°C T operation
J
▪ Thermal shutdown
Direct control of each gate output is possible via six TTL-
compatible inputs. A differential amplifier is integrated to
allow accurate measurement of the current in the three-phase
bridge.
Package 36-pin QSOP (LQ):
Diagnostic outputs can be continuously monitored to protect
the driver from short-to-battery, short-to-supply, bridge-open,
andbatteryunder/overvoltageconditions.Additionalprotection
features include dead-time, VDD undervoltage, and thermal
shutdown.
TheA3935issuppliedina36-lead0.8mmpitchQSOP(package
LQ, similar to SOICW).The lead (Pb) free variants (suffix –T)
have 100% matte tin leadframe plating.
Approximate scale 1:1
Typical Application
26301.102J
3-Phase Power MOSFET Controller for Automotive Applications
A3935
Selection Guide
Part Number
A3935KLQTR1
A3935KLQTR-T2
Pb-free
–
Packing
Terminals
36
Package
QSOP (similar to
SOICW) surface mount
1500 pieces/reel
Yes
1Variant has been determined to be obsolete and is no longer in production. Status change: October 31, 2011.
2Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that
sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for
new design applications because obsolescence in the near future is probable. Samples are no longer available.
Status change: October 31, 2011.
Absolute Maximum Ratings
Parameter
Symbol
VBAT
Conditions
Rating
Units
VBAT pin
VDRAIN
VBOOST
VBOOSTD
VGHx
VDRAIN pin
VBOOST pin
VBOOSTD pin
Load Supply Voltage
–0.6 to 40
V
GHA, GHB, and GHC pins
SA, SB, and SC pins
GLA, GLB, and GLC pins
CA, CB, and CC pins
CSN and CSP pins
LSS pin
–4 to 55
–4 to 40
–4 to 16
–0.6 to 55
V
V
V
V
VSx
Output Voltage Range
VGLx
VCx
VCSx
Sense Circuit Voltage
Logic Supply Voltage
–4 to 6.5
V
VLSS
VDD
VDD pin
VOVSET
VBOOSTS
VCSOUT
VDSTH
OVSET pin
BOOSTS pin
–0.3 to 6.5
V
Logic Input/Output
CSOUT pin
VDSTH pin
remaining logic pins
AEC-Q100-002; all pins
AEC-Q100-011; all pins
Range K
ESD Rating – Human Body Model
ESD Rating – Charged Device Model
Operating Temperature
2.5
1050
kV
V
TA
TJ(max)
Tstg
–40 to 135
°C
Fault conditions that produce excessive junction temperature
will activate device thermal shutdown circuitry. These condi-
tions can be tolerated, but should be avoided.
Junction Temperature*
150
°C
°C
Storage Temperature Range
–55 to 150
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
Functional Block Diagram
BOOSTD
VBOOST
VBAT
BOOSTS
VDRAIN
(KELVIN)
VIGN
VBAT
Motor
Supply
Voltage
Low Drop
Out
VREG
Linear
Regulator
OS
(off)
REFi
REFv
Phase A
OS
(blank)
External +5V
VDD
CA
CBOOT
AHI
Turn ON
Delay
High-Side
Driver
To P hase C
GHA
ALO
BHI
BLO
Control
Logic
SA
CHI
CLO
VREG
ENABLE
Turn ON
Delay
Low-Side
Driver
GLA
To P hase B
FAULT
OVFLT
LSS
CSP
VBAT Overvoltage
VBAT Undervoltage
UVFLT
OVSET
VBAT
cs
VREG Undervoltage
Short to Ground
Short to Battery
Bridge Open
VREG
VDD
RS
SA
CSN
GND
VDD Undervoltage
Thermal Shutdown
SB
SC
VDSTH
Drain-Source
Fault Monitor
LSS
VDD
VDRAIN
CSOUT
Dwg. FP-053
Allegro MicroSystems, Inc.
3
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBAT = 7 to 16 V, VDD = 4.75 to 5.25 V, ENABLE = 22.5 kHz,
50% duty cycle, two phases active;unless otherwise noted
Characteristics
Symbol
Conditions
Min. Typ1. Max. Units
Power Supply
DD Supply Current
V
IDD
IBAT
VBAT
All logic inputs = 0 V
All logic inputs = 0 V
–
–
–
–
–
–
7.0
3.0
40
mA
mA
V
VBAT Supply Current
–
Battery Voltage Operating Range
7.0
0.8
1.5
IDBOOT = –ICx = 10 mA, VDBOOT = VREG – VCx
DBOOT = –ICx = 100 mA
rDBOOT(100 mA) = (VDBOOT(150 mA)
– VDBOOT(50 mA)) / 100 mA
2.0
2.3
V
Bootstrap Diode Forward Voltage
VDBOOT
rDBOOT
I
V
Bootstrap Diode Resistance
2.5
–
7.5
Ω
Bootstrap Diode Current Limit2
Bootstrap Quiescent Current
IDM
ICx
3 V < VREG – VCx < 12 V
–150
10
–
–
–1150
30
mA
VCx = 40 V, GHx = ON
μA
VSx = low, to guarantee ΔV = +0.5 V refresh of 0.47 μF
Bootstrap Capacitor, CBOOT, to VCx – VSx = +10 V
VBAT = 7 to 40 V, VBOOST from Boost Regulator
Bootstrap Refresh Time
trefresh
–
–
2.0
μs
VREG Output Voltage3
VREG
12.7
–
0.9
–
14
–
V
VREG Dropout Voltage4
Gate Drive Average Supply Current
VREG Input Bias Current
Boost Supply
VREGDO VREGDO = VBOOST – VREG, IREG = 40 mA
IREG No external dc load at VREG, CREG = 10 μF
–
–
–
V
40
4.0
mA
mA
IREGbias Current into VBOOST, ENABLE = 0
–
VBOOST Output Voltage Limit
VBOOST Output Voltage Limit Hysteresis
Boost Switch On Resistance
Boost Switch Maximum Current
Boost Current Limit Threshold Voltage
Off Time
VBOOSTM VBAT = 7 V
14.9
35
–
–
16.3
180
3.3
V
mV
Ω
∆VBOOSTM
rDS(on)
IBOOSTSW
VBI(th)
toff
IBOOSTD < 300 mA
Increasing VBOOSTS
–
1.4
–
–
300
0.55
8.0
mA
V
0.45
3.0
100
–
–
μs
ns
Blanking Time
tblank
–
220
Control Logic
VI(1)
VI(0)
II(1)
Minimum high level input for logic 1
Maximum low level input for logic 0
VI = VDD
2.0
–
–
–
–
–
–
–
V
V
Logic Input Voltage
0.8
500
–
–
μA
μA
mV
Logic Input Current
II(0)
VI = 0.8 V
50
100
Logic Input Hysteresis
Logic Output High Voltage
Logic Output Low Voltage
VIhys
300
VDD
0.8
–
–
VO(H)
VO(L)
IO(H) = –800 μA
–
–
–
V
V
IO(L) = 1.6 mA
0.4
Gate Drives, GHx (internal source, or upper, switch stages)5
VREG
2.26
VREG
0.26
–
–
GHx: IxU = –10 mA, VSx = 0
GLx: IxU = –10 mA, VLSS = 0
–
–
VREG
VREG
V
V
Output High Voltage
VDSL(H)
–
VSDU = 10 V, TJ = 25°C
VSDU = 10 V, TJ = 135°C
IxU = –150 mA, TJ = 25°C
IxU = –150 mA, TJ = 135°C
800
–
–
–
mA
mA
Ω
Source Current (pulsed)
Source On Resistance
IxU
400
4.0
–
10
15
rSDU(on)
7.0
–
Ω
Continued on the next page…
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBAT = 7 to 16 V, VDD = 4.75 to 5.25 V,
ENABLE = 22.5 kHz, 50% duty cycle, two phases active;unless otherwise noted
Characteristics
Symbol
Conditions
Min. Typ1. Max. Units
Gate Drives, GLx (internal sink or lower switch stages)6
VDSL = 10 V, TJ = 25°C
–
850
–
–
mA
mA
Ω
Sink Current (pulsed)
Sink On Resistance
IxL
VDSL = 10 V, TJ = 135°C
IxL = 150 mA, TJ = 25°C
IxL = 150 mA, TJ = 135°C
550
1.8
3.0
–
–
6.0
7.5
rDSL(on)
–
Ω
Gate Drives, GHx, GLx (General)5,6
Propagation Delay, Logic only
Output Skew Time
tpd
Logic input to unloaded GHx, GLx
–
–
–
–
–
150
50
ns
ns
ns
tsk(o)
tdead
Grouped by edge, phase–to–phase
Between GHx, GLx transitions of same phase
Dead Time (shoot–through prevention)
Sense Amplifier
75
180
Input Bias Current2
Input Offset Current2
Ibias
IIO
CSP = CSN = 0 V
–180
–
–
–
–360
±35
–
μA
μA
CSP = CSN = 0 V
CSP with respect to GND
CSN with respect to GND
VID = CSP – CSN, –1.3V < CSP,N < 4V
CSP = CSN = 0 V
–
80
4.0
–
kΩ
Input Resistance
ri
–
–
kΩ
Diff. Input Operating Voltage
Output Offset Voltage
VID
VOO
ΔVOO
VIC
–
±200
450
–
mV
mV
μV/°C
V
77
–
250
100
–
Output Offset Voltage Drift
Input Common Mode Operating Range
Voltage Gain
CSP = CSN = 0 V
CSP = CSN
–1.5
4.0
AV
VID = 40 to 200 mV
18.6 19.2 19.8
V/V
mV
dB
Low Output Voltage Error
DC Common Mode Attenuation
Output Resistance
EV
VID = 0 to 40 mV, VO = (19.2 × VID) + VO + Ev
CSP = CSN = 200 mV
VCSOUT = 2.0 V
–
28
–
–
–
±25
–
AVC
rO
8.0
–
Ω
VDD
0.25
–
–
Output Dynamic Range
VCSOUT ICSOUT = –100 μA at top rail, 100 μA at bottom rail
0.075
–
V
Output Current, Sink
Output Current, Source2
Isink
VCSOUT = 2.5 V
VCSOUT = 2.5 V
20
–1.0
20
45
–
–
–
mA
mA
dB
Isource
–
VDD Supply Ripple Rejection
VREG Supply Ripple Rejection
Small Signal 3 dB Bandwidth
AC Common Mode Attenuation
Output Slew Rate (positive or negative)
Fault Logic
PSRRVDD CSP = CSN = GND, frequency = 0 to 1 MHz
PSRRVREG CSP = CSN = GND, frequency = 0 to 300 kHz
BWf3db 10 mV input
–
–
–
–
dB
1.6
–
–
MHz
dB
AVC(ac) Vcm = 250 mV(pp), frequency = 0 to 800 kHz
26
10
–
SR
200 mV step input, measured at 10/90% points
–
–
V/μs
VDD Undervoltage
VDD(uv) Decreasing VDD
∆VDD(uv) VDD(recovery) – VDD(uv)
VSET(ov)
3.8
100
0
–
–
–
–
–
–
4.3
300
VDD
2.5
1.0
40
V
mV
V
VDD Undervoltage Hysteresis
OVSET Operating Voltage Range
OVSET Calibrated Voltage Range
OVSET Input Current Range2
VSET(ov)cal
0
V
ISET(ov)
–1.0
19.4
μA
V
0 V < VSET(ov) < 2.5 V
VBAT(ov)
VBAT Overvoltage Range
Increasing VBAT, VSET(ov) = 0 V
19.4 22.4 25.4
V
VBAT Overvoltage Hysteresis
∆VBAT(ov) Percent of VBAT(ov) value set by VSET(ov)
9.0
–
15
%
Continued on the next page…
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBAT = 7 to 16 V, VDD = 4.75 to 5.25 V,
ENABLE = 22.5 kHz, 50% duty cycle, two phases active;unless otherwise noted
Characteristics
Symbol
Conditions
VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov)(0);
VBAT(ov)(0) at VSET(ov) = 0
Min. Typ1. Max. Units
VBAT Overvoltage Gain Constant
KBAT(ov)
–
12
–
V/V
VBAT Undervoltage
VBAT(uv) Decreasing VBAT
VBAT(uv) Percent of VBAT(uv)
VREG(uv) Decreasing VREG
VDSTH
5.0
8.0
5.25
5.5
12
V
%
V
VBAT Undervoltage Hysteresis
VREG Undervoltage
–
–
–
–
9.9
11.1
3.0
VDSTH Input Range
VDSTH Input Current
0.5
V
IDSTH
VDSTH > 0.8 V
40
100
μA
With a high–side driver on, as VSX decreases,
VDRAIN – VSx > VSTG causes a fault
With a low–side driver on, as VSX increases,
VDSTH
0.3
–
–
VDSTH
0.2
+
+
Short–to–Ground Threshold
VSTG(th)
–
–
–
V
V
V
VDSTH
0.3
VDSTH
0.2
Short–to–Battery Threshold
VSTB(th)
V
Sx – VLSS > VSTB causes a fault
VBAT
2.0
1.0
3.0
180
13
+
VDRAIN-Open Bridge Operating Range
VDRAIN 7 V < VBAT < 40 V
–0.3
VDRAIN-Open Bridge Current
IVDRAIN 7 V < VBAT < 40 V
0
–
–
mA
V
VDRAIN /Open Bridge Threshold Voltage
Thermal Shut Down Temperature
Thermal Shutdown Hysteresis
VBDGO(th) If VDRAIN < VBDGOTH then a bridge fault occurs
1.0
160
7.0
TJ
170
°C
∆TJ
10
°C
1Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual
units, within the specified maximum and minimum limits.
2Negative current is defined as coming out of (sourcing) the specified device terminal.
3For VBOOSTM < VBOOST < 40 V power dissipation in the VREG LDO increases. Observe TJ < 150°C limit.
4With VBOOST decreasing, dropout voltage measured at VREG = VREG(ref) – 200 mV where VREG(ref) = VREG at VBOOST = 16 V.
5For GHx: VSDU = VCx – VGHx, VDSL = VGHx – VSx, VDSL(H) = VCx – VSDU – VSx
6For GLx: VSDU = VREG – VGLx, VDSL = VGLx – VLSS, VDSL(H) = VREG – VSDU – VLSS.
.
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
Test Conditions*
Value Units
44 ºC/W
RθJA
On 4-layer PCB, based on JEDEC standard
*Additional thermal information available on Allegro Web site.
Power Dissipation versus Ambient Temperature
5.0
4.0
3.0
2.0
1.0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
7
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
Terminal Descriptions
AHI, BHI, and CHI. Direct control of high-side gate outputs
GHA, GHB, and GHC. Logic 1 drives the gate on. Logic 0 pulls
the gate down, turning off the external power MOSFET. Inter-
nally pulled down when the terminal is open.
LSS. Low-side gate driver return. Connects to the common
sources on the low sides of the power MOSFET bridge.
OVFLT. Logic 1 indicates that the VBAT level exceeded the
VBAT overvoltage trip point set by the OVSET level. It will
recover after exceeding a hysteresis below that maximum value.
Normally, it has a high-impedance state. If OVFLT and UVFLT
are both in high-impedance state; then, at least, a thermal
shutdown or VDD undervoltage has occurred.
ALO, BLO, and CLO. Direct control of low-side gate outputs
GHA, GHB, and GHC. Logic 1 drives the gate on. Logic 0 pulls
the gate down, turning off the external power MOSFET. Inter-
nally pulled down when the terminal is open.
BOOSTD. Boost converter switch drain connection.
BOOSTS. Boost converter switch source connection.
OVSET. A positive dc level that controls the VBAT overvoltage
trip point. Usually, set by a precision resistor divider network
between VDD and GND, but can be held grounded for a preset
value. When this terminal is open, it sets an unspecified but high
overvoltage trip point.
CA, CB, and CC. High-side connection for the bootstrap
capacitors, CBOOTx, positive supply for high-side gate drive.
The bootstrap capacitor is charged to VREG when the output Sx
terminal is low. When the output swings high, the voltage on this
terminal rises with the output to provide the boosted gate voltage
needed for N-channel power MOSFETs.
SA, SB, and SC. Directly connected to the motor terminals,
these terminals sense the voltages switched across the load and
are connected to the negative side of the bootstrap capacitors,
CBOOTx. Also, are the negative supply connection for the
floating high-side drivers.
CSN. Input for current-sense differential amplifier, on the
inverting, negative side. Kelvin connection for the ground side of
the current-sense resistor, RSENSE.
UVFLT. Logic 1 indicates that the VBAT level is below its
minimum value. It will recover after exceeding a hysteresis above
that minimum value. Has a high-impedance state. If UVFLT and
OVFLT are both in high-impedance state; then, at least, a thermal
shutdown or VDD undervoltage has occurred.
CSOUT. Amplifier output voltage proportional to the current
sensed across an external low-value resistor placed in the ground
side of the power MOSFET bridge.
CSP. Input for current-sense differential amplifier, on the non-
inverting, positive side. Connected to the positive side of the
sense resistor, RSENSE.
VBAT. Battery voltage. Positive input. usually connected to the
motor voltage supply.
ENABLE. Logic 0 disables the gate control signals and switches
off all the gate drivers (low) causing a coast condition. Can be
used in conjunction with the gate inputs to PWM (pulse wave
modulate) the load current. Internally pulled down when the
terminal is open.
VBOOST. Boost converter output, 16 V nominal, is also the
input to the regulator for VREG. Has internal boost-current
and boost-voltage control loops. In high-voltage systems is
approximately one diode drop below VBAT
.
VDD. Logic supply, +5 V nominal.
¯F¯¯A¯¯U¯¯L¯¯T¯. Diagnostic logic output signal. When low, indicates
that one or more fault conditions have occurred.
VDRAIN. Kelvin connection for drain-to-source voltage monitor.
Connected to the high-side drains of the MOSFET bridge. High
impedance when this terminal is open, and registers as a short-to-
ground fault on all motor phases.
GHA, GHB, and GHC. High-side gate drive outputs for
N-channel MOSFET drivers. External series gate resistors can
control the slew rate seen at the power driver gate, thereby
controlling the di/dt and dv/dt of Sx outputs.
VDSTH. A positive dc level that sets the drain-to-source monitor
threshold voltage. Internally pulled down when this terminal is
open.
GLA, GLB, and GLC. Low-side gate drive outputs for external,
N-channel MOSFET drivers. External series gate resistors can
control slew rate.
VREG. High-side gate driver supply, 13.5 V nominal. Has low-
GND. Ground, or negative, side of VDD and VBAT supplies.
voltage dropout (LDO) feature.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
Functional Description
VBAT(ov) = (ABAT(ov) × VSET(ov)) + VBAT(ov)(0)
where ABAT(ov) is the gain (12) and VBAT(ov)(0) is the value of
BAT(ov) when VSET(ov) = 0 (VBAT(ov) ≈ 22.4). For the above
,
Motor Lead Protection. A fault detection circuit monitors
the voltage across the drain-to-source of the external MOSFETs.
A fault is asserted low on the output terminal, F¯A¯¯U¯¯L¯¯T¯¯, if the
drain-to-source voltage of any MOSFET that is instructed to
turn on is greater than the voltage applied to the VDSTH input
terminal. When a high-side switch is turned on, the voltage from
VDRAIN to the appropriate motor phase output, VSX, is examined.
If the motor lead is shorted to ground before the high-side is
turned on, the measured voltage will exceed the threshold and
the F¯¯A¯¯U¯¯L¯¯T¯ terminal will go low. Similarly, when a low-side
MOSFET is turned on, the differential voltage between the motor
phase (drain) and the LSS terminal (source) is monitored. VDSTH
V
formula to be valid, all variables must be in range and below the
maximum operating specification.
UVFLT. Asserts high when a VBAT undervoltage fault occurs and
resets low after exceeding a recovery hysteresis. It has a high-
impedance state when a thermal shut down or VDD undervoltage
occurs. OVFLT and UVFLT are mutually exclusive by definition.
Current Sensing. A current-sense amplifier is provided to
allow system monitoring of the load current. The differential
amplifier inputs are intended to be Kelvin-connected across a
low-value sense resistor or current shunt. The output voltage is
represented by:
is set by a resistor divider to VDD
.
The VDRAIN is intended to be a Kelvin connection for the
high-side, drain-to-source monitor circuit. Voltage drops across
the power bus are eliminated by connecting an isolated PCB trace
from the VDRAIN terminal to the drain of the MOSFET bridge.
This allows improved accuracy in setting the VDSTH threshold
voltage. The low-side, drain-to-source monitor uses the LSS
VCSOUT = ( ILOAD ×AV × RSENSE) + VOS
where VOS is the output voltage calibrated at zero load current
and AV is the differential amplifier gain of about 19.2. If either
the CSP or CSN pin is open, the CSOUT pin will go to its
maximum positive level.
terminal, rather than VDRAIN, for comparison with VDSTH
The A3935 just reports these motor faults.
.
Fault Outputs. Transient faults on any of the fault outputs
are to be expected during switching, and will not disable the
gate drive outputs. External circuitry or controller logic must
determine if the faults represent a hazardous condition.
¯F¯¯A¯¯U¯¯L¯¯T¯. This terminal will go active low when any of the follow-
ing conditions occur:
Shut Down. If a fault occurs because of excessive junction
temperature or undervoltage on VDD or VBAT, all gate driver
outputs are driven low until the fault condition is removed. In
addition, the boost supply switch and VREG are turned off until
those undervoltages and junction temperatures recover.
• VBAT overvoltage
• Motor lead short-to-supply
or short-to-battery
Boost Supply. VBOOST is controlled by an inner current-
control loop, and by an outer voltage-feedback loop. The
current-control loop turns off the boost switch for 5 μs whenever
the voltage across the boost current-sense resistor exceeds
500 mV. A diode reverse-recovery current flows through the
sense resistor whenever the boost switch turns on, which could
result in turning off the switch again if not for the blanking-time
circuit. Adjustment of this external sense resistor determines the
maximum current in the inductor. Whenever VBOOST exceeds the
predefined threshold, 16 V nominal the boost switch is inhibited.
• VBAT undervoltage
• VREG undervoltage
• Motor lead short-to-ground
• Bridge (or VDRAIN) open
• VDD undervoltage
• Thermal shut down
OVFLT. Asserts high when a VBAT overvoltage fault occurs and
resets low after a recovery hysteresis. It has a high-impedance
state when a thermal shutdown or VDD undervoltage occurs. The
voltage at the OVSET terminal, VOVSET, controls the VBAT over-
voltage set point VBAT(ov), as follows:
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
9
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
Input Logic Table
Input
Output
Mode of Operation
All gate drive outputs low
ENABLE
xLO
xHI
GLx
GHx
0
1
1
1
1
Don’t Care Don’t Care
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
1
0
1
Both gate drive outputs low
High-side on
Low-side on
XOR circuitry prevents shoot-through
Fault Response Table
Operating Conditions
Fault Output
Regulator State
Driver Output
Fault Mode ENABLE ¯F¯¯A¯¯U¯¯L¯¯T¯ OVFLT UVFLT
Boost
ON
VREG
ON
GHx
a
GLx
a
No Fault
Don’t Care
1
0
0
0
0
0
0
0
0
0
0
0
a
a
a
a
a
a
Short-to-Battery
1b
1c
1d
ON
ON
Short-to-Ground
ON
ON
Bridge (VDRAIN) Fault
ON
ON
a
a
a
a
VREG Undervoltage
VBAT Overvoltage
VBAT Undervoltagef
VDD Undervoltagef
Thermal Shut Downf
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
0
0
0
0
0
0
1
0
0
ON
OFFe
OFF
OFF
OFF
ON
ON
0
1
OFF
OFF
OFF
0
0
0
0
0
0
High Z
High Z
High Z
High Z
aDetermined by input states: xLO, xHI, and ENABLE. See Input Logic table.
bShort-to-battery can only be detected when the corresponding GLx = 1. This fault is not detected when ENABLE = 0.
cShort-to-ground can only be detected when the corresponding GHx = 1. This fault is not detected when ENABLE = 0.
dBridge fault appears as a short-to-ground fault on all motor phases. This fault is not detected when ENABLE = 0.
eOff only because VBOOST ≈ VBAT, which is above the voltage threshold of the Boost regulator voltage control loop.
fThese faults are not only reported, but also action is taken by the internal logic to protect the A3935 and the system.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
Pin-out Diagram
CSP
VDSTH
LSS
GLC
SC
1
2
36 CSN
35 VDD
3
34 CSOUT1
33 OVSET
32 ENABLE
4
5
GHC
CC
CHI
6
31
30
29
28
27
26
25
24
23
22
21
CLO
7
GLB
SB
BLO
8
BHI
9
GHB
CB
AHI
10
11
12
13
14
ALO
GLA
SA
FAULT
OVFLT
UVFLT
VBAT
GND
GHA
CA 15
VREG 16
VDRAIN 17
VBOOST 18
BOOSTD
BOOSTS
20
19
Terminal List
Number
Name
Function
Number
Name
Function
1
2
CSP
Current-sense input, positive-side
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
BOOSTS Boost switch, source
BOOSTD Boost switch, drain
VDSTH DC input, drain-to-source monitor threshold voltage
3
LSS
GLC
SC
Gate-drive source return, low-side
Gate-drive C output, low-side
Load phase C input
GND
VBAT
UVFLT
OVFLT
¯F¯¯A¯¯U¯¯L¯¯T¯
ALO
Ground, dc supply returns, negative
Battery supply, positive
4
5
VBAT undervoltage fault output
VBAT overvoltage fault output
Active-low fault output, primary
Gate control input A, low-side
Gate control input A, high-side
Gate control input B, high-side
Gate control input B, low-side
Gate control input C, low-side
Gate control input C, high-side
6
GHC
CC
Gate-drive C output, high-side
Bootstrap capacitor C
7
8
GLB
SB
Gate-drive B output, low-side
Load phase B input
9
AHI
10
11
12
13
14
15
16
17
18
GHB
CB
Gate-drive B output, high-side
Bootstrap capacitor B
BHI
BLO
GLA
SA
Gate-drive A output, low-side
Load phase A input
CLO
CHI
GHA
CA
Gate-drive A output, high-side
Bootstrap capacitor A
ENABLE Gate output enable
OVSET DC input, overvoltage threshold setting for VBAT
CSOUT Current-sense amplifier output
VREG
Gate drive supply, positive
VDRAIN Kelvin connection to MOSFET high-side drains
VBOOST Boost supply output
VDD
CSN
Logic supply, nominally +5 V
Current-sense input, negative-side
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
11
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
Package LQ, 36-pin QSOP
15.30 ±0.10
0.80
0.60
4° ±4
36
+0.05
0.28
–0.04
2.15
B
9.50
7.50 ±0.10 10.31 ±0.30
A
+0.44
–0.43
0.84
1
2
(0.36)
36X
C
SEATING PLANE
GAGE PLANE
SEATING
PLANE
0.10
A
A
B
Terminal #1 mark area
+0.12
–0.11
Reference land pattern layout (reference IPC7351
SOP80P1033X264-36M); adjust as necessary to meet
application process requirements and PCB layout
tolerances. All pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application
process requirements and PCB layout tolerances
0.40
(0.80)
2.64 MAX For Reference Only
(QSOP, nonJEDEC standard)
Dimensions in millimeters
0.20 ±0.10
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
12
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3-Phase Power MOSFET Controller for Automotive Applications
A3935
Revision History
Revision
Revision Date
Description of Revision
Update product availability
Rev. J
October 31, 2011
Copyright ©2005-2011, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
13
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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