A3935KE [ALLEGRO]
3-PHASE POWER MOSFET CONTROLLER; 3相电源MOSFET控制器
| 型号： | A3935KE |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | 3-PHASE POWER MOSFET CONTROLLER |
| 文件： | 总16页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3935
3-PHASE POWER MOSFET CONTROLLER
— For Automotive Applications
The A3935 is designed specifically for automotive applications that
require high-power motors. Each provides six high-current gate drive
outputs capable of driving a wide range of n-channel power MOSFETs.
Package ED, 44-Pin PLCC
A requirement of automotive systems is steady operation over a
varying battery input range. The A3935 integrates a pulse-frequency
modulated boost converter to create a constant supply voltage for
driving the external MOSFETs. Bootstrap capacitors are utilized to
provide the above battery supply voltage required for n-channel FETs.
Package JP, 48-Pin LQFP
Package LQ, 36-Pin SOIC
Direct control of each gate output is possible via six TTL-compat-
ible inputs. A differential amplifier is integrated to allow accurate
measurement of the current in the three-phase bridge.
Diagnostic outputs can be continuously monitored to protect the
driver from short-to-battery, short-to-supply, bridge-open, and battery
under/overvoltage conditions. Additional protection features include
dead-time, VDD undervoltage, and thermal shutdown.
The A3935 is supplied in a choice of three packages, a 44-lead
PLCC with copper batwing tabs (suffix ED), a 48-lead low profile QFP
with exposed thermal pad (suffix JP), and a 36-lead 0.8 mm pitch SOIC
(suffix LQ).
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltages, VBAT, VDRAIN,
VBOOST, BOOSTD ... -0.6 V to 40 V
Output Voltage Ranges,
FEATURES
GHA/GHB/GHC, VGHX .. -4 V to 55 V
SA/SB/SC, VSX ............... -4 V to 40 V
GLA/GLB/GLC, VGLX.... -4 V to 16 V
CA/CB/CC, VCX .......... -0.6 V to 55 V
Sense Circuit Voltages,
CSP,CSN, LSS ............... -4 V to 6.5 V
Logic Supply Voltage,
VDD ........................... -0.3 V to +6.5 V
Logic Input/Outputs and OVSET, BOOSTS,
CSOUT, VDSTH ......... -0.3 V to 6.5 V
Operating Temperature Range,
! Drives wide range of n-channel MOSFETs in 3-phase bridges
! PFM boost converter for use with low-voltage battery supplies
! Internal LDO regulator for gate-driver supply
! Bootstrap circuits for high-side gate drivers
! Current monitor output
! Adjustable battery overvoltage detection.
! Diagnostic outputs
!
Motor lead short-to-battery, short-to-ground, and
bridge-open protection
!
Undervoltage protection
! -40 °C to +150 °C, TJ operation
! Thermal shutdown
TA ........................... -40°C to +135°C
Junction Temperature, TJ ........... +150°C
Storage Temperature Range,
TS ........................... -55°C to +150°C
* Fault conditions that produce excessive
junction temperature will activate device
thermal shutdown circuitry. These conditions
can be tolerated, but should be avoided.
Always order by complete part number, e.g., A3935KLQ .
3935
THREE-PHASE POWER
MOSFET CONTROLLER
Functional Block Diagram
See pages 8 and 9 for terminal assignments and descriptions.
115 Northeast Cutoff, Box 15036
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2003 Allegro MicroSystems, Inc.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
A3935KED (PLCC)
A3935KLQ (SOIC)
* Measured on “High-K” multi-layer PWB per JEDEC Standard JESD51-7.
† Measured on typical two-sided PWB with power tabs (terminals 1, 2, 11, 12, 22, 23, 34, and 35) connected to copper foil with an
area of 3.8 square inches (2452 mm2) on each side. See Application Note 29501.5, Improving Batwing Power Dissipation, for
additional information.
www.allegromicro.com
3
3935
THREE-PHASE POWER
MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits
Characteristics
Symbol
Conditions
Min
Typ Max
Units
Power Supply
VDD Supply Current
IDD
IBAT
VBAT
VDBOOT
All logic inputs = 0 V
All logic inputs = 0 V
–
–
–
–
–
–
–
–
–
–
–
7.0
3.0
40
mA
mA
V
VBAT Supply Current
Battery Voltage Operating Range
Bootstrap Diode Forward Voltage
7.0
0.8
1.5
2.5
-150
10
IDBOOT = -Icx = 10 mA, VDBOOT = VREG – VCX
IDBOOT = -Icx = 100 mA
2.0
2.3
7.5
-1150
30
V
V
Bootstrap Diode Resistance
Bootstrap Diode Current Limit
Bootstrap Quiescent Current
Bootstrap Refresh Time
rDBOOT
IDM
rD(100 mA) = [VD(150 mA) – VD(50 mA)]/100 mA
3 V < [VREG – VCX] < 12 V
Ω
mA
µA
µs
ICX
VCX = 40 V, GHx = ON
trefresh
VSX = low to guarantee ∆V = +0.5 V refresh of
–
2.0
0.47 µF Boot Cap at Vcx – Vsx = +10 V
1
VREG Output Voltage
VREG
VREGDO
IREG
VBAT = 7 V to 40 V, VBOOST from Boost Reg
VREGDO = Vboost – Vreg, Ireg = 40 mA
12.7
–
0.9
–
14
–
V
V
2
VREG Dropout Voltage
–
–
–
Gate Drive Avg. Supply Current
VREG Input Bias Current
Boost Supply
No external dc load at VREG, CREG = 10 µF
Current into VBOOST, ENABLE = 0
40
4.0
mA
mA
IREGBIAS
–
VBOOST Output Voltage Limit
VBOOST Output Volt. Limit Hyst.
Boost Switch ON Resistance
Max. Boost Switch Current
Boost Current Limit Threshold Volt.
OFF Time
VBOOSTM
∆VBOOSTM
rDS(on)
VBAT = 7 V
14.9
35
–
–
16.3
180
3.3
V
mV
Ω
IBOOSTD < 300 mA
Increasing VBOOSTS
–
1.4
–
IBOOSTSW
VBI(th)
–
300
0.55
8.0
mA
V
0.45
3.0
100
–
toff
–
µs
ns
Blanking Time
tblank
–
220
NOTES: Typical Data and Typical Characteristics are for design information only.
Negative current is defined as coming out of (sourcing) the specified device terminal.
1. For VBOOSTM < VBOOST < 40 V power dissipation in the VREG LDO increases. Observe TJ < 150 °C limit.
2. With VBOOST decreasing Dropout Voltage measured at VREG = VREGref – 200 mV where VREG(ref) = VREG at VBOOST = 16 V.
Continued next page …
115 Northeast Cutoff, Box 15036
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
3935
THREE-PHASE POWER
MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits
Characteristics
Control Logic
Symbol
Conditions
Min
Typ
Max
Units
Logic Input Voltages
VI(1)
VI(0)
II(1)
Minimum high level input for logical “one”
2.0
–
–
–
–
–
–
–
–
0.8
500
–
V
V
Maximum low level input for logical “zero”
–
Logic Input Currents
VI = VDD
–
50
µA
µA
mV
V
II(0)
VI = 0.8 V
Input Hysteresis
Vhys
VO(H)
VI(L)
100
300
–
Logic Output High Voltage
Logic Output Low Voltage
IO(H) = -800 µA
IO(L) = 1.6 mA
VDD–0.8
–
0.4
V
Gate Drives, GHx ( internal SOURCE or upper switch stages)
Output High Voltage
VDSL(H)
GHx: IxU = –10 mA, Vsx = 0
GLx: IxU = –10 mA, Vlss = 0
VSDU = 10 V, TJ = 25 °C
VREG–2.26
–
–
VREG
VREG
–
V
V
VREG–0.26
Source Current (pulsed)
Source ON Resistance
IxU
–
800
–
mA
mA
Ω
VSDU = 10 V, TJ = 135 °C
400
4.0
7.0
–
rSDU(on)
IxU = –150 mA, TJ = 25 °C
IxU = –150 mA, TJ = 35 °C
–
10
15
–
Ω
Gate Drives, GLx ( internal SINK or lower switch stages)
Sink Current (pulsed)
IxL
VDSL = 10 V, TJ = 25 °C
VDSL = 10 V, TJ = 135 °C
IxL = +150 mA, TJ = 25 °C
IxL = +150 mA, TJ = 135 °C
–
850
–
–
mA
mA
Ω
550
1.8
3.0
–
Sink ON Resistance
rDSL(on)
–
6.0
7.5
–
Ω
Gate Drives, GHx, GLx (General)
Phase Leakage (Source)
Propagation Delay, Logic only
Output Skew Time
ISx
tpd
ENABLE = 0, VSx = 1.7 V
0
–
–
–
–
–
100
150
50
µA
ns
ns
ns
Logic input to unloaded GHx, GLx
Grouped by edge, phase-to-phase
Between GHx, GLx transitions of same phase
tsk(o)
tdead
–
Dead Time (Shoot-Through
Prevention)
75
180
NOTES: Typical Data and Typical Characteristics are for design information only.
Negative current is defined as coming out of (sourcing) the specified device terminal.
For GHX: VSDU = VCX – VGHX, VDSL = VGHX – VSX, VDSL(H) = VCX – VSDU – VSX.
For GLX: VSDU = VREG – VGLX, VDSL = VGLX – VLSS, VDSL(H) = VREG – VSDU – VLSS.
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5
3935
THREE-PHASE POWER
MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits
Characteristics
Sense Amplifier
Input Bias Current
Input Offset Current
Input Resistance
Symbol
Conditions
Min
Typ Max
Units
Ibias
IIO
ri
CSP = CSN = 0 V
-180
–
–
–
-360
±35
–
µA
µA
CSP = CSN = 0 V
CSP with respect to GND
CSN with respect to GND
VID = CSP – CSN, -1.3V < CSP,N < 4V
CSP = CSN = 0 V
–
80
4.0
–
kΩ
–
–
kΩ
Diff. Input Operating Voltage
Output Offset Voltage
VID
VOO
∆VOO
VIC
–
±200
450
–
mV
mV
µV/°C
V
77
–
250
100
–
Output Offset Voltage Drift
Input Com-Mode Oper. Range
Voltage Gain
CSP = CSN = 0 V
CSP = CSN
-1.5
4.0
AV
VID = 40 mV to 200 mV
18.6 19.2 19.8
V/V
mV
dB
Low Output Voltage Error
DC Common-Mode Attenuation
Output Resistance
Ev
Vid = 0 to 40 mV, Vo = (19.2 x VID) + Vo + Ev
CSP = CSN = 200 mV
–
28
–
–
±25
AVC
–
ro
VCSOUT = 2.0 V
–
8.0
–
–
Ω
Output Dynamic Range
Output Current, Sink
VCSOUT
Isink
ICSOUT = -100 µA at top rail, 100 µA at bottom rail
VCSOUT = 2.5 V
0.075
20
VDD-0.25
V
–
–
–
–
–
–
–
–
mA
mA
dB
Output Current, Source
VDD Supply Ripple Rejection
VREG Supply Ripple Rejection
Small Signal 3-dB Bandwidth
AC Common-Mode Attenuation
Isource
PSRR
PSRR
f3db
VCSOUT = 2.5 V
-1.0
20
–
CSP = CSN = GND, freq. = 0 to 1 MHz
CSP = CSN = GND, freq. = 0 to 300 kHz
10 mV input
–
45
–
dB
–
1.6
–
MHz
dB
Avc
Vcm = 250 mV/pp, freq. = 0 to 800 kHz
200 mV step input, meas. 10/90% points
26
Output Slew Rate
SR
10
–
V/µs
(positive or negative)
NOTES: Typical Data and Typical Characteristics are for design information only.
Negative current is defined as coming out of (sourcing) the specified device terminal.
115 Northeast Cutoff, Box 15036
6
Worcester, Massachusetts 01615-0036 (508) 853-5000
3935
THREE-PHASE POWER
MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits
Characteristics
Symbol
Conditions
Min
Typ Max
Units
Fault Logic
VDD Undervoltage
VDD(uv)
∆VDD(uv)
VSET(ov)
VSET(ov)
ISET(ov)
Decreasing VDD
3.8
100
0
–
–
–
–
–
–
4.3
300
VDD
2.5
V
mV
V
VDD Undervoltage Hysteresis
OVSET Operating Volt. Range
OVSET Calibrated Volt. Range
OVSET Input Current Range
VBAT Overvoltage Range
VBAT Overvoltage
VDD(recovery) - VDD(uv)
0
V
-1.0
19.4
+1.0
40
µA
V
VBAT(ov)
VBAT(ov)
∆VBAT(ov)
KBAT(ov)
VBAT(uv)
∆VBAT(uv)
VREG(uv)
VDSTH
0 V < VSET(ov) < 2.5 V
Increasing VBAT, VSET(ov) = 0 V
Percent of VBAT(ov) value set by VSET(ov)
VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov) [0]
Decreasing VBAT
19.4 22.4 25.4
V
VBAT Overvoltage Hysteresis
VBAT Overvoltage Gain Constant
VBAT Undervoltage
9.0
–
–
12
5.25
–
15
–
%
V/V
V
5.0
5.5
VBAT Undervoltage Hysteresis
VREG Undervoltage
Percent of VBAT(uv)
8.0
12
%
V
Decreasing VREG
9.9
–
11.1
3.0
VDSTH Input Range
0.5
–
V
VDSTH Input Current
IDSTH
VDSTH > 0.8 V
40
–
100
µA
V
Short-to-Ground Threshold
VSTG(th)
With a high-side driver “on”, as VSX decreases,
VDRAIN - VSX > VSTG causes a fault
VDSTH-0.3
–
VDSTH+0.2
Short-to-Battery Threshold
VSTB(th)
With a low-side driver “on”, as VSX increases,
VSX - VLSS > VSTB causes a fault
VDSTH-0.3
–
VDSTH+0.2
V
VDRAIN /Open Bridge Oper. Range
VDRAIN /Open Bridge Current
VDRAIN /Open Bridge Threshold Volt.
Thermal Shutdown Temp.
VDRAIN
IVDRAIN
VBDGO(th)
TJ
7 V < VBAT < 40 V
-0.3
0
–
–
VBAT+2.0
1.0
V
mA
V
7 V < VBAT < 40 V
If VDRAIN < VBDGOTH then a bridge fault occurs
1.0
160
7.0
–
3.0
170
10
180
°C
°C
Thermal Shutdown Hysteresis
∆TJ
13
NOTES: Typical Data and Typical Characteristics are for design information only.
Negative current is defined as coming out of (sourcing) the specified device terminal.
www.allegromicro.com
7
3935
THREE-PHASE POWER
MOSFET CONTROLLER
Terminal Functions
A3935KED
(PLCC)
A3935KJP
(QLFP)
A3935KLQ
(SOIC)
Terminal Name
Function
CSP
VDSTH
LSS
Current-sense input, positive-side
DC input, drain-to-source monitor threshold voltage
Gate-drive source return, low-side
Gate-drive C output, low-side
Load phase C input
31
32
33
36
37
38
39
40
41
42
43
44
3
19
1
20
2
21
3
GLC
22
4
SC
26
5
GHC
Gate-drive C output, high-side
Bootstrap capacitor C
27
6
CC
28
7
GLB
Gate-drive B output, low-side
Load phase B input
29
8
SB
30
9
GHB
Gate-drive B output, high-side
Bootstrap capacitor B
31
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
29
30
31
32
33
–
CB
32
GLA
Gate-drive A output, low-side
Load phase A input
33
SA
34
GHA
Gate-drive A output, high-side
Bootstrap capacitor A
4
38
CA
5
39
VREG
VDRAIN
VBOOST
BOOSTS
BOOSTD
VBAT
UVFLT
OVFLT
FAULT
ALO
Gate drive supply, positive
6
40
Kelvin connection to MOSFET high-side drains
Boost supply output
7
41
8
42
Boost switch, source
9
43
Boost switch, drain
10
13
14
15
16
17
18
19
20
21
24
25
26
27
44
Battery supply, positive
46
VBAT undervoltage fault output
VBAT overvoltage fault output
Active-low fault output, primary
Gate control input A, low-side
Gate control input A, high-side
Gate control input B, high-side
Gate control input B, low-side
Gate control input C, low-side
Gate control input C, high-side
Gate output enable
3
4
5
6
AHI
7
BHI
8
BLO
9
CLO
10
CHI
11
ENABLE
OVSET
NC
12
DC input, overvoltage threshold setting for VBAT
Not connected, no external connection allowed
15
1,2,13,14,23,24,
25,35,36,37,47,48
CSOUT
VDD
Current-sense amplifier output
Logic supply, nominally +5 V
Current-sense input, negative-side
28
29
30
16
17
18
45
34
35
36
21
CSN
GND
Ground, dc supply returns, negative, and (for ED package) 1, 2, 11, 12,
heat sink tab 22, 23, 34, 35
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
3935
THREE-PHASE POWER
MOSFET CONTROLLER
Terminal Descriptions
AHI/BHI/CHI. Direct control of high-side gate outputs GHA/
GHB/GHC. Logic “1” drives the gate “on”. Logic ”0” pulls the
gate down, turning off the external power MOSFET. Internally
pulled down when terminal is open.
GND. Ground or negative side of VDD and VBAT supplies.
LSS. Low-side gate driver returns. Connects to the common
sources in the low-side of the power MOSFET bridge.
OVFLT. Logic “1” means that the VBAT exceeded the VBAT
overvoltage trip point set by OVSET level. It will recover after
a hysteresis below that maximum value. Normally has a high-
impedance state.
ALO/BLO/CLO. Direct control of low-side gate outputs GLA/
GLB/GLC. Logic “1” drives the gate “on”. Logic ”0” pulls the
gate down, turning off the external power MOSFET. Internally
pulled down when terminal is open.
OVSET. A positive, dc level that controls the VBAT overvolt-
age trip point. Usually, provided from precision resistor divider
network between VDD and GND, but can be held grounded for a
preset value. When terminal is open, sets unspecified but high
overvoltage trip point.
BOOSTD. Boost converter switch drain connection.
BOOSTS. Boost converter switch source connection.
CA/CB/CC. High-side connection for bootstrap capacitor,
positive supply for high-side gate drive. The bootstrap capacitor
is charged to VREG when the output Sx terminal is low. When
the output swings high, the voltage on this terminal rises with
the output to provide the boosted gate voltage needed for n-
channel power MOSFETs.
SA/SB/SC. Directly connected to the motor terminals, these
terminals sense the voltages switched across the load and are
connected to the negative side of the bootstrap capacitors. Also,
are the negative supply connection for the floating, high-side
drivers.
CSN. Input for current-sense, differential amplifier, inverting,
negative side. Kelvin connection for ground side of current-
sense resistor.
UVFLT. Logic “1” means that VBAT is below its minimum
value and will recover after a hysteresis above that minimum
value. Has a high-impedance state. [If UVFLT and OVFLT are
both in high-impedance state; then, at least, a thermal shutdown
or VDD undervoltage has occurred.]
CSOUT. Amplifier output voltage proportional to current
sensed across an external low-value resistor placed in the
ground-side of the power FET bridge.
VBAT. Battery voltage, positive input and is usually connected
to the motor voltage supply.
CSP. Input for current-sense differential amplifier, non-
inverting, positive side. Connected to positive side of sense
resistor.
VBOOST. Boost converter output, nominally 16 V, is also
input to regulator for VREG. Has internal boost current and
boost voltage control loops. In high-voltage systems is approxi-
ENABLE. Logic “0” disables the gate control signals and
switches off all the gate drivers “low” causing a “coast”. Can be
used in conjunction with the gate inputs to PWM the load
current. Internally pulled down when terminal is open.
mately one diode drop below VBAT
.
VDD. Logic supply, nominally +5 V.
FAULT. Diagnostic logic output signal, when “low” indicates
that one or more fault condition have occurred.
VDRAIN. Kelvin connection for drain-to-source voltage
monitor and is connected to high-side drains of MOSFET
bridge. High impedance when terminal is open and registers as
a short-to-ground fault on all motor phases.
GHA/GHB/GHC. High-side gate-drive outputs for n-channel
MOSFET drivers. External series gate resistors can control slew
rate seen at the power driver gate; thereby, controlling the di/dt
and dv/dt of Sx outputs.
VDSTH. A positive, dc level that sets the drain-to-source
monitor threshold voltage. Internally pulled down when
terminal is open.
GLA/GLB/GLC. Low-side gate drive outputs for external, n-
channel MOSFET drivers. External series gate resistors can
control slew rate.
VREG. High-side, gate-driver supply, nominally, 13.5 V. Has
low-voltage dropout (LDO) feature.
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9
3935
THREE-PHASE POWER
MOSFET CONTROLLER
Functional Description
Motor Lead Protection. A fault detection circuit monitors
the voltage across the drain to source of the external MOSFETs.
A fault is asserted “low” on the output terminal, FAULT, if the
drain-to-source voltage of any MOSFET that is instructed to turn
on is greater than the voltage applied to the VDSTH input terminal.
When a high-side switch is turned on, the voltage from VDRAIN to
the appropriate motor phase output, VSX, is examined. If the
motor lead is shorted to ground before the high side is turned on,
the measured voltage will exceed the threshold and the FAULT
terminal will go “low”. Similarly, when a low-side MOSFET is
turned on, the differential voltage between the motor phase
(drain) and the LSS terminal (source) is monitored. VDSTH is set
OVFLT. Asserts “high” when a VBAT overvoltage fault occurs
and resets “low” after a recovery hysteresis. It has a high-
impedance state when a thermal shutdown or VDD undervoltage
occurs. The voltage at the OVSET terminal, VOVSET, controls
the VBAT overvoltage set point VBAT(ov), i.e.,
VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov)(0),
where KBAT(ov) is the gain (12) and VBAT(ov)(0) is the value of
VBAT(ov) when VSET(ov) is zero (~22.4). For valid formula, all
variables must be in range and below maximum operating
specification.
UVFLT. Asserts “high” when a VBAT undervoltage fault occurs
and resets “low” after a recovery hysteresis. It has a high-
impedance state when a thermal shutdown or VDD undervoltage
occurs. OVFLT and UVFLT are mutually exclusive by defini-
tion.
by a resistor divider to VDD
.
The VDRAIN is intended to be a Kelvin connection for the high-
side, drain-source monitor circuit. Voltage drops across the
power bus are eliminated by connecting an isolated PCB trace
from the VDRAIN terminal to the drain of the MOSFET bridge.
This allows improved accuracy in setting the VDSTH threshold
voltage. The low-side, drain-source monitor uses the LSS
Current Sensing. A current-sense amplifier is provided to
allow system monitoring of the load current. The differential
amplifier inputs are intended to be Kelvin connected across a
low-value sense resistor or current shunt. The output voltage is
represented by:
terminal, rather than VDRAIN, in comparing against VDSTH
The A3935 merely reports these motor faults.
.
VCSOUT = ( ILOAD x AV x RS) + VOS
Fault Outputs. Transient faults on any of the fault outputs are
to be expected during switching and will not disable the gate
drive outputs. External circuitry or controller logic must
determine if the faults represent a hazardous condition.
where VOS is the output voltage calibrated at zero load current
and AV is the differential amplifier gain of about 19.2. If either
the CSP or CSN pin is open, the CSOUT pin will go to its
maximum positive level.
FAULT. This terminal will go active “low” when any of the
following conditions occur:
VBAT overvoltage,
Shutdown. If a fault occurs because of excessive junction
temperature or undervoltage on VDD or VBAT, all gate driver
outputs are driven “low” until the fault condition is removed. In
addition, the boost supply switch and the VREG are turned “off”
until those undervoltages and junction temperatures recover.
VBAT undervoltage,
VREG undervoltage,
Motor lead short-to-ground,
Motor lead short-to-supply (or battery),
Bridge (or VDRAIN) open,
Boost Supply. VBOOST is controlled by an inner current-
control loop, and by an outer voltage-feedback loop. The
current-control loop turns “off” the boost switch for 5 µs
whenever the voltage across the boost current-sense resistor
exceeds 500 mV. A diode reverse-recovery current flows
through the sense resistor whenever the boost switch turns “on”,
which could turn it “off” again if not for the “blanking time”
circuit. Adjustment of this external sense resistor determines the
maximum current in the inductor. Whenever VBOOST exceeds the
predefined threshold, nominally 16 V, the boost switch is
inhibited.
VDD undervoltage, or
Thermal shutdown.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
3935
THREE-PHASE POWER
MOSFET CONTROLLER
Functional Description (cont’d)
Input Logic
ENABLE xLO
xHI
X
0
GLx GHx
Mode of Operation
0
1
1
1
1
X
0
0
1
1
0
0
0
1
0
0
0
1
0
0
All gate drive outputs low
Both gate drive outputs low
High side on
1
0
Low side on
1
XOR circuitry prevents shoot-through
Fault Responses
ENABLE
Input
Boost
Reg.
VREG
Reg.
Fault Mode
No Fault
FAULT OVFLT UVFLT
GHx
"
"
"
"
"
"
0
GLx
"
"
"
"
"
"
0
X
1#
1$
1%
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Z
Z
0
0
0
0
0
0
1
Z
Z
ON
ON
ON
ON
Short-to-Battery
Short-to-Ground
ON
ON
Bridge (VDRAIN) Fault
VREG Undervoltage
VBAT Overvoltage
ON
ON
ON
ON
X
OFF&
OFF
OFF
OFF
ON
VBAT Undervoltage'
VDD Undervoltage'
Thermal Shutdown'
X
OFF
OFF
OFF
X
0
0
X
0
0
NOTES: x = “Little x ”indicates A, B, or C phase.
X = “Capital X “ indicates a “don’t care”.
Z = High-impedance state.
" = Depends on xLO input, xHI input, and ENABLE. See Input Logic table.
# = Short-to-battery can only be detected when the corresponding GLx = 1. This fault is not detected when ENABLE = 0.
$ = Short-to-ground can only be detected when the corresponding GHx = 1. This fault is not detected when ENABLE = 0.
% = Bridge fault appears as a short-to-ground fault on all motor phases. This fault is not detected when ENABLE = 0.
& = Off, only because VBOOST ≈ VBAT is above the voltage threshold of the regulator’s voltage control loop.
' = These faults are not only reported but action is taken by the internal logic to protect the A3935 and the system.
www.allegromicro.com
11
3935
THREE-PHASE POWER
MOSFET CONTROLLER
Package JP, 48-Pin LQFP
Package ED, 44-Pin PLCC
NC
GHA
37
38
39
40
41
42
43
44
45
46
24 NC
23 NC
VDRAIN
VBOOST
BOOSTS
BOOSTD
GND
7
8
39 CC
CA
22 GLC
21 LSS
20 VDSTH
38 GHC
37 SC
VREG
9
VDRAIN
VBOOST
BOOSTS
BOOSTD
GND
10
11
12
13
14
15
16
17
36 GLC
35 GND
CSP
19
18
17
16
15
CSN
VDD
CSOUT
OVSET
NC
GND
GND
LSS
34
33
32
31
30
29
VBAT
UVFLT
OVFLT
FAULT
ALO
VDSTH
CSP
VBAT
NC 47
14
13
CSN
VDD
NC
48
NC
Package LQ, 36-Pin SOIC
CSP
VDSTH
LSS
GLC
SC
1
2
36 CSN
35 VDD
3
34 CSOUT1
33 OVSET
32 ENABLE
4
5
GHC
CC
CHI
6
31
30
29
28
27
26
25
24
23
22
21
CLO
7
GLB
SB
BLO
8
BHI
9
GHB
CB
AHI
10
11
12
13
14
ALO
GLA
SA
FAULT
OVFLT
UVFLT
VBAT
GND
GHA
CA 15
VREG 16
VDRAIN 17
VBOOST 18
BOOSTD
BOOSTS
20
19
115 Northeast Cutoff, Box 15036
12
Worcester, Massachusetts 01615-0036 (508) 853-5000
3935
THREE-PHASE POWER
MOSFET CONTROLLER
A3935KED (PLCC)
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Webbed lead frame. Terminals 1, 2, 11, 12, 22, 23, 34, and 35 are internally one piece.
4. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.
www.allegromicro.com
13
3935
THREE-PHASE POWER
MOSFET CONTROLLER
A3935KJP (LQFP)
7º
0º
.20 0.008
.09 0.004
9
0.354
5
BSC
0.197
BSC
A
7
0.276
BSC
1
REF
0.039
48
1
2
.75 0.030
.45 0.018
.25 0.010
BSC
Seating Plane
Gauge Plane
.27 0.011
.17 0.007
1.60 0.063
1.40 0.055
.50 .020
BSC
.15
.05
0.006
0.002
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
A
Exposed thermal pad (bottom surface)
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
14
3935
THREE-PHASE POWER
MOSFET CONTROLLER
A3935KLQ (SOIC)
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option within limits shown.
3. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel.
www.allegromicro.com
15
3935
THREE-PHASE POWER
MOSFET CONTROLLER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
16
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