AKD4114-B_09 [AKM]
AK4114 Evaluation Board Rev.0; AK4114评估板Rev.0
| 型号： | AKD4114-B_09 |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | AK4114 Evaluation Board Rev.0 |
| 文件： | 总30页 (文件大小：737K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AKD4114-B]
AKD4114-B
AK4114 Evaluation Board Rev.0
GENERAL DESCRIPTION
AKD4114-B is the evaluation board for AK4114, 192kHz digital audio transceiver. This board has optical
and BNC connector to interface with other digital audio equipment.
Ordering guide
AKD4114-B
--- Evaluation board for AK4114
(A cable for connecting with printer port of IBM-AT compatible PC
and a control software are packed with this. The control software
does not operate on Windows NT.)
FUNCTION
Digital interface
-S/PDIF :
8 channel input (optical or BNC)
2 channel output (optical or BNC )
- Serial audio data I/F :
1 input/output (for DIR deta output/DIT data input. 10-pin port)
-B,C,U,V bit :
1 input/output port (10-pin port)
-Serial control data I/F
1 input/output port (10-pin port)
5V
GND
REG
Control
3.3V
Opt
RX0
RX1
RX7
AK4114
TX0
TX1
Opt
B,C,U,V
Serial Data out
(For DIR)
Figure 1. AKD4114-B Block Diagram
*Circuit diagram and PCB layout are attached at the end of this manual.
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Evaluation Board Manual
Operating sequence
(1) Set up the power supply lines.
[+ 5V]
[GND]
(Red) = 5V
(Black) = 0V
Each supply line should be distributed from the power supply unit.
(2) Set up the evaluation mode and jumper pins. (Refer to the following item.)
(3) Connect cables. (Refer to the following item.)
(4) Power on.
The AK4114 should be reset once bringing PDN(SW2) “L” upon power-up.
Evaluation modes
(1) Evaluation for DIR (Default)
S/PDIF in (optical or BNC) – AK4114 – Serial Data out (10pin port)
MCLK
BICK
LRCK
SDTO
MCLK
AK4114
(DIR)
Optical, XLR or
BNC connector
BICK
LRCK
SDTO
PORT2
(10pin Header)
DAC
S/PDIF
AKD4114-B
The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical
connector(PORT1: TORX176) or BNC connector. The AKD4114-B can be connected with the AKM’s DAC
evaluation board via 10-line cable.
a. Set-up of Bi-phase Input
RX0 and RX1-7 should not select BNC at the same time.
a-1. RX0
Connector
Optical (PORT1)
BNC (J2)
JP2(RXP0)
OPT
JP3(RXN0)
BNC
BNC
BNC
Table 1. Set-up of RX0
a-2. RX1, 2, 3, 4, 5, 6, and 7 can be inputted from a BNC (J2) connector only.
Only RX1, RX2 and RX 3 can be used in parallel mode. The jumper which selects the Rx channel should be
Short.
RX3
JP6
RX4
JP7
RX5
JP8
RX6
JP9
Input
JP
RX1
JP4
RX2
JP5
RX7
JP10
RX7
Short
RX4
RX5
RX6
Short
Short
Table 2. Set-up of RX1, 2, 3, 4, 5, 6 and 7
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a-3. Set-up of AK4114 input path
It sets up by SW 1_1 and SW 1_5 in parallel mode. Please set up IPS2-0 bits in serial mode.
IPS1 pin
(SW1_5)
IPS0 pin
(SW1_1)
-
INPUT Data
IPS2 bit
IPS1 bit
IPS0 bit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
Default
(In parallel mode, IPS2 is fixed to “0”)
Table 3. Recovery Data Select
b. Set-up of clock input and output
The signal level outputted/inputted from PORT2 is 3.3V.
PORT2
DIR
1
5
6
10
Figure 2. PORT2 pin layout
b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of
MCKO1/MCKO2 is selected by OCKS 1-0.
Output
JP12
signal
Default
MCKO1
MCKO2
MCKO1
MCKO2
Table 4. Set-up of MCKO1/MCKO2
OCKS1 pin OCKS0 pin
(SW3_2)
(SW3_3)
(X’tal)
MCKO1
MCKO2
fs (max)
OCKS1 bit OCKS0 bit
Default
0
0
1
1
0
1
0
1
256fs
256fs
512fs
128fs
256fs
256fs
512fs
128fs
256fs
128fs
256fs
64fs
96 kHz
96 kHz
48 kHz
192 kHz
Table 5. Master Clock Frequency Select
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b-2. Set-up of input/output of BICK and LRCK
Please select SW 3_7 (DIR_I/O) according to the setup of audio format of AK4114 (Refer to Table 7).
Audio format
Slave mode
Master mode
SW3_7 (DIR_I/O)
Default
0
1
Table 6. Set-up of DIR_I/O
c. Set-up of Audio format
It sets up by SW 1_2, SW 1_3 and SW1_4 in parallel mode. Please set up DIF2-0 bit in serial mode.
DIF2 pin DIF1 pin DIF0 pin
LRCK
I/O
BICK
Mode
DAUX
SDTO
(SW1_4) (SW1_3) (SW1_2)
DIF2 bit
DIF1 bit
DIF0 bit
I/O
O
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
16bit, Right
justified
18bit, Right
justified
20bit, Right
justified
24bit, Right
justified
0
1
2
3
0
0
0
H/L
H/L
H/L
H/L
O
O
O
O
64fs
0
0
0
0
1
1
1
0
1
64fs
64fs
64fs
O
O
O
24bit, Left
justified
24bit, Left
justified
4
5
6
7
1
1
1
1
0
0
1
1
0
1
0
1
H/L
L/H
H/L
L/H
O
O
I
64fs
64fs
O
O
I
24bit, I2S
24bit, Left
justified
24bit, I2S
24bit, Left
justified
64-128fs
64-128fs
Default
24bit, I2S
24bit, I2S
I
I
Table 7. Audio format
d. Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_1 and
JP18. In serial mode, it can be selected by CM1-0 bits.
CM1 pin
Clock
source
SDTO
source
CM0 pin (JP18)
(UNLOCK)
PLL
X'tal
(SW3_1)
CM1 bit
CM0 bit
0 (CM0)
Default
0
0
-
-
ON
OFF
ON
ON
ON
ON(Note)
ON
PLL(RX)
X'tal
RX
1 (CDTO/CM0=H)
DAUX
RX
0
1
-
ON
PLL(RX)
X'tal
1
1
0 (CM0)
ON
DAUX
DAUX
1 (CDTO/CM0=H)
ON
X'tal
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 8. Clock Operation Mode Select
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(2) Evaluation for DIT
Serial Data in(10pin port) – AK4114 – S/PDIF out(optical or BNC)
MCLK
BICK
LRCK
DAUX
MCLK
BICK
LRCK
PORT2
(10pin Header)
Optical, XLR or
BNC connector
AK4114
(DIT)
S/PDIF
ADC
DAUX *
* Input to the fifth pin.
AKD4114-B
MCLK, BICK, LRCK and DAUX are input the via 10pin header (PORT2: DIR).
a.Set-up of a Bi-phase output signal
TX0 and TX1 should not select an optical connector or a BNC connector at the same time.
a-1. The data outputted from TX1 can be selected by OPS12-10 bit.
Connector
Optical (PORT4)
BNC (J4)
JP19 (TX1)
OPT
JP14 (TX1)
BNC
BNC
BNC
Table 9. Set-up of TX1
a-2. As for TX0, only the loop back mode of RX corresponds. This mode is fixed to RX0 in parallel mode. In
serial mode, it can be selected by OPS02-00 bits.
Connector
Optical (PORT4)
BNC (J4)
JP13 (TX0)
OPT
JP19 (TXP1) JP14 (TXN1)
BNC
BNC
Open
Open
BNC
Table 10. Set-up of TX0
b.Set-up of clock input and output
The used signals are MCLK, LRCK, BICK, and DAUX.
The signal level outputted and inputted from PORT2 is 3.3V.
PORT2
DIR
1
5
6
10
Figure 3. PORT2 pin layout
Clock
MCLK
BICK
PORT
PORT2
PORT2
PORT2
PORT2
I/O
OUT
IN / OUT
IN / OUT
IN
LRCK
DAUX
Table 11. Clock input/output
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b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of
MCKO1/MCKO2 sets up by OCKS 1-0.
Output
JP12
signal
Default
MCKO1
MCKO2
MCKO1
MCKO2
Table 12. Selection of MCKO1/MCKO2
OCKS1 pin OCKS0 pin
(SW3_2) (SW3_3)
OCKS1 bit OCKS0 bit
(X’tal)
MCKO1
MCKO2
fs (max)
Default
0
0
1
1
0
1
0
1
256fs
256fs
512fs
128fs
256fs
256fs
512fs
128fs
256fs
128fs
256fs
64fs
96 kHz
96 kHz
48 kHz
192 kHz
Table 13. Master Clock Frequency Select
b-2. Set-up of input/output of BICK and LRCK
Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4114 (Refer to Table 20).
JP16 and 17 should be fixed to the “DC” side.
Audio format
Slave mode
Master mode
SW3_8 (DIT_I/O)
Default
0
1
Table 14. Set-up of DIT_I/O
c. Set-up of audio data format
Please refer to Table 7.
d. Set-up of CM1 and CM0
CM1 pin CM0 pin
SDTO
source
(UNLOCK)
PLL
X'tal
Clock source
(SW3_1)
(JP18)
CM1 bit
CM0 bit
Default
0
0
0
1
-
-
ON
OFF
ON
ON
ON
ON(Note)
ON
PLL(RX)
X'tal
RX
DAUX
RX
0
1
-
ON
PLL(RX)
X'tal
1
1
0
1
ON
DAUX
DAUX
ON
X'tal
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 15. Clock Operation Mode Select
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B, C, U, V Inputs and output
B(block start), C(channel status), U(user data) and V(validity) are inputted/outputted via 10pin header (PORT3:
BCUV). Pin arrangement of PORT3 has become like Figure 3.
PORT3
BCUV
10
1
6
5
Figure 4. PORT3 pin layout
Serial control
The AK4114 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT6
(uP-I/F) with PC by 10-line flat cable packed with the AKD4114-B. Take care of the direction of connector. There
is a mark at pin#1. The pin layout of PORT6 is as Figure 5.
Mode
4 wire Serial
IIC
SW1_6
JP18
CDTO/CM0=“H”
SDA and CM0=“L”(Note)
L
H
Note: In IIC mode, the chip address is fixed to “01”.
Table 16. Set-up of Parallel mode and Serial mode
PORT6
uP I/F
2
1
10
9
Figure 5. PORT6 pin layout
This evaluation board encloses control software. A software operation procedure is included in an evaluation board
manual.
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Toggle switch set-up
Reset switch for AK4114. Set to “H” during normal operation. Bring to “L” once after the
power is supplied.
SW2
PDN
LED indication
LE1
LE2
Bright when INT0 pin goes to “H”.
Bright when INT1 pin goes to “H”.
INT0
INT1
DIP switch (SW1) set-up: -off- means “L”
No.
1
2
3
4
Switch Name
IPS0
DIF0
DIF1
DIF2
Function
Default
OFF
OFF
ON
Set-up of IPS0 pin. (in parallel mode)
Set-up of DIF0 pin. (in parallel mode)
Set-up of DIF1 pin. (in parallel mode)
Set-up of DIF2 pin. (in parallel mode)
Set-up of IPS1 pin. (in parallel mode)
Set-up of IIC pin. (in serial mode) “L”: 4 wire Serial, “H”: IIC
Set-up of P/SN pin. “L”: Serial mode, “H”: Parallel mode
Don’t care
ON
5
IPS1/IIC
OFF
OFF
OFF
OFF
6
7
8
P/SN
TEST
ACKS
Don’t care
DIP switch (SW3) set-up: -off- means “L”
No.
1
2
3
4
Switch Name
CM1
OCKS1
OCKS0
PSEL
Function
Default
OFF
OFF
OFF
OFF
OFF
OFF
Set-up of CM1 pin. (in parallel mode)
Set-up of OCKS1 pin. (in parallel mode)
Set-up of OCKS0 pin. (in parallel mode)
Don’t care
5
6
XTL0
XTL1
See Table 17
Set-up of the transmission direction of 74AC245
DIR_I/O
DIT_I/O
7
8
“L”: When inputting from PORT2, “H”: When outputting from
PORT2
Don’t care
ON
OFF
Set-up of XTL1 and XTL0
SW3_6
XTL1
SW3_5
XTL0
X’tal Frequency
X’tal
0
0
1
1
0
1
0
1
11.2896MHz
12.288MHz
24.576MHz
Default
(Use channel status)
Table 17. Set-up of XTL1 and XTL0
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Jumper set up.
No.
Jumper Name
Function
Set-up of Power supply source for 74AC245.
D3V : D3V (default)
1
D3V/VD
VD : VD
Set-up of RXP0 input circuit.
OPT : Optical (default)
BNC : BNC
2
RXP0
4,5,6
RX1-3
Set-up of RX1-3 input circuit.
RX4-7 set-up depending serial/parallel mode
RX4-7 : Serial mode (default)
DIF2-0,IPS0 : Parallel mode
7,8,9,10 RX4-7
MCKO set-up for PORT5(DIT) and PORT2(DIR)
MCKO1 : MCKO1 of AK4114 (default)
MCKO2 : MCKO2 of AK4114
Set-up of TX0 output circuit.
DIR MCLK ,
DIT MCLK
11,12
13
TX0
OPT : Optical
BNC : BNC (default)
Set-up of SDA/CDTO pin.
4 wire Serial : CDTO/CM0=“H”. (default)
IIC : SDA
Set-up of TXP1 input circuit.
OPT : Optical (default)
BNC : BNC
18
19
SDA/CDTO
TXP1
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Control Soft Manual
Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10wire flat cable. Be aware of the direction of
the 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD
must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing the
driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This control soft
does not support the Windows NT.
3.Proceed evaluation by following the process below.
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■Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting.
1. [Port Reset]
: For when connecting to USB I/F board (AKDUSBIF-A)
Click this button after the control soft starts up when connecting USB I/F board
(AKDUSBIF-A).
2. [Write Default]
: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
: Executing write commands for all registers displayed.
: Executing read commands for all registers displayed.
: Saving current register settings to a file.
3. [All Write]
4. [All Read]
5. [Save]
6. [Load]
: Executing data write from a saved file.
7. [All Req Write]
8. [Data R/W]
9. [Sequence]
: “All Req Write” dialog box is popped up.
: “Data R/W” dialog box is popped up.
: “Sequence” dialog box is popped up.
10. [Sequence(File)] : “Sequence(File)” dialog box is popped up.
11. [Read] : Reading current register settings and display on to the Register area
(on the right of the main window).
This is different from [All Read] button, it does not reflect to a register map, only
displaying hexadecimal.
Figure 6. Window of [ FUNCTION]
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■Dialog Boxes
[All Req Write]
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
Figure 7. Window of [ All Reg Write]
[Open (left)]
[Write]
: Selecting a register setting file (*.akr).
: Executing register writing.
[Write All]
: Executing all register writings.
Writings are executed in descending order.
: Help window is popped up.
[Help]
[Save]
[Open (right)]
[Close]
: Saving the register setting file assignment. The file name is “*.mar”.
: Opening a saved register setting file assignment “*. mar”.
: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register
settings.
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[Data R/W]
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Figure 8. Window of [ Data R/W ]
Address Box : Input data address in hexadecimal numbers for data writing.
Data Box
Mask Box
: Input data in hexadecimal numbers.
: Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write]
[Close]
: Writing to the address specified by “Address” box.
: Closing the dialog box and finish the process.
Data writing can be cancelled by this button instead of [Write] button.
*The register map will be updated after executing [Write] or [Read] commands.
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[Sequence]
Click [Sequence] button to open register sequence setting dialog box.
Register sequence can be set in this dialog box.
Figure 9. Window of [ Sequence ]
Sequence Setting
Set register sequence by following process bellow.
(1)Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use
· Register
: Not using this address
: Register writing
· Reg(Mask) : Register writing (Masked)
· Interval
· Stop
· End
: Taking an interval
: Pausing the sequence
: Finishing the sequence
(2)Input sequence
[Address]
[Data]
: Data address
: Writing data
: Mask
[Mask]
[Data] box data is ANDed with [Mask] box data. This is the actual writing data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
[ Interval ] : Interval time
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Valid boxes for each process command are shown bellow.
· No_use
· Register
: None
: [Address], [Data], [Interval]
· Reg(Mask) : [Address], [Data], [Mask], [Interval]
· Interval
· Stop
: [Interval]
: None
· End
: None
Control Buttons
The function of Control Button is shown bellow.
[Start] : Executing the sequence
[Help] : Opening a help window
[Save] : Saving sequence settings as a file. The file name is “*.aks”.
[Open] : Opening a sequence setting file “*.aks”.
[Close] : Closing the dialog box and finish the process.
Stop of the sequence
When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked.
Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence,
“Start Step” will return to “1”.
The sequence can be started from any step by writing the step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
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[Sequence(File)]
Click [Sequence(File)] button to open sequence setting file dialog box.
Those files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 10. Window of [ Sequence(File) ]
[Open (left)] : Opening a sequence setting file (*.aks).
[Start]
: Executing the sequence setting.
[Start All]
: Executing all sequence settings.
Sequences are executed in descending order.
: Pop up the help window.
: Saving sequence setting file assignment. The file name is “*.mas”.
[Help]
[Save]
[Open(right)] : Opening a saved sequence setting file assignment “*. mas”.
[Close] : Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog
“*.mas” should be stored in the same folder.
(2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click “OK”
to continue the process.
Figure 11. Window of [ Sequence Pause ]
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1. [REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Grayout registers are Read Only registers. They can not be controlled.
The registers which is not defined in the datasheet are indicated as “---”.
Figure 12. Window of [ REG]
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[Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
Figure 13. Window of [ Register Set ]
[Read]: Data Read
Click [Read] button located on the right of the each corresponded address to execute register reading.
After register reading, the display will be updated regarding to the register status.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Please be aware that button statuses will be changed by Read command.
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REVISION HISTORY
Reason Page
Date
Manual
Board
Contents
(yy/mm/dd)
04/11/22
05/06/21
05/12/22
07/12/19
09/08/05
Revision
Revision
KM076600
KN076601
KM076602
KM076603
KM076604
0
0
0
0
0
First edition
Change
Addition
Modification
Change
13-15 Circuit diagram was changed
2,5
5
Block diagram at DIR/DIT Evaluation was added.
DIT Evaluation item was modified.
“Control Soft Manual” was changed.
10-18
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use
of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
[KM076604]
- 19 -
2009/08
5
4
3
2
1
CN4
D
C
B
A
D
C
B
A
P/SN
C19
2
1
10u
C20
0.1u
CN1
R61
18k
CN3
+
C21
0.47u
DIF0/RX5
1
2
48
U7
XTL1
XTL0
XTL1
XTL0
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DIF1/RX6
PDN
1
2
36
35
34
33
32
31
30
29
28
27
26
25
3
IPS0/RX4
INT0
4
PDN
AVSS
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
PDN
DIF2/RX7
IPS1/IIC
3
5
DIF0/RX5
TEST2
DIF1/RX6
AVSS
IPS1/IIC
4
6
VIN
5
7
DAUX
6
PDN
C22
8
DAUX
AK4114
OCKS0/CSN/CAD
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
INT1
7
9
DIF2/RX7
IPS1/IIC
P/SN
XTI
X1
5p
5p
MCKO1
MCKO2
C23
8
MCKO1
MCKO2
IPS1/IIC
P/SN
10
11
12
13
14
15
16
XTO
11.2896MHz
DAUX
9
DAUX
10
11
12
XTL0
XTL0
MCKO2
MCKO2
BICK
XTL1
XTL1
BICK
BICK
SDTO
LRCK
INT0
BICK
SDTO
LRCK
VIN
SDTO
SDTO
C24
0.1u
C25
0.1u
LRCK
MCKO1
C26
10u
C27
10u
1
2
1
2
Title
Size
CN2
AKD4114
Document Number
R ev
A
A3
SUB
Date:
Monday, November 22, 2004
Sheet
1
3
o f
3
5
4
3
2
5
4
3
2
1
CN1
JP1
PORT1
GND
L1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
D3V
VD
For U6
For U1, U2, U5
For U3, U4
6
5
4
3
2
1
10u
D3V
VD
6
VD
D3V
VD
D3V/VD
VCC
GND
OUT
C7
C8
+
5
TORX176
R1
0.1u
10u
C1
C2 C3 C4
C5
C6
JP2
0.1u
0.1u0.1u0.1u
0.1u 0.1u
AVDD
P/SN/ANS
ACKS
OPT
XLR
BNC
470
1
3
5
2
4
6
AVDD
P/SN/ANS
ACKS
D
C
B
A
D
C
B
A
T2
LP2950A
+5V
L2
RXN0
R3
10u
1
3
TVDD/VDD
AVDD
OUT
IN
RXP0
short
+
C11
47u
R4
VD
J2
RX0
short
C13
RX1
T3
TA48M33F
R5
75
JP4
0.1u
AVDD
RX2
R6
AVDD
DVDD
OVDD
D3V
OUT
IN
JP5
JP6
short
R7
+
+
C14
47u
C15
47u
SW1
IPS0
DIF0
DIF1
DIF2/XSEL
IPS1/IIC
P/SN/ANS
TEST
JP7
JP8
short
R8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D3V
RX3
AVDD
RX4
IPS0
AVDD
short
IPS0/RX4
ACKS
RP1
RX5
1
2
3
4
5
6
7
8
9
DIF0
CN2
DIF0/RX5
TEST
IPS1/IIC
P/SN/ANS
TEST
1
JP9
RX6
ACKS
TEST
2
DIF1/RX6
PDN
47k
DIF1
3
JP10
4
RX7
DIF2/XSEL/RX7
DVDD
5
DIF2/XSEL
R9
10k
DVDD
VIN
6
D3V
VIN
D1
7
U1
U2A
U2B
1S1588
2
3
5
R10
100
1A
1B
2A
2B
3A
3B
4A
4B
DAUX
4
1
2
3
4
DAUX2
1Y
2Y
3Y
4Y
8
H
L
6
7
74HC14
74HC14
JP11
11
10
14
13
EMCK1
9
R11
R12
C16
9
100
100
EMCK2
DAUX2
SW2
PDN
0.1u
MCKO1
MCKO2
OVDD
MCKO1
12
10
11
12
13
14
15
16
MCKO
15
1
G
A/B
MCKO2
DIT_MCLK
74LVC157
JP12
DIR_MCLK
DVDD
MCKO1
R13
R14
100
100
PORT2
10
9
8
7
MCKO2
U3
GND
GND
GND
GND
GND
MCLK
BICK
LRCK
SDTO
DAUX
R15
R16
R18
R20
1
2
3
4
5
100
100
100
100
BICK
SDTO
LRCK
R17
R19
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
100
100
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
R21
6
100
R22
R23
DIR
100k 100k 100k
1
19
DIR_I/O
DIR
OE
74AC245
Title
AKD4114-B
Size
A3
Document Number
Rev
0
MAIN
Date:
Friday, November 19, 2004
Sheet
1
1
of
2
5
4
3
2
5
4
3
2
1
CN3
PORT3
B
C
R24
R25
R26
R27
R28
1
2
3
4
5
10
B
100
100
100
100
100
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
JP19 TXP1
9
8
7
6
C
OPT
XLR
BNC
1
3
5
2
4
6
U
VOUT
VIN
VIN
U
BCUV
R29
R30
R31
R32
47k
VOUT
TVDD
TX0
TXP1
TXN1
47k
47k
47k
D
C
B
A
D
C
B
A
JP13
TX0
TVDD/VDD
PORT4
OPT
5
6
4
3
2
1
5
IN
VCC
IF
VD
C17
6
GND
R33
1k
TOTX176
0.1u
J4
T5
R36
TX0
DA02-F
1:1
240
R37
150
OVDD
OVDD
EBICK
CN4
EMCK
ELRCK
U2C
EMCK2
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
LE1
R45
6
5
9
1k
INT0
74HC14
U2D
INT0
LE2
R47
INT1
8
D3V
1k
INT1
U5
CM0/CDTO/CAD1
CM1/CDTI/SDA
OCKS1/CCLK/SCL
OCKS0/CSN/CAD0
DVDD
74HC14
R48
R49
R52
R55
10k
470
470
470
2
3
5
VD
1A
1B
2A
2B
3A
3B
4A
4B
R50
R53
4
1Y
2Y
3Y
4Y
R51
R54
10k
10k
100
100
6
7
11
10
14
13
U6A
9
PORT6
10
9
CSN
12
1
2
R56
8
6
4
2
7
5
3
1
SCL/CCLK
SDA/CDTI
51
15
1
G
A/B
74LS07
SDA(ACK)/CDTO
P/SN/ANS
R57
D3V
JP18
DVDD
74LVC157
SDA
CDTO/CM0=H
CM0=L
10k
uP-I/F
R58
R59
D3V
R60
100
10k
SW3
SDA/CDTO
100
IPS1/IIC
PSEL
CM1/FS1
OCKS1/FS2
OCKS0/FS0
PSEL
XTL0/CKS1
XTL1/TRANS
DIR_I/O
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D3V
IPS1/IIC
D3V/VD
XTL0
DIT_I/O
XTL1
RP2
1
2
3
4
5
6
7
8
9
DIR_I/O
DIT_I/O
47k
Title
Size
AKD4114-B
Document Number
Rev
0
A3
MAIN
Date:
Tuesday, June 21, 2005
Sheet
1
2
of
2
5
4
3
2
AKD4115-A L1
AKD4115-A L1_SILK
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