AKD4115-A [AKM]
AK4115 Evaluation Board Rev.3; AK4115评估板订正
| 型号： | AKD4115-A |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | AK4115 Evaluation Board Rev.3 |
| 文件： | 总32页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AKD4115-A]
AKD4115-A
AK4115 Evaluation Board Rev.3
GENERAL DESCRIPTION
AKD4115 is the evaluation board for AK4115, 192kHz digital audio transceiver. This board has optical,
cannon connector (XLR), and BNC connectors to interface with other digital audio equipment.
Ordering guide
AKD4115-A --- Evaluation board for AK4115
(A cable for connecting the printer port (parallel port) of IBM-AT compatible PC
and control software are packed with this document. Please note that the control
software does not operate on Windows NT)
FUNCTION
Digital interface
-S/PDIF :
8 channel input (optical, BNC or XLR)
2 channel output (optical, BNC or XLR)
- Serial audio data I/F :
1 input (for DIT data input. 10-pin port)
1 output (for DIR data output. 10-pin port)
-B,C,U,V bit :
1 input/output port (10-pin port)
-Serial control data I/F
1 input/output port (10-pin port)
5V
GND
REG
Control
3.3V
Opt
RX0
RX1
RX7
AK4115
Opt
TX0
TX1
Serial Data in
(To DIT)
B,C,U,V
Serial Data out
(From DIR
Figure 1. AKD4115-A Block Diagram
*Circuit diagram and PCB layout are attached at the end of this manual.
<KM076403>
2006/08
- 1 -
ASAHI KASEI
[AKD4115-A]
Evaluation Board Manual
Operating sequence
(1) Set up the power supply lines.
[+ 5V]
[GND]
(Red) = 5V
(Black) = 0V
Each supply line should be distributed from the power supply unit.
(2) Set up the evaluation mode and jumper pins. (Refer to the following item.)
(3) Connect cables. (Refer to the following item.)
(4) Power on.
The AK4115 should be reset once bringing PDN (SW2) “L” upon power-up.
Evaluation modes
(1) Evaluation for DIR
MCLK
BICK
LRCK
SDTI
MCLK
BICK
LRCK
SDTI
AK4115
(DIR)
Optical, XLR or
BNC connector
PORT2
(10pin Header)
DAC
S/PDIF
AKD4115-A
The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical
connector(PORT1: TORX176), BNC connector or cannon connector(XLR). The AKD4115 can be connected
with the AKM’s DAC evaluation board via 10-pin cable.
a. Set-up of Bi-phase Input
RXP0/RXN0 and RX1-7 should not select BNC at the same time.
a-1. RXP0/RXN0
Connector
Optical (PORT1)
XLR (J1)
JP2(RXP0)
OPT
JP3(RXN0)
BNC
XLR
XLR
BNC (J2)
BNC
BNC
Table 1. Set-up of RXP0/RXN0
a-2. RX1, 2, 3, 4, 5, 6, and 7 can be inputted from a BNC (J2) connector only.
Only RX1, RX2 and RX 3 can be used in parallel mode. The jumper which selects the Rx channel should be
Short.
RX3
JP6
RX4
JP7
RX5
JP8
RX6
JP9
Input
JP
RX1
JP4
RX2
JP5
RX7
JP10
RX7
Short
RX4
RX5
RX6
Short
Short
Table 2. Set-up of RX1, 2, 3, 4, 5, 6 and 7
<KM076403>
2006/08
- 2 -
ASAHI KASEI
[AKD4115-A]
a-3. Set-up of AK4115 input path
In Parallel Mode you will need to use SW1_1 & SW1_5.
In Serial Mode you will need to use IPS2-0 bits.
IPS1 pin
(SW1_5)
IPS0 pin
(SW1_1)
-
INPUT Data
IPS2 bit
IPS1 bit
IPS0 bit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
Default
(In parallel mode, IPS2 is fixed to “0”)
Table 3. Recovery Data Select
b. Set-up of clock input and output
The signal level outputted/inputted from PORT2 is 3.3V.
PORT2
DIR
1
5
6
10
Figure 2. PORT2 pin layout
b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2
is selected by OCKS 1-0.
Output
JP12
signal
Default
MCKO1
MCKO2
MCKO1
MCKO2
Table 4. MCKO1/MCKO2 set-up
OCKS1 pin OCKS0 pin
(SW3_2)
(SW3_3)
(X’tal)
MCKO1
MCKO2
fs (max)
OCKS1 bit OCKS0 bit
Default
0
0
1
1
0
1
0
1
256fs
256fs
512fs
128fs
256fs
256fs
512fs
128fs
256fs
128fs
256fs
64fs
96 kHz
96 kHz
48 kHz
192 kHz
Table 5. Master Clock Frequency Select
<KM076403>
2006/08
- 3 -
ASAHI KASEI
[AKD4115-A]
b-2. Set-up of BICK and LRCK input and output
Please select SW 3_7 (DIR_I/O) according to the setup of audio format of AK4115 (Refer to Table 7).
Audio format
Slave mode
Master mode
SW3_7 (DIR_I/O)
Default
0
1
Table 6. DIR_I/O set-up
c. Set-up of Audio format
It sets up by SW 1_2 and SW 1_3 in parallel mode. Please set up DIF2-0 bit and AES3 bit in serial mode.
DIF1 pin DIF0 pin
-
-
LRCK
BICK
(SW1_3) (SW1_2)
Mode
DAUX
SDTO
AES3 DIF2
bit
DIF1 bit
DIF0 bit
I/O
I/O
O
bit
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
16bit, Right
justified
18bit, Right
justified
20bit, Right
justified
24bit, Right
justified
0
1
2
3
0
0
0
0
1
1
0
1
0
1
H/L
H/L
H/L
H/L
O
O
O
O
64fs
0
0
0
0
0
0
64fs
64fs
64fs
64fs
O
O
O
24bit, Left
justified
24bit, Left
justified
4
5
6
0
0
0
1
1
1
0
0
1
0
1
0
H/L
L/H
H/L
O
O
I
O
O
I
24bit, I2S
24bit, Left
justified
24bit, I2S
24bit, Left
justified
64fs
64-128f
s
64-128f
s
Default
7
8
0
1
1
x
1
x
1
x
24bit, I2S
24bit, I2S
L/H
I
I
24bit, Left
justified
AES3 Mode H/L
O
64fs
O
Table 7. Audio format
<KM076403>
2006/08
- 4 -
ASAHI KASEI
[AKD4115-A]
d. Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_4, SW3_1
and JP18. In serial mode, it can be selected by PSEL bit and CM1-0 bits.
PSEL pin CM1 pin CM0 pin
SDTO
(UNLOCK)
PLL
X'tal
Clock source
(SW3_4) (SW3_1)
PSEL bit CM1 bit
(JP18)
source
CM0 bit
Default
0
0
0
0
0
1
-
-
ON
OFF
ON
ON
ON
ON(Note)
ON
PLL(RX)
X'tal
RX
DAUX
RX
0
1
-
ON
PLL(RX)
X'tal
0
1
0
ON
DAUX
DAUX
0
1
1
ON
X'tal
1
1
0
0
0
1
-
-
ON
OFF
ON
ON(Note) PLL(ELRCK) DAUX
ON
ON
ON
X'tal
PLL(ELRCK) DAUX
X'tal DAUX
DAUX
0
1
1
1
0
ON
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 8. Clock Operation Mode Select
<KM076403>
2006/08
- 5 -
ASAHI KASEI
[AKD4115-A]
(2) Evaluation for DIT
1. Synchronous mode
MCLK
BICK
MCLK
BICK
LRCK
PORT2
(10pin Header)
Optical, XLR or
BNC connector
AK4115
(DIT)
LRCK
ADC
S/PDIF
DAUX
DAUX
PORT5
(10pin Header)
AKD4115-A
2. Asynchronous mode
EMCK
EBICK
ELRCK
DAUX
EMCK
EBICK
ELRCK
PORT2
(10pin Header)
Optical, XLR or
BNC connector
AK4115
(DIT)
S/PDIF
ADC
DAUX
AKD4115-A
MCLK, BICK, LRCK and DAUX are input the via 10pin header (PORT5: DIT). The AKD4115-A can be
connected with the AKM’s ADC evaluation board via 10-pin cable.
a. Set-up of a Bi-phase output signal
TX0 and TXP0/TXN0 should not select an optical connector or a BNC connector at the same time.
a-1. The data outputted from TXP1/TXN1 can be selected by OPS12-10 bit.
Connector
Optical (PORT4)
XLR (J3)
JP19 (TXP1)
OPT
JP14 (TXN1)
BNC
XLR
XLR
BNC (J4)
BNC
BNC
Table 9. Set-up of TXP1/TXN1
a-2. As for TX0, only the loop back mode of RX corresponds. This mode is fixed to RX0 in parallel mode. In
serial mode, it can be selected by OPS02-00 bits.
Connector
Optical (PORT4)
BNC (J4)
JP13 (TX0)
OPT
JP19 (TXP1) JP14 (TXN1)
BNC
BNC
Open
Open
BNC
Table 10. Set-up of TX0
<KM076403>
2006/08
- 6 -
ASAHI KASEI
[AKD4115-A]
b. Set-up of clock input and output
b-1. In the case of synchronous mode (ASYNC bit="0" or Parallel mode)
The used signals are MCKO1, MCKO2, LRCK, BICK, ELRCK and DAUX.
The signal level outputted and inputted from PORT2 and PORT5 is 3.3V.
Clock
MCLK
BICK
PORT
PORT2
PORT2
LRCK
DAUX
ELRCK
PORT2
PORT5
PORT5(LRCK)
Table 11. Clock input and output
b-1-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2
sets up by OCKS 1-0.
Output
signal
JP12
JP15
JP11
Default
MCKO1
MCKO2
MCKO1
MCKO2
MCKO
MCKO
MCKO1
MCKO2
Table 12. Selection of MCKO1/MCKO2
OCKS1 pin OCKS0 pin
(SW3_2) (SW3_3)
OCKS1 bit OCKS0 bit
(X’tal)
MCKO1
MCKO2
fs (max)
Default
0
0
1
1
0
1
0
1
256fs
256fs
512fs
128fs
256fs
256fs
512fs
128fs
256fs
128fs
256fs
64fs
96 kHz
96 kHz
48 kHz
192 kHz
Table 13. Master Clock Frequency Select
b-1-2. Set-up of BICK and LRCK input and output
Please select SW 3_7 (DIR_I/O) according the setup of audio format of AK4115 (Refer to Table 7).
Audio format
Slave mode
Master mode
SW3_7 (DIR_I/O)
Default
0
1
Table 14. Set-up DIR_I/O
b-1-3. A set up of ELRCK
As a reference clock of PLL, when using ELRCK clock, it inputs from PORT5 (LRCK).
JP16
AC
JP17
AC
When inputting by AC coupling
When inputting by CMOS level
Default
DC
DC
Table 15. Set-up of ELRCK input
<KM076403>
2006/08
- 7 -
ASAHI KASEI
[AKD4115-A]
b-2. In the case of the asynchronous mode (ASYNC bit= "1" , This mode is supported in serial mode.)
The used signals are EMCK, X'tal, EBICK, ELRCK, and DAUX. These signal levels outputted / inputted from
PORT5 is 3.3V.
Clock
MCLK
BICK
PORT
PORT5
PORT5
PORT5
PORT5
PORT5
LRCK
DAUX
ELRCK
Table 16. Clock input and output
b-2-1. Set-up of Master clock
When EMCK is used
MSEL bit
Output signal
EMCK
JP15
1
EMCK
Table 17. Selection of EMCK
When X'tal is used as master clock
JP12
JP15
Output signal
MCKO1
JP11
MCKO1
MCKO2
MCKO
MCKO
MCKO1
MCKO2
MCKO2
Table 18. Selection of MCKO1/MCKO2
b-2-2. Setup of BICK and LRCK input and output
Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4115 (Refer to Table 20).
JP16 and 17 are fixed to the “DC” side.
Audio format
Slave mode
Master mode
SW3_8 (DIT_I/O)
Default
0
1
Table 19. DIT_I/O set-up
c. Set-up of audio data format
c-1. In case of synchronous mode.
Please refer to Table 7.
c-2. In case of asynchronous mode
ELRCK
I/O
EBICK
Mode EDIF1 bit EDIF0 bit
DAUX
I/O
O
O
I
4
5
6
7
0
0
1
1
0
1
0
1
24bit, Left justified
24bit, I2S
H/L
L/H
H/L
L/H
O
O
I
64fs
64fs
64-128fs
64-128fs
24bit, Left justified
Default
24bit, I2S
I
I
Table 20. Audio data format in asynchronous mode
<KM076403>
2006/08
- 8 -
ASAHI KASEI
[AKD4115-A]
d. Set-up of PSEL, CM1 and CM0
d-1. In case of synchronous mode.
Please refer to Table 8.
d-2. In case of asynchronous mode
RX
Clock
I/O
CM1 CM0
(UNLOCK)
-
PLL
ON
X'tal
Clock
source
Clock
source
Clock
I/O
bit
bit
SDTO
RX
X’tal or
EMCK
PLL
Default
0
0
0
1
ON(Note 2)
Note 3
Note 4
(RX)
(Note 5)
X’tal or
EMCK
X’tal or
EMCK
X’tal or
EMCK
X’tal or
EMCK
-
0
1
-
OFF
ON
ON
ON
ON
ON
ON
ON
X’tal
Note 3
Note 3
Note 3
Note 3
“L”
RX
“L”
“L”
Note 4
Note 4
Note 4
Note 4
PLL
(RX)
1
1
0
1
X’tal
X’tal
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note 2: When the X’tal is not used as clock comparison for sampling frequency detection (i.e. XTL1, 0 =
“1, 1”), the X’tal is OFF.
Note 3: MCKO1/2, BICK, LRCK
Note 4: EMCK OR X’tal, EBICK, ELRCK, DAUX
Note 5: When X’tal is OFF, the clock source supports EMCK only.
Table 21. Clock Operation Mode Select
<KM076403>
2006/08
- 9 -
ASAHI KASEI
[AKD4115-A]
B, C, U, V Inputs and output
B(block start), C(channel status), U(user data) and V(validity) are inputted via 10pin header (PORT3: BCUV).
When BCU_IO bit is set to “1”, they are input signals. And when BCU_IO bit is set to “0”, they are output signals.
In parallel mode, they are fixed to output signals. Pin arrangement of PORT3 has become like Figure 3.
PORT3
BCUV
10
1
6
5
Figure 3. PORT3 pin layout
Serial control
The AK4115 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect the included
10pin cable to PORT6 (uP-I/F) of the AKD4115-A. Take care of the direction of connector. There is a mark at
pin#1. And the pin layout of PORT6 is as Figure 4 shows.
Mode
4 wire Serial
SW1_5
L
JP18
CDTO/CM0=“H” (Short)
SDA (Short)
CM0=“L” (Short)
(Note)
IIC
H
Note: In IIC mode, the chip address is fixed to “01”.
Table 22. Set-up of Parallel mode and Serial mode
PORT6
uP I/F
2
1
10
9
Figure 4. PORT6 pin layout
The evaluation board also includes control software and a software operation procedure is included in the evaluation
board manual.
<KM076403>
2006/08
- 10 -
ASAHI KASEI
[AKD4115-A]
Toggle switch set-up
Reset switch for AK4115. Set to “H” during normal operation. Bring to “L” once after the
power is supplied.
SW2
PDN
LED indication
LE1
LE2
Bright when INT0 pin goes to “H”.
Bright when INT1 pin goes to “H”.
INT0
INT1
DIP switch (SW1) set-up: -off- means “L”
No.
1
Switch Name
IPS0
Function
Default
OFF
Set-up of IPS0 pin. (in parallel mode)
2
DIF0
Set-up of DIF0 pin. (in parallel mode)
OFF
3
DIF1
Set-up of DIF1 pin. (in parallel mode)
OFF
4
XSEL
Set-up of XSEL pin. (in parallel mode) “L”: X’tal 1, “H”: X’tal 2
Set-up of IPS1 pin. (in parallel mode)
Set-up of IIC pin. (in serial mode) “L”: 4 wire Serial, “H”: IIC
OFF
5
IPS1/IIC
OFF
OFF
6
7
P/SN
Set-up of P/SN pin. “L”: Serial mode, “H”: parallel mode
TEST
Set-up of TEST pin. (always “OFF”)
Set-up of ACKS pin. (in parallel mode)
“L”: Manual Setting, “H”: Auto Setting
Table 23
OFF
8
ACKS
OFF
DIP switch (SW3) set-up: -off- means “L”
No.
1
2
Switch Name
CM1
OCKS1
OCKS0
Function
Default
OFF
OFF
Set-up of CM1 pin. (in parallel mode)
Set-up of OCKS1 pin. (in parallel mode)
Set-up of OCKS0 pin. (in parallel mode)
Set-up of PSEL pin. (in parallel mode)
”L”: S/PDIF Input, “H”: ELRCK Input Clock
Set-up of XTL0 pin.
3
OFF
4
PSEL
OFF
5
6
XTL0
XTL1
OFF
OFF
Set-up of XTL1 pin.
Set-up of the transmission direction of 74AC245
“L”: When inputting from PORT2, “H”: When outputting from PORT2
Set-up of the transmission direction of 74AC245
“L”: When inputting from PORT5, “H”: When outputting from PORT5.
Table 24
DIR_I/O
DIT_I/O
7
8
ON
OFF
Set-up of XSEL, XTL1 and XTL0
SW1_4
Status
XSEL
0
1
X’tal #1
Power-Up
Power-Down
X’tal #2
Power-Down
Power-Up
Table 25. Setting of X’tal oscillator
SW3_6
SW3_5
X’tal Frequency
XTL1
XTL0
X’tal #1
11.2896MHz
12.288MHz
24.576MHz
X’tal #2
0
0
1
1
0
1
0
1
12.288MHz
11.2896MHz
22.5792MHz
Default
(Use channel status)
Table 26. Reference X’tal frequency
<KM076403>
2006/08
- 11 -
ASAHI KASEI
[AKD4115-A]
Jumper set up.
No.
Jumper Name
Function
Set-up of Power supply source for 74AC245.
D3V : D3V (default)
VD : VD
Set-up of RXP0 input circuit.
OPT : Optical (default)
XLR : XLR
1
D3V/VD
RXP0
2
BNC : BNC
Set-up of RXP0 input circuit.
OPT : Optical (default)
BNC : BNC
3
RXN0
RX1-3
4,5,6
Set-up of RX1-3 input circuit.
RX4-7 set-up depending serial/parallel mode
RX4-7 : Serial mode (default)
7,8,9,10 RX4-7
DIF2-0,IPS0 : Parallel mode
MCKO set-up for PORT5(DIT) and PORT2(DIR)
MCKO1 : MCKO1 of AK4115 (default)
MCKO2 : MCKO2 of AK4115
Set-up of TX0 output circuit.
OPT : Optical
DIR MCLK ,
DIT MCLK
11,12
13
TX0
BNC : BNC (default)
Set-up of TXN1 output circuit.
XLR : XLR
BNC : BNC (default)
MCLK input output selection of PORT5(DIT).
MCKO : MCKO (default)
EMCK : EMCK
14
15
TXN1
MCLK
Set-up of ELRCK input signal.
AC : AC
16,17
18
ELRCK
SDA/CDTO
DC : DC (default)
Set-up of SDA/CDTO pin.
4 wire Serial : CDTO/CM0=“H” (default)
IIC : SDA
Set-up of TXP1 input circuit.
OPT : Optical (default)
XLR : XLR
19
TXP1
BNC : BNC
<KM076403>
2006/08
- 12 -
ASAHI KASEI
[AKD4115-A]
Control Software Manual
Set-up of evaluation board and control software
1. Set up the AKD4115-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4115-A by 10-line type flat cable (packed with AKD4115-A). Take care
of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AKD4115-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4115-a.exe” to set up the control program.
5. Then please evaluate according to the follows.
Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
Explanation of each buttons
[Port Reset] :
Set up the USB interface board (AKDUSBIF-A) .
[Write default] : Initialize the register of AK4115.
[All Write] :
[Function1] :
[Function2] :
[Function3] :
[Function4] :
[Function5]:
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
[SAVE] :
[OPEN] :
[Write] :
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”.
<KM076403>
2006/08
- 13 -
ASAHI KASEI
[AKD4115-A]
Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to the AK4115, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog]: Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal.
Data Box:
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4115, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate volume
Address Box:
Start Data Box:
End Data Box:
Interval Box:
Step Box:
Input registers address in 2 figures of hexadecimal.
Input starts data in 2 figures of hexadecimal.
Input end data in 2 figures of hexadecimal.
Data is written to the AK4115 by this interval.
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to the AK4115, click [OK] button. If not, click [Cancel] button.
<KM076403>
2006/08
- 14 -
ASAHI KASEI
[AKD4115-A]
4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
“akr”.
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is “akr”.
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK4115. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
<KM076403>
2006/08
- 15 -
ASAHI KASEI
[AKD4115-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file
name is “aks”.
Figure 5. Window of [F3]
<KM076403>
2006/08
- 16 -
ASAHI KASEI
[AKD4115-A]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 10 opens.
Figure 6. [F4] window
<KM076403>
2006/08
- 17 -
ASAHI KASEI
[AKD4115-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 11. ( In case that the selected sequence file name is
“DAC_Stereo_ON.aks”)
Figure 7. [F4] window(2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file.
The extension of the file is “*.ak4”.
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the
change.
<KM076403>
2006/08
- 18 -
ASAHI KASEI
[AKD4115-A]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed. When [F5] button is clicked, the window as shown in Figure 12 opens.
Figure 8. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 13. (In case that the selected file name is
“DAC_Output.akr”)
(2) Click [WRITE] button, then the register setting is executed.
<KM076403>
2006/08
- 19 -
ASAHI KASEI
[AKD4115-A]
Figure 9. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file
name is “*.ak5”.
[OPEN] : The file extension assignment of the register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be
loaded again in order to reflect the change.
<KM076403>
2006/08
- 20 -
ASAHI KASEI
[AKD4115-A]
Revision History
Date
Manual
Board
Reason
Contents
(YY/MM/DD)
Revision
Revision
04/12/08
06/02/15
KM076400
KM076401
0
1
First edition
Modification
• Circuit diagram was changed (page 1/3).
• The R61 changed from 15kΩ to 10kΩ.
06/06/15
KM076402
2
Add the explanation P13
“Instruction for use” was added.
Change control software Control software was updated: 1.0 → 3.0
Control software manual was changed:
P13-14 → P14-21
Error Correct
P10
• SW_6 →SW_5
• CDTO/CM0=“H” → CDTO/CM0=“H” (Short)
• SDA and CM0=“L” → SDA (Short)
CM0=“L” (Short)
06/08/10
KM076403
3
Change device Revision AK4115: Rev. C → Rev. D
Delete the explanation P13
“Instruction for use” was deleted.
Change control software Control software was updated: 3.0 → 4.0
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application
or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or
other hazard related device or system, and AKM assumes no responsibility relating to any such use, except
with the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from
any and all claims arising from the use of said product in the absence of such notification.
<KM076403>
2006/08
- 21 -
5
4
3
2
1
CN5
C19
10u
C22
C20
0.1u
C21
0.1u
0.1u
D
C
B
A
D
C
B
A
C23
4.7u
R61
10k
U7
CN6
C24
100p
R62
24k
C25
0.01u
CN7
48
DIF0/RX5
TEST
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
DIF0/RX5
FILT
XTL1
XTL1
XTL0
TEST
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DIF1/RX6
3
3
DIF1/RX6
PDN
XTL0
PDN
PSEL
4
4
PSEL
XSEL/RX7
DVDD
IPS1/IIC
5
5
XSEL/RX7
DVDD
VIN
IPS1/IIC
BVSS
DVSS
DVDD
6
6
+
C26
10u
C27
0.1u
VIN
7
7
+
C28
C29
DAUX
DVDD
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
INT1
8
8
DAUX
DVSS
MCKO1
MCKO2
OVDD
OVSS
BICK
0.1u
10u
AK4115
9
9
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
INT1
MCKO1
MCKO2
10
11
12
13
14
15
16
10
11
12
13
14
15
16
+
C30
10u
C31
0.1u
BICK
SDTO
LRCK
INT0
INT0
ELRCK
SDTO
LRCK
ELRCK
EMCK
EMCK
C32
0.1u
C33
0.1u
12.288MHz
1
11.2896MHz
1
X1
X2
2
2
C34
10u
C39
10u
C35
5p
C36
5p
C37
5p
C38
5p
Title
AKD4115
Size
A3
Document Number
Rev
3
CN8
Sockt
Date:
Thursday, August 10, 2006
Sheet
1
1
of
3
5
4
3
2
5
4
3
2
1
CN4
JP1
1
PORT1
GND
L1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
D3V
2
For U6
For U1, U2, U5
For U3, U4
6
5
4
3
2
1
10u
2
D3V
VD
6
1
VD
D3V
VD
D3V/VD
VCC
GND
OUT
3
VD
C7
C8
+
5
TORX176
R1
0.1u
10u
C1
C2 C3 C4
C5
C6
JP2
0.1u
0.1u0.1u0.1u
0.1u 0.1u
AVDD
P/SN/ANS
ACKS
OPT
XLR
BNC
470
1
3
5
2
4
6
AVDD
P/SN/ANS
ACKS
D
C
B
A
D
C
B
A
T1
C9
DA02-F
4
8
T2
LP2950A
+5V
0.1u
C10
R2
JP3
1
L2
RXN0
R3
XLR
2
10u
2
3
1
5
110
2
3
1:1
1
3
1
2
TVDD/VDD
AVDD
OUT
IN
3
0.1u
RXP0
BNC
short
+
C11
47u
R4
J1
C12
XLIN
0.1u
VD
J2
short
C13
RX0
RX1
2
3
4
5
1
T3
TA48M033F
R5
75
JP4
0.1u
1
2
2
2
AVDD
RX2
R6
AVDD
2
1
DVDD
OVDD
D3V
OUT
IN
JP5
JP6
1
1
short
R7
+
+
C14
47u
C15
47u
SW1
IPS0
DIF0
DIF1
DIF2/XSEL
IPS1/IIC
P/SN/ANS
TEST
JP7
1
short
R8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D3V
RX3
AVDD
RX4
2
3
IPS0
AVDD
short
IPS0/RX4
ACKS
JP8
1
RP1
RX5
2
9
8
7
6
5
4
3
2
1
3
DIF0
CN1
DIF0/RX5
TEST
IPS1/IIC
P/SN/ANS
TEST
1
JP9
1
RX6
2
ACKS
TEST
2
3
DIF1/RX6
PDN
DIF1
3
47k
JP10
1
4
RX7
2
3
DIF2/XSEL/RX7
DVDD
5
D3V
DIF2/XSEL
R9
DVDD
VIN
6
U1
D3V
10k
D3V
2
3
5
1A
1B
2A
2B
3A
3B
4A
4B
VIN
4
D1
1S1588
1Y
7
U2A
74HC14
U2B
74HC14
6
7
R10
100
2Y
3Y
4Y
DAUX
11
10
14
13
1
2
3
4
EMCK1
DAUX1
DAUX2
8
R11
R12
9
100
100
EMCK2
DAUX2
H
L
12
9
C16
SW2
JP11
1
15
1
0.1u
G
A/B
MCKO1
MCKO2
OVDD
MCKO1
2
PDN
10
11
12
13
14
15
16
MCKO
3
74LVC157
MCKO2
DIT_MCLK
JP12
1
DIR_MCLK
OVDD
MCKO1
2
R13
R14
100
D3V/VD
3
100
PORT2
10
9
8
7
6
MCKO2
U3
GND
GND
GND
GND
NC
MCLK
BICK
LRCK
SDTO
R15
R16
R18
R20
1
2
3
4
5
100
100
100
100
BICK
SDTO
LRCK
R17
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
100
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
R70
R71
R72
R73
R74
R75
R19
R21
47k
47k
47k
47k
47k
47k
100
100
R76
R77
R78
R79
R80
R81
47k
47k
47k
47k
47k
47k
R22
R23
DIR
100k 100k
1
19
DIR
OE
74AC245
DIR_I/O
Title
AKD4115-A
Size
A3
Document Number
Rev
3
MAIN1
Date:
Thursday, August 10, 2006
Sheet
1
2
of
3
5
4
3
2
5
4
3
2
1
CN2
PORT3
B
C
GND
+5V
R24
R25
R26
R27
R28
1
2
3
4
5
10
B
C
U
VOUT
VIN
100
100
100
100
100
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
JP19 TXP1
9
8
7
6
T45_BK
T45_BK
OPT
XLR
BNC
1
3
5
2
4
6
VIN
U
BCUV
+5V
R29
R30
R31
R32
47k
VOUT
TVDD
TX0
TXP1
TXN1
47k
47k
47k
D
C
B
A
D
C
B
A
JP13
TVDD/VDD
PORT4
TX0
1
OPT
2
5
4
3
2
1
5
IN
VCC
IF
VD
C17
3
T4
R34
75
BNC
6
DA02-F
6
GND
R33
1k
4
8
TOTX176
0.1u
XLR JP14
3
2
3
1
5
2
2
3
J4
T5
1:1
1
R36
BNC
JP15
TX0
1
DA02-F
J3
2
3
4
5
4
8
TXN1
MCLK
XLOUT
1
3
MCKO
2
430
MCKO
EMCK1
R37
1
5
150
1:1
EMCK
R38
D3V/VD
100k
PORT5
10
U4
GND
MCLK
BICK
LRCK
DAUX
1
GND
GND
GND
NC
R82
R83
R96
R97
9
8
7
6
2
3
4
5
100
100
18
17
16
15
14
13
12
11
2
100
100
B0
B1
B2
B3
B4
B5
B6
B7
A0
1
3
DC
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
R84
R85
R86
R87
R88
R89
R90
47k
47k
47k
47k
47k
47k
47k
OVDD
R91
R92
R93
R94
R95
47k
47k
47k
47k
47k
DAUX1
OVDD
AC
R40
R41
JP16
DIT
100k
100k
R42
ELRCK
100k
EBICK
1
19
DIT_I/O
DIR
OE
74AC245
C18
0.1u
CN3
U2C
R44
JP17
0
EMCK
ELRCK
LE1
R45
ELRCK
EMCK2
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
K
6
5
1
R46
DC
1k
2
INT0
75
3
74HC14
AC
INT0
U2D
LE2
R47
INT1
A
K
8
9
D3V
D3V
1k
INT1
U5
CM0/CDTO/CAD1
CM1/CDTI/SDA
OCKS1/CCLK/SCL
OCKS0/CSN/CAD0
DVDD
74HC14
R48
R49
10k
470
470
470
2
3
5
VD
1A
1B
2A
2B
3A
3B
4A
4B
R50
R53
4
1Y
2Y
3Y
4Y
R51
R54
R52
R55
10k
10k
100
100
U2E
11
6
7
11
10
14
13
VD
10
9
PORT6
U6A
10
8
6
4
2
9
CSN
SCL/CCLK
SDA/CDTI
SDA(ACK)/CDTO
12
74HC14
U2F
R56
7
5
3
1
51
15
1
1
2
G
A/B
P/SN/ANS
DVDD
74LVC157
74LS07
13
12
uP-I/F
74HC14
R57
10k
D3V
R58
JP18
R59
1
3
2
4
6
D3V
R60
SDA
CDTO/CM0=H5
CM0=L
100
SW3
10k
IPS1/IIC
PSEL
CM1/FS1
OCKS1/FS2
OCKS0/FS0
PSEL
XTL0/CKS1
XTL1/TRANS
DIR_I/O
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D3V
IPS1/IIC
SDA/CDTO
100
D3V/VD
XTL0
DIT_I/O
RP2
XTL1
9
8
7
6
5
4
3
2
1
U6B
U6D
U6F
3
5
4
9
8
13
12
74LS07
74LS07
74LS07
DIR_I/O
DIT_I/O
U6C
6
U6E
10
Title
Size
47k
11
AKD4115-A
74LS07
74LS07
Document Number
Rev
3
A3
MAIN2
Date:
Thursday, August 10, 2006
Sheet
1
3
of
3
5
4
3
2
相关型号：
©2020 ICPDF网 联系我们和版权申明