HSDL-3202G [AGILENT]
Interface Circuit, BICMOS;
| 型号： | HSDL-3202G |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | Interface Circuit, BICMOS |
| 文件： | 总16页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HSDL-3202
®
IrDA Data 1.3 Low Power
Compliant 115.2 Kb/s Infrared
Transceiver
Data Sheet
Features
• Ultra small surface mount
package
• Minimal height: 2.5 mm
• V from 2.7 to 3.6 volts
CC
• Interface to input/output logic
circuits as low as 1.8 V
• LED supply voltage can range from
2.7 to 6 volts
• Low I shutdown current
– 10 nA typical
• Complete shutdown
– TxD, RxD, PIN diode
• Three optional external
components
• Temperature performance guaran-
teed, –25°C to 85°C
• 32 mA LED drive current
• Integrated EMI shield
• IEC825-1 class 1 eye safe
CC
Description
tance of IrDA Data 1.3 (low
power) physical layer
specification.
The HSDL-3202 is a new generation
of low-cost Infrared (IR) transceiver
modules from Agilent Technologies.
It features one of the smallest foot-
prints in the industry at 2.5 H x
8.0 W x 3.0 D mm. Although the
supply voltage can range from 2.7 V
to 3.6 V, the LED drive current is
internally compensated to a con-
stant 32 mA to guarantee link dis-
The HSDL-3202 meets the link
distance of 20 cm to other IrDA
1.3 low power devices, and 30 cm
to standard one meter IrDA 1.3
devices. It is designed to interface
to input/output logic circuits as
low as 1.8 V.
• Edge detection input
– prevents the LED from
long turn on time
Applications
• Mobile telecom
– cellular phones
– pagers
IrDA 1.3
STANDARD OR
LOW POWER
CELL PHONES
PAGERS
– smart phones
PDAs
CAMERAS
• Data communication
– PDAs
– portable printers
• Digital imaging
– digital cameras
IrDA 1.3
CELL PHONES
PAGERS
PRINTERS
PCs
LOW POWER
20 CM TO LOW POWER DEVICES
30 CM TO STANDARD DEVICES
PDAs
– photo-imaging printers
CAMERAS
• Electronic wallet
Application Circuit
8 VLED
7 TXD
LED
CURRENT
SOURCE
C1
1.0 µF
TXD
RXD
6 RXD
5 SD
Pinout, Rear View
SHUT DOWN
4 AGND
3
V
CC
8
7
6
5
4
3
2
1
RX PULSE
SHAPER
C2
1.0 µF
2
I/O V
CC
C3
1.0 µF
1 GND
I/O Pins Configuration Table
Pin Symbol Description
Notes
1
2
GND
IOV
Ground
Connect to system ground
Connect to ASIC logic
Input/Output
CC
ASIC V
controller V voltage
CC
CC
3
4
5
V
Supply Voltage
Analog Ground
Regulated, 2.7 to 3.6 volts
CC
AGND
SD
Connect to a ”quiet“ ground
Shut Down
Active High
This pin must be driven either high
or low. Do NOT float the pin.
6
7
RXD
TXD
Receiver Data Output
Active Low
Output is a low pulse for 1.6 µs
when a light pulse is seen
Transmitter Data Input Logic High turns on the LED. If
Active High
held high longer than ~ 20 µs, the
LED is turned off. TXD must be
driven high or low. Do NOT float
the pin.
8
VLED
LED Supply Voltage
May be unregulated, 2.7 to 6 volts.
–
SHIELD EMI Shield
Connect to system ground via a
low inductance trace. For best
performance, do not connect to
GND or AGND directly at the part.
Recommended Application Circuit Components
Component
Recommended Value
1.0 µF, ± 20%, Tantalum
1.0 µF, ± 20%, Tantalum
1.0 µF, ± 20%, Tantalum
Note
C1
C2
C3
1
1
1
2
Absolute Maximum Ratings
Shutdown Mode Notes
For implementations where case-to-ambient thermal resistance is ≤ 50°C/W.
When the HSDL-3202 is in Shut-
down Mode (SD pin high), the
part presents different imped-
ances to the rest of the circuit
than when it is in normal mode.
Parameter
Symbol
Min.
–40
–25
0
Max.
100
85
7
Units
°C
°C
V
Storage Temperature
Operating Temperature
LED Supply Voltage
Supply Voltage
T
T
S
A
V
V
VLED
RXD Pin: This pin is NOT Tri-
state. During shutdown the
equivalent circuit is a weak
0
7
V
CC
Input/Output Voltage
Input Voltage: TXD, SD
Output Voltage: RXD
IOV
0
7
V
CC
pullup (~300 kΩ) to V . The
CC
V
I
0
IOV + 0.5
V
CC
ESD protection diodes to V and
CC
V
O
–0.5
IOV + 0.5
V
Ground are also present.
CC
Solder Reflow
Temperature Profile
See page 12
TXD Pin: Input protection
diodes are present.
VLED Pin: Typical leakage
current of 1.5 nA.
Transceiver I/O Truth Table
The outputs (LED and RXD) are
controlled by the combination of
the TXD and SD (shutdown) pins
and light falling on the receiver.
As shown in the table below, the
transmitter is non-inverting; the
LED is on when the TXD pin is
high and off when TXD is low.
The receiver is inverting; the RXD
pin is low during IrDA signal
pulses and high when the receiver
does not see any light. When
shutdown (SD pin high), the LED
is off (the state of the TXD pin
does not matter), and the RXD
pin is pulled high with a weak
internal pullup.
SD Pin: Will draw approximately
10 nA when driven high.
SD
TXD
High
Low
LED
On
Receiver
RXD
Notes
2
Low
Don’t care
IrDA signal
No signal
Don’t care
Not valid
Low
Off
3, 4
High
High
Don’t care
Off
High
5
Caution: The BiCMOS inherent to this design of this component increases the component’s suscep-
tibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions
be taken in handling and assembly of this component to prevent damage and/or degradation
which may be induced by ESD.
3
Recommended Operating Conditions
Parameter
Symbol Min.
Max.
85
Units
°C
V
Conditions
Notes
Operating Temperature
Supply Voltage
T
–25
2.7
1.8
A
V
CC
3.6
Input/Output Voltage
IOV
V
CC
V
IOV operational at
CC
CC
1.5 V at reduced spec
LED Supply Voltage
V
LED
2.7
6
V
TXD, SD Input
Voltage
Logic High
Logic Low
V
IH
V
IL
2/3 IOV
0
IOV
1/3 IOV
V
V
IOV ≥ 1.8 V
CC
CC
CC
IOV ≥ 1.8 V
CC
CC
2
Receiver Input
Irradiance
Logic High
Logic Low
EI
EI
0.0081
500
0.4
mW/cm
µW/cm
For in-band signals
For in-band signals
7
7
H
L
2
Receiver Data Rate
Ambient Light
2.4
115.2
Kb/s
See Test Methods on page 15 for details
RXD Output Waveform
Receiver Wakeup Time Definition
t
PW
SD
V
OH
90%
50%
10%
RX
LIGHT
V
OL
RXD
VALID DATA
t
t
R
F
t
RW
LED Optical Waveform
Transmitter Wakeup Time Definition
t
PW
LED ON
90%
SD
50%
TXD
10%
LED OFF
t
t
F
R
TX
LIGHT
t
TW
TXD “Stuck ON” Protection
TXD
LED
t
OPW (MAX.)
4
Electrical & Optical Specifications
Specifications hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions
may be anywhere in their operating range. All typical values are at 25°C and 3.0 V unless otherwise noted.
Parameter
Symbol Min.
Typ.
Max.
Units
Conditions
Note
Receiver
Viewing Angle
Peak Sensitivity Wavelength
2θ
30
–
–
–
–
°
1/2
λp
880
nm
V
RXD Output
Voltage
Logic High
V
OH
IOV – 0.2 –
IOV
I
= –200 µA, EI ≤ 0.3
CC
CC
OH
2
µW/cm
Logic Low
V
0
–
–
–
0.3
3.5
70
V
I
= 200 µA
7
7
OL
PW
R
OL
RXD Pulse Width
RXD Rise Times
t
t
2.5
20
µs
ns
t
(EI) = 1.6 µs, C = 9.0 pF
PW
L
Max. value @ IOV = 1.8 V
CC
RXD Fall Times
t
t
t
–
–
–
25
20
20
50
ns
µs
µs
t
(EI) = 1.6 µs, C = 9.0 pF
PW L
F
Receiver Latency Time
Receiver Wake Up Time
50
8
9
L
100
RW
Transmitter
Radiant Intensity
IE
4
8
28.8
mW/Sr T = 25°C, θ ≤ 15°,
A 1/2
H
TXD ≥ 2/3 IOV
CC
Viewing Angle
2θ
30
–
–
60
–
°
1/2
Peak Wavelength
Spectral Line Half Width
Optical Pulse Width
λ
875
35
nm
nm
p
∆λ
–
–
1/2
t
–
–
2.0
20
2.23
30
µs
µs
t
(TXD) = 1.6 µs
PW
OPW
TXD pin stuck high
Optical Rise and Fall Times
Optical Rise and Fall Times
t
t
–
–
–
–
600
600
ns
ns
t
t
(TXD) = 1.6 µs
(TXD) = 1.6 µs
OR
OF
PW
PW
TXD Logic Levels High
Low
V
IH
V
IL
2/3 IOV
0
–
–
IOV
1/3 IOV
V
V
IOV ≥ 1.8 V
CC
CC
CC
IOV ≥ 1.8 V
CC
CC
TXD Input Current High
Low
I
I
–
–1
0.01
-0.01
1
–
µA
µA
V ≥ 2/3 IOV
I CC
0 ≤ VI ≤ 1/3 IOV
H
L
CC
LED Current
On
I
–
32
38
mA
V
= V = 3.6 V, V (TXD)
VLED
VLED CC I
≥ 2/3 IOV
CC
Off
I
–
0.0015 1
µA
V
= V = 3.6 V, V (TXD)
VLED
VLED
CC
I
≤ 1/3 IOV
CC
Shutdown
I
t
–
–
0.0015 1
µA
µs
V (SD) ≥ 2/3 IOV
I CC
VLED
TW
Transmitter Wake Up Time
12
100
10
5
Parameter
Symbol Min.
Typ. Max.
Units Conditions
Note
Transceiver
SD Logic
Levels
High
Low
V
IH
V
IL
2/3 IOV
0
–
–
IOV
1/3 IOV
V
V
IOV ≥ 1.8 V
CC
CC
CC
IOV ≥ 1.8 V
CC
CC
SD Input
Current
High
Low
I
I
–
–300
10
–10
200
–
nA
nA
V ≥ 2/3 IOV . Max value at 25°C
I CC
H
0 ≤ V ≤ 1/3 IOV . Max value at 25°C
L
I CC
Supply
Shutdown I
–
–
–
10
200
250
10.0
nA
µA
mA
V
CC
V
CC
V
CC
= 3.6 V, V = IOV
SD CC
CC1
CC2
CC3
Current
Idle
I
I
100
2.0
= 3.6 V, V (TXD) ≤ 1/3 IOV , EI=0
I
CC
Peak
= 3.6 V, V (TXD) ≤ 1/3 IOV
11, 12
11
I
CC
Active
Receive
Peak
Active
Transmit
I
I
–
–
5.0
30
9.0
mA
nA
V
CC
= 3.6 V, V (TXD) ≤ 2/3 IOV
I
CC4
CC
IOV Current
200
CC
IOV
CC
Notes:
1. C1,C2, and C3 must be placed within 0.7 cm of the HSDL-3202 to obtain optimum noise immunity. If V and V are tied together, then the
LED
CC
application may use one less capacitor.
2. If TXD is stuck in the high state, the LED will turn off after about 20 µs.
3. In-Band IrDA signals and data rates ≤ 115.2 Kb/s.
4. RXD Logic Low is a pulsed response. The condition is maintained for a duration that is dependent upon the data pattern.
5. RXD Logic High during shutdown is a weak pullup resistor (300 kΩ).
6. An in-band optical signal is a pulse/sequence where the peak wavelength, λ , is defined as 850 nm ≤ λ ≤ 900 nm, and the pulse
p
p
characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification.
2
2
7. For in-band signals [115.2 Kb/s where 8.1 µW/cm ≤ EI ≤ 500 mW/cm ].
8. Latency is defined as the time from the last TXD light output pulse until the receiver has recovered full sensitivity.
9. Receiver wake up time is measured from the SD pin high-to-low transition or V power on to valid RXD output.
CC
10. Transmitter wake up time is measured from the SD pin high-to-low transition or V power on to valid light output in response to a TXD pulse.
CC
2
11. Typical values are at EI = 10 mW/cm .
2
12. Maximum value is at EI = 500 mW/cm .
6
Package Dimensions
MOUNTING
CENTER
4.0
1.025
C
L
2.05
RECEIVER
EMITTER
2.2
2.5
1.175
0.35
0.65
0.80
1.05
1.25
2.85
2.55
4.0
8.0
3.0
2.9
1.85
C
L
UNIT: mm
TOLERANCE: ± 0.2 mm
PIN 1
0.6
3.325
6.65
7
Moisture Proof Packaging
Solder Pad, Mask and Metal Stencil
The HDSL-3202 is shipped in
moisture proof packaging. Once
opened, moisture absorption
begins.
METAL STENCIL
FOR SOLDER PASTE
PRINTING
STENCIL
APERTURE
Recommended Storage Conditions
Storage
10°C to 30°C
Temperature
Relative
Humidity
below 60% RH
LAND
PATTERN
Time from Unsealing to Soldering
SOLDER
MASK
After removal from the bag, the
parts should be soldered within
two days if stored at the recom-
mended storage conditions. If
times longer than two days are
needed, the parts must be stored
in a dry box.
PCB
Baking
If the parts are not stored in dry
conditions, they must be baked
before reflow to prevent damage
to the parts.
Recommended Land Pattern
C
L
SHIELD
SOLDER PAD
1.35
MOUNTING
CENTER
Package
In reels
In bulk
Temp.
Time
60°C
≥48 hours
1.25
2.05
100°C
125°C
150°C
≥4 hours
≥2 hours
≥1 hour
0.10
0.775
Baking should only be done once.
1.75
FIDUCIAL
0.60
0.475
1.425
UNIT: mm
2.375
3.325
8
Recommended Metal Solder
Stencil Aperture
It is recommended that only a
0.152 mm (0.006 inch) or a
0.127 mm (0.005 inch) thick
stencil be used for solder paste
printing. This is to ensure
APERTURES AS PER
LAND DIMENSIONS
t
adequate printed solder paste
volume and no shorting. See the
table below the drawing for
combinations of metal stencil
aperture and metal stencil thick-
ness that should be used.
w
l
Aperture opening for shield pad
is 2.7 mm x 1.25 mm as per land
pattern.
Stencil Thickness, t (mm)
Aperture Size (mm)
Adjacent Land Keepout and Solder
Mask Areas
Adjacent land keepout is the
maximum space occupied by the
unit relative to the land pattern.
There should be no other SMD
components within this area.
Length, l
Width, w
0.152 mm
0.127 mm
2.60 ± 0.05
3.00 ± 0.05
0.55 ± 0.05
0.55 ± 0.05
0.2 mm is the minimum solder
resist strip width required to
avoid solder bridging adjacent
pads.
8.2
0.2
2.6
3.0
It is recommended that two
fiducial crosses be placed at mid-
length of the pads for unit
alignment.
SOLDER MASK
Note: Wet/Liquid Photo-
Imageable solder resist/mask is
recommended.
UNITS: mm
9
PCB Layout Suggestion
Component Side
The following PCB layout shows a
recommended layout that should
result in good electrical and EMI
performance. Things to note:
1. The ground plane should be
continuous under the part, but
should not extend under the
shield trace.
C3
2. The shield trace is a wide, low-
inductance trace back to the
system ground.
C1
C2
3. The AGND pin is connected to
the ground plane and not to
the shield tab.
4. C1, C2, and C3 are optional
supply filter capacitors; it may
be left out if the supply is
clean.
5. V
can be connected to
LED
either unfiltered or unregu-
lated power. If C1 is used, and
if V
is also connected to
LED
V
, the connection should be
CC
Circuit Side
before the C1 cap.
10
Pick and Place Misalignment
Tolerance and Self-Alignment after
Solder Reflow
Tolerance for Rotational (θ)
Misalignment
Recommended Solder Paste/Cream
Volume for Castellation Joints
Mounted units should not be
rotated more than ± 3 degrees
with reference to center X-Y as
shown in the direction definition.
Units that are rotated more than
± 3 degrees will not self-align
after solder reflow. Units with
less than a ± 3 degree misalign-
ment will self-align after solder
reflow.
Based on calculation and experi-
ment, the printed solder paste
volume required per castellation
pad is 0.22 cubic mm (based on
either no-clean or aqueous solder
cream types with typically 60% to
65% solid content by volume).
Using the recommended stencil
will result in this volume of solder
paste.
If the printed solder paste volume
is adequate, the HSDL-3202 will
self-align after solder reflow.
Units should be properly reflowed
in IR/hot air convection oven
using the recommended reflow
profile. The direction of board
travel does not matter.
Direction Definition
Y-axis Misalignment of Castellation
In the Y direction, the HSDL-
3202 does not self-align after
solder reflow. Agilent recom-
mends that the part be placed in
line with the fiducial mark (mid-
length of land pad). This will
enable sufficient land length
(minimum of 1/2 land length) to
form a good joint. See the
drawing below.
Y
X
θ
Allowable Misalignment
Direction
Tolerance
≤ 0.2 mm
X
Y
θ
See text
EDGE
≤ ± 3 degrees
Tolerance for X-axis Alignment of
Castellation
Misalignment of castellation to
the land pad should not exceed
0.2 mm or about one-half the
width of the castellation during
placement of the unit. The
MINIMUM 1/2 THE LENGTH
OF THE LAND PAD
castellations will self-align to the
pads during solder reflow.
FIDUCIAL
11
Reflow Profile
MAX. 245°C
R3 R4
230
200
183
170
R2
150
90 sec.
MAX.
ABOVE
183°C
125
R1
R5
100
50
25
0
50
100
150
200
250
300
t-TIME (SECONDS)
P1
HEAT
UP
P2
SOLDER PASTE DRY
P3
SOLDER
REFLOW
P4
COOL
DOWN
Process Zone
Symbol ∆T
P1, R1 25°C to 125°C
125°C to 170°C
Maximum ∆T/∆time
4°C/s
Heat Up
Solder Paste Dry P2, R2
0.5°C/s
Solder Reflow
P3, R3
P3, R4
P4, R5
170°C to 230°C (245°C max.) 4°C/s
230°C to 170°C
170°C to 25°C
–4°C/s
–3°C/s
Cool Down
The reflow profile is a straight
line representation of a nominal
temperature profile for a convec-
tive reflow solder process. The
temperature profile is divided
into four process zones, each
with different ∆T/∆time tempera-
ture change rates. The ∆T/∆time
rates are detailed in the above
table. The temperatures are
measured at the component to
printed-circuit board
Process zone P2 should be of
sufficient time duration (> 60
seconds) to dry the solder paste.
The temperature is raised to a
level just below the liquidus point
of the solder, usually 170°C
(338°F).
ing in the formation of weak and
unreliable connections. The tem-
perature is then rapidly reduced
to a point below the solidus
temperature of the solder, usually
170°C (338°F), to allow the
solder within the connections to
freeze solid.
Process zone P3 is the solder
reflow zone. In zone P3, the tem-
perature is quickly raised above
the liquidus point of solder to
230°C (446°F) for optimum re-
sults. The dwell time above the
liquidus point of solder should be
between 15 and 90 seconds. It
usually takes about 15 seconds to
assure proper coalescing of the
solder balls into liquid solder and
the formation of good solder
Process zone P4 is the cool
down after solder freeze. The
cool down rate, R5, from the
liquidus point of the solder to
25°C (77°F) should not exceed
–3°C per second maximum. This
limitation is necessary to allow
the PC board and HSDL-3202
castellation I/O pins to change
dimensions evenly, putting mini-
mal stresses on the HSDL-3202
transceiver.
connections.
In process zone P1, the PC
board and HSDL-3202
castellation I/O pins are heated to
a temperature of 125°C to acti-
vate the flux in the solder paste.
The temperature ramp-up rate,
R1, is limited to 4°C per second
to allow for even heating of both
the PC board and HSDL-3202
castellation I/O pins.
connections. Beyond a dwell time
of 90 seconds, the intermetallic
growth within the solder connec-
tions becomes excessive, result-
12
Window Design
Minimum and Maximum Window Sizes
Dimensions are in mm.
To ensure IrDA compliance, some
constraints on the height and
width of the window exist. The
minimum dimensions ensure that
the IrDA cone angles are met
without vignetting. The
maximum dimensions minimize
the effects of stray light. The
minimum size corresponds to a
cone angle of 30 degrees, the
maximum to a cone angle of
60 degrees.
Depth (Z)
Y min.
1.70
2.23
2.77
3.31
3.84
4.38
4.91
5.45
5.99
6.52
7.06
X min.
6.80
Y max.
3.66
X max.
8.76
0
1
2
3
4
5
6
7
8
9
10
7.33
4.82
9.92
7.87
5.97
11.07
12.22
13.38
14.53
15.69
16.84
18.00
19.15
20.31
8.41
7.12
8.94
8.28
9.48
9.43
10.01
10.55
11.09
11.62
12.16
10.59
11.74
12.90
14.05
15.21
The drawing below shows the
module positioned in front of a
window.
Window Height Y vs. Module Depth Z
16
14
12
10
Z
Y
8
6
4
ACCEPTABLE
RANGE
X
2
0
X is the width of the window, Y is
the height of the window, and Z is
the distance from the HSDL-3202
to the back of the window. The
distance from the center of the
LED lens to the center of the
photodiode lens is 5.1 mm. The
equations for the size of the
window are as follows:
0
2
4
6
8
10
MODULE DEPTH Z – mm
Window Width X vs. Module Depth Z
22
20
18
16
X = 5.1 +2(Z + D) tan θ
Y = 2(Z + D) tan θ
Where θ is the required half angle
for viewing. For the IrDA mini-
mum, it is 15 degrees; for the
IrDA maximum, it is 30 degrees.
(D is the depth of the LED image
inside the part, 3.17 mm). These
equations result in the following
tables and graphs:
14
ACCEPTABLE
RANGE
12
10
8
6
0
2
4
6
8
10
MODULE DEPTH Z – mm
13
Curved Front and Back
Flat Window
Shape of the Window
(This option can be used if neces-
sary for application purpose. A
large radius of curvature is
recommended and both front and
back should have the same
radius.)
From an optics standpoint, the
window should be flat. This en-
sures that the window will not
alter either the radiation pattern
of the LED, or the receive pattern
of the photodiode.
If the window must be curved for
mechanical design reasons, place
a curve on the back side of the
window that has the same radius
as the front side. While this will
not completely eliminate the lens
effect of the front curved surface,
it will reduce the effects. The
amount of change in the radiation
pattern is dependent upon the
material chosen for the window,
the radius of the front and back
curves, and the distance from the
back surface to the transceiver.
Once these items are known, a
lens design can be made which
will eliminate the effect of the
front surface curve.
Curved Front, Flat Back
(This option is not recommended
and should not be used.)
The following drawings show the
effects of a curved window on the
radiation pattern. In all cases,
the center thickness of the win-
dow is 1.5 mm, the window is
made of polycarbonate plastic,
and the distance from the trans-
ceiver to the back surface of the
window is 3 mm.
14
Test Methods
Background Light and
Electromagnetic Field
There are four ambient interfer-
ence conditions in which the
receiver is to operate correctly.
The conditions are to be applied
separately:
generate 1000 lux over the
horizontal surface on which
the equipment under test rests.
The light sources are above the
test area. The source is
expected to have a filament
temperature in the 2700 to
3050 Kelvin range and a
spectral peak in the 850 to
1050 nm range.
1. Electromagnetic Field:
3 V/m maximum (please refer
to IEC 801-3, severity level 3
for details).
4. Fluorescent Lighting:
1000 lux maximum. This is
simulated with an IR source
having a peak wavelength
within the range of 850 nm to
900 nm and a spectral width of
less than 50 nm biased and
modulated to provide an
2. Sunlight:
10 kilolux maximum at the
optical port. This is simulated
with an IR source having a
peak wavelength within the
range of 850 nm to 900 nm
and a spectral width of less
than 50 nm biased to provide
optical square wave signal
2
(0 µW/cm minimum and 0.3
2
µW/cm peak amplitude with
10% to 90% rise and fall times
less than or equal to 100 ns)
over the horizontal surface on
which the equipment under
test rests. The light sources are
above the test area. The fre-
quency of the optical signal is
swept over the frequency
2
490 µW/cm (with no modula-
tion) at the optical port. The
light source faces the optical
port.
This simulates sunlight within
the IrDA spectral range. The
effect of longer wavelength
radiation is covered by the
incandescent condition.
range from 20 kHz to 200 kHz.
Due to the variety of fluores-
cent lamps and the range of IR
emissions, this condition is not
expected to cover all circum-
stances. It will provide a com-
mon floor for IrDA operation.
3. Incandescent Lighting: 1000
lux maximum. This is pro-
duced with general service,
tungsten-filament, gas-filled,
inside frosted lamps in the
60 Watt to 100 Watt range to
15
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2001 Agilent Technologies, Inc.
March 21, 2001
Obsoletes 5980-1500E (5/00)
5988-2313EN
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