HCPL3150 [AGILENT]
0.5 Amp Output Current IGBT Gate Drive Optocoupler; 0.5安培输出电流IGBT栅极驱动光电耦合器
| 型号： | HCPL3150 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | 0.5 Amp Output Current IGBT Gate Drive Optocoupler |
| 文件： | 总15页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
H
0.5 Amp Output Current IGBT
Gate Drive Optocoupler
Technical Data
HCPL-3150
Features
• 0.5 A Minimum Peak Output
Current
• 15 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 1500 V
• 1.0 V Maximum Low Level
Output Voltage (VOL)
Eliminates Need for
Negative Gate Drive
• ICC = 5 mA Maximum Supply
Current
• Under Voltage Lock-Out
Protection (UVLO) with
Hysteresis
Applications
• Isolated IGBT/MOSFET
Gate Drive
• AC and Brushless DC Motor
Drives
• Industrial Inverters
ideally suited for driving power
IGBTs and MOSFETs used in
motor control inverter applica-
tions. The high operating voltage
range of the output stage pro-
vides the drive voltages required
by gate controlled devices. The
voltage and current supplied by
this optocoupler makes it ideally
suited for directly driving IGBTs
with ratings up to 1200 V/50 A.
For IGBTs with higher ratings,
the HCPL-3120 can be used to
drive a discrete power stage
which drives the IGBT gate.
• Switch Mode Power
Supplies (SMPS)
Description
The HCPL-3150 consists of a
GaAsP LED optically coupled to
an integrated circuit with a power
output stage. This optocoupler is
• Wide Operating VCC Range:
15 to 30 Volts
• 500 ns Maximum Switching
Speeds
• Industrial Temperature
Range:
-40°C to 100°C
• Safety and Regulatory
Approval:
Functional Diagram
N/C
ANODE
CATHODE
N/C
1
8
V
V
V
V
CC
2
3
4
7
6
5
O
O
EE
SHIELD
UL Recognized
2500 Vrms for 1 min. per
UL1577
Truth Table
VCC - VEE
VCC - VEE
“Positive Going”
(i.e., Turn-On)
“Negative-Going”
(i.e., Turn-Off)
VDE 0884 Approved with
LED
VO
VIORM = 630 Vpeak
OFF
ON
ON
ON
0 - 30 V
0 - 11 V
0 - 30 V
0 - 9.5 V
9.5 - 12 V
12 - 30 V
LOW
LOW
TRANSITION
HIGH
(Option 060 only)
CSA Approved
11 - 13.5 V
13.5 - 30 V
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
5965-4780E
1-197
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example
HCPL-3150#XXX
No Option = Standard DIP package, 50 per tube.
060 = VDE 0884 V = 630 Vpeak Option, 50 per tube.
IORM
300 = Gull Wing Surface Mount Option, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 per reel.
Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.
Package Outline Drawings
Standard DIP Package
9.40 (0.370)
9.90 (0.390)
8
1
7
6
5
OPTION CODE*
DATE CODE
0.20 (0.008)
0.33 (0.013)
6.10 (0.240)
6.60 (0.260)
HP 3150 Z
YYWW
7.36 (0.290)
7.88 (0.310)
5° TYP.
2
3
4
PIN ONE
1.78 (0.070) MAX.
1.19 (0.047) MAX.
4.70 (0.185) MAX.
PIN ONE
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
0.76 (0.030)
1.40 (0.055)
0.65 (0.025) MAX.
* MARKING CODELETTER FOR OPTION NUMBERS.
"V" = OPTION 060.
2.28 (0.090)
2.80 (0.110)
OPTION NUMBERS 300 AND 500 NOT MARKED.
Gull-Wing Surface-Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
1.016 (0.040)
1.194 (0.047)
7
6
5
8
4.826
TYP.
(0.190)
HP 3150 Z
YYWW
6.350 ± 0.25
(0.250 ± 0.010)
9.398 (0.370)
9.906 (0.390)
1
3
2
4
MOLDED
0.381 (0.015)
0.635 (0.025)
1.194 (0.047)
1.778 (0.070)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
7.62 ± 0.25
(0.047)
MAX.
(0.300 ± 0.010)
0.20 (0.008)
0.33 (0.013)
4.19
MAX.
(0.165)
0.635 ± 0.25
(0.025 ± 0.010)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
(0.025 ± 0.005)
12° NOM.
2.540
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
1-198
Reflow Temperature Profile
Regulatory Information
The HCPL-3150 has been
approved by the following
organizations:
260
240
220
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
200
180
160
140
120
100
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
MAXIMUM SOLDER REFLOW THERMAL PROFILE
VDE (Option 060 only)
(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
Approved under VDE 0884/06.92
with VIORM = 630 Vpeak.
VDE 0884 Insulation Characteristics (Option 060 Only)
Description
Symbol
Characteristic
Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
I-IV
I-III
Climatic Classification
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
2
630
V
Vpeak
Vpeak
IORM
V
IORM
x 1.875 = V , 100% Production Test with t = 1 sec,
V
PR
1181
PR
m
Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
V
x 1.5 = V , Type and Sample Test, t = 60 sec,
V
PR
945
Vpeak
Vpeak
IORM
PR
m
Partial discharge < 5 pC
Highest Allowable Overvoltage*
V
IOTM
6000
(Transient Overvoltage t = 10 sec)
ini
Safety-Limiting Values – Maximum Values Allowed in the Event
of a Failure, Also See Figure 37, Thermal Derating Curve.
Case Temperature
Input Current
Output Power
T
175
230
600
°C
mA
mW
S
I
P
S, INPUT
S, OUTPUT
9
Insulation Resistance at T , V = 500 V
R
S
≥ 10
Ω
S
IO
*Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section, (VDE 0884) for a
detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-199
Insulation and Safety Related Specifications
Parameter
Symbol Value Units
Conditions
Minimum External Air Gap
(External Clearance)
Minimum External Tracking
(External Creepage)
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
L(101)
7.1
mm
mm
mm
Measured from input terminals to output
terminals, shortest distance through air.
Measured from input terminals to output
terminals, shortest distance path along body.
Through insulation distance conductor to
conductor.
L(102)
7.4
0.08
200
IIIa
CTI
Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance wtih CECC 00802.
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Average Input Current
Symbol
TS
TA
IF(AVG)
IF(TRAN)
Min.
-55
-40
Max.
125
100
25
Units
°C
°C
mA
A
Note
1
Peak Transient Input Current
1.0
(<1 µs pulse width, 300 pps)
Reverse Input Voltage
VR
IOH(PEAK)
IOL(PEAK)
(VCC - VEE)
VO(PEAK)
PO
5
Volts
A
A
Volts
Volts
mW
mW
“High” Peak Output Current
“Low” Peak Output Current
Supply Voltage
0.6
0.6
35
VCC
250
295
2
2
0
0
Output Voltage
Output Power Dissipation
Total Power Dissipation
Lead Solder Temperature
Solder Reflow Temperature Profile
3
4
PT
260°C for 10 sec., 1.6 mm below seating plane
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter
Symbol
(VCC - VEE)
IF(ON)
VF(OFF)
TA
Min.
15
7
-3.0
-40
Max.
30
16
0.8
100
Units
Volts
mA
V
Power Supply Voltage
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
°C
1-200
Electrical Specifications (DC)
Over recommended operating conditions (T = -40 to 100°C, I
= 7 to 16 mA, V = -3.0 to 0.8 V,
F(OFF)
A
F(ON)
V
CC
= 15 to 30 V, V = Ground) unless otherwise specified.
EE
Parameter
High Level
Output Current
Symbol
Min.
0.1
0.5
Typ.* Max. Units Test Conditions
Fig. Note
I
0.4
A
V = (V - 4 V)
2, 3,
17
5
2
OH
O
CC
V = (V - 15 V)
O CC
Low Level
I
0.1
0.6
A
V = (V + 2.5 V) 5, 6
5
OL
O
EE
Output Current
18
0.5
V = (V + 15 V)
2
O
EE
High Level Output
Voltage
Low Level Output
Voltage
High Level
Supply Current
Low Level
Supply Current
Threshold Input
Current Low to High
V
(V - 4) (V - 3)
V
V
I = -100 mA
1, 3
19
4, 6
20
6, 7
OH
CC
CC
O
V
OL
0.4
1.0
5.0
5.0
5.0
I = 100 mA
O
I
2.5
2.7
2.2
mA
mA
mA
V
Output Open,
7, 8
CCH
I = 7 to 16 mA
F
I
Output Open,
CCL
V = -3.0 to +0.8 V
F
I
I = 0 mA,
9, 15,
21
FLH
O
V > 5 V
O
Threshold Input
V
FHL
0.8
Voltage High to Low
Input Forward Voltage
V
F
1.2
1.5
1.8
V
I = 10 mA
F
16
Temperature
∆V /∆T
-1.6
mV/°C I = 10 mA
F
F
A
Coefficient of
Forward Voltage
Input Reverse
BV
5
V
I = 10 µA
R
R
Breakdown Voltage
Input Capacitance
UVLO Threshold
C
60
pF
V
f = 1 MHz, V = 0 V
F
IN
V
V
11.0
9.5
12.3
10.7
1.6
13.5
12.0
V > 5 V,
22,
36
UVLO+
O
IF = 10 mA
UVLO-
UVLO Hysteresis
UVLO
V
HYS
*All typical values at T = 25°C and V - V = 30 V, unless otherwise noted.
A
CC
EE
1-201
Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter
Symbol
Min.
Typ.* Max. Units
Test Conditions
Fig.
Note
Propagation Delay
Time to High
Output Level
tPLH
0.10
0.30
0.50
µs
Rg = 47 Ω,
Cg = 3 nF,
f = 10 kHz,
10, 11,
12, 13
14, 23
14
Duty Cycle = 50%
Propagation Delay
Time to Low
tPHL
0.10
0.27
0.50
µs
Output Level
Pulse Width
Distortion
Propagation Delay
PWD
PDD
0.3
µs
µs
15
10
-0.35
0.35
34,35
Difference Between (tPHL - tPLH
Any Two Parts
)
Rise Time
Fall Time
UVLO Turn On
Delay
tr
tf
0.1
0.1
0.8
µs
µs
µs
23
22
tUVLO ON
VO > 5 V,
IF = 10 mA
UVLO Turn Off
Delay
Output High Level
Common Mode
Transient
tUVLO OFF
|CMH|
0.6
30
µs
VO < 5 V,
IF = 10 mA
15
15
kV/µs TA = 25°C,
IF = 10 to 16 mA,
24
11, 12
11, 13
VCM = 1500 V,
VCC = 30 V
Immunity
Output Low Level
Common Mode
Transient
|CML|
30
kV/µs TA = 25°C,
VCM = 1500 V,
VF = 0 V,
Immunity
VCC = 30 V
Package Characteristics
Parameter
Symbol
Min.
Typ.* Max. Units
Test Conditions
Fig.
Note
Input-Output
V
ISO
2500
Vrms RH < 50%,
8, 9
Momentary
t = 1 min.,
Withstand Voltage**
Resistance
(Input - Output)
Capacitance
(Input - Output)
LED-to-Case
Thermal Resistance
LED-to-Detector
TA = 25°C
RI-O
CI-O
θLC
θLD
θDC
1012
0.6
Ω
VI-O = 500 VDC
9
pF
f = 1 MHz
391
439
119
°C/W Thermocouple
28
located at center
underside of
package
°C/W
°C/W
Thermal Resistance
Detector-to-Case
Thermal Resistance
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note
1074 entitled “Optocoupler Input-Output Endurance Voltage.”
1-202
Notes:
loads VOH will approach VCC as IOH
approaches zero amps.
7. Maximum pulse width = 1 ms,
maximum duty cycle = 20%.
under the same test condition.
11. Pins 1 and 4 need to be connected to
LED common.
12. Common mode transient immunity in
the high state is the maximum
tolerable |dVCM/dt| of the common
mode pulse, VCM, to assure that the
output will remain in the high state
(i.e., VO > 15.0 V).
13. Common mode transient immunity in
a low state is the maximum tolerable
|dVCM/dt| of the common mode
pulse, VCM, to assure that the output
will remain in a low state (i.e.,
VO < 1.0 V).
14. This load condition approximates the
gate load of a 1200 V/25 A IGBT.
15. Pulse Width Distortion (PWD) is
defined as |tPHL-tPLH| for any given
device.
1. Derate linearly above 70°C free-air
temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs,
maximum duty cycle = 0.2%. This
value is intended to allow for
component tolerances for designs
with IO peak minimum = 0.5 A. See
Applications section for additional
details on limiting IOH peak.
3. Derate linearly above 70°C free-air
temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70°C free-air
temperature at a rate of 5.4 mW/°C.
The maximum LED junction tempera-
ture should not exceed 125°C.
5. Maximum pulse width = 50 µs,
maximum duty cycle = 0.5%.
8. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 3000 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
This test is performed before the
100% production test for partial
discharge (method b) shown in the
VDE 0884 Insulation Characteristics
Table, if applicable.
9. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
10. The difference between tPHL and tPLH
between any two HCPL-3150 parts
6. In this test VOH is measured with a dc
load current. When driving capacitive
0
-1
0.50
I
I
V
V
= 7 to 16 mA
= -100 mA
I
= 7 to 16 mA
F
OUT
F
V
V
V
= V - 4 V
OUT
CC
100 °C
25 °C
-40 °C
= 15 to 30 V
= 0 V
= 15 to 30 V
= 0 V
CC
EE
CC
EE
-2
-3
-4
0.45
0.40
0.35
-1
-2
I
V
V
= 7 to 16 mA
= 15 to 30 V
-3
-4
F
CC
-5
-6
0.30
0.25
= 0 V
EE
-40 -20
0
20 40 60 80 100
0
0.2
0.4
0.6
0.8
1.0
-40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
I
– OUTPUT HIGH CURRENT – A
OH
T
– TEMPERATURE – °C
A
A
Figure 1. VOH vs. Temperature.
Figure 2. IOH vs. Temperature.
Figure 3. VOH vs. IOH
.
1.0
1.0
5
V
= -3.0 to 0.8 V
F(OFF)
= 100 mA
V
V
V
= -3.0 to 0.8 V
= 15 to 30 V
= 0 V
F(OFF)
CC
EE
I
OUT
V
V
= 15 to 30 V
= 0 V
CC
EE
0.8
0.6
0.4
0.8
0.6
0.4
4
3
2
V
V
V
V
= -3.0 to 0.8 V
F(OFF)
= 2.5 V
OUT
0.2
0
0.2
0
1
0
100 °C
25 °C
-40 °C
= 15 to 30 V
= 0 V
CC
EE
-40 -20
0
20 40 60 80 100
-40 -20
0
20 40 60 80 100
T – TEMPERATURE – °C
A
0
0.2
0.4
0.6
0.8
1.0
T
– TEMPERATURE – °C
I
– OUTPUT LOW CURRENT – A
A
OL
Figure 4. VOL vs. Temperature.
Figure 5. IOL vs. Temperature.
Figure 6. VOL vs. IOL.
1-203
3.5
3.0
2.5
3.5
3.0
2.5
5
4
3
2
V
V
= 15 TO 30 V
= 0 V
CC
EE
I
I
I
I
CCH
CCL
CCH
CCL
OUTPUT = OPEN
V
V
= 30 V
= 0 V
= 10 mA for I
CC
EE
I
I
T
= 10 mA for I
CCH
F
F
2.0
1.5
2.0
1.5
= 0 mA for I
CCL
1
0
I
I
F
F
CCH
= 25 °C
A
EE
= 0 mA for I
CCL
V
= 0 V
-40 -20
0
20 40 60 80 100
15
20
25
30
-40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
V
– SUPPLY VOLTAGE – V
A
CC
Figure 7. ICC vs. Temperature.
Figure 8. ICC vs. VCC
.
Figure 9. IFLH vs. Temperature.
500
500
500
I
T
= 10 mA
= 25 °C
I
I
V
= 10 mA
= 0 mA
V
= 30 V, V
= 0 V
EE
F
A
F(ON)
F(OFF)
CC
CC
Rg = 47 Ω, Cg = 3 nF
= 25 °C
T
T
PLH
PHL
Rg = 47 Ω
Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
= 30 V, V = 0 V
T
EE
A
400
300
400
300
400
300
Rg = 47 Ω, Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
DUTY CYCLE = 50%
f = 10 kHz
200
100
200
100
200
100
T
T
T
T
PLH
PHL
PLH
PHL
15
20
25
30
6
8
10
12
14
16
-40 -20
0
20 40 60 80 100
T – TEMPERATURE – °C
A
V
– SUPPLY VOLTAGE – V
I
– FORWARD LED CURRENT – mA
CC
F
Figure 10. Propagation Delay vs. VCC
.
Figure 11. Propagation Delay vs. IF.
Figure 12. Propagation Delay vs.
Temperature.
500
500
30
V
T
= 30 V, V
= 25 °C
= 10 mA
= 0 V
V
T
= 30 V, V
= 25 °C
= 10 mA
= 0 V
CC
A
EE
CC
A
EE
25
20
15
10
I
I
F
F
400
300
400
300
Cg = 3 nF
Rg = 47 Ω
DUTY CYCLE = 50%
f = 10 kHz
DUTY CYCLE = 50%
f = 10 kHz
200
100
200
100
5
0
T
T
T
T
PLH
PHL
PLH
PHL
0
50
100
150
200
0
20
40
60
80
100
0
I
1
2
3
4
5
Rg – SERIES LOAD RESISTANCE – Ω
Cg – LOAD CAPACITANCE – nF
– FORWARD LED CURRENT – mA
F
Figure 13. Propagation Delay vs. Rg.
Figure 14. Propagation Delay vs. Cg.
Figure 15. Transfer Characteristics.
1-204
1000
T
= 25°C
A
100
10
I
F
1
2
3
4
8
+
V
F
0.1 µF
–
+
–
4 V
1.0
0.1
7
6
5
I
= 7 to
16 mA
F
V
= 15
+
–
CC
to 30 V
I
OH
0.01
0.001
1.10 1.20
1.30
1.40
1.50
1.60
V
– FORWARD VOLTAGE – V
F
Figure 17. IOH Test Circuit.
Figure 16. Input Current vs. Forward
Voltage.
1
2
3
4
8
1
8
0.1 µF
0.1 µF
I
OL
V
OH
7
6
5
2
7
6
5
V
= 15
+
–
CC
to 30 V
I
= 7 to
16 mA
F
V
= 15
+
–
CC
to 30 V
2.5 V
+
3
4
–
100 mA
Figure 18. IOL Test Circuit.
Figure 19. VOH Test Circuit.
1
2
3
4
8
1
2
8
0.1 µF
0.1 µF
100 mA
7
6
5
7
6
5
V
= 15
V
= 15
+
–
+
–
CC
to 30 V
CC
I
F
V
> 5 V
to 30 V
O
3
4
V
OL
Figure 20. VOL Test Circuit.
Figure 21. IFLH Test Circuit.
1
2
8
0.1 µF
7
+
I
= 10 mA
V
F
CC
–
V
> 5 V
O
3
4
6
5
Figure 22. UVLO Test Circuit.
1-205
1
2
3
4
8
7
6
5
I
0.1 µF
F
I
= 7 to 16 mA
F
V
= 15
CC
to 30 V
+
–
t
t
f
r
500 Ω
+
V
O
–
90%
10 KHz
50% DUTY
CYCLE
47 Ω
50%
10%
V
3 nF
OUT
t
t
PHL
PLH
Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.
V
CM
δV
V
CM
1
2
3
4
8
7
6
5
=
δt
∆t
I
F
0.1 µF
A
B
0 V
∆t
+
–
+
–
V
O
5 V
V
= 30 V
CC
V
V
OH
V
O
SWITCH AT A: I = 10 mA
F
V
O
OL
SWITCH AT B: I = 0 mA
F
+
V
= 1500 V
CM
Figure 24. CMR Test Circuit and Waveforms.
routing the IGBT collector or
Applications Information
Eliminating Negative IGBT
Gate Drive
To keep the IGBT firmly off, the
HCPL-3150 has a very low
maximum VOL specification of
1.0 V. The HCPL-3150 realizes
this very low VOL by using a
DMOS transistor with 4 Ω
the IGBT gate is shorted to the
emitter by Rg + 4 Ω. Minimizing
Rg and the lead inductance from
the HCPL-3150 to the IGBT gate
and emitter (possibly by
mounting the HCPL-3150 on a
small PC board directly above the
IGBT) can eliminate the need for
negative IGBT gate drive in many
applications as shown in Figure
25. Care should be taken with
such a PC board design to avoid
emitter traces close to the HCPL-
3150 input as this can result in
unwanted coupling of transient
signals into the HCPL-3150 and
degrade performance. (If the
IGBT drain must be routed near
the HCPL-3150 input, then the
LED should be reverse-biased
when in the off state, to prevent
the transient signals coupled
from the IGBT drain from turning
on the HCPL-3150.)
(typical) on resistance in its pull
down circuit. When the
HCPL-3150 is in the low state,
HCPL-3150
+5 V
1
2
3
4
8
V
= 18 V
CC
+ HVDC
270 Ω
0.1 µF
+
–
7
Rg
Q1
3-PHASE
AC
CONTROL
INPUT
6
5
74XXX
OPEN
COLLECTOR
Q2
- HVDC
Figure 25. Recommended LED Drive and Application Circuit.
1-206
Selecting the Gate Resistor
(Rg) to Minimize IGBT
Switching Losses.
Step 1: Calculate Rg Minimum
From the IOL Peak Specifica-
tion. The IGBT and Rg in Figure
26 can be analyzed as a simple
RC circuit with a voltage supplied
by the HCPL-3150.
The VOL value of 2 V in the pre-
vious equation is a conservative
value of VOL at the peak current
of 0.6 A (see Figure 6). At lower
Rg values the voltage supplied by
the HCPL-3150 is not an ideal
voltage step. This results in lower
peak currents (more margin)
than predicted by this analysis.
When negative gate drive is not
used VEE in the previous equation
is equal to zero volts.
PT = PE + PO
•
•
PE = IF V Duty Cycle
F
PO = PO(BIAS) + PO (SWITCHING)
•
= ICC (VCC - VEE)
•
+ ESW(RG, QG) f
For the circuit in Figure 26 with IF
(worst case) = 16 mA, Rg =
30.5 Ω, Max Duty Cycle = 80%,
Qg = 500 nC, f = 20 kHz and TA
max = 90°C:
(V – VEE - V )
Rg≥ ––C–C–––––––––O–L––
IOLPEAK
•
•
PE = 16 mA 1.8 V 0.8 = 23 mW
(V – VEE - 1.7 V)
= ––C–C–––––––––––––
IOLPEAK
Step 2: Check the HCPL-3150
Power Dissipation and
•
PO = 4.25 mA 20 V
•
+ 4.0 µJ 20 kHz
= 85 mW + 80 mW
= 165 mW
Increase Rg if Necessary. The
HCPL-3150 total power dissipa-
tion (PT) is equal to the sum of
the emitter power (PE) and the
output power (PO):
(15 V + 5 V - 1.7 V)
= ––––––––––––––––––
0.6 A
> 154 mW (PO(MAX) @ 90°C
= 250 mW−20C 4.8 mW/C)
= 30.5 Ω
•
HCPL-3150
+5 V
1
2
3
4
8
V
= 15 V
CC
+ HVDC
270 Ω
0.1 µF
+
–
7
Rg
Q1
= -5 V
3-PHASE
AC
CONTROL
INPUT
6
5
V
EE
–
+
74XXX
OPEN
COLLECTOR
Q2
- HVDC
Figure 26. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive.
PE
PO Parameter
Description
Supply Current
Positive Supply Voltage
Negative Supply Voltage
Parameter
Description
LED Current
LED On Voltage
ICC
VCC
VEE
IF
VF
Duty Cycle
Maximum LED
Duty Cycle
ESW(Rg,Qg)
Energy Dissipated in the HCPL-3150 for each
IGBT Switching Cycle (See Figure 27)
f
Switching Frequency
1-207
The value of 4.25 mA for ICC in
the previous equation was
obtained by derating the ICC max
of 5 mA (which occurs at -40°C)
to ICC max at 90°C (see Figure 7).
shown in Figure 29. The HCPL-
3150 improves CMR performance
by using a detector IC with an
optically transparent Faraday
shield, which diverts the capaci-
tively coupled current away from
From the thermal mode in Figure
28 the LED and detector IC
junction temperatures can be
expressed as:
•
TJE = P (θLC||(θLD + θDC) + θCA)
E
Since PO for this case is greater
than PO(MAX), Rg must be
increased to reduce the HCPL-
3150 power dissipation.
the sensitive IC circuitry. How
•
θLC θDC
•
+ PD
(
–––––––––––––––– + θCA
)
+ TA ever, this shield does not
θLC + θDC + θLD
eliminate the capacitive coupling
between the LED and optocoup-
ler pins 5-8 as shown in
•
θ
θDC
TJD = PE
(
–––––L–C––––––––– + θCA
)
θLC + θDC + θLD
PO(SWITCHING MAX)
= PO(MAX) - PO(BIAS)
= 154 mW - 85 mW
= 69 mW
Figure 30. This capacitive
•
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 25), can achieve
15 kV/µs CMR while minimizing
component complexity.
+ P (θDC||(θLD + θLC) + θCA) + T
D
A
Inserting the values for θLC and
θDC shown in Figure 28 gives:
PO(SWITCHINGMAX)
ESW(MAX) = –––––––––––––––
f
•
69 mW
TJE = PE (230°C/W + θCA)
= ––––––– = 3.45 µJ
•
+ P (49°C/W + θCA) + TA
D
20 kHz
•
TJD = P (49°C/W + θCA)
E
•
+ P (104°C/W + θCA) + TA
D
For Qg = 500 nC, from Figure
27, a value of ESW = 3.45 µJ
gives a Rg = 41 Ω.
For example, given PE = 45 mW,
PO = 250 mW, TA = 70°C and θCA
= 83°C/W:
Thermal Model
The steady state thermal model
for the HCPL-3150 is shown in
Figure 28. The thermal resistance
values given in this model can be
used to calculate the tempera-
tures at each node for a given
operating condition. As shown by
the model, all heat generated
flows through θCA which raises
the case temperature TC
accordingly. The value of θCA
depends on the conditions of the
board design and is, therefore,
determined by the designer. The
value of θCA = 83°C/W was
obtained from thermal measure-
ments using a 2.5 x 2.5 inch PC
board, with small traces (no
ground plane), a single HCPL-
3150 soldered into the center of
the board and still air. The
absolute maximum power
dissipation derating specifications
assume a θCAvalue of 83°C/W.
•
•
TJE = PE 313°C/W + PD 132°C/W + T
A
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
= 45 mW• 313°C/W + 250 mW
• 132°C/W + 70°C = 117°C
•
•
TJD = PE 132°C/W + PD 187°C/W + T
A
= 45 mW• 132C/W + 250 mW
• 187°C/W + 70°C = 123°C
7
Qg = 100 nC
6
5
Qg = 250 nC
Qg = 500 nC
TJE and TJD should be limited to
125°C based on the board layout
and part placement (θCA) specific
to the application.
V
V
= 19 V
= -9 V
CC
EE
4
3
2
LED Drive Circuit
Considerations for Ultra
1
0
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
0
20
40
60
80
100
Rg – GATE RESISTANCE – Ω
Figure 27. Energy Dissipated in the
HCPL-3150 for Each IGBT Switching
Cycle.
1-208
θ
= 439°C/W
LD
TJE = LED junction temperature
TJD = detector IC junction temperature
T
T
JD
JE
TC = case temperature measured at the center of the package bottom
θLC = LED-to-case thermal resistance
θ
= 391°C/W
θ
= 119°C/W
DC
LC
T
C
θLD = LED-to-detector thermal resistance
θDC = detector-to-case thermal resistance
θ
= 83°C/W*
CA
θCA = case-to-ambient thermal resistance
θCA will depend on the board design and the placement of the part.
T
A
Figure 28. Thermal Model.
CMR with the LED On
(CMRH)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED cur-
rent of 10 mA provides adequate
margin over the maximum IFLH of
5 mA to achieve 15 kV/µs CMR.
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dVCM/dt
transient, since all the current
flowing through CLEDN must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMRL
performance. Figure 33 is an
alternative drive circuit which,
like the recommended application
circuit (Figure 25), does achieve
ultra high CMR performance by
shunting the LED in the off state.
optocoupler output will go into
the low state with a typical delay,
UVLO Turn Off Delay, of 0.6 µs.
When the HCPL-3150 output is in
the low state and the supply
voltage rises above the HCPL-
3150 VUVLO+ threshold
(11.0 < VUVLO+ < 13.5), the
optocoupler will go into the high
state (assuming LED is “ON”)
with a typical delay, UVLO TURN
On Delay, of 0.8 µs.
IPM Dead Time and
Propagation Delay
Specifications
CMR with the LED Off
(CMRL)
A high CMR LED drive circuit
must keep the LED off
Under Voltage Lockout
Feature
The HCPL-3150 includes a
The HCPL-3150 contains an
under voltage lockout (UVLO)
feature that is designed to protect
the IGBT under fault conditions
which cause the HCPL-3150
supply voltage (equivalent to the
fully-charged IGBT gate voltage)
to drop below a level necessary to
keep the IGBT in a low resistance
state. When the HCPL-3150
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices from the high-
to the low-voltage motor rails.
(VF ≤ VF(OFF)) during common
mode transients. For example,
during a -dVCM/dt transient in
Figure 31, the current flowing
through CLEDP also flows through
the RSAT and VSAT of the logic
gate. As long as the low state
voltage developed across the
logic gate is less than VF(OFF), the
LED will remain off and no
common mode failure will occur.
output is in the high state and the
supply voltage drops below the
HCPL-3150 VUVLO- threshold
(9.5 <VUVLO- <12.0), the
To minimize dead time in a given
design, the turn on of LED2
should be delayed (relative to the
1-209
C
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
LEDO1
C
C
C
C
LEDP
LEDP
C
LEDO2
LEDN
LEDN
SHIELD
Figure 29. Optocoupler Input to Output
Capacitance Model for Unshielded Optocouplers.
Figure 30. Optocoupler Input to Output
Capacitance Model for Shielded Optocouplers.
+5 V
1
2
3
4
8
7
6
5
0.1
µF
+
–
C
I
LEDP
V
= 18 V
CC
1
2
3
4
8
7
6
5
+
LEDP
V
+5 V
SAT
–
C
LEDP
• • •
• • •
C
LEDN
Rg
SHIELD
C
I
LEDN
Q1
LEDN
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV /dt.
SHIELD
CM
+
–
V
CM
Figure 31. Equivalent Circuit for Figure 25 During
Common Mode Transient.
Figure 32. Not Recommended Open
Collector Drive Circuit.
maximum dead time is equivalent
to the difference between the
maximum and minimum propaga-
tion delay difference specifica-
tions as shown in Figure 35. The
maximum dead time for the
HCPL-3150 is 700 ns (= 350 ns -
(-350 ns)) over an operating
temperature range of -40°C to
100°C.
turn off of LED1) so that under
worst-case conditions, transistor
Q1 has just turned off when
transistor Q2 turns on, as shown
in Figure 34. The amount of delay
necessary to achieve this condi-
tions is equal to the maximum
value of the propagation delay
difference specification, PDDMAX
which is specified to be 350 ns
over the operating temperature
range of -40°C to 100°C.
1
2
3
4
8
7
6
5
+5 V
C
C
LEDP
LEDN
,
SHIELD
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal tempera-
tures and test conditions since
the optocouplers under consider-
ation are typically mounted in
close proximity to each other and
are switching identical IGBTs.
Figure 33. Recommended LED Drive
Circuit for Ultra-High CMR.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
1-210
I
LED1
14
12
V
OUT1
Q1 ON
(12.3, 10.8)
10
8
Q1 OFF
Q2 ON
(10.7, 9.2)
Q2 OFF
6
V
OUT2
4
I
LED2
t
PHL MAX
2
0
t
(10.7, 0.1)
PLH MIN
(12.3, 0.1)
15
0
5
10
20
PDD* MAX = (t - t
)
= t
- t
PHL PLH MAX
PHL MAX PLH MIN
(V
- V
) – SUPPLY VOLTAGE – V
EE
CC
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 36.Under Voltage Lock Out.
Figure 34. Minimum LED Skew for Zero Dead Time.
800
P
(mW)
(mA)
S
700
600
500
400
300
I
S
I
LED1
V
OUT1
Q1 ON
Q1 OFF
Q2 ON
200
100
0
Q2 OFF
V
OUT2
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
I
LED2
t
T
PHL MIN
S
t
PHL MAX
t
PLH
MIN
Figure 37. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per
VDE 0884.
t
PLH MAX
(t
t
)
PHL- PLH MAX
= PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
- t
- t
) + (t
) – (t
- t
- t
)
)
PHL MAX PHL MIN
PLH MAX PLH MIN
= (t
PHL MAX PLH MIN PHL MIN PLH MAX
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 35. Waveforms for Dead Time.
1-211
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