HCPL316J [HP]
2.0 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback; 2.0安培门驱动光电耦合器与集成（ VCE）去饱和检测和故障状态反馈
| 型号： | HCPL316J |
| 厂家： | 
HEWLETT-PACKARD |
| 描述： | 2.0 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback |
| 文件： | 总33页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.0 Amp Gate Drive Optocoupler
with Integrated (V ) Desaturation
CE
Detection and Fault Status
Feedback
Technical Data
HCPL-316J
Features
• Drive IGBTs up to
• “Soft” IGBT Turn-off
• Integrated Fail-Safe IGBT
Protection
• Wide Operating V Range:
15 to 30 Volts
• -40°C to +100°C Operating
Temperature Range
• 15 kV/µs Min. Common Mode
Rejection (CMR) at
CC
I = 150 A, V = 1200 V
C
CE
– Desat (V ) Detection
CE
• Optically Isolated, FAULT
Status Feedback
• SO-16 Package
• CMOS/TTL Compatible
• 500 ns Max. Switching
Speeds
– Under Voltage Lock-Out
Protection (UVLO) with
Hysterisis
• User Configurable:
Inverting, Non-inverting,
Auto-Reset, Auto-Shutdown
V
CM
= 1500 V
• Regulatory Approvals: UL,
CSA, IEC/EN/DIN EN 60747-
5-2 (891 Vpeak Working
Voltage)
Fault Protected IGBT Gate Drive
+HV
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
HCPL - 316J
HCPL - 316J
HCPL - 316J
3-PHASE
INPUT
M
HCPL - 316J
HCPL - 316J
HCPL - 316J
HCPL - 316J
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
–HV
FAULT
MICRO-CONTROLLER
Agilent’s 2.0 Amp Gate Drive Optocoupler with Integrated Desaturation (V ) Detection and Fault Status
CE
Feedback makes IGBT V
fault protection compact, affordable, and easy-to-implement while
CE
satisfying worldwide safety and regulatory requirements.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
Typical Fault Protected
IGBT Gate Drive Circuit
The HCPL-316J is an easy-to-use,
intelligent gate driver which
configurable inputs, integrated
detection, under voltage
lockout (UVLO), “soft” IGBT
turn-off and isolated fault feed-
back provide maximum design
flexibility and circuit protection.
V
CE
makes IGBT V fault protection
CE
compact, affordable, and easy-to-
implement. Features such as user
HCPL-316J
1
2
3
4
5
6
7
8
V
V
V
V
16
15
IN+
E
C
BLANK
*
V
IN-
LED2+
D
DESAT
100 Ω
DESAT 14
CC1
+
–
+
–
µC
V
F
GND1
V
13
12
11
10
9
CC2
R
F
+
–
+
–
+
–
RESET
FAULT
V
C
R
G
*
V
V
CE
V
OUT
V
V
–
+
*
LED1+
EE
V
V
EE
LED1-
R
PULL-DOWN
CE
* THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED.
Figure 1. Typical Desaturation Protected Gate Drive Circuit, Non-Inverting.
Description of Operation
during Fault Condition
1. DESAT terminal monitors the
be configured as inverting or
DESAT (pin 14) detection feature
of the HCPL-316J will be the
primary source of IGBT protection.
UVLO is needed to ensure DESAT
non-inverting using the V
or
IN+
V
inputs respectively. When an
IN-
inverting configuration is desired,
must be held high and V
IGBT V voltage through
CE
V
is functional. Once V
> 11.6
IN+
IN-
UVLO+
D
DESAT
.
toggled. When a non-inverting
configuration is desired, V
V, DESAT will remain functional
until V < 12.4 V. Thus, the
2. When the voltage on the
DESAT terminal exceeds
IN-
IN+
UVLO-
must be held low and V
toggled. Once UVLO is not active
(V - V > V ), V is
DESAT detection and UVLO
features of the HCPL-316J work in
conjunction to ensure constant
IGBT protection.
7 volts, the IGBT gate voltage
(V
OUT
) is slowly lowered.
CC2
E
UVLO
OUT
3. FAULT output goes low,
notifying the microcontroller
of the fault condition.
allowed to go high, and the
4. Microcontroller takes
appropriate action.
UVLO
Desat Condition
Pin 6
(FAULT)
Output
V
IN+
V
IN-
(V
- V )
Detected on
Pin 14
V
OUT
CC2
E
Output Control
X
X
Low
X
X
X
X
Active
X
Yes
X
X
No
X
Low
X
X
High
Low
Low
Low
Low
High
The outputs (V
and FAULT)
OUT
X
X
X
of the HCPL-316J are controlled
by the combination of V , UVLO
and a detected IGBT Desat
condition. As indicated in the
below table, the HCPL-316J can
IN
High
High Low
Not Active
3
Product Overview
Description
The HCPL-316J is a highly
integrated power control device
that incorporates all the
output IC provides local
protection for the IGBT to
prevent damage during
designed on a bipolar process,
while the output Detector IC is
designed manufactured on a high
voltage BiCMOS/Power DMOS
process. The forward optical
signal path, as indicated by
LED1, transmits the gate control
signal. The return optical signal
path, as indicated by LED2,
transmits the fault status
feedback signal. Both optical
channels are completely
controlled by the input and
output ICs respectively, making
the internal isolation boundary
transparent to the
overcurrents, and a second
optical link provides a fully
isolated fault status feedback
signal for the microcontroller. A
built in “watchdog” circuit
monitors the power stage supply
voltage to prevent IGBT caused
by insufficient gate drive
voltages. This integrated IGBT
gate driver is designed to
increase the performance and
reliability of a motor drive
without the cost, size, and
complexity of a discrete design.
necessary components for a
complete, isolated IGBT gate
drive circuit with fault protection
and feedback into one SO-16
package. TTL input logic levels
allow direct interface with a
microcontroller, and an optically
isolated power output stage
drives IGBTs with power ratings
of up to 150 A and 1200 V. A
high speed internal optical link
minimizes the propagation delays
between the microcontroller and
the IGBT while allowing the two
systems to operate at very large
common mode voltage
microcontroller.
Two light emitting diodes and two
integrated circuits housed in the
same SO-16 package provide the
input control circuitry, the output
power stage, and two optical
Under normal operation, the
input gate control signal directly
controls the IGBT gate through
the isolated output detector IC.
LED2 remains off and a fault
latch in the input buffer IC is
disabled. When an IGBT fault is
detected, the output detector IC
immediately begins a “soft”
shutdown sequence, reducing the
IGBT current to zero in a
controlled manner to avoid
potential IGBT damage from
inductive overvoltages.
Simultaneously, this fault status is
transmitted back to the input
buffer IC via LED2, where the
fault latch disables the gate
control input and the active low
fault output alerts the
differences that are common in
industrial motor drives and other
power switching applications. An
channels. The input Buffer IC is
V
V
LED1-
LED1+
7
8
13
INPUT IC
V
V
CC2
C
12
1
2
V
V
IN+
LED1
D
R
I
V
E
R
IN-
UVLO
11
14
V
OUT
DESAT
3
V
CC1
DESAT
microcontroller.
9,10
16
V
V
EE
E
SHIELD
LED2
During power-up, the Under
Voltage Lockout (UVLO) feature
prevents the application of
insufficient gate voltage to the
IGBT, by forcing the
5
6
RESET
FAULT
FAULT
SHIELD
OUTPUT IC
HCPL-316J’s output low. Once
the output is in the high state, the
4
15
V
GND1
LED2+
DESAT (V ) detection feature of
CE
the HCPL-316J provides IGBT
protection. Thus, UVLO and
DESAT work in conjunction to
provide constant IGBT
protection.
4
Package Pin Out
1
2
3
4
5
6
7
8
V
V
V
V
16
15
IN+
E
V
IN-
LED2+
DESAT 14
CC1
GND1
V
13
12
11
10
9
CC2
RESET
FAULT
V
C
V
OUT
V
V
V
LED1+
EE
EE
V
LED1-
Pin Descriptions
Symbol
Description
Non-inverting gate drive voltage output
(V ) control input.
Symbol
Description
Common (IGBT emitter) output supply
voltage.
VIN+
VIN-
VE
OUT
Inverting gate drive voltage output
(V ) control input.
VLED2+ LED 2 anode. This pin must be left uncon-
nected for guaranteed data sheet
performance. (For optical coupling testing
only)
OUT
VCC1
Positive input supply voltage. (4.5 V to 5.5 V)
DESAT Desaturation voltage input. When the voltage
on DESAT exceeds an internal reference
voltage of 7 V while the IGBT is on, FAULT
output is changed from a high impedance
state to a logic low state within 5 µs. See
Note 25.
GND1 Input Ground.
VCC2
VC
Positive output supply voltage.
RESET FAULT reset input. A logic low input for at
least 0.1 µs, asynchronously resets FAULT
output high and enables VIN. Synchronous
control of RESET relative to VIN is required.
RESET is not affected by UVLO. Asserting
RESET while VOUT is high does not affect
Collector of output pull-up triple-darlington
transistor. It is connected to VCC2 directly or
through a resistor to limit output turn-on
current.
VOUT
.
FAULT Fault output. FAULT changes from a high
impedance state to a logic low output within
5 µs of the voltage on the DESAT pin
exceeding an internal reference voltage of
7 V. FAULT output remains low until RESET
is brought low. FAULT output is an open
collector which allows the FAULT outputs
from all HCPL-316Js in a circuit
V
OUT
Gate drive voltage output.
to be connected together in a “wired OR”
forming a single fault bus for interfacing
directly to the micro-controller.
VLED1+ LED 1 anode. This pin must be left uncon-
nected for guaranteed data sheet per-
VEE
Output supply voltage.
formance. (For optical coupling testing only)
VLED1- LED 1 cathode. This pin must be connected
to ground.
5
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example: HCPL-316J#XXXX
No Option = 16-Lead, Surface Mt. package, 45 per tube.
500 = Tape and Reel Packaging Option, 850 per reel.
XXXE = Lead Free Option.
Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use “–”
Option data sheets available. Contact Agilent sales representative, authorized distributor, or visit our WEB site
at http://www.agilent.com/view/optocouplers.
Package Outline Drawings
16-Lead Surface Mount
0.018
(0.457ꢀ
0.050
(1.270ꢀ
LAND PATTERN RECOMMENDATION
Dimensions in
16 15 14 13 12 11 10
9
inches
(millimeters)
TYPE NUMBER
DATE CODE
A 316J
YYWW
0.458 (11.63ꢀ
0.295 0.010
(7.493 0.254ꢀ
Notes:
Initial and continued
variation in the color of the
HCPL-316J’s white mold
compound is normal and
does note affect device
performance or reliability.
0.085 (2.16ꢀ
1
2
3
4
5
6
7
8
0.406 0.10
(10.312 0.254ꢀ
0.025 (0.64ꢀ
0.345 0.010
(8.986 0.254ꢀ
ALL LEADS
TO BE
COPLANAR
0.002
9°
Floating Lead Protrusion
is 0.25 mm (10 mils) max.
0.138 0.005
(3.505 0.127ꢀ
0.018
(0.457ꢀ
0–8°
0.008 0.003
(0.203 0.076ꢀ
STANDOFF
0.025 MIN.
0.408 0.010
(10.160 0.254ꢀ
Package Characteristics
All specifications and figures are at the nominal (typical) operating conditions of V
= 5 V, V
- V
=
CC1
CC2
EE
30 V, V - V = 0 V, and T = +25°C.
E
EE
A
Parameter
Symbol Min. Typ. Max. Units
Test Conditions
Note
Input-Output Momentary
Withstand Voltage
Resistance (Input - Output)
Capacitance (Input - Output)
Output IC-to-Pins 9 &10
Thermal Resistance
V
ISO
3750 Vrms RH < 50%, t = 1 min., 1, 2,
T = 25°C
3
3
A
9
R
C
>10
Ω
V
= 500 Vdc
I-O
I-O
1.3
30
pF
f = 1 MHz
I-O
θ
°C/W T = 100°C
A
O9-10
Input IC-to-Pin 4 Thermal Resistance
θ
I4
60
6
Solder Reflow Thermal Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
2.5°C 0.5°C/SEC.
SOLDERING
TIME
30
160°C
150°C
140°C
200°C
SEC.
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDSꢀ
Recommended Pb-Free IR Profile
TIME WITHIN 5 °C of ACTUAL
PEAKTEMPERATURE
t
p
20-40 SEC.
260 +0/-5 °C
T
T
p
217 °C
L
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 °C, T = 150 °C
T
smax
smin
7
Regulatory Information
The HCPL-316J has been approved by the following
organizations:
UL
Recognized under UL 1577, component recognition
program, File E55361.
IEC/EN/DIN EN 60747-5-2
Approved under:
CSA
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.
Approved under CSA Component Acceptance Notice #5,
File CA 88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description
Symbol
Characteristic Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
I - IV
I - III
I - II
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
Climatic Classification
55/100/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b**
V
IORM
891
V
PEAK
V
IORM
x 1.875 = V , 100% Production Test with t = 1 sec,
V
PR
1670
V
PEAK
PR
m
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a**
V
x 1.5 = V , Type and Sample Test, t = 60 sec,
V
1336
6000
V
PEAK
IORM
PR
m
PR
Partial Discharge < 5 pC
Highest Allowable Overvoltage**
(Transient Overvoltage t = 10 sec)
V
IOTM
V
PEAK
ini
Safety-limiting values - maximum values allowed in the event of
a failure, also see Figure 2.
Case Temperature
Input Power
T
175
400
1200
°C
mW
mW
S
P
P
S, INPUT
Output Power
S, OUTPUT
9
Insulation Resistance at T , V = 500 V
R
>10
Ω
S
IO
S
* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application. Surface mount classification is class A in accordance with CECCOO802.
** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations
section IEC/EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.
1400
P , OUTPUT
S
1200
1000
P , INPUT
S
800
600
400
200
0
0
25 50 75 100 125 150 175 200
T
– CASE TEMPERATURE – °C
S
Figure 2. Dependence of Safety Limiting Values on Temperature.
8
Insulation and Safety Related Specifications
Parameter
Symbol Value Units
Conditions
Minimum External Air Gap L(101)
(Clearance)
8.3
8.3
0.5
mm Measured from input terminals to output
terminals, shortest distance through air.
mm Measured from input terminals to output
terminals, shortest distance path along body.
mm Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Minimum External
L(102)
Tracking (Creepage)
Minimum Internal Plastic
Gap (Internal Clearance)
Tracking Resistance
(Comparative Tracking
Index)
CTI
>175 Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Output IC Junction Temperature
Peak Output Current
Symbol
Min.
-55
-40
Max.
125
100
125
2.5
Units
°C
Note
T
s
T
A
T
4
5
J
|I
|
A
o(peak)
Fault Output Current
I
8.0
mA
FAULT
Positive Input Supply Voltage
Input Pin Voltages
V
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
5.5
V
CC1
35
15
Volts
CC1
V
, V and V
IN+ IN-
RESET
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Gate Drive Output Voltage
Collector Voltage
(V
- V )
CC2
EE
(V - V )
E
6
4
EE
(V
V
- V )
35 - (V - V )
E EE
CC2
E
V
CC2
V
CC2
o(peak)
V
V
+ 5 V
C
EE
DESAT Voltage
V
V
V + 10
600
150
DESAT
E
E
Output IC Power Dissipation
Input IC Power Dissipation
Solder Reflow Temperature Profile
P
O
mW
P
I
See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Operating Temperature
Input Supply Voltage
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Collector Voltage
Symbol
Min.
-40
4.5
15
0
15
Max.
+100
5.5
30
15
Units
°C
Volts
Note
T
A
V
28
9
6
CC1
(V
CC2
- V )
EE
(V - V )
E
EE
(V
CC2
- V )
30 - (V - V )
E EE
E
V
C
V
+ 6
V
CC2
EE
9
Electrical Specifications (DC)
Unless otherwise noted, all typical values at T = 25°C, V
all Minimum/Maximum specifications are at Recommended Operating Conditions.
= 5 V, and V
- V = 30 V, V - V = 0 V;
CC2 EE E EE
A
CC1
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig. Note
Logic Low Input
Voltages
VIN+L, VIN-L
VRESETL
,
0.8
V
Logic High Input
Voltages
VIN+H, VIN-H
,
2.0
-0.5
5.0
-40
VRESETH
Logic Low Input
Currents
IIN+L, IIN-L
IRESETL
,
-0.4
12
mA
VIN = 0.4 V
FAULT Logic Low
Output Current
IFAULTL
IFAULTH
IOH
VFAULT = 0.4 V
VFAULT = VCC1
30
31
FAULT Logic High
Output Current
µA
High Level Output
Current
-0.5
-2.0
0.5
2.0
90
-1.5
2.3
A
VOUT = VCC2 - 4 V
VOUT = VCC2 - 15 V
VOUT = VEE + 2.5 V
VOUT = VEE + 15 V
VOUT - VEE = 14 V
3, 8,
7
5
7
5
8
32
4, 9,
33
Low Level Output
Current
IOL
Low Level Output
Current during Fault
Condition
IOLF
160
230
mA
V
5, 34
High Level Output
Voltage
VOH
VC - 3.5
VC -2.9
VC - 2.5
VC - 2.0
VC - 1.5
VC - 1.2
VC
IOUT = -100 mA
IOUT = -650 µA
IOUT = 0
6, 8, 9, 10,
35 11
Low Level Output
Voltage
VOL
ICC1H
ICCIL
ICC2
0.17
17
0.5
IOUT = 100 mA
7, 9, 26
36
High Level Input
Supply Current
22
11
5
mA
VIN+ = VCC1 = 5.5 V, 10,
V
IN- = 0 V
VIN+ = VIN- = 0 V,
CC1 = 5.5 V
37,
38
Low Level Input
Supply Current
6
V
Output Supply
Current
2.5
VOUT open
11,12, 11
39,40
Low Level Collector
Current
ICL
0.3
1.0
IOUT = 0
15,
59
27
High Level Collector
Current
ICH
0.3
1.8
1.3
3.0
0
IOUT = 0
15, 58 27
15, 57
IOUT = -650 µA
VE Low Level Supply
Current
IEL
IEH
-0.7
-0.5
-0.4
14,
61
VE High Level Supply
Current
-0.14
0
14,
40
25
Blanking Capacitor
Charging Current
ICHG
-0.13
-0.18
-0.25
-0.25
-0.33
-0.33
VDESAT = 0 - 6 V
13,
41
11,
12
VDESAT = 0 - 6 V,
TA = 25°C - 100°C
Blanking Capacitor
Discharge Current
IDSCHG
VUVLO+
VUVLO-
10
50
12.3
11.1
1.2
VDESAT = 7 V
VOUT > 5 V
VOUT < 5 V
42
UVLO Threshold
11.6
13.5
12.4
V
43 9, 11,
13
9, 11,
14
UVLO Hysteresis
DESAT Threshold
(VUVLO+
VUVLO-
-
0.4
6.5
)
VDESAT
7.0
7.5
VCC2 -VE >VUVLO
-
16,
44
11
10
Switching Specifications (AC)
Unless otherwise noted, all typical values at T = 25°C, V
all Minimum/Maximum specifications are at Recommended Operating Conditions.
= 5 V, and V
- V = 30 V, V - V = 0 V;
CC2 EE E EE
A
CC1
Parameter
Symbol
Min.
Typ. Max. Units
Test Conditions
Fig.
Note
VIN to High Level Output
Propagation Delay Time
tPLH
0.10
0.30
0.50
µs
Rg = 10 Ω
Cg = 10 nF,
17,18,19, 15
20,21,22,
VIN to Low Level Output
Propagation Delay Time
tPHL
0.10
0.32
0.02
0.50
f = 10 kHz,
45,54,
55
Duty Cycle = 50%
Pulse Width Distortion
PWD
-0.30
-0.35
0.30
0.35
16,17
Propagation Delay Difference (tPHL - tPLH
)
17,18
Between Any Two Parts
10% to 90% Rise Time
90% to 10% Fall Time
PDD
tr
0.1
0.1
0.3
45
tf
DESAT Sense to 90% VOUT
Delay
tDESAT(90%)
0.5
3.0
5
Rg = 10 Ω,
Cg = 10 nF
23,56
19
DESAT Sense to 10% VOUT
Delay
tDESAT(10%)
tDESAT(FAULT)
tDESAT(LOW)
2.0
1.8
0.25
7
V
CC2
- V = 30 V
EE
24,28,
46,56
DESAT Sense to Low Level
FAULT Signal Delay
25,47,
56
20
21
22
DESAT Sense to DESAT Low
Propagation Delay
56
RESET to High Level FAULT tRESET(FAULT)
Signal Delay
3
20
26,27,
56
RESET Signal Pulse Width
PWRESET
tUVLO ON
0.1
UVLO to V
High Delay
4.0
V
= 1.0 ms
49
13
OUT
CC2
ramp
UVLO to V
Low Delay
tUVLO OFF
|CMH|
6.0
30
14
23
OUT
Output High Level Common
Mode Transient Immunity
15
15
kV/µs T = 25°C,
50,51,
52,53
A
V
= 1500 V,
= 30 V
CM
V
CC2
Output Low Level Common
Mode Transient Immunity
|CML|
30
T = 25°C,
24
A
V
CM
= 1500 V,
V
CC2
= 30 V
11
Notes:
6. This supply is optional. Required only
when negative gate drive is
implemented.
7. Maximum pulse width = 50 µs,
maximum duty cycle = 0.5%.
8. See the Slow IGBT Gate Discharge
During Fault Condition section in the
applications notes at the end of this
data sheet for further details.
21. This is the amount of time the DESAT
threshold must be exceeded before
1. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 4500 Vrms for 1 second (leakage
V
OUT
begins to go low, and the
FAULT output to go low.
22. This is the amount of time from when
RESET is asserted low, until FAULT
output goes high. The minimum
specification of 3 µs is the guaranteed
minimum FAULT signal pulse width
when the HCPL-316J is configured
for Auto-Reset. See the Auto-Reset
section in the applications notes at
the end of this data sheet for further
details.
detection current limit, I ≤ 5 µA).
I-O
This test is performed before the
100% production test for partial
discharge (method b) shown in IEC/
EN/DIN EN 60747-5-2 Insulation
Characteristic Table, if applicable.
2. The Input-Output Momentary With-
stand Voltage is a dielectric voltage
rating that should not be interpreted
as an input-output continuous voltage
rating. For the continuous voltage
rating refer to your equipment level
safety specification or IEC/EN/DIN
EN 60747-5-2 Insulation
9. 15 V is the recommended minimum
operating positive supply voltage
(V
- V ) to ensure adequate
E
CC2
margin in excess of the maximum
threshold of 13.5 V. For High
V
UVLO+
Level Output Voltage testing, V
is
23. Common mode transient immunity in
the high state is the maximum
OH
measured with a dc load current.
When driving capacitive loads, V
tolerable dV /dt of the common
OH
CM
will approach V as I approaches
mode pulse, V , to assure that the
CC
OH
CM
zero units.
output will remain in the high state
Characteristics Table.
10. Maximum pulse width = 1.0 ms,
maximum duty cycle = 20%.
(i.e., V > 15 V or FAULT > 2 V). A
O
3. Device considered a two terminal
device: pins 1 - 8 shorted together
and pins 9 - 16 shorted together.
4. In order to achieve the absolute
maximum power dissipation
100 pF and a 3K Ω pull-up resistor is
needed in fault detection mode.
24. Common mode transient immunity in
the low state is the maximum
11. Once V
of the HCPL-316J is
OUT
allowed to go high (V
- V >
CC2
E
V
), the DESAT detection feature
UVLO
of the HCPL-316J will be the primary
source of IGBT protection. UVLO is
needed to ensure DESAT is
tolerable dV /dt of the common
CM
specified, pins 4, 9, and 10 require
ground plane connections and may
require airflow. See the Thermal
Model section in the application notes
at the end of this data sheet for
details on how to estimate junction
temperature and power dissipation. In
most cases the absolute maximum
output IC junction temperature is the
limiting factor. The actual power
dissipation achievable will depend on
the application environment (PCB
Layout, air flow, part placement,
etc.). See the Recommended PCB
Layout section in the application
notes for layout considerations.
Output IC power dissipation is
mode pulse, V , to assure that the
CM
output will remain in a low state (i.e.,
functional. Once V
> 11.6 V,
V < 1.0 V or FAULT < 0.8 V).
UVLO+
O
DESAT will remain functional until
< 12.4 V. Thus, the DESAT
25. Does not include LED2 current
during fault or blanking capacitor
discharge current.
V
UVLO-
detection and UVLO features of the
HCPL-316J work in conjunction to
ensure constant IGBT protection.
12. See the Blanking Time Control
section in the applications notes at
the end of this data sheet for further
details.
26. To clamp the output voltage at
V
- 3 V , a pull-down resistor
CC
BE
between the output and V is
EE
recommended to sink a static current
of 650 µA while the output is high.
See the Output Pull-Down Resistor
section in the application notes at the
end of this data sheet if an output
pull-down resistor is not used.
13. This is the “increasing” (i.e. turn-on
or “positive going” direction) of
V
CC2
- V .
E
14. This is the “decreasing” (i.e. turn-off
or “negative going” direction) of
27. The recommended output pull-down
resistor between V
and V does
OUT
EE
derated linearly at 10 mW/°C above
90°C. Input IC power dissipation does
not require derating.
V
- V .
not contribute any output current
when V = V
CC2 E
15. This load condition approximates the
gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is
.
EE
OUT
28. In most applications V
will be
CC1
5. Maximum pulse width = 10 µs,
maximum duty cycle = 0.2%. This
value is intended to allow for compo-
nent tolerances for designs with I
peak minimum = 2.0 A. See
Applications section for additional
details on I
from 3.0 A at +25°C to 2.5 A at
+100°C. This compensates for
increased I
powered up first (before V
) and
CC2
defined as |t
unit.
- t
PLH
| for any given
powered down last (after V
). This
PHL
CC2
is desirable for maintaining control of
the IGBT gate. In applications where
17. As measured from V , V to V
.
O
IN+ IN-
OUT
18. The difference between t
and t
PHL PLH
V
is powered up first, it is
CC2
between any two HCPL-316J parts
under the same test conditions.
19. Supply Voltage Dependent.
20. This is the amount of time from when
the DESAT threshold is exceeded,
until the FAULT output goes low.
important to ensure that V
remains
in+
peak. Derate linearly
low until V
reaches the proper
OH
CC1
operating voltage (minimum 4.5 V) to
avoid any momentary instability at
due to changes in
the output during V
ramp-down.
ramp-up or
OPEAK
over temperature.
CC1
V
OL
12
Performance Plots
7
6
5
2.0
200
175
150
125
100
75
1.8
1.6
1.4
V
V
= V
= V
+ 15 V
+ 2.5 V
OUT
OUT
EE
EE
4
3
2
1
0
-40°C
25°C
100°C
1.2
1.0
50
25
-40 -20
0
20 40 60 80 100
-40 -20
0
20 40 60 80 100
0
5
10
15
20
25
30
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
V
– OUTPUT VOLTAGE – V
OUT
A
A
Figure 3. I
vs. Temperature.
Figure 4. I vs. Temperature
Figure 5. I
vs. V
OLF OUT.
OH
OL
.
0.25
0.20
29.0
28.8
28.6
28.4
28.2
28.0
27.8
27.6
0
-1
-2
-3
+100°C
+25°C
-40°C
I
I
= -650 µA
= -100 mA
OUT
OUT
I
= 100 mA
OUT
0.15
0.10
0.05
0
-4
27.4
0
-40 -20
0
20 40 60 80 100
-40 -20
0
20 40 60 80 100
0.2
0.4
0.6
0.8
1.0
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
I
– OUTPUT HIGH CURRENT – A
A
A
OH
Figure 6. V
vs. Temperature.
Figure 7. V vs. Temperature.
Figure 8. V
vs. I
.
OH
OL
OH
OH
6
5
4
3
2
1
0
2.6
2.5
2.4
2.3
2.2
20
15
+100°C
+25°C
-40°C
I
I
CC1H
CC1L
10
5
I
I
CC2H
CC2L
0
-40 -20
0
20 40 60 80 100
0.1
0.5
1.0
1.5
2.0
2.5
-40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
I
– OUTPUT LOW CURRENT – A
T
– TEMPERATURE – °C
A
OL
A
Figure 9: V vs. I
.
OL
Figure 10. I
vs. Temperature.
Figure 11: I
vs. Temperature.
CC2
OL
CC1
13
2.60
2.55
2.50
2.45
-0.15
-0.20
0.50
0.45
0.40
I
I
EH
EL
I
I
-0.25
-0.30
CC2H
CC2L
0.35
0.30
2.40
2.35
15
20
25
30
-40 -20
0
20 40 60 80 100
-40 -20
0
20 40 60 80 100
V
– OUTPUT SUPPLY VOLTAGE – V
T
– TEMPERATURE – °C
A
T
– TEMPERATURE – °C
CC2
A
Figure 12. I
vs. V
.
Figure 13. I
vs. Temperature.
Figure 14. I vs. Temperature.
CC2
CC2
CHG
E
7.5
7.0
6.5
4
3
2
0.5
t
t
PHL
PLH
0.4
0.3
0.2
-40°C
+25°C
+100°C
1
0
6.0
0
0.5
1.0
1.5
(mAꢀ
2.0
-40 -20
0
20 40 60 80 100
-40 -20
0
20 40 60 80 100
T – TEMPERATURE – °C
A
I
T
– TEMPERATURE – °C
OUT
A
Figure 15. I vs. I
.
OUT
Figure 16. DESAT Threshold vs.
Temperature.
Figure 17. Propagation Delay vs.
Temperature.
C
0.40
0.35
0.30
0.25
0.20
0.45
0.50
V
V
V
= 5.5 V
= 5.0 V
= 4.5 V
CC1
CC1
CC1
t
t
PHL
PLH
V
V
V
= 5.5 V
= 5.0 V
= 4.5 V
CC1
CC1
CC1
0.45
0.40
0.35
0.40
0.35
0.30
0.25
0.30
0.25
15
20
25
30
-50
0
50
100
-50
0
50
100
V
– SUPPLY VOLTAGE – V
TEMPERATURE – °C
TEMPERATURE – °C
CC
Figure 20. V to Low Propagation
Figure 18. Propagation Delay vs.
Supply Voltage.
Figure 19. V to High Propagation
IN
IN
Delay vs. Temperature.
Delay vs. Temperature.
14
0.40
0.35
0.30
0.25
0.20
0.45
0.40
0.35
0.30
0.25
0.20
t
t
t
t
PLH
PHL
PLH
PHL
0.40
0.35
0.30
0.25
-50
0
50
100
0
20
40
60
80
100
0
10
20
30
40
50
TEMPERATURE – °C
LOAD CAPACITANCE – nF
LOAD RESISTANCE – Ω
Figure 21. Propagation Delay vs. Load
Capacitance.
Figure 22. Propagation Delay vs. Load
Resistance.
Figure 23. DESAT Sense to 90% V
Delay vs. Temperature.
out
3.0
2.6
0.008
V
V
V
V
= 0 V
EE
EE
EE
EE
V
V
= 15 V
= 30 V
V
V
= 15 V
= 30 V
CC2
CC2
CC2
CC2
= -5 V
= -10 V
= -15 V
2.4
2.2
2.0
2.5
2.0
1.5
1.0
0.006
0.004
0.002
0
1.8
1.6
-50
0
50
100
0
10
20
30
40
50
-50
0
50
100
TEMPERATURE – °C
LOAD CAPACITANCE – nF
TEMPERATURE – °C
Figure 24. DESAT Sense to 10% V
Delay vs. Temperature.
Figure 25. DESAT Sense to Low Level
Fault Signal Delay vs. Temperature.
Figure 26. DESAT Sense to 10% V
Delay vs. Load Capacitance.
out
out
12
0.0030
V
V
V
= 5.5 V
= 5.0 V
= 4.5 V
CC1
CC1
CC1
V
V
= 15 V
= 30 V
CC2
CC2
10
8
0.0025
0.0020
0.0015
0.0010
6
4
-50
0
50
100
150
10
20
30
40
50
TEMPERATURE – °C
LOAD RESISTANCE – Ω
Figure 27. DESAT Sense to 10% V
Delay vs. Load Resistance.
Figure 28. RESET to High Level Fault
Signal Delay vs. Temperature.
out
15
Test Circuit Diagrams
V
V
V
V
V
V
V
V
E
IN+
IN-
E
IN+
IN-
0.1 µF
0.1
µF
0.1
µF
10 mA
V
V
+
5 V
+
LED2+
LED2+
4.5 V
0.4 V
–
–
DESAT
DESAT
CC1
CC1
GND1
V
GND1
V
CC2
CC2
–
–
+
+
RESET
FAULT
V
RESET
FAULT
V
C
C
5 V
V
V
OUT
OUT
I
I
FAULT
FAULT
V
V
V
V
V
V
V
V
LED1+
LED1-
EE
EE
LED1+
LED1-
EE
EE
Figure 30. I
Test Circuit.
Figure 31. I
Test Circuit.
FAULTL
FAULTH
V
V
E
V
V
E
IN+
IN+
0.1
µF
0.1 µF
0.1 µF
–
–
5 V
+
V
V
V
V
LED2+
IN-
LED2+
+
IN-
+
–
30 V
30 V
V
DESAT
V
DESAT
CC1
CC1
GND1
V
GND1
V
CC2
CC2
0.1 µF
0.1 µF
0.1 µF
OUT
+
RESET
FAULT
V
C
RESET
FAULT
V
C
15 V
–
+
+
PULSED
I
–
–
V
V
OUT
OUT
30 V
30 V
I
OUT
+
V
V
V
V
–
0.1 µF
LED1+
EE
LED1+
EE
15 V
PULSED
V
V
V
V
LED1-
EE
LED1-
EE
Figure 32. I
Pulsed Test Circuit.
Figure 33. I Pulsed Test Circuit.
OL
OH
V
V
V
V
V
V
V
V
E
IN+
IN-
E
IN+
IN-
0.1
µF
0.1
µF
0.1 µF
0.1 µF
–
–
+
V
V
LED2+
+
LED2+
+
5 V
5 V
+
–
–
30 V
30 V
DESAT
DESAT
CC1
CC1
GND1
V
GND1
V
CC2
CC2
0.1 µF
0.1 µF
RESET
FAULT
V
RESET
FAULT
V
C
C
+
+
I
V
OUT
OUT
2A
–
–
V
V
OUT
OUT
30 V
30 V
+
0.1
µF
0.1
µF
V
V
V
V
–
LED1+
EE
LED1+
EE
14 V
PULSED
V
V
V
V
EE
LED1-
EE
LED1-
Figure 34. I
Test Circuit.
Figure 35. V
Pulsed Test Circuit.
OH
OLF
16
V
V
V
V
V
V
V
V
E
IN+
IN-
E
IN+
IN-
0.1
µF
0.1 µF
0.1
µF
–
V
V
LED2+
+
LED2+
5 V
+
–
5.5 V
+
30 V
–
DESAT
DESAT
CC1
CC1
I
CC1
GND1
V
GND1
V
CC2
CC2
0.1 µF
100
mA
RESET
FAULT
V
RESET
FAULT
V
C
C
+
–
V
V
OUT
OUT
30 V
V
OUT
V
V
V
V
V
V
V
V
LED1+
LED1-
EE
EE
LED1+
LED1-
EE
EE
0.1
µF
Figure 36. V Test Circuit.
Figure 37. I
Test Circuit.
CC1H
OL
V
V
V
V
V
V
E
IN+
IN-
E
IN+
IN-
0.1
µF
0.1
µF
0.1
µF
–
V
V
V
V
LED2+
LED2+
+
5 V
+
5.5 V
+
30 V
–
–
DESAT
DESAT
CC1
CC1
I
CC1
I
CC2
GND1
V
GND1
V
CC2
CC2
0.1 µF
RESET
FAULT
V
RESET
FAULT
V
C
C
+
–
V
V
OUT
OUT
0.1 µF
30 V
V
V
V
V
V
V
V
V
LED1+
LED1-
EE
EE
LED1+
LED1-
EE
EE
Figure 38. I
Test Circuit.
CC1L
Figure 39. I
Test Circuit.
CC2H
V
V
E
V
V
E
IN+
IN+
0.1
µF
0.1 µF
0.1
µF
–
–
V
V
LED2+
V
V
V
IN-
+
IN-
LED2+
+
I
CHG
5 V
+
30 V
30 V
–
V
DESAT
DESAT
CC1
CC1
I
CC2
GND1
V
GND1
V
CC2
0.1 µF
CC2
0.1 µF
RESET
FAULT
V
C
RESET
FAULT
V
C
+
+
–
–
V
V
OUT
OUT
30 V
0.1 µF
0.1 µF
30 V
V
V
V
V
LED1+
EE
LED1+
EE
V
V
V
V
LED1-
EE
LED1-
EE
Figure 40. I
Test Circuit.
Figure 41. I
Pulsed Test Circuit.
CHG
CC2L
17
V
V
V
V
E
V
V
V
V
E
IN+
IN-
IN+
IN-
0.1
µF
7 V
–
0.1
µF
–
+
V
V
LED2+
LED2+
+
5 V
+
–
I
30 V
DSCHG
DESAT
DESAT
CC1
CC1
GND1
V
GND1
V
CC2
CC2
0.1 µF
SWEEP
RESET
FAULT
V
C
RESET
FAULT
V
C
+
+
–
V
OUT
–
V
V
OUT
OUT
30 V
0.1 µF
0.1 µF
V
V
V
V
LED1+
EE
LED1+
EE
V
V
V
V
LED1-
EE
LED1-
EE
Figure 42. I
Test Circuit.
Figure 43. UVLO Threshold Test Circuit.
DSCHG
V
IN
V
V
V
V
E
V
V
V
V
E
IN+
IN-
IN+
IN-
–
0.1 µF
–
–
+
V
V
LED2+
+
LED2+
+
0.1
µF
0.1
µF
15 V
30 V
SWEEP
DESAT
DESAT
CC1
CC1
–
+
GND1
V
GND1
V
CC2
CC2
0.1 µF
0.1 µF
5 V
RESET
FAULT
V
C
RESET
FAULT
V
C
0.1
µF
V
OUT
+
+
–
–
V
V
OUT
OUT
10 mA
15 V
30 V
3 k
10 Ω
0.1 µF
V
V
V
V
0.1
µF
LED1+
EE
LED1+
EE
10
nF
V
V
V
V
LED1-
EE
LED1-
EE
Figure 44. DESAT Threshold Test Circuit.
Figure 45. t
, t
, t , t Test Circuit.
PLH PHL
r
f
V
V
V
V
V
V
E
IN+
IN-
E
IN+
IN-
0.1
µF
0.1
µF
0.1
µF
0.1
µF
–
–
V
V
V
V
V
V
IN
+
LED2+
IN
+
+
LED2+
+
–
–
30 V
30 V
5 V
5 V
DESAT
DESAT
CC1
CC1
GND1
V
GND1
V
CC2
CC2
0.1
µF
0.1
µF
3 k
FAULT
0.1
µF
RESET
FAULT
V
C
RESET
FAULT
V
C
0.1
µF
V
OUT
+
+
V
–
–
V
V
OUT
OUT
30 V
30 V
3 k
10 Ω
10 Ω
10
V
V
V
V
V
V
V
V
LED1+
LED1-
EE
EE
LED1+
LED1-
EE
EE
10
nF
nF
Figure 46. t
Test Circuit.
Figure 47. t
Test Circuit.
DESAT(FAULT)
DESAT(10%)
18
V
V
V
V
V
V
V
V
E
IN+
IN-
E
IN+
IN-
0.1
µF
0.1
µF
0.1
µF
–
STROBE
8 V
V
V
LED2+
+
LED2+
+
+
–
–
30 V
5 V
5 V
DESAT
DESAT
CC1
CC1
0.1
µF
GND1
V
GND1
V
V
HIGH
CC2
CC2
IN
TO LOW
3 k
RESET
FAULT
V
C
RESET
FAULT
V
C
R
AMP
0.1
µF
0.1
µF
V
OUT
+
V
FAULT
–
V
V
OUT
OUT
30 V
3 k
10 Ω
10 Ω
V
V
V
V
V
V
V
V
LED1+
LED1-
EE
EE
LED1+
LED1-
EE
EE
10
nF
10
nF
Figure 48. t
Test Circuit.
Figure 49. UVLO Delay Test Circuit.
RESET(FAULT)
1
2
3
4
5
6
7
8
V
V
V
V
16
15
DESAT 14
IN+
IN-
E
V
5 V
LED2+
1
2
3
4
5
6
7
8
V
V
V
V
16
15
IN+
IN-
E
25 V
CC1
0.1
µF
V
5 V
LED2+
GND1
V
13
12
11
10
9
CC2
0.1 µF
3 kΩ
DESAT 14
CC1
RESET
FAULT
V
C
25 V
0.1
µF
GND1
V
13
12
11
10
9
CC2
SCOPE
V
OUT
0.1 µF
3 kΩ
RESET
FAULT
V
C
10 Ω
10 nF
V
V
V
V
LED1+
LED1
EE
EE
100 pF
SCOPE
V
OUT
10 Ω
750 Ω
V
V
V
V
LED1+
LED1
EE
EE
100 pF
–
10 nF
+
9 V
V
V
Cm
Cm
Figure 50. CMR Test Circuit, LED2 off.
Figure 51. CMR Test Circuit, LED2 on.
1
2
3
4
5
6
7
8
V
V
V
V
16
15
1
2
3
4
5
6
7
8
V
V
V
V
16
15
DESAT 14
IN+
IN-
E
IN+
IN-
E
V
V
5 V
5 V
LED2+
LED2+
DESAT 14
25 V
25 V
CC1
CC1
0.1
µF
0.1
µF
0.1 µF
GND1
V
13
12
11
10
9
GND1
V
13
12
11
10
9
CC2
CC2
0.1 µF
3 kΩ
3 kΩ
RESET
FAULT
V
RESET
FAULT
V
C
C
SCOPE
10 nF
V
V
SCOPE
OUT
OUT
10 Ω
100
pF
100 pF
V
V
V
V
10 Ω
LED1+
EE
LED1+
EE
V
V
V
V
EE
LED1
EE
LED1
10 nF
V
V
Cm
Cm
Figure 52. CMR Test Circuit, LED1 off.
Figure 53. CMR Test Circuit, LED1 on.
19
V
V
IN-
2.5 V
5.0 V
2.5 V
V
V
0 V
IN-
IN+
2.5 V
2.5 V
IN+
t
t
f
t
t
f
r
r
90%
90%
50%
10%
50%
10%
V
V
OUT
OUT
t
t
t
t
PLH
PHL
PLH
PHL
Figure 54. V
Propagation Delay Waveforms,
Figure 55. V
Propagation Delay Waveforms, Inverting
OUT
OUT
Noninverting Configuration.
Configuration.
t
DESAT (FAULTꢀ
t
DESAT (10%ꢀ
t
DESAT (LOWꢀ
7 V
V
V
DESAT
OUT
50%
t
DESAT (90%ꢀ
90%
10%
FAULT
RESET
50% (2.5 Vꢀ
t
RESET (FAULTꢀ
50%
Figure 56. Desat, V
, Fault, Reset Delay Waveforms.
OUT
20
V
V
V
V
E
V
V
V
V
E
IN+
IN-
IN+
IN-
0.1
µF
0.1
µF
0.1 µF
0.1 µF
–
–
5 V
+
5 V
+
V
V
LED2+
+
LED2+
+
–
–
30 V
30 V
DESAT
DESAT
CC1
CC1
GND1
V
GND1
RESET
FAULT
V
V
CC2
0.1 µF
CC2
0.1 µF
I
I
C
C
RESET
FAULT
V
C
V
C
+
0.1 µF
650 µA
+
–
–
V
V
0.1 µF
OUT
OUT
30 V
30 V
V
V
V
LED1+
EE
LED1+
LED1-
EE
V
V
V
V
LED1-
EE
EE
Figure 57. I
Test Circuit.
Figure 58. I
Test Circuit.
CH
CH
I
E
V
V
V
V
V
V
V
V
IN+
IN-
E
IN+
E
0.1
µF
0.1 µF
–
–
5 V
+
V
V
LED2+
+
IN-
LED2+
+
0.1
µF
–
30 V
30 V
DESAT
DESAT
CC1
CC1
GND1
V
V
GND1
V
V
CC2
CC2
0.1 µF
0.1 µF
I
C
RESET
FAULT
V
RESET
FAULT
V
C
C
+
+
–
–
0.1 µF
0.1 µF
OUT
OUT
30 V
30 V
V
V
V
V
V
V
V
V
LED1+
LED1-
EE
EE
LED1+
LED1-
EE
EE
Figure 59. I Test Circuit.
Figure 60. I
Test Circuit.
CL
EH
I
E
V
V
V
V
E
IN+
IN-
0.1
µF
–
5 V
+
V
LED2+
+
0.1
µF
–
30 V
DESAT
CC1
GND1
V
V
CC2
0.1 µF
RESET
FAULT
V
C
+
–
0.1 µF
OUT
30 V
V
V
V
V
LED1+
LED1-
EE
EE
Figure 61. I Test Circuit.
EL
21
Applications Information
Typical Application/
Operation
Introduction to Fault
The HCPL-316J satisfies these
criteria by combining a high
speed, high output current driver,
high voltage optical isolation
between the input and output,
local IGBT desaturation detection
and shut down, and an optically
isolated fault status feedback
signal into a single 16-pin surface
mount package.
on a preset current threshold to
predict the safe limit of
operation. Therefore, an overly-
conservative overcurrent
threshold is not needed to protect
the IGBT.
Detection and Protection
The power stage of a typical three
phase inverter is susceptible to
several types of failures, most of
which are potentially destructive
to the power IGBTs. These failure
modes can be grouped into four
basic categories: phase and/or
rail supply short circuits due to
user misconnect or bad wiring,
control signal failures due to
noise or computational errors,
overload conditions induced by
the load, and component failures
in the gate drive circuitry. Under
any of these fault conditions, the
current through the IGBTs can
increase rapidly, causing
excessive power dissipation and
heating. The IGBTs become
damaged when the current load
approaches the saturation current
of the device, and the collector to
emitter voltage rises above the
saturation voltage level. The
drastically increased power
Recommended Application
Circuit
The HCPL-316J has both
inverting and non-inverting gate
control inputs, an active low reset
input, and an open collector fault
output suitable for wired ‘OR’
applications. The recommended
application circuit shown in
Figure 62 illustrates a typical
gate drive implementation using
the HCPL-316J.
The fault detection method,
which is adopted in the
HCPL-316J, is to monitor the
saturation (collector) voltage of
the IGBT and to trigger a local
fault shutdown sequence if the
collector voltage exceeds a
predetermined threshold. A small
gate discharge device slowly
reduces the high short circuit
IGBT current to prevent
damaging voltage spikes. Before
the dissipated energy can reach
destructive levels, the IGBT is
shut off. During the off state of
the IGBT, the fault detect
The four supply bypass
capacitors (0.1 µF) provide the
large transient currents necessary
during a switching transition.
Because of the transient nature of
the charging currents, a low
current (5 mA) power supply
suffices. The desat diode and 100
pF capacitor are the necessary
external components for the fault
detection circuitry. The gate
resistor (10 Ω) serves to limit
gate charge current and indirectly
control the IGBT collector
circuitry is simply disabled to
prevent false ‘fault’ signals.
dissipation very quickly overheats
the power device and destroys it.
To prevent damage to the drive,
fault protection must be
implemented to reduce or
turn-off the overcurrents during a
fault condition.
The alternative protection
scheme of measuring IGBT
current to prevent desaturation is
effective if the short circuit
capability of the power device is
known, but this method will fail if
the gate drive voltage decreases
enough to only partially turn on
the IGBT. By directly measuring
the collector voltage, the
HCPL-316J limits the power
dissipation in the IGBT even with
insufficient gate drive voltage.
Another more subtle advantage of
the desaturation detection
voltage rise and fall times. The
open collector fault output has a
passive 3.3 kΩ pull-up resistor
and a 330 pF filtering capacitor.
A 47 kΩ pulldown resistor on
A circuit providing fast local fault
detection and shutdown is an
ideal solution, but the number of
required components, board
space consumed, cost, and
complexity have until now limited
its use to high performance
drives. The features which this
circuit must have are high speed,
low cost, low resolution, low
power dissipation, and small size.
V
OUT
provides a more predictable
high level output voltage (V ).
OH
In this application, the IGBT gate
driver will shut down when a fault
is detected and will not resume
switching until the
microcontroller applies a reset
signal.
method is that power dissipation
in the IGBT is monitored, while
the current sense method relies
22
HCPL-316J
1
2
3
4
5
6
7
8
V
V
V
V
16
15
IN+
IN-
E
0.1
µF
0.1
µF
100 pF
V
LED2+
D
DESAT
100 Ω
DESAT 14
CC1
+
–
5 V
+
–
0.1
µF
µC
V
F
GND1
V
13
12
11
10
9
CC2
3.3
kΩ
Q1
Q2
V
= 18 V
CC2
+
+
–
RESET
FAULT
V
C
V
CE
R
g
V
OUT
–
0.1
µF
3-PHASE
OUTPUT
47
kΩ
V
V
V
V
LED1+
LED1-
EE
EE
330 pF
–
+
+
V
= -5 V
EE
V
CE
–
Figure 62. Recommended Application Circuit.
Description of Operation/
Timing
Figure 63 below illustrates input
and output waveforms under the
conditions of normal operation, a
desat fault condition, and normal
reset behavior.
FAULT output is high and the
RESET input should be held high.
See Figure 63.
the purpose of notifying the
micro-controller of the fault
condition. See Figure 63.
Fault Condition
When the voltage on the DESAT
pin exceeds 7 V while the IGBT is
Reset
The FAULT output remains low
until RESET is brought low. See
Figure 63. While asserting the
RESET pin (LOW), the input pins
must be asserted for an output
on, V
is slowly brought low in
OUT
Normal Operation
order to “softly” turn-off the IGBT
and prevent large di/dt induced
voltages. Also activated is an
internal feedback channel which
brings the FAULT output low for
During normal operation, V
of
OUT
the HCPL-316J is controlled by
either V or V , with the IGBT
low state (V
is LOW or V is
IN+
IN-
IN+
IN-
HIGH). This may be
accomplished either by software
control (i.e. of the
collector-to-emitter voltage being
monitored through D . The
DESAT
microcontroller) or hardware
control (see Figures 73 and 74).
NORMAL
OPERATION
FAULT
CONDITION
RESET
V
IN-
IN+
IN-
0 V
5 V
NON-INVERTING
CONFIGURED
INPUTS
V
V
V
5 V
INVERTING
CONFIGURED
INPUTS
IN+ 5 V
7 V
V
V
DESAT
OUT
FAULT
RESET
Figure 63. Timing Diagram.
23
Slow IGBT Gate
Discharge During Fault
Condition
When a desaturation fault is
detected, a weak pull-down
device in the HCPL-316J output
drive stage will turn on to ‘softly’
turn off the IGBT. This device
slowly discharges the IGBT gate
to prevent fast changes in drain
current that could cause
damaging voltage spikes due to
lead and wire inductance. During
the slow turn off, the large output
pull-down device remains off until
value can be scaled slightly to
adjust the blanking time, though
a value smaller than 100 pF is not
recommended. This nominal
blanking time also represents the
longest time it will take for the
HCPL-316J to respond to a
DESAT fault condition. If the
IGBT is turned on while the
collector and emitter are shorted
to the supply rails (switching into
a short), the soft shut-down
sequence will begin after
approximately 3 µsec. If the IGBT
collector and emitter are shorted
to the supply rails after the IGBT
is already on, the response time
will be much quicker due to the
parasitic parallel capacitance of
the DESAT diode. The
recommended 100 pF capacitor
should provide adequate blanking
as well as fault response times for
most applications.
region and quickly overheat. The
UVLO function causes the output
to be clamped whenever
insufficient operating supply
(V
CC2
) is applied. Once V
CC2
exceeds V
(the positive-
UVLO+
going UVLO threshold), the
UVLO clamp is released to allow
the device output to turn on in
response to input signals. As
V
CC2
is increased from 0 V (at
some level below V
), first
UVLO+
the DESAT protection circuitry
becomes active. As V is
CC2
further increased (above
), the UVLO clamp is
V
UVLO+
the output voltage falls below V
+ 2 Volts, at which time the large
pull down device clamps the
EE
released. Before the time the
UVLO clamp is released, the
DESAT protection is already
active. Therefore, the UVLO and
DESAT FAULT DETECTION
features work together to provide
seamless protection regardless of
IGBT gate to V .
EE
DESAT Fault Detection
Blanking Time
The DESAT fault detection
circuitry must remain disabled for
a short time period following the
turn-on of the IGBT to allow the
collector voltage to fall below the
DESAT theshold. This time
period, called the DESAT
supply voltage (V ).
CC2
Under Voltage Lockout
The HCPL-316J Under Voltage
Lockout (UVLO) feature is
designed to prevent the
application of insufficient gate
voltage to the IGBT by forcing
the HCPL-316J output low during
power-up. IGBTs typically require
gate voltages of 15 V to achieve
blanking time, is controlled by
the internal DESAT charge
current, the DESAT voltage
threshold, and the external
DESAT capacitor. The nominal
blanking time is calculated in
terms of external capacitance
their rated V
voltage. At
CE(ON)
gate voltages below 13 V
typically, their on-voltage
(C
), FAULT threshold
BLANK
increases dramatically, especially
at higher currents. At very low
gate voltages (below 10 V), the
IGBT may operate in the linear
voltage (V
charge current (I
), and DESAT
DESAT
) as
CHG
t
= C
x V
/ I
.
BLANK
BLANK
DESAT CHG
The nominal blanking time with
the recommended 100 pF
capacitor is 100 pF * 7 V / 250 µA
= 2.8 µsec. The capacitance
24
Behavioral Circuit
Schematic
signal input are both latched. The
fault output changes to an active
low state, and the signal LED is
forced off (output LOW). The
latched condition will persist until
the Reset pin is pulled low.
are never on at the same time. If
an undervoltage condition is
detected, the output will be
actively pulled low by the 50x
DMOS device, regardless of the
LED state. If an IGBT
desaturation fault is detected
while the signal LED is on, the
Fault signal will latch in the high
state. The triple darlington AND
the 50x DMOS device are
disabled, and a smaller 1x DMOS
pull-down device is activated to
slowly discharge the IGBT gate.
When the output drops below two
volts, the 50x DMOS device again
turns on, clamping the IGBT gate
firmly to Vee. The Fault signal
remains latched in the high state
until the signal LED turns off.
The functional behavior of the
HCPL-316J is represented by the
logic diagram in Figure 64 which
fully describes the interaction and
sequence of internal and external
signals in the HCPL-316J.
Output IC
Three internal signals control the
state of the driver output: the
state of the signal LED, as well as
the UVLO and Fault signals. If no
fault on the IGBT collector is
detected, and the supply voltage
is above the UVLO threshold, the
LED signal will control the driver
output state. The driver stage
logic includes an interlock to
ensure that the pull-up and pull-
down devices in the output stage
Input IC
In the normal switching mode, no
output fault has been detected,
and the low state of the fault
latch allows the input signals to
control the signal LED. The fault
output is in the open-collector
state, and the state of the Reset
pin does not affect the control of
the IGBT gate. When a fault is
detected, the FAULT output and
250 µA
V
(16ꢀ
E
DESAT (14ꢀ
+
V
V
(1ꢀ
(2ꢀ
IN+
IN–
–
LED
7 V
V
(3ꢀ
CC1
V
(13ꢀ
(12ꢀ
CC2
–
UVLO
GND (4ꢀ
DELAY
+
12 V
V
C
FAULT (6ꢀ
Q
V
(11ꢀ
OUT
R
S
50 x
RESET (5ꢀ
FAULT
V
(9,10ꢀ
EE
1 x
Figure 64. Behavioral Circuit Schematic.
25
HCPL-316J
1
2
3
4
5
6
7
8
V
V
V
IN+
IN-
HCPL-316J
HCPL-316J
V
16
15
V
16
15
E
E
V
V
100 pF
LED2+
CC1
LED2+
+
–
µC
3.3
DESAT 14
DESAT 14
GND1
kΩ
100 Ω
D
DESAT
V
13
12
11
10
9
V
13
12
11
10
9
CC2
CC2
RESET
FAULT
V
C
V
C
V
V
OUT
OUT
R
R
g
g
V
V
LED1+
LED1-
330 pF
V
V
EE
EE
R
PULL-DOWN
V
V
EE
EE
Figure 65. Output Pull-Down Resistor.
Figure 66. DESAT Pin Protection.
Figure 67. FAULT Pin CMR Protection.
value of 15 kV/µs. The added
capacitance does not increase the
fault output delay when a
desaturation condition is
detected.
DESAT Pin Protection
Other Recommended
Components
The freewheeling of flyback
diodes connected across the
IGBTs can have large
The application circuit in Figure
62 includes an output pull-down
resistor, a DESAT pin protection
resistor, a FAULT pin capacitor
(330 pF), and a FAULT pin pull-
up resistor.
instantaneous forward voltage
transients which greatly exceed
the nominal forward voltage of
the diode. This may result in a
large negative voltage spike on
the DESAT pin which will draw
substantial current out of the IC if
protection is not used. To limit
this current to levels that will not
damage the IC, a 100 ohm
resistor should be inserted in
series with the DESAT diode. The
added resistance will not alter the
DESAT threshold or the DESAT
blanking time.
Pull-up Resistor on FAULT Pin
The FAULT pin is an open-
collector output and therefore
requires a pull-up resistor to
provide a high-level signal.
Output Pull-Down Resistor
During the output high transition,
the output voltage rapidly rises to
Driving with Standard CMOS/
TTL for High CMR
within 3 diode drops of V
. If
CC2
the output current then drops to
zero due to a capacitive load, the
output voltage will slowly rise
Capacitive coupling from the
isolated high voltage circuitry to
the input referred circuitry is the
primary CMR limitation. This
coupling must be accounted for
to achieve high CMR perform-
from roughly V -3(V ) to V
CC2
BE
CC2
within a period of several
microseconds. To limit the output
voltage to V -3(V ), a pull-
CC2
BE
Capacitor on FAULT Pin for
High CMR
ance. The input pins V
and
IN+
down resistor between the output
V
IN-
must have active drive
and V is recommended to sink
EE
Rapid common mode transients
can affect the fault pin voltage
while the fault output is in the
high state. A 330 pF capacitor
(Fig. 66) should be connected
between the fault pin and ground
to achieve adequate CMOS noise
margins at the specified CMR
signals to prevent unwanted
switching of the output under
extreme common mode transient
conditions. Input drive circuits
that use pull-up or pull-down
resistors, such as open collector
configurations, should be
a static current of several 650 µA
while the output is high. Pull-
down resistor values are
dependent on the amount of
positive supply and can be
adjusted according to the
formula, R
=
pull-down
avoided. Standard CMOS or TTL
drive circuits are recommended.
[V -3 * (V )] / 650 µA.
CC2
BE
26
User-Configuration of the Driving Input pf HCPL-316J in
configuration is desired, V
is
IN–
HCPL-316J Input Side
Non-Inverting/Inverting Mode
held low by connecting it to
GND1 and V is toggled. As
IN+
The V , V , FAULT and
The Gate Drive Voltage Output of
the HCPL-316J can be
configured as inverting or
IN+
IN-
shown in Figure 69, when an
inverting configuration is desired,
is held high by connecting it
RESET input pins make a wide
variety of gate control and fault
configurations possible,
V
IN+
non-inverting using the V and
IN–
to V
and V
is toggled.
CC1
IN–
depending on the motor drive
requirements. The HCPL-316J
has both inverting and non-
inverting gate control inputs, an
open collector fault output
suitable for wired ‘OR’
V
inputs. As shown in Figure
IN+
68, when a non-inverting
applications and an active low
reset input.
HCPL-316J
HCPL-316J
1
2
3
4
5
6
7
8
V
V
V
1
2
3
4
5
6
7
8
V
V
V
IN+
IN-
IN+
IN-
CC1
CC1
+
–
+
–
µC
µC
GND1
GND1
RESET
FAULT
RESET
FAULT
V
V
V
V
LED1+
LED1-
LED1+
LED1-
Figure 68. Typical Input Configuration, Non-Inverting.
Figure 69. Typical Input Configuration, Inverting.
27
gate control signal is a
Local Shutdown, Local Reset
HCPL-316J
continuous PWM signal, the fault
latch will always be reset by the
next time the input signal goes
high. This configuration protects
the IGBT on a cycle-by-cycle
basis and automatically resets
before the next ‘on’ cycle. The
fault outputs can be wire ‘OR’ed
together to alert the
microcontroller, but this signal
would not be used for control
purposes in this (Auto-Reset)
configuration. When the
1
2
3
4
5
6
7
8
V
V
V
As shown in Figure 70, the fault
output of each HCPL-316J gate
driver is polled separately, and
the individual reset lines are
asserted low independently to
reset the motor controller after a
fault condition.
IN+
IN-
CC1
+
–
µC
GND1
RESET
FAULT
Global-Shutdown, Global
Reset
As shown in Figure 71, when
configured for inverting
operation, the HCPL-316J can be
configured to shutdown
automatically in the event of a
fault condition by tying the
V
V
LED1+
LED1-
HCPL- 316J is configured for
Auto-Reset, the guaranteed
minimum FAULT signal pulse
width is 3 µs.
Figure 70. Local Shutdown, Local
Reset Configuration.
FAULT output to V . For high
IN+
HCPL-316J
reliability drives, the open
1
2
3
4
5
6
7
8
V
V
V
IN+
IN-
Resetting Following a Fault
Condition
To resume normal switching
operation following a fault
condition (FAULT output low),
the RESET pin must first be
asserted low in order to release
the internal fault latch and reset
the FAULT output (high). Prior to
asserting the RESET pin low, the
collector FAULT outputs of each
HCPL-316J can be wire ‘OR’ed
together on a common fault bus,
forming a single fault bus for
interfacing directly to the micro-
controller. When any of the six
gate drivers detects a fault, the
fault output signal will disable all
six HCPL-316J gate drivers
simultaneously and thereby
provide protection against further
catastrophic failures.
CC1
+
–
µC
GND1
RESET
FAULT
V
V
LED1+
LED1-
CONNECT
TO OTHER
RESETS
input (V ) switching signals must
IN
be configured for an output (V )
OL
CONNECT
TO OTHER
FAULTS
low state. This can be handled
directly by the microcontroller or
by hardwiring to synchronize the
RESET signal with the
appropriate input signal. Figure
73a shows how to connect the
Auto-Reset
As shown in Figure 72, when the
Figure 71. Global-Shutdown, Global
Reset Configuration.
inverting V input is connected
IN-
to ground (non-inverting
configuration), the HCPL-316J
can be configured to reset
automatically by connecting
HCPL-316J
RESET to the V
signal for safe
IN+
1
2
3
4
5
6
7
8
V
V
V
IN+
automatic reset in the non-
inverting input configuration.
Figure 73b shows how to
IN-
RESET to V
. In this case, the
IN+
gate control signal is applied to
the non-inverting input as well as
the reset input to reset the fault
latch every switching cycle.
During normal operation of the
IGBT, asserting the reset input
low has no effect. Following a
fault condition, the gate driver
remains in the latched fault state
until the gate control signal
CC1
configure the V /RESET signals
IN+
+
–
µC
so that a RESET signal from the
microcontroller causes the input
to be in the “output-off” state.
Similarly, Figures 73c and 73d
show automatic RESET and
microcontroller RESET safe
configurations for the inverting
input configuration.
GND1
RESET
FAULT
V
V
LED1+
LED1-
changes to the ‘gate low’ state
and resets the fault latch. If the
Figure 72. Auto-Reset Configuration.
28
HCPL-316J
HCPL-316J
V
IN+
1
2
3
4
5
6
7
8
V
V
V
1
2
3
4
5
6
7
8
V
V
V
IN+
IN-
IN+
IN-
V
V
CC
CC
CC1
CC1
µC
µC
GND1
GND1
V
/
IN+
RESET
RESET
FAULT
RESET
FAULT
RESET
FAULT
FAULT
V
V
V
V
LED1+
LED1-
LED1+
LED1-
Figure 73a. Safe Hardware Reset for Non-Inverting
Input Configuration (Automatically Resets for Every
IN+
Figure 73b. Safe Hardware Reset for Non-Inverting Input
Configuration.
V
Input).
HCPL-316J
HCPL-316J
V
V
V
V
CC
CC
CC
CC
1
2
3
4
5
6
7
8
V
V
V
1
2
3
4
5
6
7
8
V
V
V
IN+
IN-
IN+
IN-
V
IN-
V
IN-
CC1
CC1
µC
µC
GND1
GND1
RESET
RESET
FAULT
RESET
FAULT
RESET
FAULT
FAULT
V
V
V
V
LED1+
LED1-
LED1+
LED1-
Figure 73c. Safe Hardware Reset for Inverting Input
Configuration.
Figure 73d. Safe Hardware Reset for Inverting Input
Configuration (Automatically Resets for Every V
Input).
IN-
User-Configuration of the
HCPL-316J Output Side
than the peak discharge current
(I < I ). For this
condition, an optional resistor
R + R = [V
– V
– (V )]
OH EE
C
G
CC2
I
ON,PEAK
OFF,PEAK
OH,PEAK
R and Optional Resistor R :
G
C
(R ) can be used along with R
= [4 V – (-5 V)]
0.5 A
C
G
The value of the gate resistor R
G
to independently determine
(along with V
and V
)
CC2
EE
I
and I
without
ON,PEAK
OFF,PEAK
determines the maximum amount
of gate-charging/discharging
using a steering diode. As an
example, refer to Figure 74.
= 18 Ω
current (I
and I
)
ON,PEAK
OFF,PEAK
Assuming that R is already
➯ R = 8 Ω
G
C
and thus should be carefully
chosen to match the size of the
IGBT being driven. Often it is
desirable to have the peak gate
determined and that the design
= 0.5 A, the value of R
I
See “Power and Layout
Considerations” section for more
information on calculating value
OH,PEAK
C
can be estimated in the following
way:
charge current be somewhat less
of R .
G
29
Higher Output Current Using
an External Current Buffer:
allowing sensing of the IGBT’s
saturated collector-to-emitter
HCPL-316J
To increase the IGBT gate drive
current, a non-inverting current
buffer (such as the npn/pnp
voltage, V
is “on”) and to block high
voltages (when the IGBT is “off”).
During the short period of time
when the IGBT is switching, there
is commonly a very high dV /dt
voltage ramp rate across the
IGBT’s collector-to-emitter. This
results in I
, (when the IGBT
V
16
15
CESAT
E
V
100 pF
LED2+
DESAT 14
buffer shown in Figure 75) may
be used. Inverting types are not
compatible with the desaturation
fault protection circuitry and
should be avoided. To preserve
the slow IGBT turn-off feature
during a fault condition, a 10 nF
capacitor should be connected
V
13
12
11
10
9
CC2
R
8 Ω
C
CE
V
C
10 Ω
10 nF
V
OUT
(= C
x
CHARGE
D-DESAT
V
V
EE
EE
dV /dt) charging current which
CE
will charge the blanking
capacitor, C
15 V
-5 V
from the buffer input to V and
. In order to
EE
BLANK
a 10 Ω resistor inserted between
the output and the common npn/
pnp base. The MJD44H11 /
MJD45H11 pair is appropriate
for currents up to 8A maximum.
The D44VH10 / D45VH10 pair is
appropriate for currents up to 15
A maximum.
minimize this charging current
and avoid false DESAT triggering,
it is best to use fast response
diodes. Listed in the below table
are fast-recovery diodes that are
suitable for use as a DESAT diode
Figure 74. Use of R to Further Limit
ON,PEAK
C
I
.
(D
). In the recommended
DESAT
application circuit shown in
Figure 62, the voltage on pin 14
DESAT Diode and DESAT
Threshold
(DESAT) is V
= V + V
,
CE
DESAT
F
(where V is the forward ON
F
voltage of D
IGBT collector-to-emitter
voltage). The value of V which
and V is the
DESAT
CE
The DESAT diode’s function is to
conduct forward current,
HCPL-316J
V
16
15
E
CE
100 pF
triggers DESAT to signal a
V
LED2+
FAULT condition, is nominally 7V
DESAT 14
– V . If desired, this DESAT
F
V
13
12
11
10
9
threshold voltage can be
CC2
MJD44H11 or
decreased by using multiple
DESAT diodes in series. If n is
the number of DESAT diodes
then the nominal threshold value
D44VH10
V
C
4.5 Ω
10 Ω
10 nF
V
OUT
2.5 Ω
V
V
EE
EE
MJD45H11 or
D45VH10
becomes V
= 7 V – n
CE,FAULT(TH)
x V . In the case of using two
F
15 V
-5 V
diodes instead of one, diodes with
half of the total required
maximum reverse-voltage rating
may be chosen.
Figure 75. Current Buffer for Increased Drive Current.
Max. Reverse Voltage
Rating, V (Volts)
Part Number
MUR1100E
MURS160T3
UF4007
Manufacturer
Motorola
Motorola
General Semi.
Philips
t
(ns)
75
Package Type
59-04 (axial leaded)
rr
RRM
1000
600
1000
1000
1000
600
75
75
75
75
75
Case 403A (surface mount)
DO-204AL (axial leaded)
SOD64 (axial leaded)
SOD57 (axial leaded)
SOD87 (surface mount)
BYM26E
BYV26E
BYV99
Philips
Philips
Power/Layout
Considerations
Operating Within the
Maximum Allowable Power
Ratings (Adjusting Value of
When choosing the value of R ,
The steps for doing this are:
1. Calculate the minimum desired
G
it is important to confirm that the
power dissipation of the
HCPL-316J is within the
maximum allowable power
rating.
R ;
G
2. Calculate total power
dissipation in the part
referring to Figure 77.
R ):
G
30
MAX. I , I
vs. GATE RESISTANCE
/ V = 25 V / 5 V
ON OFF
(Average switching energy
supplied to HCPL-316J per
The HCPL-316J total power
dissipation (P ) is equal to the
(V
CC2 EE2
4
T
cycle vs. R plot);
sum of the input-side power (P )
and output-side power (P ):
O
G
I
3
2
3. Compare the input and output
power dissipation calculated in
step #2 to the maximum
P = P + P
T
I
O
1
I
I
(MAX.ꢀ
OFF
recommended dissipation for
the HCPL-316J. (If the
maximum recommended level
has been exceeded, it may be
necessary to raise the value of
P = I
* V
CC1
I
CC1
0
P = P
O
+ P
O,SWTICH
O(BIAS)
(MAX.ꢀ
ON
-1
-2
-3
= I
* (V
–V ) +
CC2
E
CC2 EE
* f
SWITCH
SWITCH
R to lower the switching
G
0
20 40 60 80 100120140160180 200
where,
power and repeat step #2.)
Rg (Ωꢀ
P
= steady-state power
O(BIAS)
dissipation in the HCPL-316J
due to biasing the device.
Figure 76. Typical Peak I
and I
OFF
As an example, the total input
and output power dissipation can
be calculated given the following
conditions:
ON
Currents vs. Rg (for HCPL-316J
Output Driving an IGBT Rated at
600 V/100 A.
P
= transient power
O(SWITCH)
dissipation in the HCPL-316J
due to charging and discharging
power device gate.
• I
~ 2.0 A
SWITCHING ENERGY vs. GATE RESISTANCE
(V / V = 25 V / 5 V
ON, MAX
CC2
EE2
• V
= 18 V
CC2
9
8
7
6
5
4
3
2
• V = -5 V
EE
• f
= 15 kHz
CARRIER
E
= Average Energy
SWITCH
dissipated in HCPL-316J due to
switching of the power device
over one switching cycle
(µJ/cycle).
Step 1: Calculate R minimum
G
from I peak specification:
OL
Ess (Qg = 650 nCꢀ
To find the peak charging l
OL
assume that the gate is initially
charged the steady-state value of
f
= average carrier signal
SWITCH
1
0
V
. Therefore apply the
EE
frequency.
following relationship:
0
50
100
150
200
For R = 10.5, the value read
G
Rg (Ωꢀ
from Figure 77 is E
=
SWITCH
Figure 77. Switching Energy Plot for
Calculating Average Pswitch (for
HCPL-316J Output Driving an IGBT
Rated at 600 V/100 A).
R =
G
6.05 µJ. Assume a worst-case
[V @650 µA – (V +V )]
OH
OL
EE
average I = 16.5 mA (which is
CC1
I
OL,PEAK
given by the average of I
and
CC1H
I
I
). Similarly the average
= 5.5 mA.
CC1L
= [V
– 1 – (V + V )]
OL EE
CC2
CC2
I
OL,PEAK
P = 90.8 mW < 150 mW
I
P = 16.5 mA * 5.5 V = 90.8 mW
(abs. max.) ➱ OK
I
18 V – 1 V – (1.5 V + (-5 V))
2.0 A
P = P
+ P
P = 217.3 mW < 400 mW
O
O(BIAS)
O,SWITCH
O
(abs. max.) ➱ OK
= 10.25 Ω
= 5.5 mA * (18 V – (–5 V)) +
6.051 µJ * 15 kHz
≈ 10.5 Ω (for a 1% resistor)
Therefore, the power dissipation
absolute maximum rating has not
been exceeded for the example.
= 126.5 mW + 90.8 mW
= 217.3 mW
(Note from Figure 76 that the
real value of I may vary from
OL
the value calculated from the
simple model shown.)
Please refer to the following
Thermal Model section for an
explanation on how to calculate
the maximum junction
temperature of the HCPL-316J
for a given PC board layout
configuration.
Step 3: Compare the
calculated power dissipation
with the absolute maximum
values for the HCPL-316J:
Step 2: Calculate total power
dissipation in the HCPL-316J:
For the example,
31
Thermal Model
Since θ and θ
are
9,10A
If we, however, assume a worst
case PCB layout and no air flow
4A
dependent on PCB layout and
airflow, their exact number may
not be available. Therefore, a
more accurate method of calcu-
lating the junction temperature is
with the following equations:
The HCPL-316J is designed to
dissipate the majority of the heat
through pins 4 for the input IC
and pins 9 and 10 for the output
where the estimated θ and
4A
θ
are 100°C/W. Then the
9,10A
junction temperatures become
IC. (There are two V pins on
EE
T = (90.8 mW)(60°C/W
ji
the output side, pins 9 and 10,
for this purpose.) Heat flow
through other pins or through the
package directly into ambient are
considered negligible and not
modeled here.
+ 100°C/W) + 100°C = 115°C
T = P θ + T
ji
i i4
P4
T
= P θ
+ T
T = (240 mW)(30°C/W
jo
o o9,10
P9,10
jo
+ 100°C/W) + 100°C = 131°C
These equations, however,
require that the pin 4 and pins
9,10 temperatures be measured
with a thermal couple on the pin
at the HCPL-316J package edge.
The output IC junction
temperature exceeds the absolute
maximum specification of 125°C.
In this case, PCB layout and
airflow will need to be designed
so that the junction temperature
of the output IC does not exceed
125°C.
In order to achieve the power
dissipation specified in the
absolute maximum specification,
it is imperative that pins 4, 9, and
10 have ground planes connected
to them. As long as the maximum
power specification is not
From the earlier power
dissipation calculation
example:
exceeded, the only other limita-
tion to the amount of power one
can dissipate is the absolute
maximum junction temperature
specification of 125°C. The
junction temperatures can be
calculated with the following
equations:
P = 90.8 mW, P = 314 mW, T
A
If the calculated junction
temperatures for the thermal
model in Figure 78 is higher than
125°C, the pin temperature for
pins 9 and 10 should be
measured (at the package edge)
under worst case operating
environment for a more accurate
estimate of the junction
i
o
= 100°C, and assuming the
thermal model shown in Figure
77 below.
T = (90.8 mW)(60°C/W
ji
+ 50°C/W) + 100°C = 110°C
T
= (240 mW)(30°C/W
jo
T = P (θ + θ ) + T
ji
i
i4
4A
A
+ 50°C/W) + 100°C = 119°C
temperatures.
T
= P (θ
+ θ
) + T
jo
o
o9,10
9,10A A
both of which are within the
absolute maximum specification
of 125°C.
where P = power into input IC
i
and P = power into output IC.
o
T = junction temperature of input side IC
ji
T = junction temperature of output side IC
jo
T
T
θ
= pin 4 temperature at package edge
P4
T
T
jo
ji
= pin 9 and 10 temperature at package edge
P9,10
θ
= 60°C/W
θ
= 30°C/W
O9,10
i4
= input side IC to pin 4 thermal resistance
I4
θ
θ
θ
= output side IC to pin 9 and 10 thermal resistance
= pin 4 to ambient thermal resistance
I9,10
T
T
P9,10
P4
4A
9,10A
θ
= 50°C/W*
θ
= 50°C/W*
9,10A
4A
= pin 9 and 10 to ambient thermal resistance
T
A
*The θ and θ
values shown here are for PCB layouts shown in Figure 78 with
4A
9,10A
reasonable air flow. This value may increase or decrease by a factor of 2 depending
on PCB layout and/or airflow.
Figure 78. HCPL-316J Thermal Model.
Printed Circuit Board
Layout Considerations
bypass capacitors. Maintaining
short bypass capacitor trace
lengths will ensure low supply
ripple and clean switching
waveforms.
details on how to estimate
junction temperature.
Adequate spacing should always
be maintained between the high
voltage isolated circuitry and any
input referenced circuitry. Care
must be taken to provide the
same minimum spacing between
two adjacent high-side isolated
regions of the printed circuit
board. Insufficient spacing will
reduce the effective isolation and
increase parasitic coupling that
will degrade CMR performance.
The layout examples below have
good supply bypassing and
thermal properties, exhibit small
PCB footprints, and have easily
connected signal and supply
lines. The four examples cover
single sided and double sided
component placement, as well as
minimal and improved
Ground Plane connections are
necessary for pin 4 (GND1) and
pins 9 and 10 (V ) in order to
EE
achieve maximum power
dissipation as the HCPL-316J is
designed to dissipate the majority
of heat generated through these
pins. Actual power dissipation
will depend on the application
environment (PCB layout, air
flow, part placement, etc.) See
the Thermal Model section for
performance circuits.
The placement and routing of
supply bypass capacitors requires
special attention. During switch-
ing transients, the majority of the
gate charge is supplied by the
Figure 79. Recommended Layout(s).
System Considerations
Propagation Delay Difference
(PDD)
transistor Q1 has just turned off
when transistor Q2 turns on, as
shown in Figure 80. The amount
of delay necessary to achieve this
condition is equal to the maxi-
mum value of the propagation
delay difference specification,
time is equivalent to the
difference between the maximum
and minimum propagation delay
difference specifications as
shown in Figure 81. The
maximum dead time for the
HCPL-316J is 800 ns (= 400 ns -
(-400 ns)) over an operating
temperature range of -40°C to
100°C.
The HCPL-316J includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
PDD
, which is specified to be
MAX
400 ns over the operating
temperature range of -40°C to
100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal tempera-
tures and test conditions since
the optocouplers under consider-
ation are typically mounted in
close proximity to each other and
are switching identical IGBTs.
transistors (Q1 and Q2 in
Delaying the HCPL-316J turn-on
signals by the maximum
Figure 62) are off. Any overlap in
Q1 and Q2 conduction will result
in large currents flowing through
the power devices between the
high and low voltage motor rails,
a potentially catastrophic condi-
tion that must be prevented.
propagation delay difference
ensures that the minimum dead
time is zero, but it does not tell a
designer what the maximum dead
time will be. The maximum dead
To minimize dead time in a given
design, the turn-on of the
V
IN+1
HCPL-316J driving Q2 should be
delayed (relative to the turn-off of
the HCPL-316J driving Q1) so
that under worst-case conditions,
V
OUT1
Q1 ON
Q1 OFF
Q2 ON
Q2 OFF
V
OUT2
V
IN+1
V
IN+2
t
PHL
MIN
t
PHL
V
OUT1
Q1 ON
MAX
Q1 OFF
Q2 ON
t
PLH
MIN
t
PLH
MAX
= PDD*
MAX
MAX
Q2 OFF
(t
t
ꢀ
PHL- PLH
V
OUT2
V
IN+2
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLERꢀ
t
PHL
MAX
= (t
= (t
= PDD*
- t
- t
– PDD*
ꢀ + (t
- t
PLH
ꢀ
MIN
t
PHL
PHL
PHL
PLH
PLH
PLH
MAX
MAX
MAX
MIN
MIN
MAX
MIN
- t
ꢀ – (t
- t
ꢀ
PLH
MAX
PHL
MIN
PDD* MAX = (t
ꢀ
= t
- t
PLH
MAX MIN
PHL PLH
PHL
MAX
MIN
*PDD = PROPAGATION DELAY
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 80. Minimum LED Skew for Zero Dead Time.
Figure 81. Waveforms for Dead Time Calculation.
For product information and a complete list of
Agilent contacts and distributors, please go to
our web site.
www.agilent.com/semiconductors
E-mail: SemiconductorSupport@agilent.com
Data subject to change.
Copyright © 2005 Agilent Technologies, Inc.
Obsoletes 5989-0784EN
March 1, 2005
5989-2143EN
相关型号：
HCPL3700SD
Logic IC Output Optocoupler, 1-Element, 2500V Isolation, SURFACE MOUNT PACKAGE-8
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明