TSI-8_技术文档

Hardware Design Guide, Revision 1

November 2, 2005

TSI-8

8K x 8K Time-Slot Interchanger

This document describes the hardware interfaces to the

Agere Systems Inc. TSI-8 device. Information relevant to

the use of the device in a board design is covered. Ball de-

scriptions, dc electrical characteristics, timing diagrams, ac

timing parameters, packaging, and operating conditions are

included.

1 Introduction

The last issue of this data sheet was May, 2002 (This docu-

ment was previously labeled Advance Information.) A

change history is included in 9 Change History on page 25.

Red change bars have been installed on all text, figures,

and tables that were added or changed. All changes to the

text are highlighted in red. Changes within figures, and the

figure title itself, are highlighted in red, if feasible. Formatting

or grammatical changes have not been highlighted. Deleted

sections, paragraphs, figures, or tables will be specifically

mentioned.

1.1 Related Documents

More information on the TSI-8 is contained in the following

documents:

TSI-8 Product Description

TSI-8 Register Description

TSI-8 Systems Design Guide

®

If the reader displays this document in Acrobat Reader ,

clicking on any blue entry in the text will bring the reader to

that reference point.

2 Description

2.1 Block Diagram and High-Level Interface Definition

TEST PATTERN

GENERATOR

TEST PATTERN

MONITOR

TRANSLATION

TABLE LOOKUP

TEST ACCESS

PORT

8K X 8K SWITCH

FABRIC

32

RECEIVE

CHI

32

TRANSMIT

CHI

DATA

STORE

WRITE ADDRESS

COUNTER

CONNECTION

STORE

READ ADDRESS

COUNTER

MICROPROCESSOR

INTERFACE

CLOCK

GENERATOR

Figure 2-1. Block Diagram and High-Level Interface Definition

TSI-8

Hardware Design Guide, Revision 1

November 2, 2005

8K x 8K Time-Slot Interchanger

Table of Contents

Page Contents

Contents

Page

1 Introduction ..............................................................1

1.1 Related Documents ..........................................1

2 Description ...............................................................1

2.1 Block Diagram and High-Level Interface

Figure 6-13. Typical Receive CHI Timing with 8.192

Mbits/s Data and 8.192 MHz CHICLK.....20

Figure 6-14. Transmit CHI Timing with 8.192 Mbits/s

Data and 8.192 MHz CHICLK .................20

Figure 6-15. CHI 3-State Output Control...................21

Figure 6-16. Microprocessor Port Timing—

Definition ..........................................................1

3 Ball Information ........................................................3

3.1 Ball Diagram .....................................................3

3.2 Package Ball Assignments ...............................4

3.3 Ball Types .........................................................8

3.4 Ball Definitions ..................................................8

4 Absolute Maximum Ratings ...................................11

4.1 Handling Precautions .....................................11

4.2 ESD Tolerance ...............................................11

4.3 Package Thermal Characteristics ...................11

4.4 Recommended Operating Conditions ............12

5 dc Electrical Characteristics ..................................13

6 Timing Diagrams and ac Characteristics ...............14

7 Outline Diagrams ...................................................24

8 Ordering Information ..............................................25

9 Change History ......................................................25

Read Cycle.............................................22

Figure 6-17. Microprocessor Port Timing—

Write Cycle.............................................23

Tables

Page

Table 3-1. Package Ball Assignments in Signal Name

Order ...........................................................4

Table 3-2. Package Ball Assignments in Ball Number

Order (Top View) .........................................6

Table 3-3. Package Ball Assignments in Ball Number

Order (Bottom View) (continued).................7

Table 3-4. Ball Types ...................................................8

Table 3-5. Timing Port..................................................8

Table 3-6. Transmit and Receive Concentration

Highways.....................................................8

Figures

Page

Table 3-7. Control Port.................................................9

Table 3-8. Initialization and Test Access......................9

Table 3-9. Power Balls...............................................10

Table 4-1. Absolute Maximum Ratings...................... 11

Table 4-2. ESD Tolerance.......................................... 11

Table 4-3. Power Consumption ................................. 11

Table 4-4. Operating Conditions................................12

Table 5-1. CMOS Inputs ............................................13

Table 5-2. CMOS Outputs .........................................13

Table 5-3. CMOS Bidirectionals (Excluding

Figure 2-1. Block Diagram and High-Level Interface

Definition ...................................................1

Figure 3-1. Package Diagram (Top View) ...................3

Figure 6-1. CHICLK Timing Specifications................14

Figure 6-2. MPUCLK Timing Specifications ..............14

Figure 6-3. ac Timing Specification ...........................15

Figure 6-4. CHI Interface Timing ...............................15

Figure 6-5. Typical Receive CHI Timing with 16.384

Mbits/s Data and 16.384 MHz CHICLK...16

Figure 6-6. Transmit CHI Timing with 16.384 Mbits/s

Data and 16.384 MHz CHICLK ...............16

Figure 6-7. Typical Receive CHI Timing with 8.192

Mbits/s Data and 16.384 MHz CHICLK...17

Figure 6-8. Transmit CHI Timing with 8.192 Mbits/s

Data and 16.384 MHz CHICLK ...............17

Figure 6-9. Typical Receive CHI Timing with 4.096

Mbits/s Data and 16.384 MHz CHICLK...18

TXD[31:00])...............................................13

Table 5-4. CMOS Bidirectionals (TXD[31:00])...........13

Table 6-1. CHICLK Timing Specifications..................14

Table 6-2. MPUCLK Timing Specifications ................14

Table 6-3. CMOS Output ac Timing Specification * ...15

Table 6-4. CHI Interface Timing.................................15

Table 6-5. CHI 3-State Output Control.......................21

Table 6-6. Microprocessor Port Timing—

Figure 6-10. Transmit CHI Timing with 4.096 Mbits/s

Data and 16.384 MHz CHICLK ...............18

Read Cycle................................................22

Table 6-7. Microprocessor Port Timing—

Figure 6-11. Typical Receive CHI Timing with 2.048

Mbits/s Data and 16.384 MHz CHICLK...19

Write Cycle23

Table 8-1. Ordering Information.................................25

Figure 6-12. Transmit CHI Timing with 2.048 Mbits/s

Data and 16.384 MHz CHICLK ...............19

2

Agere Systems Inc.

Hardware Design Guide, Revision 1

November 2, 2005

TSI-8

8K x 8K Time-Slot Interchanger

3 Ball Information

3.1 Ball Diagram

The TSI-8 is housed in a 240-ball plastic ball grid array. Figure 3-1 shows the ball arrangement viewed from the top of the

package. The balls are spaced on a 1.0 mm pitch.

1

2

4

5

7

8

9 10

12 13

15 16

18

17

3

6

11

14

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

Figure 3-1. Package Diagram (Top View)

Agere Systems Inc.

3

TSI-8

Hardware Design Guide, Revision 1

November 2, 2005

8K x 8K Time-Slot Interchanger

3.2 Package Ball Assignments

Table 3-1. Package Ball Assignments in Signal Name Order

Symbol

ADDR00

ADDR01

ADDR02

ADDR03

ADDR04

ADDR05

ADDR06

ADDR07

ADDR08

ADDR09

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

AS

Ball

A17

A16

A15

A14

A13

A12

A11

A10

A9

Symbol

DATA13

DATA14

DATA15

DT

Ball

P18

P17

P16

H17

T11

R17

H16

K15

R18

P15

J17

H15

F17

F18

E15

E16

E17

D17

B18

C18

D18

T18

V17

V2

Symbol

RXD11

RXD12

RXD13

RXD14

RXD15

RXD16

RXD17

RXD18

RXD19

RXD20

RXD21

RXD22

RXD23

RXD24

RXD25

RXD26

RXD27

RXD28

RXD29

RXD30

RXD31

TCK

Ball

V7

Symbol

TXD08

TXD09

TXD10

TXD11

TXD12

TXD13

TXD14

TXD15

TXD16

TXD17

TXD18

TXD19

TXD20

TXD21

TXD22

TXD23

TXD24

TXD25

TXD26

TXD27

TXD28

TXD29

TXD30

TXD31

VDD15

Ball

F1

Symbol

VDD15

VDD33

VDDPLL

VIO

Ball

D13

D14

G4

T8

G3

G2

G1

H2

H1

J2

U8

V8

H4

FSYNC

HIZ

U9

L4

V9

M4

R7

INT

V10

U10

V11

U11

V12

U12

V13

U13

V14

U14

V15

U15

T15

V16

U16

G17

G16

G18

G15

H18

B1

MPUCLK

PAR0

J1

R8

K1

K2

L1

R11

R12

C9

A8

PAR1

A7

R/W

A6

RESET

RSV1

L2

C10

C17

D9

A5

M1

M2

N1

N2

N3

P1

P2

R1

R2

T1

A4

RSV2

A3

RSV3

D10

E3

A2

RSV4

J16

R16

E18

D16

J18

K18

K17

L18

L17

L16

M18

M17

M16

M15

N18

N17

N16

N15

RSV5

F3

CHICLK

CKSPD0

CKSPD1

CS

RSV6

F15

H3

RSV7

RSV8

J3

RSV9

K16

P3

DATA00

DATA01

DATA02

DATA03

DATA04

DATA05

DATA06

DATA07

DATA08

DATA09

DATA10

DATA11

DATA12

RSV10

RSV11

RXD00

RXD01

RXD02

RXD03

RXD04

RXD05

RXD06

RXD07

RXD08

RXD09

RXD10

TDI

T2

R3

TDO

U1

C5

C6

C7

C12

C13

C14

D5

D6

D7

D12

T5

U3

TMS

T6

V3

TRSTN

TXD00

TXD01

TXD02

TXD03

TXD04

TXD05

TXD06

TXD07

VDD15

T9

U4

VDD15

T10

T14

T17

R14

K3

V4

C2

VDD15

U5

C1

VDD15

V5

D2

VDD15

U6

D1

VDD15

V6

E2

VDD15

VPRE

VSS

T4

T7

E1

VDD15

A1

U7

F2

VDD15

VSS

A18

4

Agere Systems Inc.

Hardware Design Guide, Revision 1

November 2, 2005

TSI-8

8K x 8K Time-Slot Interchanger

Table 3-1. Package Ball Assignments in Signal Name Order (continued)

Symbol

VSS

Ball

B2

Symbol

VSS

Ball

C8

Symbol

VSS

Ball

J9

Symbol

VSS

Ball

R4

B3

C11

C15

C16

D3

J10

J11

J15

K4

VSS

R5

B4

VSS

R6

B5

VSS

R9

B6

VSS

R10

R15

T3

B7

D4

K8

VSS

B8

D8

K9

VSS

B9

D11

D15

E4

K10

K11

L3

VSS

T12

T13

T16

U2

B10

B11

B12

B13

B14

B15

B16

B17

C3

VSS

F4

L8

VSS

F16

H8

L9

VSS

U17

U18

V1

L10

L11

L15

M3

N4

VSS

H9

VSS

H10

H11

J4

VSS

V18

R13

VSSPLL

C4

J8

P4

Agere Systems Inc.

5

TSI-8

Hardware Design Guide, Revision 1

November 2, 2005

8K x 8K Time-Slot Interchanger

3.3 Ball Types

This table describes each type of input, output, and I/O ball used on the TSI-8.

Table 3-4. Ball Types

Type Label

Description

I

CMOS input, TTL switching thresholds.

I pd

I pu

O

CMOS input, TTL switching thresholds with internal pull-down resistor.

CMOS input, TTL switching thresholds with internal pull-up resistor.

CMOS output.

O od

I/O

Open drain output.

Bidirectional ball; CMOS input with TTL switching thresholds and CMOS output.

Analog inputs for external resistors, capacitors, voltage references, etc.

Power and ground.

None

P

The dc switching and other electrical characteristics are specified later in this document.

3.4 Ball Definitions

This section describes the function of each of the device balls. The balls are listed by ball name. Package ball numbers are

listed in Table 3-1 of this document. The static parameters (drive currents, switching thresholds, etc.) for each ball type (in-

put, output, etc.) are described in Table 5-1 through Table 5-4.

Table 3-5. Timing Port

Ball Name Type

Name/Description

FSYNC

I

Frame Synchronization. This signal indicates the beginning of a 125 µs frame event (8 kHz). The

FSYNC ball can be programmed as active-low or active-high, but its polarity is the same for all concen-

tration highway interfaces (CHI). FSYNC can be sampled on either the positive or negative edge of

CHICLK. Time-slot numbers and bit offsets for each CHI are assigned relative to the detection of

FSYNC.

CHICLK

CKSPD0

I

Clock. This is the master synchronous clock for the transmit and receive concentration highways. The

frequency can be 8.192 MHz or 16.384 MHz. It must be at least as fast as the highest CHI data rate.

Clock Speed. Static control input that should be tied according to the frequency of CHICLK. If CHICLK

is connected to an 8.192 MHz source, CKSPD0 should be tied to VSS. If CHICLK is connected to a

16.384 MHz source, CKSPD0 should be tied to VDD33.

CKSPD1 I pd Clock Speed. Reserved, leave disconnected. 20 kΩ pull-down resistor.

Table 3-6. Transmit and Receive Concentration Highways

Ball Name Type

Name/Description

RXD[31:00] I pd Receive Data [31:00]. Receive concentration highways. These are serial, synchronous data streams

which may be individually programmed to operate at 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or

16.384 Mbits/s. They carry 32, 64, 128, or 256 time slots (respectively) each occupying eight contiguous

bits. 20 kΩ pull-down resistor.

TXD[31:00] I/O Transmit Data [31:00]. Normally these are output concentration highway data streams with data rate

options identical to the RXD inputs. These balls can be configured to operate as bidirectional multiplex

ports such as H.110. Further information can be found in the system design guide. 20 kΩ resistor

connected to VPRE.

8

Agere Systems Inc.

Hardware Design Guide, Revision 1

November 2, 2005

TSI-8

8K x 8K Time-Slot Interchanger

Table 3-7. Control Port

Ball Name Type

Name/Description

MPUCLK

I

Processor Clock. This clock is used to sample address, data, and control signals from the

microprocessor. This clock must be within the range of 0 MHz—66 MHz. Required for operation.

CS

Chip Select. Active-low chip select. This input is held low for the duration of any read or write access

to the TSI-8. Required for operation.

AS

Address Strobe. Active-low address strobe that is one MPUCLK cycle wide at the start of a

microprocessor access cycle to the TSI-8. This is used to initiate a microprocessor access. Required

for operation.

R/W

I

Read/Write. Cycle selection. R/W is set high during a read cycle, or set low for a write cycle.

Required for operation.

ADDR[15:00] I pu Address [15:00]. ADDR[15] is the most significant bit and ADDR[00] is the least significant bit for

addressing all the internal registers during microprocessor access cycles. All addresses are

16-bit word addresses; hence, in a typical application ADDR[00] of the TSI-8 device would be

connected to address bit 1 of a byte addressable system address bus. Required for operation. 200

kΩ pull-up resistor.

Note: The TSI-8 is little-endian; the least significant byte is stored in the lowest address and the most

significant byte is stored in the highest address. Care must be exercised in connection to

microprocessors that use big-endian byte ordering.

DATA[15:00] I/O Data [15:00]. Data bus for all transfers between the microprocessor and the internal registers. The

balls are inputs during write cycles and outputs during read cycles. DATA[15] is the most significant

bit, and DATA[00] is the least significant bit. Required for operation.

PAR[1:0]

I/O Control Port Parity [1:0]. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8], and

PAR[0] is the parity for DATA[7:0]. The parity sense (even or odd) is application programmable via a

register bit in the TSI-8. Not required for operation.

DT

O

Data Transfer Acknowledge. Active-low for one MPUCLK cycle. Indicates that data has been

written during write cycles or that data is valid during read cycles. High impedance when CS is a 1

and driven when CS is 0. Required for operation.

INT

O od Interrupt. This output is asserted low to indicate that an interrupt condition has occurred. This signal

remains active-low until the interrupt status register has been cleared or masked.

Table 3-8. Initialization and Test Access

Ball Name Type

Name/Description

I pu Reset. Global reset, active-low. Initializes all internal registers to their default state. The reset occurs

asynchronously, but RESET should be held low for at least two CHICLK periods. 20 kΩ pull-up resistor.

RESET

TCK

I pu Test Clock. This signal provides timing for the boundary scan and test access port (TAP) controller.

Should be static except during boundary-scan testing. 20 kΩ pull-up resistor.

TDI

TMS

I pu Test Data In. Data input for the boundary scan. Sampled on the rising edge of TCK. 20 kΩ pull-up

resistor.

I pu Test Mode Select (Active-Low). Controls boundary-scan test operations. TMS is sampled on the rising

edge of TCK. 20 kΩ pull-up resistor.

TRSTN

TDO

I pd Test Reset (Active-Low). This signal is an asynchronous reset for the TAP controller. 20 kΩ pull-down

resistor.

O

Test Data Out. Updated on the falling edge of TCK. The TDO output is high impedance except when

scanning out test data.

I pu Output Enable. All output and bidrectional buffers will be high impedance when this input is low unless

boundary scan is enabled (TRSTN = 1). 20 kΩ pull-up resistor.

HIZ

RSV[11:1]

—

Reserved [11:1]. These balls are used by Agere Systems during the manufacturing process. They must

be left unconnected.

Agere Systems Inc.

9

TSI-8

Hardware Design Guide, Revision 1

November 2, 2005

8K x 8K Time-Slot Interchanger

Table 3-9. Power Balls

Symbol Type

Name/Description

VDD33

VDD15

VSS

P

I/O Power. Power supply balls for the I/O pads (3.3 V ± 5%).

Core Power. Power supply balls for the core (1.5 V ± 5%).

Ground. Common ground balls for 3.3 V and 1.5 V supplies.

VPRE

Precharge. Precharge voltage to support H.110 hot insertion on TXD[31:00]. If the device is used in an

H.110 hot insertion applications, the signal should be connected to backplane early voltage; otherwise

connect this signal to ground.

VIO

P

PCI Buffer Voltage Select. For an H.110 application using TXD[31:00] in a 5 V signaling environment,

connect this signal to 5 V. For an H.110 application using TXD[31:00] in a 3 V signaling environment,

connect this signal to VDD33. For all other applications, connect this signal to VDD33.

VDDPLL

VSSPLL

P

PLL Power. 1.5 V power supply for the internal phase-locked loop. Must include local 0.01 µF capacitor to

VSSPLL.

PLL Ground. Isolated ground for the internal phase-locked loop.

10

Agere Systems Inc.

Hardware Design Guide, Revision 1

November 2, 2005

TSI-8

8K x 8K Time-Slot Interchanger

4 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress

ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the

operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect

device reliability.

Table 4-1. Absolute Maximum Ratings

Parameter

Supply Voltage (VDD33)

Min

–0.5

Max

4.2

Unit

V

Supply Voltage (VDD15)

1.8

V

Input Voltage:

TXD[31:00]

All Other Inputs

–0.5

–0.3

5.5

VDD33 + 0.3

V

Storage Temperature

Junction Temperature

–40

—

125

°C

4.1 Handling Precautions

Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be

taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere

employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to deter-

mine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit param-

eters used in each of the models, as defined by JEDEC’s JESD22-A114 (HBM) and JESD22-C101 (CDM) standards.

4.2 ESD Tolerance

Table 4-2. ESD Tolerance

Device

Voltage

2,000 V

500 V

Type

TSI-8

HBM (human-body model)

CDM (charged-device model)

4.3 Package Thermal Characteristics

ΘJA = 24.0 °C/W.

Table 4-3. Power Consumption

*

Supply Voltage

VDD33

Typ

Max

100 mW at 3.3 V

275 mW at 1.5 V

150 mW at 3.47 V

325 mW at 1.6 V

VDD15

*MPUCLK = 66 MHz, CHICLK = 16.384 MHz, TA = 25 °C, all CHIs active, all outputs loaded with 50 pF.

Agere Systems Inc.

11

TSI-8

Hardware Design Guide, Revision 1

November 2, 2005

8K x 8K Time-Slot Interchanger

4.4 Recommended Operating Conditions

Recommended conditions apply unless otherwise specified.

Table 4-4. Operating Conditions

Parameter

Supply Voltage (VDD33)

Min

3.14

1.4

Typ

3.3

1.5

—

Max

3.47

1.6

Unit

V

Supply Voltage (VDD15)

Ambient Temperature

V

–40

85

°C

12

Agere Systems Inc.

Hardware Design Guide, Revision 1

November 2, 2005

TSI-8

8K x 8K Time-Slot Interchanger

5 dc Electrical Characteristics

This section describes the static parameters associated with all the ball types used in the TSI-8 device.

Table 5-1. CMOS Inputs

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input Leakage Current

High-Input Voltage

Low-Input Voltage

Input Capacitance

IIL

VIH

VIL

CI

VSS < VIN < VDD33

—

2.0

–0.3

—

1^*

VDD33 + 0.3

0.8

µA

V

—

V

2.5

—

pF

* Excludes current due to pull-up or pull-down resistors.

Table 5-2. CMOS Outputs

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Output Voltage Low

Output Voltage High

Output Current Low

Output Current High

Output Capacitance

HIZ Output Leakage Current

VOL

VOH

IOL

IOL = –10 mA

—

2.4

—

3

0.4

—

V

IOL = 10 mA

V

—

10

—

mA

pF

µA

IOH

CO

IOZ

—

10

Table 5-3. CMOS Bidirectionals (Excluding TXD[31:00])

Parameter

Leakage Current

Symbol

Conditions

Min

Typ

Max

Unit

IL

VSS < VIN < VDD33

—

2.0

–0.3

—

5.0

—

11

µA

V

High-Input Voltage

Low-Input Voltage

Biput Capacitance

Output Voltage Low

Output Voltage High

VIH

VIL

—

VDD33 + 0.3

0.8

—

V

CIB

VOL

VOH

—

pF

V

IOL = –10 mA

IOL = 10 mA

—

0.4

—

2.4

V

Table 5-4. CMOS Bidirectionals (TXD[31:00])

Parameter

Leakage Current

Symbol

Conditions

Min

Max

Unit

IL

VSS < VIN < VDD33

—

10

µA

V

High-Input Voltage

VIH

VIO = 5.0 V

VIO = 3.3 V

2.0

0.5 VDD33

5.5

VDD33 + 0.5

Low-Input Voltage

VIL

VIO = 5.0 V

VIO = 3.3 V

–0.5

0.8

0.3 VDD33

V

Biput Capacitance

Output Voltage Low

CIB

—

10

pF

V

VOL

IOL = 1.5 mA, VIO = 3.3 V

IOL = 6.0 mA, VIO = 5.0 V

—

0.1 VDD33

0.55

Output Voltage High

VOH

IOL = –0.5 mA, VIO = 3.3 V

IOL = –2.0 mA, VIO = 5.0 V

0.9 VDD33

2.4

—

V

Positive-Going Threshold

Negative-Going Threshold

Hysteresis (Vt+ – Vt–)

Vt+

Vt–

—

1.2

0.6

0.4

2.0

1.6

—

V

VHYS

Agere Systems Inc.

13

TSI-8

Hardware Design Guide, Revision 1

November 2, 2005

8K x 8K Time-Slot Interchanger

6 Timing Diagrams and ac Characteristics

Figure 6-1 and Figure 6-2 describe the timing specifications for the input clocks on the TSI-8.

t2

t1

t3

VDD33

VIH

t4

50%

VIL

Figure 6-1. CHICLK Timing Specifications

Table 6-1. CHICLK Timing Specifications

Parameter

Description

CHICLK Rise Time

Min

Typ

Max

Unit

t1

t2

t3

t4

—

48.84

24.42

—

2

—

7

73.24

36.62

7

ns

CHICLK Width (8.192 MHz)*

CHICLK Width (16.384 MHz)*

CHICLK Fall Time

—

2

CHICLK Period (8.192 MHz)

CHICLK Period (16.384 MHz)

—

122.07

61.03

—

* VIH to VIH or VIL to VIL.

t6

t5

t7

VDD33

VIH

t8

50%

VIL

Figure 6-2. MPUCLK Timing Specifications

Table 6-2. MPUCLK Timing Specifications

Parameter

Description

MPUCLK Rise Time

Min

Typ

Max

Unit

t5

t6

t7

t8

—

6.06

—

2

—

2

7

—

7

ns

MPUCLK Width*

MPUCLK Fall Time

MPUCLK Period

15.2

—

* VIH to VIH or VIL to VIL.

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Agere Systems Inc.

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TSI-8

8K x 8K Time-Slot Interchanger

Figure 6-3 shows the ac timing specifications for the CMOS outputs on the device.

80 %

20%

20 %

t9

t10

Figure 6-3. ac Timing Specification

Table 6-3. CMOS Output ac Timing Specification *

Parameter

Description

Min

Typ

Max

Unit

t9

Rise Time (20%—80%)

Fall Time (80%—20%)

—

1.5

7

ns

t10

* Test load = 50 pF (total).

FSYNC

t

13

t

14

CHICLK

t15

t

16

RXD

TXD

t

19

t18

t

17

Note: This figure assumes TSI-8 is programmed to sample FSYNC on rising edge of CHICLK.

Figure 6-4. CHI Interface Timing

Table 6-4. CHI Interface Timing

Parameter

Description

Min

Max

Unit

t13

t14

t15

t16

t17

t18

t19

FSYNC Setup Time to Active CHICLK Edge

FSYNC Hold Time from Active CHICLK Edge

RXD Setup to Active CHICLK Edge

10

5

—

15

12

15

ns

10

5

RXD Hold Time from Active CHICLK Edge

TXD High Z to Data Valid

—

2

TXD Propagation Delay from Active CHICLK Edge

Transmit Data High Impedance*

—

* Applies if Driver_Enable_Control = 01. For Driver_Enable_Control = 11 refer to Figure 6-15 CHI 3-State Output Control on page 21.

Agere Systems Inc.

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TSI-8

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8K x 8K Time-Slot Interchanger

All timing specifications also apply under the following conditions:

If FS is active-low.

If the falling edge of CHICLK is specified as the active edge.

At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of

16.384 MHz or 8.192 MHz.

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ ¾ bit offset

w/ bit offset = 1

w/ 2¾ bit offset

w/ bit offset = 7

TS255 B6 TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

data sampled

TS0 B0

TS0 B1

data sampled

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS255 B6 TS255 B7

TS0 B0

TS0 B1

data sampled

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS255 B5 TS255 B6 TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS0 B3

data sampled

TS0 B0

data sampled

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7

data sampled

TS0 B0

TS0 B1

TS0 B2

TS254 B7 TS255 B0 TS255 B1 TS255 B2 TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7

data sampled

TS0 B 0

TS0 B1

TS0 B0

w/ TS offset = 1,

bit offset = 0

TS254 B6 TS254 B7 TS255 B0 TS255 B1 TS255 B2 TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7

data sampled

w/ TS offset = 13,

bit offset = 3¼

TS242 B3 TS242 B4 TS242 B5 TS242 B6 TS242 B7 TS243 B0 TS243 B1 TS243 B2 TS243 B3 TS243 B4 TS243 B5

data sampled

w/ TS offset = 255,

bit offset = 7¾

TS255 B6 TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS0 B6

TS0 B7

TS1 B0

data sampled

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-5. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

w/ ½ bit offset

w/ bit offset = 1

TS255 B5

TS255 B6

TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS255 B5

TS255 B6

TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS255 B4

TS254 B5

TS255 B5

TS254 B6

TS255 B6

TS254 B7

TS255 B7

TS255 B0

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

w/ TS offset = 1,

bit offset = 0

TS255 B1

TS255 B2

TS255 B3

TS255 B4

TS255 B5

w/ TS offset = 255,

bit offset = 7½

TS255 B6

TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

Notes:

1/4 bit offset not valid with 16 Mbits/s data.

For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and sampled by the rising edge of the CHICLK.

Figure 6-6. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK

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Agere Systems Inc.

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TSI-8

8K x 8K Time-Slot Interchanger

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ ¾ bit offset

w/ bit offset = 1

w/ 2¾ bit offset

w/ bit offset = 7

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

data sampled

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

data sampled

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

data sampled

TS 127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

data sampled

TS0 B0

TS127 B6

TS127 B7

TS0 B1

TS0 B2

TS0 B3

data sampled

TS 127 B4

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

data sampled

TS127 B0

TS126 B7

TS127 B1

TS127 B0

TS127 B2

TS127 B1

TS127 B3

TS127 B2

TS127 B4

TS127 B3

TS127 B5

TS127 B4

data sampled

w/ TS offset = 1,

bit offset = 0

w/ TS offset = 13,

bit offset = 3¼

TS114 B4

TS114 B5

TS114 B6

TS114 B7

TS115 B0

TS115 B1

data sampled

TS0 B1

w/ TS offset = 127,

bit offset = 7¾

TS 127 B7

TS0 B0

TS0 B2

TS0 B3

TS0 B4

data sampled

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-7. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ bit offset = 1

TS 127 B6

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS 127 B5

TS 126 B6

TS127 B6

TS126 B7

TS127 B7

TS127 B0

TS0 B0

TS0 B1

TS0 B2

w/ TS offset = 1,

bit offset = 0

TS127 B1

TS127 B2

TS127 B3

w/ TS offset = 127,

bit offset = 7¾

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-8. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK

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8K x 8K Time-Slot Interchanger

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ ¾ bit offset

w/ bit offset = 1

w/ 2¾ bit offset

w/ bit offset = 7

TS0 B0

TS0 B1

TS0 B2

data sampled

TS0 B0

TS63 B7

TS0 B1

TS0 B2

data sampled

TS63 B7

TS0 B0

TS0 B1

TS0 B2

data sampled

TS0 B0

TS63 B7

TS0 B1

data sampled

TS63 B7

TS0 B0

TS0 B1

data sampled

TS63 B5

TS63 B6

TS63 B7

data sampled

TS63 B1

TS63 B0

TS63 B2

TS63 B1

TS63 B3

TS63 B2

data sampled

w/ TS offset = 1,

bit offset = 0

w/ TS offset = 13,

bit offset = 3¼

TS50 B4

TS50 B5

TS50 B6

TS50 B7

data sampled

TS0 B1

w/ TS offset = 63,

bit offset = 7¾

TS0 B0

TS0 B2

data sampled

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-9. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ bit offset = 1

TS63 B7

TS0 B0

TS0 B1

TS63 B7

TS0 B0

TS0 B1

TS63 B6

TS63 B7

TS0 B0

TS63 B6

TS62 B7

TS63 B7

TS63 B0

TS0 B0

w/ TS offset = 1,

bit offset = 0

TS63 B1

w/ TS offset = 63,

bit offset = 7¾

TS63 B7

TS0 B0

TS0 B1

TS0 B2

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-10. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK

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Agere Systems Inc.

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TSI-8

8K x 8K Time-Slot Interchanger

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ ¾ bit offset

w/ bit offset = 1

w/ 2¾ bit offset

w/ bit offset = 7

TS0 B0

TS0 B1

data sampled

TS0 B0

data sampled

TS0 B0

TS31 B7

data sampled

TS31 B7

TS31 B5

TS0 B0

TS0

data sampled

TS31 B7

TS0 B0

data sampled

TS31 B6

TS31

TS31 B1

TS31 B0

TS31 B2

TS31 B1

w/ TS offset = 1,

bit offset = 0

data sampled

TS18 B5

w/ TS offset = 13,

bit offset = 3¼

TS18 B6

data sampled

w/ TS offset = 31,

bit offset = 7¾

TS0 B0

TS0 B1

TS0

data sampled

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-11. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ bit offset = 1

TS31 B7

TS0 B0

TS0 B1

TS31 B7

TS0 B0

TS31 B7

TS0 B0

TS31 B6

TS30 B7

TS31 B7

TS31 B0

TS0 B0

w/ TS offset = 1,

bit offset = 0

TS31 B01

w/ TS offset = 31,

bit offset = 7¾

TS31 B7

TS0 B0

TS0 B1

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-12. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK

Agere Systems Inc.

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8K x 8K Time-Slot Interchanger

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ ¾ bit offset

w/ bit offset = 1

w/ 2¾ bit offset

w/ bit offset = 7

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

data sampled

TS127 B6

TS127 B7

TS0 B0

TS0 B1

data sampled

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

data sampled

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

data sampled

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

data sampled

TS127 B3

TS127 B4

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

data sampled

TS126 B7

TS126 B6

TS127 B0

TS126 B7

TS127 B1

TS127 B2

TS127 B3

TS127 B2

TS127 B4

TS127 B3

TS127 B5

TS127 B4

TS127 B6

TS127 B5

TS127 B7

TS0 B 0

TS0 B1

TS0 B0

data sampled

w/ TS offset = 1,

bit offset = 0

TS127 B0

TS127 B1

TS127 B6

TS127 B7

data sampled

w/ TS offset = 13,

bit offset = 3¼

TS114 B3

TS114 B4

TS114 B5

TS114 B6

TS114 B7

TS115 B0

TS115 B1

TS115 B2

TS115 B3

TS115 B4

TS115 B5

data sampled

w/ TS offset = 127,

bit offset = 7¾

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS0 B6

TS0 B7

TS1 B0

data sampled

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-13. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

w/ ½ bit offset

w/ bit offset = 1

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS127 B4

TS126 B5

TS127 B5

TS126 B6

TS127 B6

TS126 B7

TS127 B7

TS127 B0

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

w/ TS offset = 1,

bit offset = 0

TS127 B1

TS127 B2

TS127 B3

TS127 B4

TS127 B5

w/ TS offset = 127,

bit offset = 7½

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

Notes:

1/4 bit offset not valid with 8 MHz data and 8 MHz clock.

For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-14. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK

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Agere Systems Inc.

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TSI-8

8K x 8K Time-Slot Interchanger

CHICLK

16.384 MHz

t

20

TXD

16.384 Mbits/s

CHICLK

8.192 MHz

t

21

TXD

8.192 Mbits/s

CHICLK

8.192 MHz

t

22

TXD

8.192 Mbits/s

Figure 6-15. CHI 3-State Output Control

Table 6-5. CHI 3-State Output Control

Control in the table below refers to bits [6:4] in the Transmit_CHI_Global_Configuration register (0x0C84). This only applies

if bits 13 and 12 of the corresponding Transmit_CHI_Control register (0x0C00—0x0C3E) are set to 11. See the TSI-8 Reg-

ister Description document.

*

Parameter Control

Reference Point

After Previous Like Edge in 16 MHz

Min

Max^*

Unit

t20

t21

t22

000

001

010

011

000

001

010

011

100

101

110

111

50

44

38

32

50

44

38

32

111

105

99

93

59

53

ns

After Previous Like Edge in 16 MHz

47

After Previous Like Edge in 16 MHz

41

After Previous Opposite Edge in 8 MHz

After Previous Like Edge (8 MHz mode only)

59

53

47

41

120

114

108

102

* Like edge is the reference edge (rising or falling) as defined by the Transmit_Clock_Edge bit in the Transmit_CHI_Global_Configuration (0x0C84) regis-

ter. See the TSI-8 Register Description document for further details.

Agere Systems Inc.

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Hardware Design Guide, Revision 1

November 2, 2005

8K x 8K Time-Slot Interchanger

MPUCLK

t

23

t

24

ADDR[15:00]

CS

t26

t

25

t

27

AS

t

28

t

30

t

29

R/W

t

32

t

31

t

33

DATA[15:00]

PAR[1:0]

t

35

t

35

t

36

t

34

DT

Figure 6-16. Microprocessor Port Timing—Read Cycle

Table 6-6. Microprocessor Port Timing—Read Cycle

Parameter

Description

Min

Max

Unit

t23

t24

t25

t26

t27

Address Setup

Address Hold

5

1

—

ns

Chip Select Setup

Chip Select Hold

5

1

5

1

—

ns

Address Strobe Setup

Address Strobe Hold

t28

t29

t30

t31

t32

t33

R/W Setup

5

1

—

15

7

ns

R/W Hold

Data Output Enable

Data Clock to Valid

Data High-Impedance

—

1

—

1

8

DT High-Impedance to Valid

DT Clock to Out

15

t34

t35

t36

1

7

8

ns

DT Valid to High-Impedance

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Agere Systems Inc.

Hardware Design Guide, Revision 1

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TSI-8

8K x 8K Time-Slot Interchanger

MPUCLK

t

37

t

38

ADDR[15:00]

CS

t

40

t

39

t

41

AS

t

42

t

44

t

43

R/W

t

46

t

45

DATA[15:00]

PAR[1:0]

t

48

t

48

t

49

t

47

DT

Figure 6-17. Microprocessor Port Timing—Write Cycle

Table 6-7. Microprocessor Port Timing—Write Cycle

Parameter

Description

Min

Max

Unit

t37

t38

t39

t40

t41

Address Setup

Address Hold

5

1

—

ns

Chip Select Setup

Chip Select Hold

5

1

5

1

—

ns

Address Strobe Setup

Address Strobe Hold

t42

t43

t44

R/W Setup

R/W Hold

Data Setup

5

1

5

—

ns

t45

t46

t47

t48

t49

Data Hold

1

—

15

7

ns

DT High-Impedance to Valid

DT Clock to Out

DT Valid to High-Impedance

8

Note: Posted writes follow the same timing shown in Figure 6-17 and Table 6-7. A posted write may return a DT prior to the

device completing the write cycle. This allows the microprocessor to continue operation while the TSI-8 completes the

write.

Agere Systems Inc.

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TSI-8

Hardware Design Guide, Revision 1

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8K x 8K Time-Slot Interchanger

7 Outline Diagrams

Dimensions are in millimeters.

TOP VIEW

19.00

SQUARE

+0.70

17.70

1.75 TYP.

–0.05

A1 INDICATOR

(PLATED)

SQUARE

USE OF EJECTOR

PINS IS OPTIONAL

4.00 x 45° APPROX

TYP 4 CORNERS

1.20 x 45° APPROX

TYP 3 PLACES

30°

APPROX

ALL SIDES

0.80 ± 0.050

0.35

Z

0.50 R MAX

ALL EDGES

0.20

Z

0.10

Z

SEATING PLANE

0.56 ± 0.06

1.86 ± 0.21

0.50 ± 0.10

17

15

13

11

A1 INDICATOR

(UNDER SOLDER MASK)

18

16

14

12

10 9 1

8

7 5 3 2

6 4

A

B

C

D

E

1.00

TYP

F

G

H

J

K

L

0.50

M

N

P

R

T

U

V

CENTER ARRAY

FOR THERMAL

ENHANCEMENT

+0.07

–0.13

0.63

DIA

BOTTOM VIEW

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Agere Systems Inc.

Hardware Design Guide, Revision 1

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TSI-8

8K x 8K Time-Slot Interchanger

8 Ordering Information

Table 8-1. Ordering Information

Device

Part Number

Ball Count

Package

Comcode

TSI-8

TTSI008321BL-2-DB

L-TTSI008321BL-2-DB

240

PBGAM1

700046829

700078759*

* Pb-free/RoHS.

9 Change History

On page 1, updated Figure 2-1.

On page 15, deleted 2 sentences at the beginning of the page. (All timing parameters are referenced to VIHmin and VILmax.

The reference signal polarity may be inverted for some timing parameters.)

On page 15, updated Figure 6-3, ac Timing Specification.

On page 15, updated Table 6-3. CMOS Output ac Timing Specification * .

On page 15, under Table 6-4 eliminated the following sentence: All timing specifications are with respect to VIHmin and

VILmax as shown in Figure 5.

On page 21, deleted footnote † under Table 6-5 and clarified the remaining footnote.

On page 22, deleted the footnote under Table 6-6.

On page 23, deleted the footnote under Table 6-7.

On page 26, changed the part numbers.

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November 2, 2005

DS02-122SWCH-1 (Replaces DS02-122SWCH)


型号：	TSI-8
厂家：	AGERE SYSTEMS
描述：	8K x 8K Time-Slot Interchanger 8K x 8K的时间时隙交换器
文件：	总25页 (文件大小：674K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TSI-8 [AGERE]

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