LUCL9214GAJ-D_技术文档

Preliminary Data Sheet

October 2001

L9214A/G

Low-Cost Ringing SLIC

Applications

Introduction

■ Voice over Internet Protocol (VoIP)

■ Cable Modems

The Agere Systems Inc. L9214 is a subscriber line

interface circuit that is optimized to provide a very

low-cost solution for short- and medium-loop applica-

tions. This device provides the complete set of line

interface functionality, including power ringing

needed to interface to a subscriber loop. This device

has the capability to operate with a V^CCsupply of

3.3 V or 5 V and is designed to minimize external

components required at all device interfaces.

■ Terminal Adapters (TA)

■ Wireless Local Loop (WLL)

■ Telcordia Technologies™ GR-909 Access

■ Network Termination (NT)

■ PBX

■ Key Systems

Features

■ Low-cost solution

Description

■ Onboard ringing generation with software adjust-

able crest factor switching

This device is optimized to provide battery feed, ring-

ing, and supervision on short- and medium-loop plain

old telephone service (POTS) loops. Supported

round trip loop length is up to 1000 Ω.

■ Flexible VCC options:

— 3.3 V or 5 V V^CC

— No –5 V required

This device provides power ring to the subscriber by

the use of line reversal to create either a sine wave

ringing signal with a PWM input or a trapezoidal ring-

ing signal with a selectable crest factor from a square

wave input. It provides forward and reverse battery

feed states, on-hook transmission, a low-power scan

state, and a forward disconnect state.

■ Power control options:

— Power control resistor

— Automatic battery switch to minimize off-hook

power

■ Eight operating states:

— Scan mode for minimal power dissipation

— Forward and reverse battery active

— On-hook transmission states

— Ring mode

The device requires a V^CCand line feed battery to

operate. V^CCmay be either a 3.3 V or a 5 V supply.

The ringing signal is derived from the high-voltage

battery. An automatic battery switch is included to

allow for use of a second lower voltage battery in the

off-hook mode, thus minimizing short-loop off-hook

power consumption and dissipation. If the user

desires single battery operation, a power resistor is

required to reduce the power dissipation in the SLIC.

— Disconnect mode

■ Low on-hook power:

— 25 mW scan mode

— 165 mW active mode

■ Two SLIC gain options to minimize external com-

ponents in codec interface

Loop closure, ring trip, and ground key detectors are

available. The loop closure detector has a fixed

threshold with hysteresis. The ring trip detector and

ground key detector threshold and time constants are

externally set.

■ Loop start, ring trip, and ground key detectors

■ Programmable current limit

■ On-hook and scan mode line voltage clamp

■ Thermal protection

The dc current limit is programmed by an external

resistor, the maximum current limit determined by the

Vcc supply.

■ 48-pin MLCC, 32-pin PLCC, and 28-pin SOG

(Please contact your Agere Sales Representative

for availability) packages

The overhead voltage for this device is fixed and the

device is capable of supporting 3.17 dB into a 600 Ω

load with minimal overhead.

The device is offered with two gain options. This

allows for an optimized codec interface, with minimal

external components regardless of whether a first-

generation or a programmable third-generation

codec is used.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Table of Contents

Contents

Page

Contents

Page

Introduction..................................................................1

Features....................................................................1

Applications...............................................................1

Description................................................................1

Features ......................................................................4

Description...................................................................4

Architecture Diagram...................................................7

Pin Information ............................................................8

Operating States........................................................12

State Definitions ........................................................12

Forward Active (Fast Polarity Reversal) .................12

Off-hook................................................................12

On-hook................................................................12

Forward Active (Slow Polarity Reversal).................12

Off-hook................................................................12

On-hook................................................................12

Reverse Active (Fast Polarity Reversal) .................13

Off-hook................................................................13

On-hook................................................................13

Reverse Active (Slow Polarity Reversal) ................13

Off-hook................................................................13

On-hook................................................................13

Scan........................................................................13

Disconnect ..............................................................13

Ring.........................................................................13

Thermal Shutdown..................................................13

Absolute Maximum Ratings.......................................14

Electrical Characteristics ...........................................15

Test Configurations ...................................................22

Applications ...............................................................24

Power Control .........................................................24

dc Loop Current Limit..............................................25

Overhead Voltage...................................................25

Active Mode .........................................................25

Scan Mode ...........................................................25

On-Hook Transmission Mode...............................25

Ring Mode............................................................26

Loop Range ........................................................... 26

Battery Reversal Rate............................................ 26

Supervision............................................................... 27

Loop Closure.......................................................... 27

Ring Trip ................................................................ 27

Tip or Ring Ground Detector.................................. 27

Power Ring ............................................................ 27

Periodic Pulse Metering (PPM) ................................ 29

ac Applications ......................................................... 29

ac Parameters........................................................ 29

Codec Types.......................................................... 29

First-Generation Codecs ..................................... 29

Third-Generation Codecs.................................... 29

ac Interface Network .............................................. 29

Design Examples................................................... 30

First-Generation Codec ac Interface

Network—Resistive Termination ...................... 30

Example 1, Real Termination.............................. 31

First-Generation Codec ac Interface

Network—Complex Termination....................... 34

Complex Termination Impedance Design

Example............................................................ 34

ac Interface Using First-Generation Codec......... 33

Transmit Gain...................................................... 35

Receive Gain....................................................... 36

Hybrid Balance.................................................... 36

Blocking Capacitors............................................. 37

Third-Generation Codec ac Interface

Network—Complex Termination....................... 40

Outline Diagram........................................................ 41

28-Pin SOG............................................................ 42

32-Pin PLCC .......................................................... 43

48-Pin MLCC.......................................................... 44

48-Pin MLCC, JEDEC MO-220 VKKD-2................ 45

Ordering Information................................................. 46

2

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Table of Contents (continued)

Page Tables

Figures

Page

Figure 1. Architecture Diagram ...................................7

Figure 2. 28-Pin SOG Diagram ..................................8

Figure 3. 32-Pin PLCC Diagram .................................8

Figure 4. 48-Pin MLCC Diagram .................................9

Figure 5. Basic Test Circuit (3 REN Configuration) ..22

Figure 6. Metallic PSRR ...........................................23

Figure 7. Longitudinal PSRR ....................................23

Figure 8. Longitudinal Balance .................................23

Figure 9. ac Gains ....................................................23

Figure 10. Ringing Waveform Crest Factor = 1.6 .....27

Figure 11. Ringing Waveform Crest Factor = 1.2 .....27

Figure 12. Ring Operation ........................................28

Figure 13. ac Equivalent Circuit ................................31

Figure 14. Agere T7504 First-Generation Codec;

Resistive Termination (5 REN

Table 1. Pin Descriptions ......................................... 10

Table 2. Control States ............................................ 12

Table 3. Typical Operating Characteristics .............. 14

Table 4. Thermal Characteristics.............................. 14

Table 5. Environmental Characteristics ................... 15

Table 6. 5.0 V Supply Currents ............................... 15

Table 7. 5. 0 V Powering .......................................... 15

Table 8. 3.3 V Supply Currents ................................ 16

Table 9. 3.3 V Powering .......................................... 16

Table 10. Two-Wire Port .......................................... 17

Table 11. Analog Pin Characteristics ...................... 18

Table 12. ac Feed Characteristics ........................... 19

Table 13. Logic Inputs and Outputs

(V^CC= 5.0 V) .............................................. 20

Table 14. Logic Inputs and Outputs

Configuration)...........................................32

Figure 15. Interface Circuit Using First-Generation

Codec (Blocking Capacitors

Not Shown) ..............................................35

Figure 16. ac Interface Using First-Generation

Codec (Including Blocking Capacitors)

(V^CC= 3.3 V) ............................................ 20

Table 15. Ringing Specifications ............................. 20

Table 16. Ring Trip (3 REN Configuration) .............. 21

Table 17. Ring Trip (5 REN Configuration)............... 21

Table 18. Typical Active Mode On- to Off-Hook

Tip/Ring Current-Limit Transient

for Complex Termination Impedance ......37

Figure 17. Agere T7504 First-Generation Codec;

Complex Termination with Power Control

Resistor (3 REN Configuration)................38

Figure 18. Third-Generation Codec ac Interface

Network; Complex Termination (3 REN

Response ................................................ 25

Table 19. FB1/FB2 Values vs. Typical Ramp Time

at V^BAT1= –65 V ....................................... 26

Table 20. L9214 Parts List for Agere T7504

First-Generation Codec; Resistive

Termination .............................................. 33

Table 21. L9214 Parts List for Agere T7504 First-

Generation Codec; Complex Termination

Configuration)...........................................40

with Power Control Resistor .................... 38

Table 22. L9214 Parts List for Agere T8536

Third-Generation Codec Meter Pulse

Application ac and dc Parameters;

Fully Programmable ................................ 41

Agere Systems Inc.

3

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

■ Overhead voltage:

— Automatically adjusted in active mode

Features

— Clamped <56.5 V in scan and on-hook modes

■ Onboard balanced trapezoidal ringing generation,

40 Vrms, 1.2 crest factor:

■ Thermal shutdown protection with hysteresis

— 3 REN ring load (2330 Ω + 24 µF), 600 Ω loop

— 2 REN ring load (3500 Ω + 16 µF), 1000 Ω loop

— 2 REN ring load (3500 Ω + 1.8 µF), 500 Ω loop

— No ring relay

■ Longitudinal balance:

— ETSI/ITU-T balance

— GR-909

— No bulk ring generator required

— 15 Hz to 70 Hz ring frequency supported

■ Meter pulse compatible

■ ac interface:

■ Power supplies requirements:

— V^CCtalk battery and ringing battery required

— No –5 V supply required

— Two SLIC gain options to minimize external com-

ponents required for interface to first- or third-gen-

eration codecs

— Sufficient dynamic range for direct coupling to

codec output

— No high-voltage positive supply required

■ Flexible Vcc options:

— 3.3 V or 5 V V^CCoperation

— 3.3 V or 5 V V^CCinterchangeable and transparent

to users

■ 28-pin SOG, 32-pin PLCC, and 48-pin MLCC pack-

age options

■ 90 V CBIC-S technology

■ Power control options:

— Automatic battery switch

— Power control resistor

Description

■ Minimal external components required

The L9214 is designed to provide battery feed, ringing,

and supervision functions on short and medium plain

old telephone service (POTS) loops. Supported round-

trip loop length is up to 1000 Ω of wiring resistance plus

handset or ringing load. This device is designed to min-

imize power in all operating states.

■ Ten operating states:

— Forward active, fast polarity reversal

— Reverse active, fast polarity reversal

— Forward active, slow polarity reversal

— Reverse active, slow polarity reversal

— Scan

The L9214 offers eight operating states. The device

assumes use of a lower-voltage talk battery, a higher-

voltage ringing battery and a single V^CCsupply.

— Disconnect

— Ringing, line forward with high slope

— Ringing, line reverse with high slope

— Ringing, line forward with low slope

— Ringing, line reverse with low slope

The L9214 requires only a positive V^CCsupply. No

–5 V supply is needed. The L9214 can operate with a

V^CCof either 5.0 V or 3.3 V, allowing for greater user

flexibility. The choice of V^CCvoltage is transparent to

the user; the device will function with either supply volt-

age connected.

■ Unlatched parallel data control interface

■ Low SLIC power:

— Scan 24 mW (V^CC= 5.0 V)

— Forward/reverse active 148 mW (V^CC= 5.0 V)

— Scan 17 mW (V^CC= 3.3 V)

Two batteries may be used:

— Forward/reverse on-hook 135 mW (V^CC= 3.3 V)

1. A high-voltage ring battery (V^BAT1). VBAT1 is a maxi-

mum –70 V and is used for power ringing, scan, and

on-hook transmission modes. This supply is current

limited to the maximum power ringing current of

approximately 90 mApeak.

■ Supervision:

— Loop start, fixed threshold with hysteresis

— Ring trip filtering, fixed threshold not a function of

battery voltage, user adjustable with an external

resistor

— Common-mode current for ground key applica-

tions, user-adjustable threshold

2. A lower-voltage talk battery (V^BAT2). VBAT2 is nor-

mally used for active mode powering.

Alternatively, operation may be from a single high-volt-

age battery supply with a power control resistor to

reduce the power dissipation in the SLIC.

■ Adjustable current limit:

— 10 mA to 45 mA programming range at 5 V Vcc

— 10 mA to 35 mA programming range at 3.3 V Vcc

4

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

halted to enable on-hook transmission. The ring trip

detector and common-mode current detector are active

during the ring mode. The user may adjust the crest

factor of the ring signal by selecting one of the two slew

rates. The two rates, high or low, allow the designer to

chose one set of external capacitors to meet the crest

factor range of 1.2 to 1.6 over a 3:1 frequency range by

software control alone. For increased power efficiency,

the crest factor should be kept as low as possible.

Description (continued)

Forward and reverse battery active modes are used for

off-hook conditions. Since this device is designed for

short- and medium-loop applications, the lower-voltage

V^BAT2is normally applied during the forward and

reverse active states. Battery reversal is quiet, without

breaking the ac path. The rate of battery reversal may

be ramped to control switching time.

With maximum V^BAT1, the L9214 has sufficient power to

ring a 3 REN (2310 Ω + 24 µF) ringing load into 600 Ω

of physical wiring resistance. With maximum V^BAT1, the

L9214 has sufficient power to ring a 2 REN (3500 Ω +

16 µF) ringing load into <1000 Ω of physical wiring

resistance. Loop ranges may be expanded by applying

a lower crest factor trapezoidal input waveform.

The magnitude of the overhead voltage in the forward

and reverse active modes allows for an undistorted sig-

nal of 3.17 dBm into 600 Ω. The ring trip detector is

turned off during active modes to conserve power.

On-hook transmission is not permitted in the scan

mode. In this mode, the tip ring voltage is derived from

the higher V^BAT1rather than VBAT2.

This feature eliminates the need for a separate external

ring relay, associated external circuitry, and a bulk ring-

ing generator. See the Applications section of this data

sheet for more information.

In the scan and active modes, the overhead voltage is

set such that the tip/ring open loop voltage is 42.5 V

minimum for a primary battery of 63 V to 70 V for com-

patibility with maintenance termination units (MTUs).

Also, the maximum voltage with respect to ground

(tip or ring to ground) is 56.5 V to comply with UL™

1950/60950 ANNEX M.2 method B and IEC^®60950

(quiet interval of ringing). If the primary battery is below

–63 V, the magnitude of the tip/ring open circuit voltage

is approximately 17 V less than the battery.

Where PPM is required, it is injected into the audio

receive pins (ac-coupled). PPM shaping must be

done externally and the PPM level must be within the

1.12 Vrms (3.17 dBm, 600 Ω) level set by the amplifier

overhead in the active state.

Both the ring trip and loop closure supervision func-

tions are included. The loop closure has a fixed typical

10 mA on- to off-hook threshold in the active and scan

mode. In either case, there is a 2 mA hysteresis. The

ring trip detector requires a simple filter at the input.

The ring trip threshold internally at a given battery volt-

age is fixed, but the threshold can be adjusted through

an external voltage divider. Typical ring trip threshold is

20.1 mA for a –65 V V^BAT1.

To minimize on-hook power, a low-power scan mode is

available. In this mode, all functions except off-hook

supervision are turned off to conserve power. On-hook

transmission is not allowed in the scan mode.

A forward disconnect mode is provided, where all cir-

cuits are turned off and power is denied to the loop.

The device offers a ring mode, in which a power ring

signal is provided to the tip/ring pair. During the ring

mode, the user, by use of the input states, performs

line reversals at the required frequency, which gener-

ates the power ringing signal. This signal may be

applied continuously but is normally cadenced to meet

country-specific requirements. The input states are

normally set to an active state when power ringing is

A common-mode current detector for tip or ring ground

detection is included for ground key applications. The

threshold is user programmable via external resistors.

See the Applications section of this data sheet for more

information on supervision functions.

Agere Systems Inc.

5

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

A receive gain of 2 is more appropriate when choosing

a third-generation type codec. Third-generation codecs

will synthesize termination impedance and set hybrid

balance and overall gains. To accomplish these func-

tions, third-generation codecs typically have both ana-

log and digital gain filters. For optimal signal to noise

performance, it is best to operate the codec at a higher

gain level. If the SLIC then provides a high gain, the

SLIC output may be saturated causing clipping distor-

tion of the signal at tip and ring. To avoid this situation,

with a higher gain SLIC, external resistor dividers are

used. These external components are not necessary

with the lower gain offered by the L9214. See the Appli-

cations section of this data sheet for more information.

Description (continued)

Longitudinal balance is consistent with European ETSI

and North American GR-909 requirements. Specifica-

tions are given in Table 10.

Data control is via a parallel unlatched control scheme.

The dc current limit is programmable in the active

modes by use of an external resistor connected

between DCOUT and I^PROG. Design equations for this

feature are given in the dc Loop Current Limit section

within the Applications section of this data sheet.

Programming range is 15 mA to 45 mA with V^CC=

5.0 V and 15 mA to 35 mA with V^CC= 3.3 V. Program-

ming accuracy is ±10% over this current range.

The L9214 is internally referenced to 1.5 V. The SLIC

output VITR is referenced to AGND; therefore, it must

be ac-coupled to the codec input. However, the SLIC

inputs RCVP/RCVN are floating inputs. If there is not

feedback from RCVP/RCVN to VITR, RCVP/RCVN

may be directly coupled to the codec output. If there is

feedback from RCVP/RCVN to VITR, RCVP/RCVN

must be ac coupled to the codec output.

Circuitry is added to the L9214 to minimize the inrush

of current from the V^CCsupply and to the battery supply

during an on- to off-hook transition, thus saving in

power supply design cost. See the Applications section

of this data sheet for more information.

Transmit and receive gains have been chosen to mini-

mize the number of external components required in

the SLIC-codec ac interface, regardless of the choice

of codec.

The L9214 is thermally protected to guard against

faults. Upon reaching the thermal shutdown tempera-

ture, the device will enter an all-off mode. Upon cool-

ing, the device will re-enter the state it was in prior to

thermal shutdown. Hysteresis is built in to prevent

oscillation.

The L9214 uses a voltage feed-current sense architec-

ture; thus, the transmit gain is a transconductance. The

L9214 transconductance is set via a single external

resistor, and this device is designed for optimal perfor-

mance with a transconductance set at 300 V/A.

The L9214 is packaged in the 28-pin SOG, 32-pin

PLCC and 48-pin MLCC surface-mount packages. The

L9214A is set for gain of eight applications, and the

L9214G is set for gain of two applications.

The L9214 offers an option for a single-ended to differ-

ential receive gain of either 8 or 2. These options are

mask programmable at the factory and are selected by

choice of product code.

A receive gain of 8 is more appropriate when choosing

a first-generation type codec where termination imped-

ance, hybrid balance, and overall gains are set by

external analog filters. The higher gain is typically

required for synthesization of complex termination

impedance.

6

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Architecture Diagram

AGND VCC BGND VBAT2 VBAT1

IPROG

NSTAT

RTFLT DCOUT

IREF

CURRENT

LIMIT

RING

TRIP

AND

VITR

POWER/BATTERY SWITCH

INRUSH

CONTROL

X20

LOOP

CLOSURE

AAC

REFERENCE

CIRCUIT

COMMON-

MODE

CURRENT

DETECTOR

ICM

TXI

ITR

VTX

RECTIFIER

X1

TRGDET

–

(ITR/308)

VREF

VTX

AX

CF2

+

–

RFT

PT

18 Ω

X1

ITR

+

CF1

FB2

FB1

VBAT1 VBAT2

TIP/RING

CURRENT

SENSE

–

RCVN

RCVP

ITR

+

–

GAIN

RFR

PR

+

18 Ω

ac INTERFACE

9214A GAIN = 4

9214G GAIN = 1

VBAT1 VBAT2

PARALLEL

DATA

INTERFACE

B0 B1 B2 B3

12-3530.C (F)

Figure 1. Architecture Diagram

Agere Systems Inc.

7

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Pin Information

NSTAT

VITR

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

TXI

2

VTX

ITR

RCVP

RCVN

DCOUT

IPROG

CF2

3

4

B0

5

B1

6

B2

7

B3

L9214

28-PIN SOG

CF1

8

PR

RTFLT

IREF

9

PT

10

11

12

13

14

FB1

FB2

ICM

TRGDET

BGND

AGND

VCC

VBAT1

VBAT2

12-3568 (F)

Figure 2. 28-Pin SOG Diagram

4

3

2

1

32

31

30

RCVN

5

29

28

27

26

25

24

B0

B1

B2

B3

PR

PT

NC

6

7

8

9

NC

L9214

DCOUT

32-PIN PLCC

I^PROG

CF2

10

11

12

13

23

22

21

FB1

FB2

ICM

CF1

RTFLT

14

15

16

17

18

19

20

Figure 3. 32-Pin PLCC Diagram

8

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Pin Information (continued)

48 47 46 45 44 43 42 41 40 39 38 37

1

36

35

34

33

32

31

30

29

28

27

26

25

B0

B1

B2

B3

NC

2

NC

3

4

5

NC

PR

NC

PT

NC

DCOUT

6

L9214A/G

48-PIN MLCC

7

I

PROG

NC

8

9

NC

FB1

FB2

CF2

CF1

NC

10

11

12

RTFLT

13 14 15 16 17 18 19 20 21 22 23 24

12-3361f(F)

Figure 4. 48-Pin MLCC Diagram

Agere Systems Inc.

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L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Pin Information (continued)

Table 1. Pin Descriptions

28-Pin 32-Pin

48-Pin

MLCC

Symbol

Type

Name/Function

SOG

PLCC

1

43

NSTAT

O

Loop Closure Detector Output—Ring Trip Detector

Output. When low, this logic output indicates that an off-

hook condition exists or ringing is tripped.

—

5, 14, 18,

28, 32, 39,

42, 44

NC

—

No Connection. May be used as a tie point.

2, 6, 7, 8 1—4, 8,

11, 17, 21,

27, 30, 37,

46

No Connection. May not be used as a tie point.

2

3

4

5

3

4

5

9

45

47

48

6

VITR

RCVP

RCVN

DCOUT

O

I

Transmit ac Output Voltage. Output of internal AAC

amplifier. This output is a voltage that is directly propor-

tional to the differential ac tip/ring current.

Receive ac Signal Input (Noninverting). This high-

impedance input controls to ac differential voltage on tip

and ring. This node is a floating input.

I

Receive ac Signal Input (Inverting). This high-imped-

ance input controls to ac differential voltage on tip and

ring. This node is a floating input.

O

dc Output Voltage. This output is a voltage that is

directly proportional to the absolute value of the differen-

tial tip/ring current. This is used to set the dc current limit

and the ring trip threshold.

6

10

7

I^PROG

I

Current-Limit Program Input. A resistor is connected

from this pin to DCOUT to program the dc current limit for

the device.

7

8

9

11

12

13

9

CF2

CF1

—

Filter Capacitor. Connect a capacitor from this node to

ground.

10

12

Filter Capacitor. Connect a capacitor from this node to

CF2.

RTFLT

Ring Trip Filter. Connect this lead to DCOUT via a resis-

tor and to AGND with a capacitor or a resistor capacitor

combination, depending on the ringing type, to filter the

ring trip circuit to prevent spurious responses.

10

14

13

I^REF

I

SLIC Internal Reference Current. Connect a resistor

between this pin and AGND to generate an internal refer-

ence current.

11

12

15

16

15

16

AGND

V^CC

GND Analog Signal Ground.

PWR Analog Power Supply. User choice of 5 V or 3.3 V nom-

inal power supply.

13

14

17

18

19

20

V^BAT1

V^BAT2

PWR Battery Supply 1. High-voltage battery.

PWR Battery Supply 2. Low-voltage battery or power control

resistor.

15

19

22

BGND

GND Battery Ground. Ground return for the battery supplies.

10

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Pin Information (continued)

Table 1. Pin Descriptions (continued)

28-Pin 32-Pin

48-Pin

MLCC

Symbol

Type

Name/Function

SOG

PLCC

16

20

23

24

25

26

TRGDET

O

Tip/Ring Ground Detect. When high, this open collector

output indicates the presence of a ring ground or a tip

ground. This supervision output may be used in ground

key or common-mode fault detection applications.

17

18

19

21

22

23

ICM

FB2

FB1

I

Common-Mode Current Sense. To program tip or ring

ground sense threshold, connect a resistor to V^CCand

connect a capacitor to AGND to filter 50/60 Hz. If unused,

the pin is connected to ground.

—

Polarity Reversal Slowdown Capacitor. Connect a

capacitor from this node for controlling rate of battery

reversal. Also used for ringing, this pin cannot be left

open.

Polarity Reversal Slowdown Capacitor. Connect a

capacitor from this node for controlling rate of battery

reversal. Also used for ringing, this pin cannot be left

open.

20

21

24

25

29

31

PT

I/O

Protected Tip. The input to the loop sensing circuit and

output drive of the tip amplifier. Connect to loop through

overvoltage and overcurrent protection.

PR

Protected Ring. The input to the loop sensing circuit and

output drive of the ring amplifier. Connect to loop through

overvoltage and overcurrent protection.

22

23

24

25

26

27

28

29

30

33

34

35

36

38

B3

B2

B1

B0

ITR

I

State Control Input.

Transmit Gain. Input to AX amplifier. Connect a resistor

from this node to VTX to set transmit gain. Gain shaping

for termination impedance with a COMBO I codec is also

achieved with a network from this node to VTX.

27

28

31

32

40

41

VTX

TXI

O

I

ac/dc Output Voltage. Output of internal AX amplifier.

The voltage at this pin is directly proportional to the differ-

ential tip/ring current.

ac/dc Separation. Input to internal AAC amplifier. Con-

nect a 0.1 µF capacitor from this pin to VTX.

Agere Systems Inc.

11

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Operating States

Table 2. Control States

B3

0

1

B2

0

1

0

1

B1

0

1

0

1

0

1

0

1

B0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

State

Disconnect

Ringing, (line reverse with high slope)

Unused*

Ringing, (line forward with high slope)

Disconnect

Reverse active and on-hook, fast polarity reversal

Scan

Forward active and on-hook, fast polarity reversal

Disconnect

Ringing, (line reverse with low slope)

Unused*

Ringing, (line forward with low slope)

Disconnect

Reverse active and on-hook, slow polarity reversal

Scan

Forward active and on-hook, slow polarity reversal

* In this state, all supervision functions are disabled, on hook transmission is disabled, pin PT is positive with respect to PR, VBAT1 is applied to

tip/ring, and the tip to ring voltage will be equivalent to the scan state.

■ Loop closure and common-mode detect are active.

State Definitions

■ Ring trip detector is turned off to conserve power.

Forward Active (Fast Polarity Reversal)

■ On-hook transmission is enabled.

Off-hook

■ Overhead is set to nominal 17.0 V for undistorted

transmission of 0 dBm into 600 Ω.

■ Pin PT is positive with respect to PR.

■ VBAT2 is applied to tip/ring drive amplifiers for the

majority of loop lengths. This may also be derived

from V^BAT1through a power control resistor.

Forward Active (Slow Polarity Reversal)

Off-hook

■ Loop closure and common-mode detect are active.

■ Ring trip detector is turned off to conserve power.

■ Same as the forward active (fast polarity reversal)

state, but with slower polarity reversal.

■ Overhead is set for undistorted transmission of

+3.17 dBm into 600 Ω.

On-hook

■ Same as the forward active (fast polarity reversal)

state, but with slower polarity reversal.

■ Pin PT is positive with respect to PR.

■ VBAT1 is applied to tip/ring drive amplifiers. The tip to

ring on-hook differential voltage will be between

–42.5 V and –56.5 V with a primary battery of –65 V.

12

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Scan

State Definitions (continued)

■ Except for loop closure, all circuits (including ring trip

and common-mode detector) are powered down.

Reverse Active (Fast Polarity Reversal)

Off-hook

■ On-hook transmission is disabled.

■ Pin PT is positive with respect to PR, and VBAT1 is

applied to tip/ring.

■ Pin PR is positive with respect to PT.

■ VBAT2 is applied to tip/ring drive amplifiers via the soft

battery switch for the majority of loop lengths. This

may also be derived from V^BAT1through a power

control resistor.

■ The tip to ring on-hook differential voltage will be

between –42.5 V and –56.5 V with a –65 V primary

battery.

■ Loop closure and common-mode detect are active.

■ Ring trip detector is turned off to conserve power.

Disconnect

■ Overhead is set to nominal 4.0 V for undistorted

transmission of 0 dBm into 600 Ω and may be

increased automatically for larger signal levels.

■ The tip/ring amplifiers and all supervision are turned

off.

■ The SLIC goes into a high-impedance state.

■ NSTAT is forced high (on-hook).

On-hook

■ Pin PR is positive with respect to PT.

Ring

■ VBAT1 is applied to tip/ring drive amplifiers. The tip to

ring on-hook differential voltage will be between

–42.5 V and –56.5 V with a primary battery of –65 V.

■ Ringing controlled digitally or by a PWM input signal

■ Power ring signal is applied to tip and ring.

■ Software-selectable slew rate, fast or slow.

■ Loop closure and common-mode detect are active.

■ Ring trip detector is turned off to conserve power.

■ On-hook transmission is enabled.

■ Ring trip supervision and common-mode current

supervision are active; loop closure is inactive.

■ Overhead is set to nominal 17.0 V for undistorted

transmission of 0 dBm into 600 Ω.

■ Overhead voltage is reduced to typically 2.5 V and

current limit set at I^PROGis disabled.

■ Current is limited by saturation current of the amplifi-

ers themselves, typically 72 mA peak at 125 °C.

Reverse Active (Slow Polarity Reversal)

Off-hook

Thermal Shutdown

■ Same as the reverse active (fast polarity reversal)

state, but with slower polarity reversal.

■ Not controlled via truth table inputs.

■ This mode is caused by excessive heating of the

device, such as may be encountered in an extended

power-cross situation.

On-hook

■ Same as the reverse active (fast polarity reversal)

state, but with slower polarity reversal.

Agere Systems Inc.

13

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Absolute Maximum Ratings (at TA = 25 °C)

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Parameter

Symbol

—

Min

–0.5

—

Typ

—

Max

7.0

Unit

V

dc Supply (V^CC)

Battery Supply (V^BAT1)

—

–80

V

Battery Supply (V^BAT2)

—

VBAT1

V^CC+ 0.5

125

V

Logic Input Voltage

—

–0.5

–40

5

V

Logic Output Voltage

—

V

Operating Temperature Range

Storage Temperature Range

Relative Humidity Range

Ground Potential Difference (BGND to AGND)

—

°C

%

V

—

150

—

95

—

±1

Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when

powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the

device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.

Table 3. Typical Operating Characteristics

Parameter

5 V dc Supplies (V^CC)

Min

—

Typ

5.0

3.3

–65

–21

25

Max

5.25

—

Unit

V

3 V dc Supplies (V^CC)

2.97

–63

–15

0

V

High Office Battery Supply (V^BAT1)

Auxiliary Office Battery Supply (V^BAT2)

Operating Temperature Range (28-pin SOG)

Operating Temperature Range (32-pin PLCC)

–70

VBAT1

70

V

°C

–40

25

85

Table 4. Thermal Characteristics

Parameter

Min

Typ

Max

Unit

Thermal Protection Shutdown (Tjc)

150

165

—

°C

28-pin SOG Thermal Resistance Junction to Ambient (θJA)^{1, 2}

:

Natural Convection 2S2P Board

Wind Tunnel 200 Linear Feet per Minute (LFPM) 2S2P Board

—

70

59

—

°C/W

32-pin PLCC Thermal Resistance Junction to Ambient (θJA)^{1, 2}

Natural Convection 2S2P Board

Natural Convection 2S0P Board

Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board

Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board

:

—

35.5

50.5

31.5

42.5

—

°C/W

48-pin MLCC Thermal Resistance Junction to Ambient (θJA)^{1, 2}

—

38

—

°C/W

1. This parameter is not tested in production. It is guaranteed by design and device characterization.

2. Airflow, PCB board layers, and other factors can greatly affect this parameter.

14

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Electrical Characteristics

Table 5. Environmental Characteristics

Parameter

Min

0

Typ

—

Max

70

Unit

°C

Temperature Range (28-pin SOG)

Temperature Range (32-pin PLCC and 48-pin MLCC)

Humidity Range¹

–40

5

—

85

95¹

°C

—

%RH

1. Not to exceed 26 grams of water per kilogram of dry air.

Table 6. 5.0 V Supply Currents

V^BAT1= –65 V, VBAT2 = –21 V, VCC = 5.0 V.

Parameter

Min

Typ

Max

Unit

Supply Currents (scan state; no loop current):

I^VCC

IVBAT1

IVBAT2

—

2.90

0.09

0.04

3.80

0.20

0.07

mA

Supply Currents (forward/reverse active; no loop current, V^BAT1applied):

I^VCC

IVBAT1

IVBAT2

—

4.8

1.5

1.0

6.00

1.95

1.20

mA

Supply Currents (disconnect mode):

I^VCC

IVBAT1

IVBAT2

—

1.60

0.02

0.01

2.20

0.10

0.02

mA

Supply Currents (ringing mode, no load applied):

I^VCC

IVBAT1

IVBAT2

—

4.40

1.70

0.57

5.0

2.2

0.7

mA

Table 7. 5.0 V Powering

V^BAT1= –65 V, VBAT2 = –21 V, VCC = 5.0 V.

Parameter

Power Dissipation (scan state; no loop current)

Power Dissipation (forward/reverse active; no loop current, V^BAT1applied)

Power Dissipation (disconnect mode)

Min

Typ

Max

Unit

mW

—

21

143

10

33

182

18

Power Dissipation (ring mode; no load applied)

144

183

Note: Refer to the power control description in the Applications section to calculate power dissipation in the forward/reverse off-hook state.

Agere Systems Inc.

15

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Electrical Characteristics (continued)

Table 8. 3.3 V Supply Currents

V^BAT1= –65 V, VBAT2 = –21 V, VCC = 3.3 V.

Parameter

Min

Typ

Max

Unit

Supply Currents (scan state; no loop current):

I^VCC

IVBAT1

IVBAT2

—

2.30

0.09

0.04

3.00

0.18

0.07

mA

Supply Currents (forward/reverse active; no loop current, V^BAT1applied):

I^VCC

IVBAT1

IVBAT2

—

4.40

1.50

0.97

5.30

1.90

1.20

mA

Supply Currents (disconnect mode):

I^VCC

IVBAT1

IVBAT2

—

1.20

0.02

0.01

1.70

0.10

0.02

mA

Supply Currents (ringing mode, no load applied):

I^VCC

IVBAT1

IVBAT2

—

4.00

1.64

0.54

4.75

2.16

0.60

mA

Table 9. 3.3 V Powering

V^BAT1= –65 V, VBAT2 = –21 V, VCC = 3.3 V.

Parameter

Power Dissipation (scan state; no loop current)

Power Dissipation (forward/reverse active; no loop current, V^BAT1applied)

Power Dissipation (disconnect mode)

Min

Typ

Max

Unit

mW

—

14

132

5

23

166

13

Power Dissipation (ring mode; no loop current)

131

169

Note: Refer to the power control description in the Applications section to calculate power dissipation in the forward/reverse off-hook state.

16

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Electrical Characteristics (continued)

Table 10. Two-Wire Port

Parameter

Tip or Ring Drive Current = dc + Longitudinal + Signal Currents

Tip or Ring Drive Current = Ringing + Longitudinal

Signal Current

Min

72

37

5

Typ

—

Max

—

Unit

mApeak

mArms

—

Longitudinal Current Capability per Wire (Longitudinal current is indepen-

dent of dc loop current.)

8.5

15

—

Ringing Current (R^LOAD= 2330 Ω + 24 µF)

Ringing Current (R^LOAD= 3500 Ω + 1.8 µF)

Ringing Current Limit (R^LOAD= 100 Ω)

25

12

—

90

mApeak

dc Loop Current—I^LIM(RLOOP = 500 Ω):

Programming Range (V^CC= 5.0 V)

Programming Range (V^CC= 3.3 V)

15

—

45

35

mA

dc Current Variation (current limit 15 mA to 45 mA)

—

±10

%

dc Loop Current (R^LOOP= 100 Ω, on to off hook transition)

t < 20 ms

—

350

100

mApeak

mA

dc Loop Current (R^LOOP= 100 Ω, on to off hook transition)

t < 50 ms

—

150%

I^LIM

dc Feed Resistance, 2 x RF (excluding protection resistors)

25

36

50

Ω

Loop Resistance Range*, (0 dB overload into 600 Ω)

I^LOOP= 20 mA, VBAT2 = –24 V, 50 Ω (2 x RF), 60 Ω (2 x RP), 300 Ω RLOOP plus 840

Handset

—

Ω

I^LOOP= 25 mA, VBAT1 = –65 V, 50 Ω (2 x RF), 60 Ω (2 x RP), 1000 Ω RLOOP

1540

plus Handset

Open Loop Voltages, |VBAT1| = –63 V to –70 V:

Scan/On-Hook Transmission Mode:

|PT – PR| – Differential

42.5

—

48

—

56.5

V

|PT| or |PR| Referenced to BGND

Ring Mode, |V^BAT1| = –63 V to –70 V:

|PT – PR| – Differential, (open loop ring voltage)

40

—

Vrms

Loop Closure Threshold:

Scan/Active/On-hook Transmission Modes

—

10

2

—

mA

Loop Closure Threshold Hysteresis:

Ground Key:

Differential Detector Threshold

Detection

5

50

8

—

10

—

mA

ms

Longitudinal to Metallic Balance at PT/PR

Test Method per Figure 8, 1 kHz^†58 dB minimum, 60 dB typical:

300 Hz to 600 Hz

55

58

—

dB

600 Hz to 3.4 kHz

Metallic to Longitudinal (harm) Balance:

200 Hz to 1000 Hz

100 Hz to 4000 Hz

40

—

dB

PSRR 500 Hz—3000 Hz:

V^BAT1, VBAT2

VCC (3.3 V operation)

40

25

—

dB

* Values guaranteed by design, not subject to production test.

† Corresponds to 55 dB minimum with 1%, 30 Ω resistors per Q552 (11/96) Section 2.1.2 and IEEE 455.

®

Agere Systems Inc.

17

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Electrical Characteristics (continued)

Table 11. Analog Pin Characteristics

Parameter

Min

Typ

Max

Unit

TXI (input impedance)

—

100

—

kΩ

Output Offset (VTX)

Output Offset (VITR)

Output Drive Current (VTX)

Output Drive Current (VITR)

Output Voltage Swing (VTX) (V^CC= 5.0 V)

Output Voltage Swing (VITR) (V^CC= 5.0 V)

Output Short-circuit Current (VTX)

Output Short-circuit Current (VITR)

Output Load Resistance (VTX and VITR)

Output Load Capacitance (VTX)

Output Load Capacitance (VITR)

—

±3.7

—

10

—

±5

±70

±500

±250

—

±5

±6

—

mV

µA

V

—

+5/–8

±3.1

—

V

mA

kΩ

pF

—

20

50

RCVN and RCVP:

Input Voltage Range (V^CC= 5.0 V)

Input Voltage Range (V^CC= 3.3 V)

Input Bias Current

0

—

V^CC– 0.5

V^CC– 0.3

±1.5

V

µA

18

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Electrical Characteristics (continued)

Table 12. ac Feed Characteristics

Parameter

Min

Typ

Max

Unit

ac Termination Impedance¹

150

600

1400

Ω

Total Harmonic Distortion (200 Hz—4 kHz)²:

Off-hook

On-hook

—

0.3

1.0

%

Transmit Gain (f = 1004 Hz, 1020 Hz)³:

PT/PR Current to VITR

291

300

309

V/A

Receive Gain⁴(f = 1004 Hz to 1020 Hz):

RCVP or RCVN to PT—PR (gain of 8 option, L9214A)

RCVP or RCVN to PT—PR (gain of 2 option, L9214G)

7.6

1.9

8

2

8.4

2.1

—

Gain vs. Frequency (transmit and receive)², 600 Ω Termination

(Q.552), 1004 Hz, 1020 Hz reference:

200 Hz—300 Hz

300 Hz—3.4 kHz

3.4 kHz—3.6 kHz

–0.30

–0.05

–1.50

–3.00

—

0

–0.1

—

0.05

–0.05

–2.0

dB

3.6 kHz—20 kHz

20 kHz—266 kHz

Gain vs. Level (transmit and receive)², 0 dBV Reference (Q.552):

–55 dB to +3.0 dB

–0.05

0

0.05

dB

Idle-channel Noise (tip/ring) 600 Ω Termination:

Psophometric

C-Message

3 kHz Flat

—

–82

8

—

–77

13

20

dBmp

dBrnC

dBrn

Idle-channel Noise (VTX) 600 Ω Termination:

Psophometric

C-Message

3 kHz Flat

—

–82

8

—

–77

13

20

dBmp

dBrnC

dBrn

1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between

150 Ω and 1400 Ω can be synthesized.

2. This parameter is not tested in production. It is guaranteed by design and device characterization.

3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750 Ω, the recommended value. Positive cur-

rent is defined as the differential current flowing from PT to PR.

4. Tested per Figure 9. The gain reading is adjusted by the ratio of 696/660 to account for the 36 Ω nominal ac feed resistance.

Agere Systems Inc.

19

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Electrical Characteristics (continued)

Table 13. Logic Inputs and Outputs (V^CC= 5.0 V)

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltages:

Low Level

High Level

V^IL

VIH

–0.5

2.0

0.4

2.4

0.7

V^CC

V

Input Current:

Low Level (V^CC= 5.25 V, VI = 0.4 V)

High Level (V^CC= 5.25 V, VI = 2.4 V)

I^IL

IIH

—

±250

µA

Output Voltages (open collector with internal pull-up resistor):

Low Level (V^CC= 4.75 V, IOL = 200 µA)

High Level (V^CC= 4.75 V, IOH = –10 µA)

V^OL

VOH

0

2.4

0.2

—

0.4

V^CC

V

Table 14. Logic Inputs and Outputs (V^CC= 3.3 V)

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltages:

Low Level

High Level

V^IL

VIH

–0.5

2.0

0.2

2.5

0.5

V^CC

V

Input Current:

Low Level (V^CC= 3.46 V, VI = 0.4 V)

High Level (V^CC= 3.46 V, VI = 2.4 V)

I^IL

IIH

—

±250

µA

Output Voltages (open collector with internal pull-up resistor):

Low Level (V^CC= 3.13 V, IOL = 200 µA)

High Level (V^CC= 3.13 V, IOH = –5 µA)

V^OL

VOH

0

2.2

0.2

—

0.5

V^CC

V

Table 15. Ringing Specifications

Parameter

Min

Typ

Max

Unit

Ring Signal Isolation:

PT/PR to VITR

Ring Mode

—

60

—

dB

Ringing Voltage (5 REN 1386 Ω + 40 µF load, 200 Ω loop, 2 x 30 Ω protection

resistors, –69 V battery, 1.2 crest factor)¹

40

—

Vrms

Ringing Voltage (3 REN 2330 Ω + 24 µF load, 600 Ω loop, 2 x 30 Ω protection

resistors, –69 V battery, 1.2 crest factor)¹

Ringing Voltage (2 REN 3500 Ω + 16 µF load, 1000 Ω loop, 2 x 30 Ω protec-

tion resistors, –69 V battery, 1.2 crest factor)¹

Ringing Voltage (2 REN 3500 Ω + 1.8 µF load, 500 Ω loop, 2 x 30 Ω protection

resistors, –69 V battery, 1.2 crest factor)²

Ring Signal Distortion:

5 REN 1386 Ω, 40 µF Load, 200 Ω Loop

3 REN 2330 Ω, 24 µF Load, 600 Ω Loop

2 REN 3500 Ω, 16 µF Load, 1000 Ω Loop

2 REN 3500 Ω, 1.8 µF Load, 500 Ω Loop

—

5

—

10

%

1. Voltage is measured across both resistive and capacitive elements of the ringer load.

2. Voltage is measured only across the resistive element of the ringer load.

20

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Electrical Characteristics (continued)

Table 16. Ring Trip (3 REN Configuration)

Parameter

Min

Typ

Max

Unit

Ring Trip (NSTAT = 0): Loop Resistance (total)

Ring Trip (NSTAT = 1): Loop Resistance (total)

Ringer Load

0

—

1000

Ω

10

—

2330 Ω + 24 µF

130

kΩ

—

Trip Time (f = 20 Hz)

ms

Ringing will not be tripped by the following loads:

■ 100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.

■ 10 kΩ resistor in parallel with a 4 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.

Table 17. Ring Trip (5 REN Configuration)

Parameter

Min

Typ

Max

Unit

Ring Trip (NSTAT = 0): Loop Resistance (total)

Ring Trip (NSTAT = 1): Loop Resistance (total)

Ringer Load

0

—

600

Ω

10

—

1386 Ω + 40 µF

150

kΩ

—

Trip Time (f = 20 Hz)

ms

Ringing will not be tripped by the following loads:

■ 100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.

■ 10 kΩ resistor in parallel with a 6 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.

Note: Refer to the application section for further description of the 3 REN configuration vs. 5 REN configuration.

Agere Systems Inc.

21

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Test Configurations

133 kΩ

1 µF

RTFLT

75 kΩ

DCOUT

5.76 kΩ

RCVP

RCVN

RCVP

RCVN

IPROG

IREF

28.7 kΩ

VITR

30 Ω

VITR

TIP

PR

0.1 µF

RLOOP

100 Ω/600 Ω

L9214

TXI

30 Ω

VTX

RING

PT

4750 Ω

ITR

0.047 µF

FB2

0.047 µF

B0

B1

B2

B3

B0

B1

B2

B3

FB1

CF1

0.47 µF

0.1 µF

CF2

VBAT2

VBAT1

BGND VCC

AGND

ICM TRGDET NSTAT

0.1 µF

600 kΩ

0.1 µF

VBAT2

VBAT1

VCC

12-3531.j (F)

Figure 5. Basic Test Circuit, VCC = 3.3 V (3 REN Configuration)

22

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Test Configurations (continued)

100 µF

368 Ω

VBAT OR VCC

VITR

TIP

VS

100 Ω

DISCONNECT

BYPASS CAPACITOR

BASIC

4.7 µF

TEST CIRCUIT

368 Ω

100 µF

VS

RING

VBAT OR

VCC

TIP

+

VT/R

–

BASIC

TEST CIRCUIT

VS

VITR

LONGITUDINAL BALANCE = 20log

600 Ω

12-2584.D (F)

RING

Figure 8. Longitudinal Balance

VS

VT/R

PSRR = 20log

12-2582.c (F)

VITR

Figure 6. Metallic PSRR

PT

+

BASIC

TEST CIRCUIT

RCVN

OR

RCVP

VT/R

600 Ω

VBAT OR VCC

RCVN

OR

–

DISCONNECT

BYPASS CAPACITOR

100 Ω

4.7 µF

PR

RCVP

VS

VBAT OR

VCC

VXMT

------------

G^XMT=

VT ⁄ R

67.5 Ω

TIP

VT ⁄ R

------------------------------------------------

G^RCV=

10 µF

BASIC

TEST CIRCUIT

VRCVP OR VRCVN

12-2587.J (F)

67.5 Ω

56.3 Ω

+

RING

VM

–

Figure 9. ac Gains

10 µF

VS

VM

PSRR = 20log

12-2583.b (F)

Figure 7. Longitudinal PSRR

Agere Systems Inc.

23

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Typically IBIAS is 3.5 mA. This additional VBAT1 current

contributes to the loop current and the remaining loop

current is supplied by VBAT2, so that

Applications

Power Control

I^VBAT2= IQ2 + ILOOP – IBIAS

Under normal device operating conditions, power dissi-

pation must be controlled to prevent the device temper-

ature from rising too close to the thermal shutdown

point. Power dissipation is highest with higher battery

voltages, higher current limit, and under shorter dc loop

conditions. Additionally, higher ambient temperature

will reduce thermal margin. Increasing the number of

PC board layers and increasing airflow around the

device are typical ways of improving thermal margin.

IVCC is the current drawn from VCC and is relatively con-

stant as the phone goes off hook.

The total power from the power supplies is:

P^TOTAL= {[(IQ1 + IBIAS) * VBAT1] + [(IQ2 + ILOOP – IBIAS) *

V^BAT2] + [(IVCC) * VCC]}

The maximum values of I^Q1and IQ2 are 1.95 mA and

1.20 mA respectively from Table 4.

The maximum recommended junction temperature for

the L9214 is 150 °C. The junction temperature is:

If the current limit is set to 25 mA, given the current limit

tolerance of 10%, the maximum current limit is

27.5 mA. Also, assume 20 Ω of wire resistance, 30 Ω

of protection resistance, and 200 Ω for the handset

Tj = T^AMBIENT+ θJA * PSLIC

The thermal impedance of this device depends on the

package type as well as number of PCB layers and air-

flow. The thermal impedance of the 28-pin SOG pack-

age is somewhat higher than the 32-pin PLCC

package. The 28-pin SOG package in still air with a

single-sided PCB is rated at 70 °C/W. The 32-pin

PLCC package thermal impedance with no airflow on a

four-layer PCB is estimated at 37 °C/W.

P^TOTAL= {[(1.95 mA + 3.5 mA) * (65 V)] + [(1.20 mA +

27.5 mA – 3.5 mA) * (21 V)] + [(6 mA) * (5 V)]

= 913.45 mW

The power delivered to the loop and the protection

resistors (P^LOOP) is:

P^LOOP= {(ILOOP)²* [(2 * RPROTECTION) + (RWIRE) +

(R^PHONE)]} = {(27.5 mA)²* [(2 * 30 Ω) + (20 Ω) +

200 Ω)]} = 212 mW

The power handling capability of the package is:

P^SLIC= (150 °C – TAMBIENT)/θJA

Thus, the total power dissipated by the SLIC is:

which is a minimum of 0.93 W for the 28-pin SOG

package with a single-sided PCB and no airflow and as

much as 2.15 W for the 32-pin PLCC package with a

multilayer PCB.

P^Dof SLIC = Total power (PTOTAL) – power delivered to

loop and protection resistors (P^LOOP).

P^D= 913.45 mW – 212 mW

= 701.45 mW for this example.

This device is intended to operate with a high-voltage

primary battery of –63 V to –70 V. Under short-loop

conditions, an internal soft battery switch shunts most

(all but I^BIAS= 3.5 mA) of the loop current to an auxiliary

battery of lower absolute voltage (typically –21 V).

Where single battery operation is required, an external

power control resistor can be connected from the V^BAT2

pin to V^BAT1and all but 3.5 mA of the loop current will

flow through the power control resistor.

Since the minimum power handling capability of the

28-pin SOG package is 0.93 W, in this case either

package type is acceptable even with a single-sided

PCB. At higher battery voltages, higher ambient tem-

perature, and higher current limit, the required thermal

impedance drops and the 32-pin PLCC package, more

PCB layers, or some airflow might be required.

Another case to consider is the case of the power con-

trol resistor. In this case, the effective V^BAT2voltage is:

The power dissipated in the device is best illustrated by

an example. Assume V^BAT1is –65 V, VBAT2 is –21 V,

and the current limit is is I^LOOP.

V^BAT2= VBAT1 – RPWR * (ILOOP – IBIAS + IQ2)

For the case of the 27.5 mA maximum current limit,

choosing R^PWR= 1.75 kΩ would give VBAT2 = –21 V and

the same SLIC power as above. The power in the

resistor would be:

Let I^Q1and IQ2 be the quiescent currents drawn from

V^BAT1and VBAT2 respectively (the current drawn from

the battery when the phone is on-hook). Let I^BIASbe

the additional current drawn from V^BAT1when the

phone is off-hook.

P^RPWR= (ILOOP – IBIAS + IQ2)²* RPWR = 1.11 W

Choosing a larger R^PWRwould result in lower VBAT2 and

lower SLIC power, but more power in the resistor. Simi-

larly, choosing a smaller RPWR results in higher VBAT2,

higher SLIC power, and less power in the resistor.

I^BIAS= IVBAT1(off-hook) – IQ1

24

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

The default overhead provides sufficient headroom for

on-hook transmission of a +3.17 dBm signal into

600 Ω.

+3.17 dBm = 10 log (Vrms²/ P0 * R600 Ω)

Applications (continued)

dc Loop Current Limit

In the active modes, dc current limit is programmable

via an external resistor. The resistor is connected

between I^PROGand DCOUT. The loop current limit

(I^LOOP) with 100 Ω load is related to the RIPROG pro-

gramming resistor by:

dBm = 10 log (Vrms²/ 0.001 W * 600 Ω)

Vrms²

-------------------------------

+3.17 dBm = 10 log

0.6(IV × R)

Vrms = 1.12 V and Vpeak = 1.58 V are supported.

I^LOOP(mA) = 4 mA/kΩ * RIPROG (kΩ) + 2 mA

Note that the overall current-limit accuracy achieved

will be affected by the specified accuracy of the internal

SLIC current-limit circuit and the accuracy of the exter-

nal resistor.

Scan Mode

If the magnitude of the primary battery is greater than

a nominal –63 V, the magnitude of the open-loop tip

to ring voltage is clamped to between –42.5 V and

–56.5 V.

The above equation describes the active mode steady-

state current-limit response. There will be a transient

response of the current-limit circuit upon an on- to off-

hook transition. Typical active mode transient current-

limit response is given in Table 18.

Again, the overhead is not symmetrical with respect to

tip and ring. With the magnitude of the primary battery

greater than a nominal –63 V, the tip to ground voltage

is clamped between –0.1 V and –0.6 V and the ring to

ground voltage is clamped between –42.5 V and

–56.5 V. If the magnitude of the primary battery is less

than a nominal –63 V, the tip to ground voltage is

–0.1 V to –0.6 V and the ring to battery voltage is typi-

cally 17 V less than V^BAT1.

Table 18. Typical Active Mode On- to Off-Hook Tip/

Ring Current-Limit Transient Response

Parameter

Value

Unit

dc Loop Current: Active Mode

R^LOOP= 100 Ω On- to Off-hook

Transition t < 20 ms

I^LOOP+ 60 mA

On-Hook Transmission Mode

dc Loop Current: Active Mode

R^LOOP= 100 Ω On- to Off-hook

Transition t < 30 ms

I^LOOP+ 20 mA

If the magnitude of the primary battery is greater than

63 V, the magnitude of the open-loop tip to ring voltage

will be greater than 42.5 V. If the magnitude of the pri-

mary battery is less than 63 V, the open-loop voltage

may be less than 42.5 V and is approximately 17 V less

than the magnitude of the primary battery voltage. For

primary battery voltages less than 70 V, the magnitude

of the ring to ground voltage will be less than 56.5 V.

dc Loop Current: Active Mode

R^LOOP= 100 Ω On- to Off-hook

Transition t < 50 ms

I^LOOP

mA

Overhead Voltage

Active Mode

Again, the overhead is not symmetrical with respect to

tip and ring. The tip voltage to ground is between –2 V

and –4.5 V and the ring to primary voltage is 14.5 V

typical.

The overhead is preprogrammed in the active mode.

Note that overhead is not symmetrical with respect to

tip and ring. Under default conditions, the tip to ground

voltage is 2.1 V to 2.6 V and the ring to battery over-

head is 14.5 V typical.

Agere Systems Inc.

25

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

The point of change over between VBAT2 and VBAT1

occurs at:

Applications (continued)

Overhead Voltage (continued)

Ring Mode

|VBAT2| – (0.9 + 2.5) V > [(2RP + RDC + RL) * ILOOP] V

VBAT2 is typically applied under off-hook conditions for

power conservation and SLIC thermal considerations.

The L9214 is intended for short- and medium-loop

applications and, therefore, will always be in current

limit during off-hook conditions. However, note that the

ringing loop length rather than the dc loop length will be

the factor to determine operating loop length. Where

V^BAT2is insufficient to support the loop length, the

power will be taken from V^BAT1.

In the ring mode, to maximize ringing loop length, the

overhead is decreased to the saturation of the tip ring

drive amplifiers, a nominal 4 V. The tip to ground volt-

age is 1 V, and the ring to V^BAT1voltage is 3 V.

The AX amplifier at VTX is active during the ring mode,

differential ring current may be sensed at VTX during

the ring mode.

Battery Reversal Rate

Loop Range

The rate of battery reverse is controlled or ramped by

capacitors FB1 and FB2. A chart showing FB1/FB2 val-

ues versus typical ramp time is given below. Leave

FB1 and FB2 open if it is not desired to ramp the rate of

battery reversal.

The dc loop range for medium-loop applications is cal-

culated using:

( VBAT1 – VOHH)

----------------------------------------------

ILOOP

R^L=

– 2RP – Rdc

The dc loop range for short-loop applications is calcu-

lated using:

Table 19. FB1/FB2 Values vs. Typical Ramp Time at

V^BAT1= –65 V

( VBAT2 – VOHL)

----------------------------------------------

ILOOP

RL =

– 2RP – Rdc

Transition Time Transition Time

Fast, B3 = 0

CFB1/CFB2

Slow, B3 = 1

20 ms

220 ms

440 ms

900 ms

1.8 s

where:

V^OHH= 19.5 (2.5 V + 17 V) and

V^OHL= 3.4 V (2.5 V + 0.9 V)

0.01 µF

0.1 µF

0.22 µF

0.47 µF

1.0 µF

1.22 µF

1.3 µF

1.4 µF

1.6 µF

7 ms

75 ms

145 ms

300 ms

600 ms

750 ms

830 ms

900 ms

1070 ms

and where:

R^L= loop resistance, not including protection resistors.

R^P= protection resistor value.

Rdc = SLIC internal dc feed resistance.

|V^BAT1| and |VBAT2| = battery voltage magnitude.

I^LOOP= loop current.

2.25 s

2.5 s

2.7 s

3.2 s

V^OHH= overhead voltage when power is drawn from

V^BAT1.

V^OHL= overhead voltage when power is drawn from

VBAT2.

26

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

use of the state input pins. It is possible to select either

fast or slow slew rates to alter the crest factor of the

ringing signal. This allows designers to set the external

capacitors to a specific factor and change the ringing

frequency under software control while maintaining the

crest factor between 1.2 and 1.6 for the trapezoidal sig-

nal.

Supervision

The L9214 offers the loop closure and ring trip supervi-

sion functions. Internal to the device, the outputs of

these detectors are multiplexed into a single package

output, NSTAT. Additionally, a common-mode current

detector for tip or ring ground detection is included for

ground key applications.

During the ring mode, it is also possible to supply a

pulse-width modulated, PWM, signal into the device’s

B1 input. This signal is used to produce the power ring

signal. This signal must be removed during nonring

mode states. The user may input any crest factor ring

signal using this method; thus, the device will support a

sine wave (crest factor 1.414) or a lower or higher crest

factor input for increased power efficiency ring signal.

Various crest factors are shown below.

Loop Closure

The loop closure has a fixed typical 10 mA on- to off-

hook threshold in the active mode and a fixed 10 mA

on- to off-hook threshold from the scan mode. In either

case, there is a 2 mA hysteresis with V^CC= 5.0 V and

with V^CC= 3.3 V.

80

60

Ring Trip

40

The ring trip detector requires an external filter at the

input, minimizing external components. An R + R//C

combination of 75 kΩ and 133 kΩ // 1 µF, for a filter

pole at 3.3 Hz, is recommended for a 3 REN config-

uration. For a 5 REN configuration, a 150 kΩ and

100 kΩ // 1 µF (for a filter pole at 2.65 Hz) combination

is recommended.

20

0

–20

–40

–60

–80

0.00 0.04 0.08 0.12 0.16 0.20

0.02 0.06 0.10 0.14 0.18

The ring trip threshold is internally fixed and is indepen-

dent of battery voltage. The threshold, I^RT= 20.1 mA.

TIME (s)

12-3346a (F)

Note: Slew rate = 5.65 V/ms; trise = tfall = 23 ms; pwidth = 2 ms;

period = 50 ms.

Tip or Ring Ground Detector

Figure 10. Ringing Waveform Crest Factor = 1.6

In the ground key or ground start applications a com-

mon-mode current detector is used to indicate either a

tip- or ring-ground has occurred (ground key) or an off-

hook has occurred (ground start). The detection thresh-

old is set by connecting a resistor from ICM to V^CC.

80

60

40

1000 * V^CC/RICM (kΩ) = ITH (mA)

20

0

where:

–20

–40

–60

RICM > 80 kΩ @ VCC = 3.3 V

RICM > 150 kΩ @ VCC = 5.0 V

Additionally, a filter capacitor across RICM will set the

time constant of the detector. No hysteresis is associ-

ated with this detector.

–80

0.00 0.04 0.08 0.12 0.16 0.20

0.02 0.06 0.10 0.14 0.18

TIME (s)

12-3347a (F)

Note: Slew rate = 10.83 V/ms; trise = tfall = 12 ms; pwidth = 13 ms;

period = 50 ms.

Power Ring

The device offers a ring mode, in which a power ring

signal is provided to the tip/ring pair. The standard

method of ringing is to perform trapezoidal ringing by

Figure 11. Ringing Waveform Crest Factor = 1.2

Agere Systems Inc.

27

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

First, calculate the equivalent ringing load resistance at

25 Hz.

Supervision (continued)

Power Ring (continued)

RLOAD = {(3500 Ω)²+ (2 * π * 25 * 16E–6)^–2}^0.5

RLOAD = 3522 Ω

The ring signal will appear balanced on tip and ring.

That is, the ring signal is applied on both tip and ring,

with the signal on tip 180° out of phase from the signal

on ring. This operation is shown in Figure 12 below.

40 Vrms = {(67 – 4)/1.2)} {3522 Ω/(RLOOP + 3522 Ω +

60 Ω)}

RLOOP = 1040 Ω

Ringing loop range is calculated as follows:

Effects such as power supply tolerance and crest factor

tolerance can affect this calculation.

V^RINGLOAD= {(VBATTERY – 4)/Crest Factor} *

{R^LOAD/(RLOAD + RLOOP + 2 x RPROTECTION)}

Crest factor is estimated by the formula:

1

As a practical example, calculate the maximum dc loop

length, assuming the following conditions:

-------------------------------------------------------------------------------------------------------

=

(4 × f × C^FB× VBAT1 – VOHH )

-----------------------------------------------------------------------------------------

1 –

3 × ICS

Minimum required ring voltage = 40 Vrms

V^BATTERY= –67 V

Where:

Trapezoidal ringing, crest factor = 1.2

Protection resistors = 30 Ω each

Ring Load = 2 North American REN = 3500 Ω + 16 µF

Ringing frequency = 25 Hz

f = ringing frequency; C^FB= (CFB1 + CFB2)/2;

Ics = 30 µA with B3 = 1 and 90 µA with B3 = 0;

V^OHH= 4 V

L9214

1/2 R^LOOP+ RPROTECTION

PT

PR

GND

1 V

+1

RING

SQUARE WAVE OR

PWM SIGNAL

V^TIP

B1

VRING

LOAD

3 V

–1

VBAT

1/2 RLOOP + RPROTECTION

12-3532.B (F)

Figure 12. Ring Operation

28

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Third-Generation Codecs

Periodic Pulse Metering (PPM)

This class of devices includes all ac parameters set

digitally under microprocessor control. Depending on

the device, it may or may not have data control latches.

Additional functionality sometimes offered includes

tone plant generation and reception, PPM generation,

test algorithms, and echo cancellation. Again, this type

of codec may be 3.3 V, 5 V only, or ±5 V operation, sin-

gle-, quad-, or 16-channel, and µ-law/A-law or 16-bit

linear coding selectable. Examples of this type of

codec are the Agere T8535/6 (5 V only, quad, standard

features), T8537/8 (3.3 V only, quad, standard fea-

tures), T8533/4 (5 V only, quad with echo cancellation),

and the T8531/32 (5 V only, eight- or 16-channel).

Periodic pulse metering (PPM), also referred to as tele-

tax (TTX), is applied to the audio input of the L9214.

When in the active state, this signal is presented to the

tip/ring subscriber loop along with the audio signal. The

L9214 assumes that a shaped PPM signal is applied to

the audio input.

ac Applications

ac Parameters

There are four key ac design parameters. Termination

impedance is the impedance looking into the 2-wire

port of the line card. It is set to match the impedance of

the telephone loop in order to minimize echo return to

the telephone set. Transmit gain is measured from the

2-wire port to the PCM highway, while receive gain is

done from the PCM highway to the transmit port.

Transmit and receive gains may be specified in terms

of an actual gain, or in terms of a transmission level

point (TLP), that is the actual ac transmission level in

dBm. Finally, the hybrid balance network cancels the

unwanted amount of the receive signal that appears at

the transmit port.

ac Interface Network

The ac interface network between the L9214 and the

codec will vary depending on the codec selected. With

a first-generation codec, the interface between the

L9214 and codec actually sets the ac parameters. With

a third-generation codec, all ac parameters are set dig-

itally, internal to the codec; thus, the interface between

the L9214 and this type of codec is designed to avoid

overload at the codec input in the transmit direction

and to optimize signal to noise ratio (S/N) in the receive

direction.

Codec Types

Because the design requirements are very different

with a first- or third-generation codec, the L9214 is

offered with two different receive gains. Each receive

gain was chosen to optimize, in terms of external com-

ponents required, the ac interface between the L9214

and codec.

At this point in the design, the codec needs to be

selected. The interface network between the SLIC and

codec can then be designed. Below is a brief codec

feature summary.

With a first-generation codec, the termination imped-

ance is set by providing gain shaping through a feed-

back network from the SLIC VITR output to the SLIC

RCVN/RCVP inputs. The L9214 provides a transcon-

ductance from T/R to VITR in the transmit direction and

a single-ended to differential gain from either RCVN or

RCVP to T/R in the receive direction. Assuming a short

from VITR to RCVN or RCVP, the maximum imped-

ance that is seen looking into the SLIC is the product of

the SLIC transconductance times the SLIC receive

gain, plus the protection resistors. The various speci-

fied termination impedance can range over the voice-

band as low as 300 Ω up to over 1000 Ω. Thus, if the

SLIC gains are too low, it will be impossible to synthe-

size the higher termination impedances. Further, the

termination that is achieved will be far less than what is

calculated by assuming a short for SLIC output to SLIC

input.

First-Generation Codecs

These perform the basic filtering, A/D (transmit), D/A

(receive), and µ-law/A-law companding. They all have

an op amp in front of the A/D converter for transmit

gain setting and hybrid balance (cancellation at the

summing node). Depending on the type, some have

differential analog input and output stages, +5 V only or

±5 V operation, and µ-law/A-law selectability. These

are available in single and quad designs. This type of

codec requires continuous time analog filtering via

external resistor/capacitor networks to set the ac

design parameters. An example of this type of codec is

the Agere T7504 quad 5 V only codec.

This type of codec tends to be the most economical in

terms of piece part price, but tends to require more

external components than a third-generation codec.

The ac parameters are fixed by the external R/C net-

work so software control of ac parameters is difficult.

Agere Systems Inc.

29

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Thus, it appears that the solution is to have a SLIC with

a low gain, especially in the receive direction. This will

allow the codec to operate near its maximum output

signal (to optimize S/N), without an external resistor

divider (to minimize cost).

ac Applications (continued)

ac Interface Network (continued)

In the receive direction, in order to control echo, the

gain is typically a loss, which requires a loss network at

the SLIC RCVN/RCVP inputs, which will reduce the

amount of gain that is available for termination imped-

ance. For this reason, a high-gain SLIC is required with

a first-generation codec.

To meet the unique requirements of both type of

codecs, the L9214 offers two receive gain choices.

These receive gains are mask programmable at the

factory and are offered as two different code variations.

For interface with a first-generation codec, the L9214 is

offered with a receive gain of 8. For interface with a

third-generation codec, the L9214 is offered with a

receive gain of 2. In either case, the transconductance

in the transmit direction or the transmit gain is 300 Ω,

(300 V/A).

With a third-generation codec, the line card designer

has different concerns. To design the ac interface, the

designer must first decide upon all termination imped-

ance, hybrid balances, and transmission level point

(TLP) requirements that the line card must meet. In the

transmit direction, the only concern is that the SLIC

does not provide a signal that is too hot and overloads

the codec input. Thus, for the highest TLP that is being

designed to, given the SLIC gain, the designer, as a

function of voiceband frequency, must ensure the

codec is not overloaded. With a given TLP and a given

SLIC gain, if the signal will cause a codec overload, the

designer must insert some sort of loss, typically a resis-

tor divider, between the SLIC output and codec input.

This selection of receive gain gives the designer the

flexibility to maximize performance and minimize exter-

nal components, regardless of the type of codec cho-

sen.

Design Examples

First-Generation Codec ac Interface Network—

Resistive Termination

Note also that some third-generation codecs require

the designer to provide an inherent resistive termina-

tion via external networks. The codec will then provide

gain shaping, as a function of frequency, to meet the

return loss requirements. This feedback will increase

the signal at the codec input and increase the likeli-

hood that a resistor divider is needed in the transmit

direction. Further stability issues may add external

components or excessive ground plane requirements

to the design.

The following reference circuit shows the complete

SLIC schematic for interface to the Agere T7504 first-

generation codec for a resistive termination imped-

ance. For this example, the ac interface was designed

for a 600 Ω resistive termination and hybrid balance

with transmit gain and receive gain set to 0 dBm. For

illustration purposes, no PPM injection was assumed in

this example.

This is a lower feature application example and uses

single battery operation, fixed overhead, current limit,

and loop closure threshold.

In the receive direction, the issue is to optimize the

S/N. Again, the designer must consider all the TLPs.

The idea is, for all desired TLPs, to run the codec at or

as close as possible to its maximum output signal, to

optimize the S/N. Remember noise floor is constant, so

the hotter the signal from the codec, the better the S/N.

The problem is if the codec is feeding a high-gain SLIC,

either an external resistor divider is needed to knock

the gain down to meet the TLP requirements, or the

codec is not operated near maximum signal levels,

thus compromising the S/N.

Resistor RGN is optional. It compensates for any mis-

match of input bias voltage at the RCVN/RCVP inputs.

If it is not used, there may be a slight offset at tip and

ring due to mismatch of input bias voltage at the

RCVN/RCVP inputs. It is very common to simply tie

RCVN directly to ground in this particular mode of oper-

ation. If used, to calculate RGN, the impedance from

RCVN to ac ground should equal the impedance from

RCVP to ac ground.

30

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Transmit Gain:

ac Applications (continued)

Design Examples (continued)

Example 1, Real Termination

VGSX

g^tx= ----------

VT/R

–RX 300

-------- --------

gtx =

×

RT2

Z^T/R

The following design equations refer to the circuit in

Figure 13. Use these to synthesize real termination

impedance.

Hybrid Balance:

h^bal= 20log

RX

RHB

Termination Impedance:

-----------

– gtx × grcv

V^T/R

–IT/R

------------

zT =

VGSX

--------------

h^bal= 20log

2400

zT = 36 Ω + 2RP +

VFR

----------------------------------

1 +

R^T1

RT1

+

-------- -----------

RGP RRCV

To optimize the hybrid balance, the sum of the currents

at the VFX input of the codec op amp should be set to

0. The expression for ZHB becomes the following:

Receive Gain:

VT/R

-----------

g^rcv=

RX

VFR

-------------------

RHB(kΩ) =

gtx × grcv

8

grcv =

------------------------------------------------------------------

R^RCVRRCV

Z^T

1 +

+

1 +

--------

----------- -----------

RT1

RGP

ZT/R

RX

VGSX

–0.300 V/mA

RT2

VFXIN

VFXIP

–

VITR

+

RT1

RCVN

RCVP

RHB1

–

18 Ω

+2.4 V

ZT/R

RP

TIP

AV = 4

+

AV = 1

RRCV

VFR

IT/R

+

CURRENT

SENSE

VS

ZT

VT/R

–

RP

RGP

+

AV = –1

RING

18 Ω

–

L9214

1/4 T7504 CODEC

12-3569 (F)

Figure 13. ac Equivalent Circuit

Agere Systems Inc.

31

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

ac Applications (continued)

Design Examples (continued)

Example 1, Real Termination (continued)

V^BAT1

VBAT2 VCC

RRT1

CVBAT1

CVBAT2

CCC

100 kΩ

DBAT1

0.1 µF 0.1 µF

0.1 µF

C^RT

1 µF

VBAT1

BGND VBAT2 VCC AGND ICM TRGDET

ITR

ground key

not used

RTFLT

RGX

RRT2

4750 Ω

150 kΩ

RX

VTX

DCOUT

100 kΩ

R^IPROG

5.76 kΩ

CTX

0.1 µF

GSX

IPROG (ILOOP = 25 mA)

IREF

TXI

CC1

0.1 µF

R^T6

49.9 kΩ

–

R^IREF

28.7 kΩ

DX

VITR

VFXIN

+

RT3

L9214A

R^HB1

100 kΩ

PCM

HIGHWAY

69.8 kΩ

+2.4 V

FUSIBLE RESISTOR

OR PTC

CC2

0.1 µF

R^RCV

60.4 kΩ

VFRO

PR

PT

DR

30 Ω

RCVP

AGERE

L7591

RGP

RCR

5 kΩ

VBAT1

FSE

FSEP

MCLK

SYNC

AND

CLOCK

26.7 kΩ

CCC1

150 nF

30 Ω

RCVN

FUSIBLE RESISTOR

OR PTC

RGN

17.65 kΩ

CONTROL

INPUTS

ASEL

CF1

CF2

FB1

FB2

NSTAT B3 B2 B1 B0

CF1

1/4 T7504

CODEC

0.22 µF

CF2

0.1 µF

CFB1

0.01 µF

CFB2

0.01 µF

FROM/TO

CONTROL

12-3533.L (F)

Figure 14. Agere T7504 First-Generation Codec; Resistive Termination (5 REN Configuration)

32

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

ac Applications (continued)

Design Examples (continued)

Example 1, Real Termination (continued)

Table 20. L9214 Parts List for Agere T7504 First-Generation Codec; Resistive Termination

Name

Fault Protection

RPT

Value Tolerance

Rating

Function

30 Ω

1%

—

Fusible or PTC Protection resistor.

RPR

Protector

Agere

L7591

—

Secondary protection.

Power Supply

CVBAT1

0.1 µF

20%

—

20%

100 V

50 V

—

10 V

100 V

VBAT filter capacitor.

CVBAT2

VBAT filter capacitor. |VBAT2| < |VBAT1|.

Reverse current.

DBAT1

CCC

1N4004

0.1 µF

0.22 µF

0.1 µF

VCC filter capacitor.

Filter capacitor.

CF1

CF2

Filter capacitor.

dc Profile

RIPROG

RIREF

5.76 kΩ

28.7 kΩ

1%

1/16 W

With RIREF, fixes dc current limit.

With RIPROG, fixes dc current limit.

Ringing/Ring Trip

CRT

1.0 µF

20%

1%

10 V

Ring trip filter capacitor.

Ring trip filter resistor.

RRT1

RRT2

CFB1

100 kΩ

150 kΩ

0.01 µF

1/16 W

100 V

20%

With CFB2, slows rate of battery reversal. Sets crest factor

of balanced power ring signal.

CFB2

0.01 µF

20%

100 V

With CFB1, slows rate of battery reversal. Sets crest factor

of balanced power ring signal.

ac Interface

RGX

4750 Ω

5 kΩ

1%

5%

1/16 W

10 V

Sets T/R to VITR transconductance.

Compensation resistor.

Compensation capacitor.

ac/dc separation.

RCR

CCC1

CTX

150 pF

0.1 µF

69.8 kΩ

20%

1%

CC1

dc blocking capacitor.

CC2

10 V

1/16 W

dc blocking capacitor.

With RGP and RRCV, sets termination impedance and

receive gain.

RT3

RT6

49.9 kΩ

100 kΩ

60.4 kΩ

1%

1/16 W

With RX, sets transmit gain.

With RT6, sets transmit gain.

With RX, sets hybrid balance.

With RGP and RT3, sets termination impedance and

receive gain.

RX

RHB1

RRCV

RGP

26.7 kΩ

17.6 kΩ

1%

1/16 W

With RRCV and RT3, sets termination impedance and

receive gain.

Optional. Compensates for input offset at RCVN/RCVP.

RGN Optional

Note: TX = 0 dBm, RX = 0 dBm, termination impedance = 600 Ω, hybrid balance = 600 Ω.

Agere Systems Inc.

33

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

ac Interface Using First-Generation Codec

ac Applications (continued)

Design Examples (continued)

R^GX/RTGS/CGS (ZTG): These components give gain

shaping to get good gain flatness. These components

are a scaled version of the specified complex termina-

tion impedance.

First-Generation Codec ac Interface Network—

Complex Termination

Note for pure (600 Ω) resistive terminations, compo-

nents R^TGSand CGS are not used. Resistor RGX is used

and is still 4750 Ω.

The following reference circuit shows the complete

SLIC schematic for interface to the Agere T7504 first-

generation codec for the German complex termination

impedance. For this example, the ac interface was

designed for a 220 Ω + (820 Ω || 115 nF) complex ter-

mination and hybrid balance with transmit gain and

receive gain set to 0 dBm.

R^X/RT6: With other components set, the transmit gain

(for complex and resistive terminations) R^Xand RT6 are

varied to give specified transmit gain.

R^T3/RRCV/RGP: For both complex and resistive termina-

tions, the ratio of these resistors sets the receive gain.

For resistive terminations, the ratio of these resistors

sets the return loss characteristic. For complex termi-

nations, the ratio of these resistors sets the low-fre-

quency return loss characteristic.

Complex Termination Impedance Design Example

The gain shaping necessary for a complex termination

impedance may be done by shaping across the Ax

amplifier at nodes ITR and VTX.

C^N/RN1/RN2: For complex terminations, these compo-

nents provide high-frequency compensation to the

return loss characteristic.

Complex termination is specified in the form:

R2

For resistive terminations, these components are not

used and RCVN is connected to ground via a resistor.

R1

C

R^HB: Sets hybrid balance for all terminations.

5-6396(F)

Set Z^TG—gain shaping:

To work with this application, convert termination to the

form:

Z^TG= RGX || RTGS + CGS which is a scaled version of

Z^T/R(the specified termination resistance) in the

R¹´ || R2´ + C´ form.

R1´

R^GXmust be 4750 Ω to set SLIC transconductance to

300 V/A.

R2´ C´

5-6398(F)

R^GX= 4750 Ω

where:

At dc, CGS and C´ are open.

R^GX= M x R1´

R¹´ = R1 + R2

R1

-------

R2

R2´ =

(R1 + R2)

where M is the scale factor.

4750

--------------

M =

C´ =

²C

R2

R¹′

---------------------

R1 + R2

It can be shown:

R^TGS= M x R2´

and

C′

M

------

C^TGS=

34

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

ac Applications (continued)

Design Examples (continued)

ac Interface Using First-Generation Codec (continued)

RTGS CGS

Rx

RGX = 4750 Ω

–IT/R

318.25

0.1 µF

RT6

–

20

+

VTX

TXI

VITR

CODEC

OP AMP

CN

RT3

RHB

RN1

RCVN

RCVP

CODEC

OUTPUT

DRIVE

AMP

RRCV

RN2

RGP

5-6400.H (F)

Figure 15. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown)

Transmit Gain

Using R^EQ, calculate the desired transmit gain, taking

into account the impedance transformation:

Transmit gain will be specified as a gain from T/R to

PCM, T^X(dB). Since PCM is referenced to 600 Ω and

assumed to be 0 dB, and in the case of T/R being refer-

enced to some complex impedance other than 600 Ω

resistive, the effects of the impedance transformation

must be taken into account.

600

R^EQ

T^X(dB) = TX (specified[dB]) + 20log ----------

T^{X (specified[dB])}is the specified transmit gain. 600 Ω is the

impedance at the PCM, and R^EQis the impedance at

600

R^EQ

Tip and ring. 20log ---------- represents the power

Again, specified complex termination impedance at T/R

is of the form:

loss/gain due to the impedance transformation.

R2

Note in the case of a 600 Ω pure resistive termination

600

R1

at T/R 20log ---------- = 20log --------- = 0.

R^EQ600

C

Thus, there is no power loss/gain due to impedance

transformation and T^X(dB) = TX (specified[dB]).

5-6396(F)

First, calculate the equivalent resistance of this network

at the midband frequency of 1000 Hz.

Finally, convert T^X(dB) to a ratio, gtx:

T^X(dB) = 20log gtx

R^EQ=

2

(2 πf) C1 R1R2²+ R1 + R2

2 πfR2 C1

The ratio of RX/RT6 is used to set the transmit gain:

-----------------------------------------------------------------------------

--------------------------------------------------

+

2

1 + (2 πf) R2 C1

RX

RT6

318.25

20

1

M

----------

= g^tx• ----------------- • ---- with a quad Agere codec

such as T7504:

R^X< 200 kΩ

Agere Systems Inc.

35

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Hybrid Balance

ac Applications (continued)

Design Examples (continued)

Set the hybrid cancellation via R^HB.

RX

grcv × gtx

------------------------

R^HB=

ac Interface Using First-Generation Codec (contin-

ued)

If a 5 V only codec such as the Agere T7504 is used,

dc blocking capacitors must be added as shown in Fig-

ure 16. This is because the codec is referenced to

2.5 V and the SLIC to ground—with the ac coupling, a

dc bias at T/R is eliminated and power associated with

this bias is not consumed.

Receive Gain

Ratios of R^RCV, RT3, RGP will set both the low-frequency

termination and receive gain for the complex case. In

the complex case, additional high-frequency compen-

sation, via C^N, RN1, and RN2, is needed for the return

loss characteristic. For resistive termination, C^N, RN1,

and R^N2are not used and RCVN is tied to ground via a

resistor.

Typically, values of 0.1 µF to 0.47 µF capacitors are

used for dc blocking. The addition of blocking capaci-

tors will cause a shift in the return loss and hybrid bal-

ance frequency response toward higher frequencies,

degrading the lower-frequency response. The lower

the value of the blocking capacitor, the more pro-

nounced the effect is, but the cost of the capacitor is

lower. It may be necessary to scale resistor values

higher to compensate for the low-frequency response.

This effect is best evaluated via simulation. A PSPICE^®

model for the L9214 is available.

Determine the receive gain, g^rcv, taking into account the

impedance transformation in a manner similar to trans-

mit gain.

R^EQ

R^X(dB) = RX (specified[dB]) + 20log

R^X(dB) = 20log grcv

----------

600

Design equation calculations seldom yield standard

component values. Conversion from the calculated

value to standard value may have an effect on the ac

parameters. This effect should be evaluated and opti-

mized via simulation.

Then:

4

-----------------------------------------------

R^RCVRRCV

g^rcv=

--------------- ---------------

1 +

+

RT3

RGP

and low-frequency termination

2400

--------------------------------------------

Z^TER(low)=

+ 2RP + 36 Ω

R^T3

RT3

----------- ---------------

1 +

+

RGP RRCV

ZTER(low) is the specified termination impedance assum-

ing low frequency (C or C´ is open).

R^Pis the series protection resistor.

36 Ω is the typical internal feed resistance.

These two equations are best solved using a computer

spreadsheet.

Next, solve for the high-frequency return loss compen-

sation circuit, C^N, RN1, and RN2:

2RP

C^NRN2 = ------------ CG RTGP

2400

R^TGS

-------------

2400

2R^P

RN1 = RN2 ------------

– 1

RTGP

There is an input offset voltage associated with nodes

RCVN and RCVP. To minimize the effect of mismatch

of this voltage at T/R, the equivalent resistance to ac

ground at RCVN should be approximately equal to that

at RCVP. Refer to Figure 16 (with dc blocking capaci-

tors). To meet this requirement, R^N2= RGP || RT3.

36

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

ac Applications (continued)

Design Examples (continued)

ac Interface Using First-Generation Codec (continued)

Blocking Capacitors

RTGS

CGS

Rx

RGX = 4750 Ω

–IT/R

CB1

0.1 µF

318.25

RT6

RT3

–

20

+

VTX

TXI

VITR

CODEC

OP AMP

CN

RHB

CB2

RN1

RCVN

RCVP

RRCV

RGP

2.5 V

RN2

CODEC

OUTPUT

DRIVE

AMP

5-6401.G (F)

Figure 16. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex

Termination Impedance

Agere Systems Inc.

37

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

ac Applications (continued)

Design Examples (continued)

ac Interface Using First-Generation Codec (continued)

RPWR

2.0 kΩ

VBAT1

VCC

CVBAT1

CVBAT2

CCC

RRT1

133 kΩ

DBAT1

0.1 µF

CRT

1 µF

VBAT1

BGND

VBAT2 VCC AGND ICM TRGDET

ITR

ground key

not used

R^TGS

RTFLT

RGX

1.74 kΩ

RRT2

4750 Ω

CGS

12 nF

75 kΩ

VTX

TXI

DCOUT

R^IPROG

CTX

0.1 µF

5.76 kΩ

R^X

115 kΩ

IPROG (ILOOP = 25 mA)

IREF

GSX

R^IREF

R^T6

C^C1

28.7 kΩ

40.6 kΩ 0.1 µF

VITR

–

L9214A

CN

120 pF

VFXIN

FUSIBLE RESISTOR

OR PTC

DX

+

RT3

PCM

R^HB1

PR

PT

+2.4 V

HIGHWAY

49.9 kΩ

30 Ω

113 kΩ

VFRO

AGERE

L7591

RCVP

RCVN

VBAT1

DR

RRCV

59.0 kΩ

C^C2

0.1 µF

R^N1

127 kΩ

30 Ω

FSE

FSEP

MCLK

SYNC

AND

CLOCK

RGP

54.9 kΩ

FUSIBLE RESISTOR

OR PTC

R^N2

47.5 kΩ

CF1

CF2

FB1

FB2

NSTAT B3 B2 B1 B0

FROM/TO CONTROL

CONTROL

INPUTS

ASEL

CF1

0.22 µF

CFB1

C^FB2

0.01 µF

CF2

1/4 T7504

CODEC

0.01 µF

0.1 µF

12-3535.m (F)

Figure 17. Agere T7504 First-Generation Codec; Complex Termination with Power Control Resistor (3 REN

Configuration)

Table 21. L9214 Parts List for Agere T7504 First-Generation Codec; Complex Termination with Power

Control Resistor

Name

Value Tolerance

Rating

Function

Fault Protection

RPT

30 Ω

1%

—

Fusible or Protection resistor.

PTC

RPR

30 Ω

Fusible or Protection resistor.

PTC

Protector

Agere

L7591

—

Secondary protection.

38

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Applications (continued)

Design Examples (continued)

ac Interface Using First-Generation Codec (continued)

Table 21. L9214 Parts List for Agere T7504 First-Generation Codec; Complex Termination with Power Con-

trol Resistor (continued)

Name

Value Tolerance

Rating

Function

Power Supply

CVBAT1

CVBAT2

DBAT1

CCC

0.1 µF

20%

—

100 V

50 V

—

VBAT filter capacitor.

0.1 µF

1N4004

0.1 µF

0.22 µF

0.1 µF

2.0 kΩ

VBAT filter capacitor. |VBAT2| < |VBAT1|.

Reverse current.

20%

5%

10 V

100 V

2 W

VCC filter capacitor.

CF1

Filter capacitor.

CF2

Filter capacitor.

RPWR

dc Profile

RIPROG

RIREF

Power control resistor, provides single battery supply operation.

5.76 kΩ

28.7 kΩ

1%

1/16 W With RIREF, fixes dc current limit.

1/16 W With RIPROG, fixes dc current limit.

Ringing/Ring Trip

CRING

RRT1

RRT2

CFB1

1.0 µF

133 kΩ

75 kΩ

20%

1%

10 V

Ring trip filter capacitor.

1/16 W Ring trip filter resistor.

1%

0.01 µF

20%

100 V

With CFB2, slows rate of battery reversal. Sets crest factor of bal-

anced power ring signal.

CFB2

0.01 µF

20%

100 V

With CFB1, slows rate of battery reversal. Sets crest factor of bal-

anced power ring signal.

ac Interface

RGX

4750 Ω

1.74 kΩ

12 nF

1%

1/16 W Sets T/R to VITR transconductance.

1/16 W Gain shaping for complex termination.

RTGS

CGS

5%

10 V

Gain shaping for complex termination.

ac/dc separation.

CTX

0.1 µF

20%

1%

CC1

0.1 µF

dc blocking capacitor.

CC2

0.1 µF

dc blocking capacitor.

RT3

49.9 kΩ

40.2 kΩ

115 kΩ

113 kΩ

59.0 kΩ

54.9 kΩ

120 pF

127 kΩ

47.5 kΩ

1/16 W With RGP and RRCV, sets termination impedance and receive gain.

1/16 W With RX, sets transmit gain.

RT6

1%

RX

1%

1/16 W With RT6, sets transmit gain.

RHB1

RRCV

RGP

1%

1/16 W With RX, sets hybrid balance.

1%

1/16 W With RGP and RT3, sets termination impedance and receive gain.

1/16 W With RRCV and RT3, sets termination impedance and receive gain.

1%

CN

20%

1%

10 V

High frequency compensation.

RN1

1/16 W High frequency compensation.

RN2

1%

1/16 W High frequency compensation, compensate for dc offset at

RCVP/RCVN.

Note: TX = 0 dBm, RX = 0 dBm, termination impedance = 220 Ω + (820 Ω || 115 nF), hybrid balance = 220 Ω + (820 Ω || 115 nF).

Agere Systems Inc.

39

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

ac Applications (continued)

Design Examples (continued)

Third-Generation Codec ac Interface Network—Complex Termination

The following reference circuit shows the complete SLIC schematic for interface to the Agere T8536 third-genera-

tion codec. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that no external

components are required in the ac interface to provide a dc termination impedance or for stability. Please see the

T8535/6 data sheet for information on coefficient programming.

VBAT1

VBAT2 VCC

CVBAT1

CVBAT2

CCC

RRT1

133 kΩ

CCC1

820 pF

DBAT1

0.1 µF 0.1 µF

BGND

0.1 µF

RCR

2 kΩ

C^RT

1 µF

VBAT1

VBAT2 VCC

AGND ICM TRGDET

ITR

ground key

not used

RTFLT

RGX

RRT2

4750 Ω

75 kΩ

VTX

DCOUT

R^IPROG

CTX

5.76 kΩ

0.1 µF

IPROG (ILOOP = 25 mA)

IREF

TXI

CC1

0.1 µF

R^IREF

28.7 kΩ

VITR

VFXI

DX0

DR0

FUSIBLE RESISTOR

OR PTC

L9214G

PCM

HIGHWAY

PR

PT

DX1

DR1

50 Ω

AGERE

L7591

VBAT1

VF^ROP

VF^RON

RCVP

RCVN

50 Ω

FUSIBLE RESISTOR

OR PTC

SYNC

AND

CLOCK

FS

BCLK

B3

B2

SLIC5a

SLIC4a

CF1

CF2

FB1

FB2

NSTAT B3 B2 B1 B0

CF1

B1

B0

SLIC3a

SLIC2a

CFB1

0.01 µF

C^FB2

0.01 µF

0.22 µF

DGND

V^DD

CF2

0.1 µF

FROM/TO

CONTROL

NSTAT

SLIC0a

V^DD

1/4 T8536

CODEC

12-3534.Z1 (F)

Figure 18. Third-Generation Codec ac Interface Network; Complex Termination (3 REN Configuration)

40

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

ac Applications (continued)

Design Examples (continued)

Third-Generation Codec ac Interface Network—Complex Termination (continued)

Table 22. L9214 Parts List for Agere T8536 Third-Generation Codec Meter Pulse Application ac and dc

Parameters; Fully Programmable

Name

Value

Tolerance

Rating

Function

Fault Protection

RPT

RPR

30 Ω

1%

—

Fusible orPTC Protection resistor*.

Protector

Agere L7591

—

Secondary protection.

Power Supply

CVBAT1

CVBAT2

DBAT1

0.1 µF

1N4004

0.1 µF

0.22 µF

0.1 µF

20%

—

100 V

50 V

—

VBAT filter capacitor.

VBAT filter capacitor. |VBAT2| < |VBAT1|.

Reverse current.

CCC

20%

10 V

100 V

VCC filter capacitor.

Filter capacitor.

CF1

CF2

Filter capacitor.

dc Profile

RIPROG

RIREF

5.76 kΩ

28.7 kΩ

1%

1/16 W

With RIREF, fixes dc current limit.

With RIPROG, fixes dc current limit.

Ringing/Ring Trip

CRT

1.0 µF

20%

1%

10 V

Ring trip filter capacitor.

Ring trip filter resistor.

RRT1

RRT2

CFB1

133 kΩ

75 kΩ

1/16 W

100 V

1%

0.01 µF

20%

With CFB2, slows rate of battery reversal. Sets crest fac-

tor of balanced power ring signal.

CFB2

0.01 µF

20%

100 V

With CFB1, slows rate of battery reversal. Sets crest fac-

tor of balanced power ring signal.

ac Interface

RGX

4750 Ω

10 kΩ

1%

5%

1/16 W

10 V

Sets T/R to VITR transconductance.

Compensation resistor.

Compensation capacitor.

ac/dc separation.

RCR

CCC1

270 pF

0.1 µF

20%

CTX

10 V

CC1

10 V

dc blocking capacitor.

* For loop stability, increase to 50 Ω minimum if synthesizing 900 Ω or 900 Ω + 2.16 µF termination impedance.

Agere Systems Inc.

41

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Outline Diagrams

28-Pin SOG

Note: The dimensions in these outline diagrams are intended for informational purposes only. For detailed draw-

ings to assist your design efforts, please contact your Agere Sales Representative.

L

N

B

1

PIN #1 IDENTIFIER ZONE

W

H

SEATING PLANE

0.10

0.61

0.51 MAX

1.27 TYP

0.28 MAX

Package Dimensions

Number Maximum Maximum Width Maximum Width MaximumHeight

Package

Description

of Pins

N

Length

L

Without Leads Including Leads

Above Board

H

B

W

SOG (small outline gull-wing)

28

18.11

7.62

10.64

2.67

5-4414

42

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Outline Diagrams (continued)

32-Pin PLCC

Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-

ics to assist your design efforts, please contact your Agere Sales Representative.

12.446 ± 0.127

11.430 ± 0.076

PIN #1 IDENTIFIER

ZONE

4

1

30

5

29

13.970

± 0.076

14.986

± 0.127

13

21

14

20

3.175/3.556

SEATING PLANE

0.10

0.38 MIN

TYP

1.27 TYP

0.330/0.533

5-3813r2 (F)

Agere Systems Inc.

43

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Outline Diagrams (continued)

48-Pin MLCC

Dimensions are in millimeters.

Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-

ics to assist your design efforts, please contact your Agere Sales Representative.

The exposed pad on the bottom of the package will be at V^BAT1potential.

C

7.00

6.75

CL

3.50

3.375

0.50 BSC

1

2

3

DETAIL A

VIEW FOR EVEN TERMINAL/SIDE

6.75

7.00

PIN #1

IDENTIFIER ZONE

0.18/0.30

0.00/0.05

SECTION C–C

DETAIL A

0.65/0.80

1.00 MAX

12°

SEATING PLANE

0.08

0.20 REF

0.01/0.05

11 SPACES @

0.50 = 5.50

0.24/0.60

0.18/0.30

0.13/0.23

0.24/0.60

0.20/0.45

5.10

± 0.15

3

2

1

0.30/0.45

EXPOSED PAD

0.50 BSC

0195

44

Agere Systems Inc.

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Outline Diagrams (continued)

48-Pin MLCC, JEDEC MO-220 VKKD-2

Dimensions are in millimeters.

Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-

ics to assist your design efforts, please contact your Agere Sales Representative.

The exposed pad on the bottom of the package will be at V^BAT1potential.

7.00

CL

3.50

PIN #1

IDENTIFIER ZONE

0.50 BSC

3.50

INDEX AREA

DETAIL A

VIEW FOR EVEN TERMINAL/SIDE

(7.00/2 x 7.00/2)

7.00

0.18

0.23

0.18

TOP VIEW

SIDE VIEW

0.23

1.00 MAX

SEATING PLANE

0.08

0.20 REF

DETAIL B

0.02/0.05

11 SPACES @

0.50 = 5.50

DETAIL A

0.18/0.30

0.30/0.50

2.50/2.625

5.00/5.25

3

2

1

EXPOSED PAD

0.50 BSC

DETAIL B

BOTTOM VIEW

0195

Agere Systems Inc.

45

L9214A/G

Low-Cost Ringing SLIC

Preliminary Data Sheet

October 2001

Ordering Information

Device Part No.

LUCL9214AAJ-D

LUCL9214AAJ-DT

LUCL9214AAU-D

LUCL9214AAU-DT

LUCL9214ARG-D

Description

Package

Comcode

SLIC Gain = 8

28-Pin SOG*, Dry-bagged

108553892

28-Pin SOG*, Dry-bagged, Tape and Reel

32-Pin PLCC, Dry-bagged

108553900

108697905

108697913

109058636

109058644

108560723

108560731

108698309

108698317

109058651

109058669

32-Pin PLCC, Dry-bagged, Tape and Reel

48-Pin MLCC, Dry-bagged

LUCL9214ARG-DT SLIC Gain = 8

48-Pin MLCC, Dry-bagged, Tape and Reel

28-Pin SOG*, Dry-bagged

LUCL9214GAJ-D

LUCL9214GAJ-DT

LUCL9214GAU-D

SLIC Gain = 2

28-Pin SOG*, Dry-bagged, Tape and Reel

32-Pin PLCC, Dry-bagged

LUCL9214GAU-DT SLIC Gain = 2

LUCL9214GRG-D SLIC Gain = 2

LUCL9214GRG-DT SLIC Gain = 2

32-Pin PLCC, Dry-bagged, Tape and Reel

48-Pin MLCC, Dry-bagged

48-Pin MLCC, Dry-bagged, Tape and Reel

* Please contact your Agere Sales Representative for availability.

UL is a trademark of Underwriters Laboratories, Inc.

IEC is a registered trademark of the International Electrotechnical Commission.

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

PSPICE is a registered trademark of MicroSim Corporation.

Telcordia Technologies is a trademark of Bell Communications Research, Inc.

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET:

E-MAIL:

http://www.agere.com

docmaster@agere.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA:

Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

Tel. (44) 7000 624624, FAX (44) 1344 488 045

EUROPE:

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

October 2001

DS01-144ALC (Replaces DS00-342ALC)


型号：	LUCL9214GAJ-D
厂家：	AGERE SYSTEMS
描述：	Low-Cost Ringing SLIC 低成本振铃SLIC
文件：	总46页 (文件大小：750K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LUCL9214GAJ-D [AGERE]

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