LUCL9215AAU-D [AGERE]
Short-Loop Sine Wave Ringing SLIC; 短环正弦波振铃SLIC
| 型号： | LUCL9215AAU-D |
| 厂家： | 
AGERE SYSTEMS |
| 描述： | Short-Loop Sine Wave Ringing SLIC |
| 文件： | 总50页 (文件大小：1068K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
September 2001
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Applications
Introduction
■ Voice over Internet Protocol (VoIP)
The Agere Systems Inc. L9215 is a subscriber line
interface circuit that is optimized for short-loop,
power-sensitive applications. This device provides
the complete set of line interface functionality (includ-
ing power ringing) needed to interface to a subscriber
loop. This device has the capability to operate with a
VCC supply of 3.3 V or 5 V and is designed to mini-
mize external components required at all device
interfaces.
■ Cable Modems
■ Terminal Adapters (TA)
■ Wireless Local Loop (WLL)
■ Telcordia Technologies™ GR-909 Access
■ Network Termination (NT)
■ Key Systems
Features
Description
■ Onboard ringing generation
This device is optimized to provide battery feed, ring-
ing, and supervision on short-loop plain old tele-
phone service (POTS) loops.
■ Three ringing input options:
— Sine wave
— PWM
— Logic level square wave
This device provides power ring to the subscriber
loop through amplification of a low-voltage input. It
provides forward and reverse battery feed states, on-
hook transmission, a low-power scan state, meter
pulse states, and a forward disconnect state.
■ Flexible VCC options:
— 5 V or 3.3 V VCC
— No –5 V required
■ Battery switch to minimize off-hook power
The device requires a VCC and battery to operate.
VCC may be either a 5 V or a 3.3 V supply. The ring-
ing signal is derived from the high-voltage battery. A
battery switch is included to allow for use of a lower-
voltage battery in the off-hook mode, thus minimizing
short-loop off-hook power.
■ 11 operating states:
— Scan mode for minimal power dissipation
— Forward and reverse battery active
— On-hook transmission states
— Meter pulse states
— Ring mode
— Disconnect mode
Loop closure, ring trip, and ground key detectors are
available. The loop closure detector has a fixed
threshold with hysteresis. The ring trip detector
requires a single-pole filter, thus minimizing external
components required.
■ Ultralow on-hook power:
— 27 mW scan mode
— 42 mW active mode
■ Two SLIC gain options to minimal external compo-
This device supports meter pulse applications. Meter
pulse is injected into a dedicated meter pulse input.
Injection of meter pulse onto tip and ring is controlled
by the device’s logic input pin.
nents in codec interface
■ Loop start, ring trip, and ground key detectors
■ Software- or hardware-controllable current-limit
and overhead voltage
Both the dc current limit and overhead voltage are
programmable. Programming may be done by exter-
nal resistors or an applied voltage source. If the volt-
age source is programmable, the current limit and
overhead may be set via software control.
■ Meter pulse compatible
■ 32-pin PLCC package
■ 48-pin MLCC package
The device is offered with two gain options. This
allows for an optimized codec interface, with minimal
external components regardless of whether a first-
generation or a programmable third-generation
codec is used.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Table of Contents
Contents
Page
Contents
Page
Introduction..................................................................1
Features....................................................................1
Applications...............................................................1
Description................................................................1
Features ......................................................................4
Description...................................................................4
Architecture Diagram...................................................7
Pin Information ............................................................8
Operating States........................................................11
State Definitions ........................................................12
Forward Active........................................................12
Reverse Active........................................................12
Forward Active with PPM........................................12
Reverse Active with PPM........................................12
Scan........................................................................12
On-Hook Transmission—Forward Battery..............12
On-Hook Transmission with PPM—Forward
Loop Range ........................................................... 26
Battery Reversal Rate............................................ 26
Supervision............................................................... 27
Loop Closure.......................................................... 27
Ring Trip ................................................................ 27
Tip or Ring Ground Detector.................................. 27
Power Ring ............................................................ 27
Sine Wave Input Signal and Sine Wave Power
Ring Signal Output............................................ 28
PWM Input Signal and Sine Wave Power
Ring Signal Output............................................ 30
5 V VCC Operation ............................................... 31
3.3 V VCC Operation ............................................ 32
Square Wave Input Signal and Trapezoidal
Power Ring Signal Output ................................ 32
Periodic Pulse Metering (PPM) ................................ 34
ac Applications ......................................................... 34
ac Parameters........................................................ 34
Codec Types.......................................................... 34
First-Generation Codecs ..................................... 34
Third-Generation Codecs.................................... 34
ac Interface Network .............................................. 34
Design Examples................................................... 35
First-Generation Codec ac Interface
Battery....................................................................13
On-Hook Transmission—Reverse Battery..............13
On-Hook Transmission with PPM—Reverse
Battery....................................................................13
Disconnect ..............................................................13
Ring.........................................................................13
Thermal Shutdown..................................................13
Absolute Maximum Ratings.......................................14
Electrical Characteristics ...........................................15
Test Configurations ...................................................22
Applications ...............................................................24
Power Control .........................................................24
dc Loop Current Limit..............................................24
Overhead Voltage...................................................25
Active Mode .........................................................25
On-Hook Transmission Mode...............................26
Scan Mode ...........................................................26
Ring Mode............................................................26
Network—Resistive Termination ...................... 35
Example 1, Real Termination.............................. 36
First-Generation Codec ac Interface
Network—Complex Termination....................... 39
Complex Termination Impedance Design
Example............................................................ 39
ac Interface Using First-Generation Codec......... 39
Set ZTG—Gain Shaping....................................... 39
Transmit Gain...................................................... 40
Receive Gain....................................................... 41
Hybrid Balance.................................................... 41
Blocking Capacitors............................................. 42
Third-Generation Codec ac Interface
Network—Complex Termination....................... 45
Outline Diagrams...................................................... 47
32-Pin PLCC .......................................................... 47
48-Pin MLCC.......................................................... 48
48-Pin MLCC, JEDEC MO-220 VKKD-2................ 49
Ordering Information................................................. 50
2
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Table of Contents (continued)
Page Tables
Figures
Page
Figure 1. Architecture Diagram ...................................7
Figure 2. 32-Pin PLCC Diagram .................................8
Figure 3. 48-Pin MLCC Diagram .................................8
Figure 4. Basic Test Circuit ......................................22
Figure 5. Metallic PSRR ...........................................23
Figure 6. Longitudinal PSRR ....................................23
Figure 7. Longitudinal Balance .................................23
Figure 8. ac Gains ....................................................23
Figure 9. Ringing Waveform Crest Factor = 1.6 .......27
Figure 10. Ringing Waveform Crest Factor = 1.2 .....27
Figure 11. Ring Mode Typical Operation...................28
Figure 12. RINGIN Operation ....................................29
Figure 13. L9215/16 Ringing Input Circuit Selection
Table for Square Wave and PWM
Inputs........................................................30
Figure 14. Modulation Waveforms ............................31
Figure 15. 5 V PWM Signal Amplitude ......................31
Figure 16. Ringing Output on RING, with
Vcc = 5 V..................................................31
Figure 17. 3.3 V PWM Signal Amplitude ...................32
Figure 18. Ringing Output on RING, with
Table 1. Pin Descriptions ........................................... 9
Table 2. Control States ............................................ 11
Table 3. Supervision Coding .................................... 11
Table 4. Recommended Operating
Characteristics ........................................... 14
Table 5. Thermal Characteristics.............................. 14
Table 6. Environmental Characteristics.................... 15
Table 7. 5 V Supply Currents ................................... 15
Table 8. 5 V Powering .............................................. 15
Table 9. 3.3 V Supply Currents................................. 16
Table 10. 3.3 V Powering ......................................... 16
Table 11. 2-Wire Port .............................................. 17
Table 12. Analog Pin Characteristics ...................... 18
Table 13. ac Feed Characteristics ........................... 19
Table 14. Logic Inputs and Outputs (VCC = 5 V) ...... 20
Table 15. Logic Inputs and Outputs (VCC = 3.3 V) ... 20
Table 16. Ringing Specifications ............................. 21
Table 17. Ring Trip .................................................. 21
Table 18. PPM ......................................................... 21
Table 19. Typical Active Mode On- to Off-Hook
Tip/Ring Current-Limit Transient
Vcc = 3.1 V...............................................32
Figure 19. Square Wave Input Signal and Trapezoidal
Power Ring Signal Output........................32
Figure 20. Crest Factor vs. Battery Voltage...............33
Figure 21. Crest Factor vs. R (kΩ) ............................33
Figure 22. ac Equivalent Circuit ................................36
Figure 23. Agere T7504 First-Generation Codec
Resistive Termination; Nonmeter Pulse
Application................................................37
Figure 24. Interface Circuit Using First-Generation
Codec (Blocking Capacitors
Not Shown) ..............................................40
Figure 25. ac Interface Using First-Generation
Codec (Including Blocking Capacitors)
Response ................................................ 25
Table 20. FB1 and FB2 Values vs. Typical
Ramp Time .............................................. 26
Table 21. Onset of Power Ringing Clipping
VCC = 5 V, Cinput = 0.47 µF .................... 29
Table 22. Onset of Power Ringing Clipping
VCC = 3.1 V, Cinput = 0.47 µF ................. 29
Table 23. Signal and Component Selection Chart ... 30
Table 24. Parts List L9215; Agere T7504
First-Generation Codec Resistive Termina-
tion; Nonmeter Pulse Application ............ 38
Table 25. Parts List L9215; Agere T7504
First-Generation Codec Complex Termina-
tion; Meter Pulse Application ................... 44
Table 26. Parts List L9215; Agere T8536
for Complex Termination Impedance ......42
Figure 26. Agere T7504 First-Generation Codec
Complex Termination; Meter Pulse
Third-Generation Codec Meter Pulse
Application ac and dc Parameters;
Application................................................43
Figure 27. Third-Generation Codec ac Interface
Network; Complex Termination ...............45
Fully Programmable ................................ 46
Agere Systems Inc.
3
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
■ Adjustable current limit:
— 10 mA to 70 mA programming range
Features
■ Onboard balanced ringing generation:
— No ring relay
■ Overhead voltage:
— Clamped typically <51 V differentially
— Clamped maximum <56.5 V single-ended
— Adjustable in active mode
— No bulk ring generator required
— 15 Hz to 70 Hz ring frequency supported
— Sine wave input-sine wave output
— PWM input-sine wave output
— Square wave input-trapezoidal output
■ Thermal shutdown protection with hysteresis
■ Longitudinal balance:
— ETSI/ITU-T balance
— Telcordia Technologies GR-909 balance
■ Power supplies requirements:
— VCC talk battery and ringing battery required
— No –5 V supply required
■ Meter pulse compatible:
— Dedicated meter pulse signal input
— On-hook transmission of PPM
— No high-voltage positive supply required
■ Flexible Vcc options:
— 5 V or 3.3 V VCC operation
— 5 V or 3.3 V VCC interchangeable and transparent
to users
■ ac interface:
— Two SLIC gain options to minimize external com-
ponents required for interface to first- or third-gen-
eration codecs
■ Logic-controlled battery switch:
— Sufficient dynamic range for direct coupling to
codec output
— Minimize off-hook power dissipation
■ Minimal external components required
■ 32-pin PLCC package/48-pin MLCC package
■ 90 V CBIC-S technology
■ 11 operating states:
— Forward active, VBAT2 applied
— Polarity reversal active, VBAT2 applied
— On-hook transmission, VBAT1 applied
— On-hook transmission polarity reversal, VBAT1
applied
Description
— PPM active forward active, VBAT2 applied
— PPM active polarity reversal active, VBAT2 applied
— PPM active on-hook transmission, VBAT1 applied
— PPM active on-hook transmission polarity rever-
sal, VBAT1 applied
— Scan
— Forward disconnect
— Ring mode
The L9215 is designed to provide battery feed, ringing,
and supervision functions on short plain old telephone
service (POTS) loops. This device is designed for
ultralow power in all operating states.
The L9215 offers 11 operating states. The device
assumes use of a lower-voltage talk battery, a higher-
voltage ringing battery, and a VCC supply.
The L9215 requires only a positive VCC supply. No
–5 V supply is needed. The L9215 can operate with a
VCC of either 5 V or 3.3 V, allowing for greater user flex-
ibility. The choice of VCC voltage is transparent to the
user; the device will function with either supply voltage
connected.
■ Unlatched parallel data control interface
■ Ultralow SLIC power:
— Scan 38 mW (VCC = 5 V)
— Forward/reverse active 57 mW (VCC = 5 V)
— Scan 27 mW (VCC = 3.3 V)
— Forward/reverse active 42 mW (VCC = 3.3 V)
Two batteries are used:
■ Supervision:
1. A high-voltage ring battery (VBAT1).
— Loop start, fixed threshold with hysteresis
— Ring trip, single-pole ring trip filtering, fixed thresh-
old as a function of battery voltage
— Common-mode current for ground key applica-
tions, user-adjustable threshold
VBAT1 is a maximum –75 V. VBAT1 is used for power
ring signal amplification and for scan and on-hook
transmission modes. This supply is current limited
to approximately the maximum power ringing cur-
rent, typically 50 mA.
2. A lower-voltage talk battery (VBAT2).
VBAT2 is used for active mode powering.
4
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
This feature eliminates the need for a separate external
ring relay, associated external circuitry, and a bulk ring-
ing generator. See the Applications section of this data
sheet for more information.
Description (continued)
Forward and reverse battery active modes are used for
off-hook conditions. Since this device is designed for
short-loop applications, the lower-voltage VBAT2 is
applied during the forward and reverse active states.
Battery reversal is quiet, without breaking the ac path.
Rate of battery reversal may be ramped to control
switching time.
PPM is injected at the PPMIN pin (ac coupled). This is a
high-impedance input that controls the PPM differential
voltage on tip and ring. The PPM signal may be
present at this pin at all times; however, PPM will only
be transmitted to tip and ring during a PPM active
mode. There are forward and reverse active, and for-
ward and reverse on-hook transmission modes with
PPM active.
The magnitude of the overhead voltage in the forward
and reverse active modes has a typical default value of
6.0 V, allowing for an undistorted signal of 3.14 dBm
into 900 Ω. This overhead can be increased to accom-
modate higher signal levels and/or PPM. The ring trip
detector is turned off during active modes to conserve
power.
No PPM shaping is done by the device. It is assumed
that a shaped PPM input is presented to PPMIN.
The maximum allowed PPM current at the 200 Ω ac
meter pulse load to avoid saturation of the device’s
internal AAC amplifier is 3 mArms. This signal level
is sufficient to provide a minimum 200 mVrms to the
200 Ω PPM load under maximum specified dc loop
conditions. Above 3 mArms PPM current, external
meter pulse rejection may be required. See the Appli-
cations section of this data sheet for more information if
on-hook transmission of PPM is required. Sufficient
overhead to accommodate on-hook transmission must
be programmed by the user at the OVH input.
Because on-hook transmission is not allowed in the
scan mode, an on-hook transmission mode is defined.
This mode is functionally similar to the active mode,
except the tip ring voltage is derived from the higher
VBAT1 rather than VBAT2.
In the on-hook transmission modes with a primary bat-
tery whose magnitude is greater than a nominal
51 V, the magnitude of the tip-to-ground and ring-to-
ground voltage is clamped at less than 56.5 V.
Both the ring trip and loop closure supervision func-
tions are included. The loop closure has a fixed typical
10.5 mA on- to off-hook threshold in the active mode
and a fixed 11.5 mA on- to off-hook threshold from the
scan mode. In either case, there is a 2 mA hysteresis.
The ring trip detector requires only a single-pole filter at
the input, minimizing external components. The ring
trip threshold at a given battery voltage is fixed. Typical
ring trip threshold is 42.5 mA for a –75 V VBAT1.
To minimize on-hook power, a low-power scan mode is
available. In this mode, all functions except off-hook
supervision are turned off to conserve power. On-hook
transmission is not allowed in the scan mode.
In the scan mode with a primary battery whose magni-
tude is greater than a nominal 51 V, the magnitude of
the tip-to-ground and ring-to-ground voltage is clamped
at less than 56.5 V.
A forward disconnect mode is provided, where all cir-
cuits are turned off and power is denied to the loop.
The device offers a ring mode, in which a power ring
signal is provided to the tip/ring pair. During the ring
mode, a user-supplied, low-voltage ring signal (ac cou-
pled) is input to the device’s RINGIN input. This signal is
amplified to produce the power ring signal. This signal
may be a sine wave or filtered square wave to produce
a sine wave on trapezoidal output. Ring trip detector
and common-mode current detector are active during
the ring mode.
Agere Systems Inc.
5
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
The L9215 uses a voltage feed-current sense architec-
ture; thus, the transmit gain is a transconductance. The
L9215 transconductance is set via a single external
resistor, and this device is designed for optimal perfor-
mance with a transconductance set at 300 V/A.
Description (continued)
A common-mode current detector for tip or ring ground
detection is included for ground key applications. The
threshold is user programmable via external resistors.
See the Applications section of this data sheet for more
information on supervision functions.
The L9215 offers an option for a single-ended to differ-
ential receive gain of either 8 or 2. These options are
mask programmable at the factory and are selected by
choice of code.
Upon reaching the thermal shutdown temperature, the
device will enter an all off mode. Upon cooling, the
device will re-enter the state it was in prior to thermal
shutdown. Hysteresis is built in to prevent oscillation.
A receive gain of 8 is more appropriate when choosing
a first-generation type codec where termination imped-
ance, hybrid balance, and overall gains are set by
external analog filters. The higher gain is typically
required for synthesization of complex termination
impedance.
Longitudinal balance is consistent with European ETSI
and North American GR-909 requirements. Specifica-
tions are given in Table 6.
Data control is via a parallel unlatched control scheme.
A receive gain of 2 is more appropriate when choosing
a third-generation type codec. Third-generation codecs
will synthesize termination impedance and set hybrid
balance and overall gains. To accomplish these func-
tions, third-generation codecs typically have both ana-
log and digital gain filters. For optimal signal-to-noise
performance, it is best to operate the codec at a higher
gain level. If the SLIC then provides a high gain, the
SLIC output may be saturated causing clipping distor-
tion of the signal at tip and ring. To avoid this situation,
with a higher gain SLIC, external resistor dividers are
used. These external components are not necessary
with the lower gain offered by the L9215. See the Appli-
cations section of this data sheet for more information.
The dc current limit is programmable in the active
modes via an applied voltage source. The voltage
source may be an external independent voltage
source. Also, the programming voltage may be derived
via a resistor divider network from the VREF SLIC out-
put. A programmable external voltage source may be
used to provide software control of the loop closure
threshold. Design equations for this feature are given in
the dc Loop Current Limit section of the Applications
section of this data sheet.
Programming range is 10 mA to 70 mA with VCC =
5 V and 10 mA to 45 mA with VCC = 3.3 V. Program-
ming accuracy is ±8% at 22 mA to 28 mA current limit.
The L9215 is internally referenced to 1.5 V. This refer-
ence voltage is output at the VREF output of the device.
The SLIC output VITR is also referenced to 1.5 V;
therefore, it must be ac coupled to the codec input.
However, the SLIC inputs RCVP/RCVN are floating
inputs. If there is not feedback from RCVP/RCVN to
VITR, RCVP/RCVN may be directly coupled to the
codec output. If there is feedback from RCVP/RCVN to
VITR, RCVP/RCVN must be ac coupled to the codec
output.
Circuitry is added to the L9215 to minimize the inrush
of current from the VCC supply and to the battery supply
during an on- to off-hook transition, thus saving in
power supply design cost. See the Applications section
of this data sheet for more information.
Overhead is programmable in the active modes via an
applied voltage source. The voltage source may be an
external independent voltage source. Also the pro-
gramming voltage may be derived via a resistor divider
network from the VREF SLIC output.
The L9215 is packaged in a 32-pin PLCC surface-
mount package and a 48-pin MLCC ultrasmall surface-
mount package. Use L9215A for gain of 8 applications
and L9215G for gain of 2 applications.
If the overhead is not programmed, a default overhead
of approximately 6.0 V is achieved. This is adequate
for a 3.14 dBm overload into 900 Ω. For the default
overhead, pin OVH is connected to ground. See the
Applications section of this data sheet for more infor-
mation.
Transmit and receive gains have been chosen to mini-
mize the number of external components required in
the SLIC-codec ac interface, regardless of the choice
of codec.
6
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Architecture Diagram
AGND VCC BGND VBAT2 VBAT1
VPROG
NSTAT
RTFLT DCOUT
VREF
CURRENT
LIMIT
RING
TRIP
AND
VITR
POWER
INRUSH
CONTROL
B = 20
LOOP
CLOSURE
AAC
1.5 V
BAND-GAP
COMMON-
MODE
CURRENT
DETECTOR
ICM
REFERENCE
TXI
ITR
VITR
RECTIFIER
X1
TRGDET
–
(ITR/306)
OUT
AX
VTX
CF2
OVH
CF1
VREF
+
–
+
RFT
PT
+1
18 Ω
ITR
X1
VREG
TIP/RING
CURRENT
SENSE
FB2
FB1
–
RCVN
RCVP
ITR
+
–
GAIN
RFR
PR
–1
+
ac INTERFACE
18 Ω
9215A GAIN = 4
9215G GAIN = 1
VREG
PPM
2x
PARALLEL
DATA
INTERFACE
RINGING
27.5x
RINGIN
PPMIN
BR B0 B1 B2
12-3530.g (F)
Figure 1. Architecture Diagram
Agere Systems Inc.
7
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Pin Information
4
3
2
1
32
31
30
RCVN
RINGIN
PPMIN
5
6
7
29
28
27
BR
B0
B1
OVH
DCOUT
VPROG
CF2
8
26
25
24
23
22
21
B2
L9215A/G
9
PR
32-PIN PLCC
PT
10
11
12
13
FB2
FB1
ICM
CF1
RTFLT
14
15
16
17
18
19
20
Figure 2. 32-Pin PLCC Diagram
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
BR
B0
RINGINN
PPMIN
NC
2
3
B1
NC
4
B2
5
NC
PR
NC
PT
OVH
DCOUT
6
L9215A/G
48-PIN MLCC
7
VPROG
NC
8
9
NC
NC
FB1
FB2
CF2
CF1
NC
10
11
12
RTFLT
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. 48-Pin MLCC Diagram
8
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Pin Information (continued)
Table 1. Pin Descriptions
32-Pin
PLCC
48-Pin
MLCC
Symbol Type
Name/Function
1
43
NSTAT
NC
O
Loop Closure Detector Output—Ring Trip Detector Output. When
low, this logic output indicates that an off-hook condition exists or ring-
ing is tripped.
2
3, 4, 8, 11,
14, 17, 18,
21, 27, 28,
30, 32, 37,
39, 42, 44, 46
—
No Connection.
3
4
5
6
45
47
48
1
VITR
RCVP
RCVN
RINGIN
O
I
Transmit ac Output Voltage. Output of internal AAC amplifier. This
output is a voltage that is directly proportional to the differential ac tip/
ring current.
Receive ac Signal Input (Noninverting). This high-impedance input
controls to ac differential voltage on tip and ring. This node is a floating
input.
I
Receive ac Signal Input (Inverting). This high-impedance input con-
trols to ac differential voltage on tip and ring. This node is a floating
input.
I
Power Ring Signal Input. ac-couple to a sine wave or lower crest fac-
tor low-voltage ring signal. The input here is amplified to provide the
full-power ring signal at tip and ring. This signal may be applied contin-
uously, even during nonringing states.
7
8
2
5
PPMIN
OVH
I
I
Receive PPM Signal Input. ac-couple to a 12 kHz or 16 kHz PPM sig-
nal. The input here is amplified to provide the differential PPM voltage
on tip and ring. This signal may be applied continuously, even during
non-PPM modes.
Overhead Voltage Program Input. Connect a voltage source to this
point to program the overhead voltage. Voltage source may be external
or derived via a resistor divider from VREF. A programmable external
voltage source may be used to provide software control of the over-
head voltage. If a resistor or voltage source is not connected, the over-
head voltage will default to a nominal 6.0 V. If the default overhead is
desired, connect this pin to ground.
9
6
7
DCOUT
VPROG
O
I
dc Output Voltage. This output is a voltage that is directly proportional
to the absolute value of the differential tip/ring current. This is used to
set ring trip threshold.
10
Current-Limit Program Input. Connect a voltage source to this point
to program the dc current limit. Voltage source may be external or
derived via a resistor divider from VREF. A programmable external volt-
age source may be used to provide software control of the current limit.
11
12
13
9
CF2
CF1
—
—
—
Filter Capacitor. Connect a capacitor from this node to ground.
Filter Capacitor. Connect a capacitor from this node to CF2.
10
12
RTFLT
Ring Trip Filter. Connect this lead to DCOUT via a resistor and to
AGND with a capacitor to filter the ring trip circuit to prevent spurious
responses. A single-pole filter is needed.
14
13
VREF
O
SLIC Internal Reference Voltage. Output of internal 1.5 V reference
voltage.
Agere Systems Inc.
9
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued)
32-Pin 48-Pin Symbol Type
PLCC MLCC
Name/Function
15
16
15
16
AGND
VCC
GND Analog Signal Ground.
PWR Analog Power Supply. User choice of 5 V or 3.3 V nominal power or sup-
ply.
17
18
19
20
19
20
22
23
VBAT1
VBAT2
PWR Battery Supply 1. High-voltage battery.
PWR Battery Supply 2. Lower-voltage battery.
GND Battery Ground. Ground return for the battery supplies.
BGND
TRGDET
O
Tip/Ring Ground Detect. When high, this open collector output indicates
the presence of a ring ground or a tip ground. This supervision output may
be used in ground key or common-mode fault detection applications.
21
22
23
24
25
24
25
26
29
31
ICM
FB2
FB1
PT
I
Common-Mode Current Sense. To program tip or ring ground sense
threshold, connect a resistor to VCC and connect a capacitor to AGND to fil-
ter 50/60 Hz. If unused, the pin is connected to ground.
—
—
Polarity Reversal Slowdown Capacitor. Connect a capacitor from this
node for controlling rate of battery reversal. If ramped battery reversal is
not desired, this pin is left open.
Polarity Reversal Slowdown Capacitor. Connect a capacitor from this
node for controlling rate of battery reversal. If ramped battery reversal is
not desired, this pin is left open.
I/O Protected Tip. The output drive of the tip amplifier and input to the loop
sensing circuit. Connect to loop through overvoltage and overcurrent pro-
tection.
PR
I/O Protected Ring. The output drive of the ring amplifier and input to the loop
sensing circuit. Connect to loop through overvoltage and overcurrent pro-
tection.
Iu
26
27
28
29
30
33
34
35
36
38
B2
B1
State Control Input. These pins have an internal 60 kΩ pull-up.
B0
BR
ITR
I
Transmit Gain. Input to AX amplifier. Connect a resistor from this node to
VTX to set transmit gain. Gain shaping for termination impedance with a
COMBO I codec is also achieved with a network from this node to VTX.
31
32
40
41
VTX
TXI
O
I
ac Output Voltage. Output of internal AX amplifier. The voltage at this pin
is directly proportional to the differential tip/ring current.
ac/dc Separation. Input to internal AAC amplifier. Connect a 0.1 µF capac-
itor from this pin to VTX.
10
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Operating States
Table 2. Control States
B0
1
B1
1
B2
0
BR
1
State
Forward active
1
1
0
0
Forward active with PPM
Reverse active
1
0
0
1
1
0
0
0
Reverse active with PPM
1
1
1
1
On-hook transmission forward battery (in this state, the device will power up)
1
1
1
0
On-hook transmission with PPM forward battery
1
0
1
1
On-hook transmission reverse battery
1
0
1
0
On-hook transmission with PPM reverse battery
0
1
1
1
Scan
0
0
0
1
Disconnect
Ring
0
1
1
0
Table 3. Supervision Coding
NSTAT
TRGDET
0 = off-hook or ring trip or TSD.
0 = no ring or tip ground
1 = on-hook and no ring trip and no 1 = ring or tip ground
TSD or DISCONNECT state.
Agere Systems Inc.
11
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Reverse Active with PPM
State Definitions
■ Pin PR is positive with respect to PT.
■ VBAT2 is applied to tip/ring drive amplifiers.
■ Loop closure and common-mode detect are active.
■ Ring trip detector is turned off to conserve power.
■ PPM input is on.
Forward Active
■ Pin PT is positive with respect to PR.
■ VBAT2 is applied to tip/ring drive amplifiers.
■ Loop closure and common-mode detect are active.
■ Ring trip detector is turned off to conserve power.
■ PPM input is off.
■ Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω and may be
increased via OVH to accommodate higher-voltage
meter pulse signals.
■ Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω and may be
increased via OVH.
Scan
Reverse Active
■ Except for loop closure, all circuits (including ring trip
and common-mode detector) are powered down.
■ Pin PR is positive with respect to PT.
■ VBAT2 is applied to tip/ring drive amplifiers.
■ Loop closure and common-mode detect are active.
■ Ring trip detector is turned off to conserve power.
■ PPM input is off.
■ On-hook transmission is disabled.
■ Pin PT is positive with respect to PR and VBAT1 is
applied to tip/ring.
■ The tip-to-ring on-hook differential voltage will be typ-
ically between –44 V and –51 V with a –70 V primary
battery.
■ Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω and may be
increased via OVH.
On-Hook Transmission—Forward Battery
■ Pin PT is positive with respect to PR.
Forward Active with PPM
■ VBAT1 is applied to tip/ring drive amplifiers.
■ Pin PT is positive with respect to PR.
■ VBAT2 is applied to tip/ring drive amplifiers.
■ Loop closure and common-mode detect are active.
■ Ring trip detector is turned off to conserve power.
■ PPM input is on.
■ Supervision circuits, loop closure, and common-
mode detect are active.
■ Ring trip detector is turned off to conserve power.
■ On-hook transmission is allowed.
■ The tip-to-ring on-hook differential voltage will be
between –41 V and –49 V with a –70 V primary bat-
tery.
■ Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω and may be
increased via OVH to accommodate higher-voltage
meter pulse signals.
■ PPM is off.
12
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
■ Ring trip detector is turned off to conserve power.
■ On-hook transmission is allowed.
State Definitions (continued)
On-Hook Transmission with PPM—Forward
Battery
■ The tip-to-ring on-hook differential voltage will be
between –41 V and –49 V with a –70 V primary bat-
tery.
■ Pin PT is positive with respect to PR.
■ PPM is on.
■ VBAT1 is applied to tip/ring drive amplifiers.
■ Supervision circuits, loop closure, and common-
mode detect are active.
Disconnect
■ Ring trip detector is turned off to conserve power.
■ On-hook transmission is allowed.
■ The tip/ring amplifiers and all supervision are turned
off.
■ The SLIC goes into a high-impedance state.
■ NSTAT is forced high (on-hook).
■ The tip-to-ring on-hook differential voltage will be
between –41 V and –49 V with a –70 V primary bat-
tery.
■ PPM is on.
Ring
■ Power ring signal is applied to tip and ring.
■ Input waveform at RINGIN is amplified.
On-Hook Transmission—Reverse Battery
■ Pin PR is positive with respect to PT.
■ Ring trip supervision and common-mode current
supervision are active; loop closure is inactive.
■ VBAT1 is applied to tip/ring drive amplifiers.
■ Supervision circuits, loop closure, and common-
mode detect are active.
■ Overhead voltage is reduced to typically 4 V, regard-
less of programming on OVH, and current limit set at
VPROG is disabled.
■ Ring trip detector is turned off to conserve power.
■ On-hook transmission is allowed.
■ Current is limited by saturation current of the amplifi-
ers themselves, typically 100 mA at 125 °C.
■ The tip-to-ring on-hook differential voltage will be
between –41 V and –49 V with a –70 V primary bat-
tery.
Thermal Shutdown
■ PPM is off.
■ Not controlled via truth table inputs.
■ NSTAT is forced low (off-hook) during this state
On-Hook Transmission with PPM—Reverse
Battery
■ This mode is caused by excessive heating of the
device, such as may be encountered in an extended
power cross situation.
■ Pin PR is positive with respect to PT.
■ VBAT1 is applied to tip/ring drive amplifiers.
■ Supervision circuits, loop closure, and common-
mode detect are active.
Agere Systems Inc.
13
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Absolute Maximum Ratings (@ TA = 25 °C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Symbol
Min
–0.5
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
7.0
Unit
V
dc Supply (VCC)
—
Battery Supply (VBAT1)
—
–80
V
Battery Supply (VBAT2)
—
—
VBAT1
VCC + 0.5
VCC + 0.5
125
V
Logic Input Voltage
—
–0.5
–0.5
–40
–40
5
V
Logic Output Voltage
—
V
Operating Temperature Range
Storage Temperature Range
Relative Humidity Range
—
—
°C
°C
%
V
150
—
95
Ground Potential Difference (BGND to AGND)
PT or PR Fault Voltage (dc)
PT or PR Fault Voltage (10 x 1000 µs)
—
—
±1
VPT, VPR
VBAT – 5
3
V
VPT, VPR VBAT – 15
15
V
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when
powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the
device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.
Table 4. Recommended Operating Characteristics
Parameter
5 V dc Supplies (VCC)
Min
—
Typ
5.0
3.3
–70
—
Max
5.25
—
Unit
V
3 V dc Supplies (VCC)
3.13
–60
–12
–40
V
High Office Battery Supply (VBAT1)
Auxiliary Office Battery Supply (VBAT2)
Operating Temperature Range
–75
VBAT1
85
V
V
25
°C
Table 5. Thermal Characteristics
Parameter
Min
Typ
Max
Unit
Thermal Protection Shutdown (Tjc)
150
165
—
°C
32-pin PLCC Thermal Resistance Junction to Ambient (θJA)1, 2
Natural Convection 2S2P Board
Natural Convection 2S0P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board
:
—
—
—
—
35.5
50.5
31.5
42.5
—
—
—
—
°C/W
°C/W
°C/W
°C/W
48-pin MLCC Thermal Resistance Junction to Ambient (θJA)1, 2
—
38
—
°C/W
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Airflow, PCB board layers, and other factors can greatly affect this parameter.
14
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics
Table 6. Environmental Characteristics
Parameter
Min
–40
5
Typ
—
Max
85
951
Unit
°C
Temperature Range
Humidity Range1
—
%RH
1. Not to exceed 26 grams of water per kilogram of dry air.
Table 7. 5 V Supply Currents
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 5 V.
Parameter
Min
Typ
Max
Unit
Supply Currents (scan state; no loop current):
IVCC
IVBAT1
IVBAT2
—
—
—
4.30
0.24
3
4.80
0.35
6
mA
mA
µA
Supply Currents (forward/reverse active; no loop current, with or without PPM,
VBAT2 applied):
IVCC
IVBAT1
—
—
—
5.95
25
1.2
7.0
85
1.40
mA
µA
mA
IVBAT2
Supply Currents (on-hook transmission mode; no loop current, with or without
PPM, VBAT1 applied):
IVCC
IVBAT1
IVBAT2
—
—
—
6.0
1.5
1.5
7.0
1.9
6
mA
mA
µA
Supply Currents (disconnect mode):
IVCC
IVBAT1
IVBAT2
—
—
—
2.7
15
3.5
3.75
110
25
mA
µA
µA
Supply Currents (ring mode; no load):
IVCC
IVBAT1
IVBAT2
—
—
—
5.9
1.8
2
6.5
2.2
6
mA
mA
µA
Table 8. 5 V Powering
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 5 V.
Parameter
Min
—
Typ
38
Max
46
Unit
mW
mW
Power Dissipation (scan state; no loop current)
Power Dissipation (forward/reverse active; no loop current, with or without PPM)
—
57
64
Power Dissipation (on-hook transmission mode; no loop current, with or without
PPM, VBAT1 applied)
—
—
—
135
14
165
23
mW
mW
mW
Power Dissipation (disconnect mode)
Power Dissipation (ring mode; no load)
156
184
Agere Systems Inc.
15
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 9. 3.3 V Supply Currents
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 3.3 V.
Parameter
Min
Typ
Max
Unit
Supply Currents (scan state; no loop current):
IVCC
IVBAT1
IVBAT2
—
—
—
3.2
0.24
3
3.6
0.35
6
mA
mA
µA
Supply Currents (forward/reverse active; no loop current, with/without PPM,
VBAT2 applied):
IVCC
IVBAT1
—
—
—
4.8
25
1.2
5.7
85
1.4
mA
µA
mA
IVBAT2
Supply Currents (on-hook transmission mode; no loop current, with/without
PPM, VBAT1 applied):
IVCC
IVBAT1
IVBAT2
—
—
—
4.9
1.5
1.5
5.7
1.9
6
mA
mA
µA
Supply Currents (disconnect mode):
IVCC
IVBAT1
IVBAT2
—
—
—
1.8
8
2
2.5
110
25
mA
µA
µA
Supply Currents (ring mode; no loop current):
IVCC
IVBAT1
IVBAT2
—
—
—
4.70
1.8
2
5.4
2.2
6
mA
mA
µA
Table 10. 3.3 V Powering
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 3.3 V.
Parameter
Min
Typ
Max
Unit
Power Dissipation (scan state; no loop current)
—
27
36.5
mW
Power Dissipation (forward/reverse active; no loop current, with/without PPM,
VBAT2 applied)
—
—
—
—
42
53
151
15
mW
mW
mW
mW
Power Dissipation (on-hook transmission mode; no loop current, with/without
PPM, VBAT1 applied)
121
6.5
Power Dissipation (disconnect mode)
Power Dissipation (ring mode; no loop current)
141
172
16
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 11. 2-Wire Port
Parameter
Tip or Ring Drive Current = dc + Longitudinal + Signal Currents + PPM
Tip or Ring Drive Current = Ringing + Longitudinal
Signal Current
Min
105
65
Typ
—
Max
—
Unit
mAp
—
—
mAp
10
—
—
mArms
mArms
Longitudinal Current Capability per Wire (Longitudinal current is indepen-
dent of dc loop current.)
8.5
15
—
PPM Signal Current = 1.25 VMAX into 200 Ω ac
Ringing Current (RLOAD = 1386 Ω + 40 µF)
Ringing Current Limit (RLOAD = 100 Ω)
6.25
29
—
—
—
—
—
50
mArms
mArms
mAp
—
dc Loop Current—ILIM (RLOOP = 100 Ω):
Programming Range (VCC = 5 V)
Programming Range (VCC = 3.3 V)
Voltage at VPROG
15
15
0.194
—
—
—
70
45
1.01
mA
mA
V
dc Current Variation (current limit 22 mA to 28 mA)
dc Current Variation (current limit 70 mA)
—
—
—
—
—
50
±8
±10
—
%
%
Ω
dc Feed Resistance (does not include protection resistors)
Open Loop Voltages:
Scan Mode:
|VBAT1| > 51 V |VTIP| – |VRING|
PR to Battery Ground
PT to Battery Ground
OHT Mode:
44
—
—
51
—
—
—
56.5
56.5
V
V
|VBAT1| > 51 V (VOH = 0 V) |VTIP| – |VRING|
PR to Battery Ground
PT to Battery Ground
Active Mode (VOH = 0 V):
|PT – PR| – |VBAT2|
41
—
—
49
—
—
—
56.5
56.5
V
V
5.65
—
6.0
4.0
6.5
—
V
V
Ring Mode:
|PT – PR| – |VBAT1|
Agere Systems Inc.
17
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 11. 2-Wire Port (continued)
Parameter
Min
Typ
Max
Unit
Loop Closure Threshold:
Active/On-hook Transmission Modes
Scan Mode
—
—
10.5
11.5
—
—
mA
mA
Loop Closure Threshold Hysteresis:
VCC = 5 V
VCC = 3.3 V
—
—
2
1
—
—
mA
mA
Ground Key:
Differential Detector Threshold
Detection
5
50
8
—
10
—
mA
ms
Longitudinal to Metallic Balance at PT/PR
Test Method: Q552 (11/96) Section 2.1.2 and IEEE® 455:
300 Hz to 600 Hz
52
52
—
—
—
—
dB
dB
600 Hz to 3.4 kHz
Metallic to Longitudinal (harm) Balance:
200 Hz to 1000 Hz
100 Hz to 4000 Hz
40
40
—
—
—
—
dB
dB
PSRR 500 Hz—3000 Hz:
VBAT1, VBAT2
VCC (5 V operation)
45
35
—
—
—
—
dB
dB
Table 12. Analog Pin Characteristics
Parameter
Min
Typ
Max
Unit
TXI (input impedance)
—
100
—
kΩ
Output Offset (VTX)
Output Offset (VITR)
—
—
±300
±10
—
—
—
—
±10
±100
—
mV
mV
µA
Output Drive Current (VTX)
Output Drive Current (VITR)
Output Voltage Swing:
Maximum (VTX, VITR)
Minimum (VTX)
—
µA
AGND
AGND + 0.25
AGND + 0.35
—
—
—
—
—
20
VCC
VCC – 0.5
VCC – 0.4
±50
V
V
V
mA
kΩ
pF
Minimum (VITR)
Output Short-circuit Current
Output Load Resistance
Output Load Capacitance
—
10
—
—
—
RCVN and RCVP:
Input Voltage Range (VCC = 5 V)
Input Voltage Range (VCC = 3.3 V)
Input Bias Current
0
0
—
—
—
0.05
VCC – 0.5
VCC – 0.3
—
V
V
µA
Differential PT/PR Current Sense (DCOUT):
Gain (PT/PR to DCOUT)
Offset Voltage at ILOOP = 0
—
–20
67
—
—
20
V/A
mV
18
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 13. ac Feed Characteristics
Parameter
Min
Typ
Max
Unit
ac Termination Impedance1
150
600
1400
Ω
Total Harmonic Distortion (200 Hz—4 kHz)2:
Off-hook
On-hook
—
—
—
—
0.3
1.0
%
%
Transmit Gain (f = 1004 Hz, 1020 Hz, current limit)3:
PT/PR Current to VITR
300 – 3%
300
300 + 3%
V/A
Receive Gain, f = 1004 Hz, 1020 Hz Open Loop:
RCVP or RCVN to PT—PR (gain of 8 option, L9215A)
RCVP or RCVN to PT—PR (gain of 2 option, L9215G)
7.76
1.94
8
2
8.24
2.06
—
—
Gain vs. Frequency (transmit and receive)2 600 Ω Termination,
1004 Hz, 1020 Hz Reference:
200 Hz—300 Hz
300 Hz—3.4 kHz
3.4 kHz—20 kHz
–0.3
–0.05
–3.0
—
0
0
0
0.05
0.05
0.05
2.0
dB
dB
dB
dB
20 kHz—266 kHz
—
Gain vs. Level (transmit and receive)2 0 dBV Reference:
–55 dB to +3.0 dB
–0.05
0
0.05
dB
Idle-channel Noise (tip/ring) 600 Ω Termination:
Psophometric
C-Message
3 kHz Flat
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
Idle-channel Noise (VTX) 600 Ω Termination:
Psophometric
C-Message
3 kHz Flat
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between
150 Ω and 1400 Ω can be synthesized.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750 Ω, the recommended value. Positive cur-
rent is defined as the differential current flowing from PT to PR.
Agere Systems Inc.
19
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 14. Logic Inputs and Outputs (VCC = 5 V)
Parameter
Symbol
Min
Typ
Max
Unit
Input Voltages:
Low Level
High Level
VIL
VIH
–0.5
2.0
0.4
2.4
0.7
VCC
V
V
Input Current:
Low Level (VCC = 5.25 V, VI = 0.4 V)
High Level (VCC = 5.25 V, VI = 2.4 V)
IIL
IIH
—
—
—
—
±50
±50
µA
µA
Output Voltages (open collector with internal pull-up resistor):
Low Level (VCC = 4.75 V, IOL = 200 µA)
High Level (VCC = 4.75 V, IOH = –20 µA)
VOL
VOH
0
2.4
0.2
—
0.4
VCC
V
V
Table 15. Logic Inputs and Outputs (VCC = 3.3 V)
Parameter
Symbol
Min
Typ
Max
Unit
Input Voltages:
Low Level
High Level
VIL
VIH
–0.5
2.0
0.2
2.5
0.5
VCC
V
V
Input Current:
Low Level (VCC = 3.46 V, VI = 0.4 V)
High Level (VCC = 3.46 V, VI = 2.4 V)
IIL
IIH
—
—
—
—
±50
±50
µA
µA
Output Voltages (open collector with internal pull-up resistor):
Low Level (VCC = 3.13 V, IOL = 200 µA)
High Level (VCC = 3.13 V, IOH = –5 µA)
VOL
VOH
0
2.2
0.2
—
0.5
VCC
V
V
20
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 16. Ringing Specifications
Parameter
Min
Typ
Max
Unit
RINGIN (This input is ac coupled through 0.47 µF.):
Input Voltage Swing
Input Impedance
0
—
—
100
VCC
—
V
kΩ
Ring Signal Isolation:
PT/PR to VITR
Ring Mode
—
60
—
dB
Ring Signal Isolation:
RINGIN to PT/PR
Nonring Mode
—
80
—
dB
Ringing Voltage (5 REN 1380 Ω + 40 µF load, 100 Ω loop, 2 x 50 Ω protection
resistors, –70 V battery)
40
40
—
—
—
—
Vrms
Vrms
Ringing Voltage (3 REN 2310 Ω + 24 µF load, 250 Ω loop, 2 x 50 Ω protection
resistors, –70 V battery)
Ring Signal Distortion:
5 REN 1380 Ω, 40 µF Load, 100 Ω Loop
3 REN 2310 Ω, 24 µF Load, 250 Ω Loop
—
—
3
3
—
—
%
%
Differential Gain:
RINGIN to PT/PR—No Load
—
55
—
—
Table 17. Ring Trip
Parameter
Min
Typ
Max
Unit
Ring Trip (NSTAT = 0): Loop Resistance (total)
Ring Trip (NSTAT = 1): Loop Resistance (total)
Trip Time (f = 20 Hz)
100
—
—
—
—
600
10
Ω
kΩ
ms
—
100
Ringing will not be tripped by the following loads:
■ 10 kΩ resistor in parallel with a 6 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
■ 100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
Table 18. PPM
Parameter
Min
Typ
Max
Unit
PPM Source*:
Frequency (f1)
Frequency (f2)
Input Signal
11.88
15.80
0
12
16
1.1
12.12
16.20
1.25
kHz
kHz
Vrms
Input Impedance
—
5.5
—
50
6
—
6.5
—
5
kΩ
dB
dB
%
Signal Gain (2.2 Vrms maximum at PT/PR)
Isolation
60
—
Harmonic Distortion
—
*
PPM signal should be ac coupled through 10 nF.
Agere Systems Inc.
21
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Test Configurations
RTFLT
RINGIN
PPMIN
RINGIN
0.1 µF
0.47 µF
383 kΩ
PPMIN
26.7 kΩ
10 nF
DCOUT
30 Ω
RCVP
RCVN
VITR
RCV
RCV
VITR
TIP
PR
60.4 kΩ
69.8 kΩ
RLOOP
100 Ω/600 Ω
0.1 µF
30 Ω
RING
PT
L9215
BASIC TEST
CIRCUIT
0.1 µF
OVH
TXI
VPROG
VREF
FB2
VTX
4750 Ω
ITR
BR
B0
B1
B2
BR
B0
B1
B2
FB1
CF1
0.1 µF
0.1 µF
CF2
VBAT2
VBAT1
BGND VCC
AGND
ICM TRGDET NSTAT
0.1 µF
0.1 µF
82.3 kΩ
0.1 µF
0.1 µF
VBAT2
VBAT1
VCC
VCC
12-3531.E (F)
Figure 4. Basic Test Circuit
22
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Test Configurations (continued)
100 µF
VBAT OR VCC
TIP
VS
100 Ω
368 Ω
368 Ω
+
DISCONNECT
BYPASS CAPACITOR
BASIC
TEST CIRCUIT
4.7 µF
VM
–
VS
RING
VBAT OR
VCC
100 µF
TIP
+
VT/R
–
BASIC
TEST CIRCUIT
VS
VM
LONGITUDINAL BALANCE = 20log
600 Ω
12-2584.c (F)
RING
Figure 7. Longitudinal Balance
VS
VT/R
PSRR = 20log
12-2582.c (F)
VITR
Figure 5. Metallic PSRR
PT
+
BASIC
TEST CIRCUIT
VT/R
600 Ω
VBAT OR VCC
–
RCV
DISCONNECT
BYPASS CAPACITOR
100 Ω
4.7 µF
PR
RCV
VS
VS
VBAT OR
VCC
VXMT
VT/R
GXMT =
67.5 Ω
VT/R
VRCV
TIP
GRCV =
10 µF
BASIC
TEST CIRCUIT
12-2587.G (F)
67.5 Ω
56.3 Ω
+
Figure 8. ac Gains
RING
VM
–
10 µF
VS
VM
PSRR = 20log
12-2583.b (F)
Figure 6. Longitudinal PSRR
Agere Systems Inc.
23
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Thus, if the total power dissipated in the SLIC is less
than 1.29 W, it will not enter the thermal shutdown
state. Total SLIC power is calculated as:
Applications
Power Control
Total PD = maximum battery • maximum current
Under normal device operating conditions, power dissi-
pation on the device must be controlled to prevent the
device temperature from rising above the thermal shut-
down and causing the device to shut down. Power dis-
sipation is highest with higher battery voltages, higher
current limit, and under shorter dc loop conditions.
Additionally, higher ambient temperature will also
reduce thermal margin.
limit + SLIC quiescent power.
For the L9215, the worst-case SLIC on-hook active
power is 76.4 mW. Thus,
Total off-hook power = (ILOOP)(current-limit
tolerance)*(VBATAPPLIED) + SLIC on-hook power
Total off-hook power = (0.030 A)(1.08) * (21) +
76.4 mW
Total off-hook power = 756.8 mW
To support required power ringing voltages, this device
is meant to operate with a high-voltage primary battery
(–65 V to –75 V typically). Thus, power control is nor-
mally achieved by use of the battery switch and an aux-
iliary lower absolute voltage battery. Operating
temperature range, maximum current limit, maximum
battery voltage, minimum dc loop length and protection
resistors values, airflow, and number of PC board lay-
ers will influence the overall thermal performance. The
following example illustrates typical thermal design
considerations.
The power dissipated in the SLIC is the total power dis-
sipation less the power that is dissipated in the loop.
SLIC PD = total power – loop power
Loop off-hook power = (ILOOP * 1.08)2 • (RLOOP(dc)
min + 2RHANDSET)
Loop off-hook power = (0.030 A)(1.08)2 • (20 Ω +
60 Ω + 200 Ω)
Loop off-hook power = 293.9 mW
SLIC off-hook power = Total off-hook power – loop
off-hook power
The thermal resistance of the 32-pin PLCC package is
typically 50.5 °C/W, which is representative of the natu-
ral airflow as seen in a typical switch cabinet with a
two-layer board.
SLIC off-hook power = 756.8 mW – 293.9 mW
SLIC off-hook power = 462.9 mW < 1.29 W
Thus, under the worst-case normal operating condi-
tions of this example, the thermal design, using the
auxiliary, is adequate to ensure the device is not driven
into thermal shutdown under worst-case operating con-
ditions.
The L9215 will enter thermal shutdown at a minimum
temperature of 150 °C. The thermal design should
ensure that the SLIC does not reach this temperature
under normal operating conditions.
For this example, assume a maximum ambient operat-
ing temperature of 85 °C, a maximum current limit of
30 mA, a maximum battery of –70 V, and an auxiliary
battery of –21 V. Assume a (worst-case) minimum dc
loop of 20 Ω of wire resistance, 30 Ω protection resis-
tors, and 200 Ω for the handset. Additionally, include
the effects of parameter tolerance.
dc Loop Current Limit
In the active modes, dc current limit is programmable
via an applied voltage source at the device’s VPROG
control input. The voltage source may be an external
voltage source or derived via a resistor divider network
from the VREF SLIC output or an external voltage
source. A programmable external voltage source may
be used to provide software control of the loop current
limit. The loop current limit (ILIM) is related to the VPROG
voltage at the onset of current limit by:
1. TTSD – TAMBIENT(max) = allowed thermal rise.
150 °C – 85 °C = 65 °C.
2. Allowed thermal rise = package thermal
impedance • SLIC power dissipation.
65 °C = 50.5 °C/W • SLIC power dissipation
SLIC power dissipation (PD) = 1.29 W.
ILIM (mA) = 67 (mA/V) * VPROG (V)
Note that there is a 12.5 kΩ slope to the I/V character-
istic in the current-limit region; thus, once in current
limit, the actual loop current will increase slightly, as
loop length decreases.
24
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Overhead Voltage
Applications (continued)
Active Mode
dc Loop Current Limit (continued)
Overhead is programmable in the active mode via an
applied voltage source at the device’s OVH control
input. The voltage source may be an external voltage
source or derived via a resistor divider network from
the VREF SLIC output or an external voltage source. A
programmable external voltage source may be used to
provide software control of the overhead voltage. The
overhead voltage (VOH) is related to the OVH voltage
by:
Note that the overall current-limit accuracy achieved
will not only be affected by the specified accuracy of
the internal SLIC current-limit circuit (accuracy associ-
ated with the 67 term), but also by the accuracy of the
voltage source and the accuracy of any external resis-
tor divider network used and voltage offsets due to the
specified input bias current. Tolerance of the current
limit is ±8%. If a resistor divider from VREF is used, it is
recommended that the sum of the two resistors be
greater than 100 kΩ.
VOH = 6.0 V + 5 * VOVH (V)
The above equations describe the active mode steady-
state current-limit response. There will be a transient
response of the current-limit circuit upon an on- to off-
hook transition. Typical active mode transient current-
limit response is given in Table 19.
Overall accuracy is determined by the accuracy of the
voltage source and the accuracy of any external resis-
tor divider network used and voltage offsets due to the
specified input bias current. If a resistor divider from
VREF is used, a lower magnitude resistor will give a
more accurate result due to a lower offset associated
with the input bias current; however, lower value resis-
tors will also draw more power from VREF.
Table 19. Typical Active Mode On- to Off-Hook Tip/
Ring Current-Limit Transient Response
Parameter
dc Loop Current:
Value
Unit
Note that a default overhead voltage of 6.0 V is
achieved by shorting input pin OVH to analog ground.
ILIM + 60
mA
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 5 ms
The default overhead provides sufficient headroom for
an on-hook transmission of a 3.14 dBm signal into
900 Ω.
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 50 ms
ILIM + 20
mA
mA
Overhead voltage may need to be increased to accom-
modate on-hook transmission of higher-voltage sig-
nals, such as meter pulse. The following example is
meant to illustrate the design procedure that can be fol-
lowed.
dc Loop Current:
Active Mode
ILIM
Assume we need on-hook transmission of a 1.0 Vrms
meter pulse into 200 Ω. Further, assume 50 Ω protec-
tion resistors are used.
RLOOP = 100 Ω On- to Off-hook
Transition t < 300 ms
VOH = 6.0 V + (1+ [2 * Rp]/200) * Vpeak
VOH = 6.0 + (1+ [2 * 50]/200) * 1 (1.414)
VOH = 8.121 V
Agere Systems Inc.
25
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
transmit direction at VITR is deactivated. However, if
the AX amplifier at VTX is active during the ring mode,
differential ring current may be sensed at VTX during
the ring mode.
Applications (continued)
Overhead Voltage (continued)
Active Mode (continued)
Loop Range
Adding 0.5 V for tolerance, the overhead needs to be
increased to (8.121 V + 0.5 V) = 8.621 V to allow for an
undistorted on-hook transmission of a 1 Vrms meter
pulse into 200 Ω. This is done by applying voltage to
pin VOH.
The dc loop range is calculated using:
VBAT2 – VOH
-------------------------------------
RL =
– 2RP – RDC
ILIMIT
VOH (V) = 6.0 V + 5 * VOVH (V)
8.621 V = 6 V + 5 * VOVH
VOVH = 0.5242 V
VBAT2 is typically applied under off-hook conditions for
power conservation and SLIC thermal considerations.
The L9215 is intended for short-loop applications and,
therefore, will always be in current limit during off-hook
conditions. However, note that the ringing loop length
rather than the dc loop length, will be the factor to
determine operating loop length.
Thus, a nominal 0.5242 V is applied to pin VOVH to
increase the overhead.
Scan Mode
If the magnitude of the primary battery is greater than
51 V, the magnitude of the open loop tip-to-ring open
loop voltage is clamped typically between 44 V and
51 V. If the magnitude of the primary battery is less
than a nominal 51 V, the overhead voltage will track the
magnitude of the battery voltage, i.e., the magnitude of
the open circuit tip-to-ring voltage will be 4 V to 6 V less
than battery. In the scan mode, overhead is unaffected
by VOVH.
Battery Reversal Rate
The rate of battery reverse is controlled or ramped by
capacitors FB1 and FB2. A chart showing FB1 and FB2
values versus typical ramp time is given below. Leave
FB1 and FB2 open if it is not desired to ramp the rate of
battery reversal.
Table 20. FB1 and FB2 Values vs. Typical Ramp
Time
On-Hook Transmission Mode
CFB1 and CFB2
Transition Time
If the magnitude of the primary battery is greater than
51 V, the magnitude of the open loop tip-to-ring open
loop voltage is clamped typically between 41 V and
49 V. If the magnitude of the primary battery is less
than a nominal 51 V, the overhead voltage will track the
magnitude of the battery voltage, i.e., the magnitude of
the open circuit tip-to-ring voltage will be 6 V to 8 V less
than battery. In the scan mode, overhead is unaffected
by VOVH.
0.01 µF
0.1 µF
0.22 µF
0.47 µF
1.0 µF
1.22 µF
1.3 µF
1.4 µF
1.6 µF
20 ms
220 ms
440 ms
900 ms
1.8 s
2.25 s
2.5 s
2.7 s
3.2 s
Ring Mode
In the ring mode, to maximize ringing loop length, the
overhead is decreased to the saturation of the tip ring
drive amplifiers, a nominal 4 V. The tip-to-ground volt-
age is 1 V, and the ring to VBAT1 voltage is 3 V. In the
ring mode, overhead is unaffected by VOVH.
During the ring mode, to conserve power the receive
input at RCVN/RCVP is deactivated. During the ring
mode, to conserve power, the ACC amplifier in the
26
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
is input to the device’s RINGIN input. This signal is
amplified to produce the balanced power ring signal.
The user may supply a sine wave input, PWM input, or
a square wave to produce sinusoidal or trapezoidal
ringing at tip and ring.
Supervision
The L9215 offers the loop closure and ring trip supervi-
sion functions. Internal to the device, the outputs of
these detectors are multiplexed into a single package
output, NSTAT. Additionally, a common-mode current
detector for tip or ring ground detection is included for
ground key applications.
Various crest factors are shown below for illustrative
purposes.
80
60
Loop Closure
40
The loop closure has a fixed typical 10.5 mA on- to off-
hook threshold in the active mode and a fixed 11.5 mA
on- to off-hook threshold from the scan mode. In either
case, there is a 2 mA hysteresis with VCC = 5 V and a
1 mA hysteresis with VCC = 3.3 V.
20
0
–20
–40
–60
–80
0.00 0.04 0.08 0.12 0.16 0.20
0.02 0.06 0.10 0.14 0.18
Ring Trip
TIME (s)
12-3346a (F)
The ring trip detector requires only a single-pole filter at
the input, minimizing external components. An R/C
combination of 383 kΩ and 0.1 µF, for a filter pole at
5.15 Hz, is recommended.
Note: Slew rate = 5.65 V/ms; trise = tfall = 23 ms; pwidth = 2 ms;
period = 50 ms.
Figure 9. Ringing Waveform Crest Factor = 1.6
The ring trip threshold is internally fixed as a function of
battery voltage and is given by:
80
60
RT (mA) = 67 * {(0.0045 * VBAT1) + 0.317}
where:
40
RT is ring trip current in mA.
20
VBAT1 is the magnitude of the ring battery in V.
There is a 6 mA to 8 mA hysteresis.
0
–20
–40
–60
Tip or Ring Ground Detector
–80
0.00 0.04 0.08 0.12 0.16 0.20
0.02 0.06 0.10 0.14 0.18
In the ground key or ground start applications, a com-
mon-mode current detector is used to indicate either a
tip- or ring-ground has occurred (ground key) or an off-
hook has occurred (ground start). The detection thresh-
old is set by connecting a resistor from ICM to VCC.
TIME (s)
12-3347a (F)
Note: Slew rate = 10.83 V/ms; trise = tfall = 12 ms; pwidth = 13 ms;
period = 50 ms.
Figure 10. Ringing Waveform Crest Factor = 1.2
170 x VCC/RICM (kΩ) = ITH (mA)
Additionally, a filter capacitor across RICM will set the
time constant of the detector. No hysteresis is associ-
ated with this detector.
Voltage applied to the load may be increased by using
a filtered square wave input to produce a lower crest
factor trapezoidal power ring signal at tip and ring.
Power Ring
The device offers a ring mode, in which a balanced
power ring signal is provided to the tip/ring pair. During
the ring mode, a user-supplied low-voltage ring signal
Agere Systems Inc.
27
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
11. Thus, the total voltage swing is 52 V (60 V to 8 V)
for a 1 V input, which is approximately the differential
gain of the device. Note that the tip and ring power ring
signals will swing around VBATTERY divided by two. In
this case, there is a –70 V battery so tip and ring swing
around –34 V.
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring
Signal Output
The low-voltage sine wave input is applied to the L9215
at pin RINGIN. This signal should be ac-coupled
through 0.47 µF. During the ring mode, the signal at
RINGIN is amplified and presented to the subscriber
loop. The differential gain from RINGIN to tip and ring is
a nominal 55.
0
VRING
VTIP
–20
–40
–60
When the device enters the ring mode, the tip/ring
overhead set at OVH and the scan clamp circuit is dis-
abled, allowing the voltage magnitude of the power ring
signal to be maximized. Additionally, in the ring mode,
the loop current limit is increased 2.5X the value set by
the VPROG voltage.
0.60 0.62
0.64
0.66
0.68
0.70
0.72
0.74
0.76
0.78 0.80
TIME
12-3573F
1.0
VRINGIN
0.5
The magnitude of the power ring voltage will be a func-
tion of the gain of the ring amplifier, the high-voltage
battery, and the input signal at RINGIN. The input range
of the signal at RINGIN is 0 V to Vcc. As the input volt-
age at RINGIN is increased, the magnitude of the power
ring voltage at tip and ring will increase linearly, per the
differential gain of 55, until the tip and ring drive amplifi-
ers begin to saturate. Once the tip and ring amplifiers
reach saturation, further increases of the input signal
will cause clipping distortion of the power ring signal at
tip and ring. The ring signal will appear balanced on tip
and ring. That is, the power ring signal is applied to
both tip and ring, with the signal on tip 180° out of
phase from the signal on ring.
0.0
–0.5
–1.0
0.60 0.62
0.64
0.66
0.68
0.70
TIME
0.72
0.74
0.76
0.78 0.80
12-3574F
Figure 11. Ring Mode Typical Operation
Figure 11 shows typical operation of the ring mode,
prior to saturation of the tip and ring drive amplifiers. A
–70 V battery is used with a 100 Ω loop and a 1 REN
load. The input signal is 1 V through a 0.47 µF capaci-
tor at RINGIN, (the input circuit is shown in Figure 12).
This produces a voltage swing from –34 V to –60 V on
ring and from –8 V to –34 V on tip, as shown in Figure
28
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)
It is recommended that the input level at RINGIN be adjusted so that the power ring signal at tip and ring is just at
the edge or slightly clipping. This gives maximum power transfer with minimal distortion of the sine wave. The tip
side will saturate at a nominal 1 V above ground. The ring side will saturate at a nominal 3 V above battery. The
input circuit for a sine wave along with waveforms to illustrate the tip and ring saturation is shown in Figure 12.
L9215
PT
GND
+1
1 V
3 V
RINGIN
27.5x
VTIP
0.47 µF
INPUT
71 V
VRING
–1
VBAT
TR
100 kΩ
VBAT = –75 V
12-3532.H(F)
Figure 12. RINGIN Operation
The point at which clipping of the power ring signal begins at tip and ring is a function of the battery voltage, the
input capacitor at RINGIN, and the input signal at RINGIN and Vcc. Typical characteristic conditions showing the
onset of clipping are given below.
Table 21. Onset of Power Ringing Clipping VCC = 5 V, Cinput = 0.47 µF
Input
T/R
VBAT1 (V)
–70.15
–68.06
–66.00
–64.08
–62.04
–60.05
Vrms (mV)
891
Vrms (V)
46.88
45.11
Gain
52.62
52.58
52.45
52.30
52.23
52.36
858
833
43.69
42.57
41.21
39.11
814
789
747
Table 22. Onset of Power Ringing Clipping VCC = 3.1 V, Cinput = 0.47 µF
Input T/R
VBAT1 (V)
–70.12
–68.07
–66.06
–64.01
–62.00
–60.00
Vrms (mV)
894
Vrms (V)
47.15
45.11
Gain
52.74
52.76
52.65
52.5
855
824
43.38
41.95
40.79
39.09
799
780
52.29
52.19
749
Agere Systems Inc.
29
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)
During nonring modes, the sinusoidal ringing waveform may be left on at RINGIN. Via the state table, the ring signal
will be removed from tip and ring even if the low-voltage input is still present at RINGIN. There are certain timing
considerations that should be made with respect to state changes which are detailed in the Switching Behavior of
L9215 Ringing SLIC Application Note.
PWM Input Signal and Sine Wave Power Ring Signal Output
A pulse-width modulated (PWM) signal may be used to provide the ringing input to RINGIN. The signal is applied
through a low-pass filter and ac-coupled into RINGIN as shown below. This approach gives a sine wave output at
tip and ring.
L9215/16
R1
C2
RINGIN
INPUT
C1
12-3578bF
Figure 13. L9215/16 Ringing Input Circuit Selection Table for Square Wave and PWM Inputs
Table 23. Signal and Component Selection Chart
VBAT
70 V
70 V
70 V
70 V
70 V
70 V
85 V
85 V
85 V
85 V
85 V
85 V
VCC
5 V
3 V
5 V
3 V
5 V
3 V
5 V
3 V
5 V
3 V
5 V
3 V
Input
R1
C1
C2
CF Typical 5 REN Ringing Voltage RMS
5 V Square
3 V Square
12 kΩ
7 kΩ
1 µF
1 µF
0.47 µF
0.47 µF
1.3
1.3
48 V
49 V
42 V
42 V
42 V
42 V
59 V
51 V
51 V
47 V
51 V
49 V
10 kHz PWM 5 V 10 kΩ 0.22 µF 0.47 µF sine
10 kHz PWM 3 V 10 kΩ 0.22 µF 0.47 µF sine
90 kHz PWM 5 V
90 kHz PWM 3 V
5 V Square
7 kΩ
7 kΩ
10 kΩ
7 kΩ
0.1 µF 0.47 µF sine
0.1 µF 0.47 µF sine
1 µF
1 µF
0.47 µF
0.47 µF
1.3
1.3
3 V Square
10 kHz PWM 5 V 10 kΩ 0.22 µF 0.47 µF sine
10 kHz PWM 3 V
90 kHz PWM 5 V
90 kHz PWM 3 V
4 kΩ 0.22 µF 0.47 µF sine
4 kΩ
4 kΩ
0.1 µF 0.47 µF sine
0.1 µF 0.47 µF sine
30
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
5 V VCC Operation
Supervision (continued)
Power Ring (continued)
A PWM signal was generated with an HP™ 8116
Function Generator modulated with a 20 Hz signal. The
optimal frequency used was 10 kHz. THE PWM signal
amplitude was 5.0 V (0 V to 5 V). This signal is shown
in Figure 15.
PWM Input Signal and Sine Wave Power Ring Sig-
nal Output (continued)
Modulation waveforms showing PWM are in Figure 14
below.
12-3575F
Figure 15. 5 V PWM Signal Amplitude
12-3381(F)
A. Upper = Pwm Signal Centered at 10 kHz
Lower = Modulation Signal
This input produced 44.96 Vrms ringing signal on
tip/ring under open loop conditions and 42.0 Vrms was
delivered to 5 REN load. The ringing output on ring,
with VCC = 5 V, is shown in Figure 16.
12-3380(F)
1660
B. Same as A but Expanded
Notes:
The modulating 20 Hz signal THD was measured at 1.3 %.
Figure 14. Modulation Waveforms
The tip/ring 20 Hz signal THD was measured at 1 %.
VBAT1 = –70.6 V, VBAT2 = –26.5 V, VCC = 5.019 V.
PWM input 10 kHz, 5.0 Vp-p.
R1 = 10 kΩ, C1 = 0.22 µF, C2 = 0.47 µF.
Figure 16. Ringing Output on RING, with VCC = 5 V
Agere Systems Inc.
31
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
During nonring modes, the PWM waveform may be left
on at RINGIN. Via the state table, the ring signal will be
removed from tip and ring even if the low-voltage input
is still present at RINGIN. There are certain timing con-
sideration that should be made with respect to state
changes which are detailed in the Switching Behavior
of L9215 Ringing SLIC Application Note.
Supervision (continued)
Power Ring (continued)
3.3 V VCC Operation
A PWM signal was generated with an HP 8116 Func-
tion Generator modulated with a 20 Hz signal. The opti-
mal frequency used was 10 kHz. The PWM signal
amplitude was 3.10 V (0 V to 3.10 V). This input signal
is shown in Figure 17.
Square Wave Input Signal and Trapezoidal Power
Ring Signal Output
A low-voltage square wave signal may be used to pro-
vide the ringing input to RINGIN. The signal is applied
through a low-pass filter and ac-coupled into RINGIN as
shown in Figure 13 and Table 23. This approach gives
a trapezoidal wave output at tip and ring.
Using this approach, a trapezoidal waveform can be
achieved at tip and ring. This has the advantage of
increasing the power transfer to the load for a given
battery voltage, thus increasing the effective ringing
loop length as compared to a sine wave. The actual
crest factor achieved is a function of the magnitude of
the battery, the magnitude of the input voltage, fre-
quency, and R1.
12-3571F
Figure 17. 3.3 V PWM Signal Amplitude
This produced 44.96 Vrms ringing signal on tip/ring
under open-loop conditions and 42.0 Vrms was deliv-
ered to 5 REN load. The ringing output on ring, with
VCC = 3.1 V is shown in Figure 18.
CH1
CH2
CH3
CH4
1660
12-3572F
Notes:
Notes:
The modulating 20 Hz signal THD was measured at 1.3 %.
CH1 = CMOS Input (5 V) at RINGIN.
The tip/ring 20 Hz signal THD was measured at 1 %.
VBAT1 = –70.6 V, VBAT2 = –26.5 V, VCC = 3.10 V.
PWM input 10 kHz, 3.1 Vp-p.
CH2 = Filtered input at RINGIN.
CH3 = Tip.
CH4 = Ring.
R1 = 10 kΩ, C1 = 0.22 µF, C2 = 0.47 µF.
R1 = 14 kΩ, C1 = 1.0 µF, C2 = 0.47 µF.
VBAT1 = –70 V, Vrms = 51 V, Vp-p = 67 V, frequency = 20 Hz, crest
factor = 1.3.
Figure 18. Ringing Output on RING, with VCC = 3.1 V
Figure 19. Square Wave Input Signal and Trapezoi-
dal Power Ring Signal Output
32
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Supervision (continued)
Power Ring (continued)
Square Wave Input Signal and Trapezoidal Power Ring Signal Output (continued)
The following charts are meant to give some guidance to the relationship between crest factor, battery voltage, and
R1 value.
1.36
1.35
1.34
1.33
1.32
1.31
1.3
1.29
1.28
1.27
1.26
58
60
62
64
66
68
70
72
BAT V
12-3576F
Figure 20. Crest Factor vs. Battery Voltage
1.5
1.45
1.4
1.35
1.3
1.25
10
10.5
11
11.5
12
12.5
13
13.5
14
R (kΩ)
12-3577F
Figure 21. Crest Factor vs. R (kΩ)
During nonring modes, the square wave input may be left on or removed from RINGIN. Via the state table, the ring
signal will be removed from tip and ring even if the low-voltage input is still present at RINGIN. However, removing
the waveform has certain advantages in terms of the timing of state. These advantages are detailed in the Switch-
ing Behavior of L9215 Ringing SLIC Application Note.
Agere Systems Inc.
33
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Codec Types
Periodic Pulse Metering (PPM)
At this point in the design, the codec needs to be
selected. The interface network between the SLIC and
codec can then be designed. Below is a brief codec
feature summary.
Periodic pulse metering (PPM), also referred to as tele-
tax (TTX), is input to the PPMIN input of the L9215.
Upon application of appropriate logic control, this sig-
nal is presented to the tip/ring subscriber loop. The
state of the L9215 should be changed while applying
PPM signals during the quiet interval of the PPM
cadence. The L9215 assumes that a shaped PPM sig-
nal is applied to the PPMIN input.
First-Generation Codecs
These perform the basic filtering, A/D (transmit), D/A
(receive), and µ-law/A-law companding. They all have
an op amp in front of the A/D converter for transmit
gain setting and hybrid balance (cancellation at the
summing node). Depending on the type, some have
differential analog input stages, differential analog out-
put stages, 5 V only or ±5 V operation, and µ-law/A-law
selectability. These are available in single and quad
designs. This type of codec requires continuous time
analog filtering via external resistor/capacitor networks
to set the ac design parameters. An example of this
type of codec is the Agere T7504 quad 5 V only codec.
PPM input signals may be a maximum 1.25 V at
PPMIN. The gain from PPMIN to tip/ring is 6 dB. Thus,
for 1.0 Vrms at tip and ring, apply a 0.50 Vrms signal at
PPMIN. The PPM signal should be ac coupled to
PPMIN through a 10 nF capacitor.
When applied to tip and ring, the PPM signal will also
be returned through the SLIC and will appear at the
SLIC VITR output. The concern is that this high-voltage
signal can overload an internal SLIC amplifier or the
codec input and cause distortion of the (desired) ac
signal. Because the L9215 is intended for short dc
loops, the assumption is that low meter pulse signals
are sufficient. The maximum allowed PPM current at
the 200 Ω ac meter pulse load to avoid saturation of the
device’s internal AAC amplifier is 3 mArms. This signal
level is sufficient to provide a minimum 200 mVrms to
the 200 Ω PPM load under maximum specified dc loop
conditions. Above 3 mArms PPM current, external
meter pulse rejection may be required. If on-hook
transmission of PPM is required, sufficient overhead to
accommodate on-hook transmission must be pro-
grammed by the user at the OVH input.
This type of codec tends to be the most economical in
terms of piece part price, but tends to require more
external components than a third-generation codec.
Further ac parameters are fixed by the external R/C
network so software control of ac parameters is diffi-
cult.
Third-Generation Codecs
This class of devices includes all ac parameters set
digitally under microprocessor control. Depending on
the device, it may or may not have data control latches.
Additional functionality sometimes offered includes
tone plant generation and reception, PPM generation,
test algorithms, and echo cancellation. Again, this type
of codec may be 3.3 V, 5 V only, or ±5 V operation, sin-
gle quad or 16 channel, and µ-law/A-law or 16-bit linear
coding selectable. Examples of this type of codec are
the Agere T8535/6 (5 V only, quad, standard features),
T8537/8 (3.3 V only, quad, standard features), T8533/4
(5 V only, quad with echo cancellation), and the
T8531/32 (5 V only 16 channel).
ac Applications
ac Parameters
There are four key ac design parameters. Termination
impedance is the impedance looking into the 2-wire
port of the line card. It is set to match the impedance of
the telephone loop in order to minimize echo return to
the telephone set. Transmit gain is measured from the
2-wire port to the PCM highway, while receive gain is
done from the PCM highway to the transmit port.
Transmit and receive gains may be specified in terms
of an actual gain, or in terms of a transmission level
point (TLP), that is the actual ac transmission level in
dBm. Finally, the hybrid balance network cancels the
unwanted amount of the receive signal that appears at
the transmit port.
ac Interface Network
The ac interface network between the L9215 and the
codec will vary depending on the codec selected. With
a first-generation codec, the interface between the
L9215 and codec actually sets the ac parameters. With
a third-generation codec, all ac parameters are set dig-
itally, internal to the codec; thus, the interface between
34
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Note also that some third-generation codecs require
the designer to provide an inherent resistive termina-
tion via external networks. The codec will then provide
gain shaping, as a function of frequency, to meet the
return loss requirements. This feedback will increase
the signal at the codec input and increase the likeli-
hood that a resistor divider is needed in the transmit
direction. Further stability issues may add external
components or excessive ground plane requirements
to the design.
ac Applications (continued)
ac Interface Network (continued)
the L9215 and this type of codec is designed to avoid
overload at the codec input in the transmit direction
and to optimize signal to noise ratio (S/N) in the receive
direction.
Because the design requirements are very different
with a first- or third-generation codec, the L9215 is
offered with two different receive gains. Each receive
gain was chosen to optimize, in terms of external com-
ponents required, the ac interface between the L9215
and codec.
In the receive direction, the issue is to optimize the
S/N. Again, the designer must consider all the consid-
ered TLPs. The idea is, for all desired TLPs, to run the
codec at or as close as possible to its maximum output
signal, to optimize the S/N. Remember, noise floor is
constant, so the hotter the signal from the codec, the
better the S/N. The problem is if the codec is feeding a
high-gain SLIC, either an external resistor divider is
needed to knock the gain down to meet the TLP
requirements, or the codec is not operated near maxi-
mum signal levels, thus compromising the S/N.
With a first-generation codec, the termination imped-
ance is set by providing gain shaping through a feed-
back network from the SLIC VITR output to the SLIC
RCVN/RCVP inputs. The L9215 provides a transcon-
ductance from T/R to VITR in the transmit direction and
a single-ended to differential gain from either RCVN or
RCVP to T/R in the receive direction. Assuming a short
from VITR to RCVN or RCVP, the maximum imped-
ance that is seen looking into the SLIC is the product of
the SLIC transconductance times the SLIC receive
gain, plus the protection resistors. The various speci-
fied termination impedance can range over the voice-
band as low as 300 Ω up to over 1000 Ω. Thus, if the
SLIC gains are too low, it will be impossible to synthe-
size the higher termination impedances. Further, the
termination that is achieved will be far less than what is
calculated by assuming a short for SLIC output to SLIC
input. In the receive direction, in order to control echo,
the gain is typically a loss, which requires a loss net-
work at the SLIC RCVN/RCVP inputs, which will
reduce the amount of gain that is available for termina-
tion impedance. For this reason, a high-gain SLIC is
required with a first-generation codec.
Thus, it appears that the solution is to have a SLIC with
a low gain, especially in the receive direction. This will
allow the codec to operate near its maximum output
signal (to optimize S/N), without an external resistor
divider (to minimize cost).
To meet the unique requirements of both type of
codecs, the L9215 offers two receive gain choices.
These receive gains are mask-programmable at the
factory and are offered as two different code variations.
For interface with a first-generation codec, the L9215 is
offered with a receive gain of 8. For interface with a
third-generation codec, the L9215 is offered with a
receive gain of 2. In either case, the transconductance
in the transmit direction or the transmit gain is 300 Ω.
This selection of receive gain gives the designer the
flexibility to maximize performance and minimize exter-
nal components, regardless of the type of codec cho-
sen.
With a third-generation codec, the line card designer
has different concerns. To design the ac interface, the
designer must first decide upon all termination imped-
ance, hybrid balances, and transmission-level point
(TLP) requirements that the line card must meet. In the
transmit direction, the only concern is that the SLIC
does not provide a signal that is too hot and overloads
the codec input. Thus, for the highest TLP that is being
designed to, given the SLIC gain, the designer, as a
function of voiceband frequency, must ensure the
codec is not overloaded. With a given TLP and a given
SLIC gain, if the signal will cause a codec overload, the
designer must insert some sort of loss, typically a resis-
tor divider, between the SLIC output and codec input.
Design Examples
First-Generation Codec ac Interface Network—
Resistive Termination
The following reference circuit shows the complete
SLIC schematic for interface to the Agere T7504 first-
generation codec for a resistive termination imped-
ance. For this example, the ac interface was designed
for a 600 Ω resistive termination and hybrid balance
with transmit gain and receive gain set to 0 dBm. For
illustration purposes, no PPM injection was assumed in
this example. This implies use of the default overhead
voltage and no components for meter pulse rejection.
Agere Systems Inc.
35
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Receive Gain:
ac Applications (continued)
Design Examples (continued)
VT/R
-----------
grcv =
VFR
First-Generation Codec ac Interface Network—
Resistive Termination (continued)
8
grcv =
------------------------------------------------------------------
RRCV RRCV
ZT
1 +
+
1 +
--------
----------- -----------
RT1
RGP
ZT/R
This is a lower feature application example and uses
single battery operation, fixed overhead, current limit,
and loop closure threshold.
Transmit Gain:
VGSX
----------
gtx =
Resistor RGN is optional. It compensates for any mis-
match of input bias voltage at the RCVN/RCVP inputs.
If it is not used, there may be a slight offset at tip and
ring due to mismatch of input bias voltage at the
RCVN/RCVP inputs. It is very common to simply tie
RCVN directly to ground in this particular mode of oper-
ation. If used, to calculate RGN, the impedance from
RCVN to ac ground should equal the impedance from
RCVP to ac ground.
VT/R
–RX 300
-------- --------
gtx =
×
RT2
ZT/R
Hybrid Balance:
RX
RHB
-----------
hbal = 20log
– gtx × grcv
Example 1, Real Termination
VGSX
--------------
hbal = 20log
The following design equations refer to the circuit in
Figure 22. Use these to synthesize real termination
impedance.
VFR
To optimize the hybrid balance, the sum of the currents
at the VFX input of the codec op amp should be set to
0. The expression for ZHB becomes the following:
Termination Impedance:
VT/R
–IT/R
------------
zT =
RX
RHB(kΩ) = -------------------
gtx × grcv
2400
zT = 50 Ω + 2RP +
----------------------------------
RT1
RT1
1 +
+
-------- -----------
RGP RRCV
RX
VGSX
–0.300 V/mA
RT2
VFXIN
VFXIP
–
+
VITR
RT1
RHB1
RCVN
RCVP
–
–
ZT/R
18 Ω
+2.4 V
RP
TIP
AV = 4
AV = 1
RRCV
VFR
+
IT/R
+
+
CURRENT
SENSE
VS
ZT
VT/R
–
RP
RGP
+
AV = –1
RING
18 Ω
–
L9215
1/4 T7504 CODEC
12-2554.V (F)
Figure 22. ac Equivalent Circuit
36
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
VBAT1
VBAT2 VCC
CBAT1
CBAT2
CCC
DBAT1
0.1 µF 0.1 µF
0.1 µF
VBAT1
BGND VBAT2 VCC AGND
ICM TRGDET
ground key
not used
CRT
ITR
RTFLT
RGX
0.1 µF
4750 Ω
RRT
RX
VTX
TXI
383 kΩ
100 kΩ
DCOUT
PR
CTX
0.1 µF
GSX
FUSIBLE OR PTC
30 Ω
CC1
RT6
49.9 kΩ
AGERE
VBAT1
–
+
0.1 µF
L7591
DX
VITR
30 Ω
VFXIN
RHB1
100 kΩ
PT
RT3
69.8 kΩ
L9215A
PCM
HIGHWAY
FUSIBLE OR PTC
+2.4 V
CC2
0.1 µF
OVH (DEFAULT OVERHEAD)
RRCV
60.4 kΩ
VFRO
DR
RCVP
RCVN
RVPROG
RGP
23.7 kΩ
FSE
FSEP
MCLK
26.7 kΩ
SYNC
AND
CLOCK
VPROG (ILIMIT = 25 mA)
VREF
RVREF
80.6 kΩ
rate of battery
reversal not
not
used
RN2
17.65 kΩ
VREF
CF1
ramped
CONTROL
INPUTS
ASEL
CF2 FB1 FB2 NSTAT BR B2 B1 B0 RINGIN PPMIN
CF1
1/4 T7504
CODEC
VREF
C2
0.47 µF
0.22 µF
CF2
0.1 µF
R1
12 kΩ
C1
1.0 µF
Figure 23. Agere T7504 First-Generation Codec Resistive Termination; Nonmeter Pulse Application
Agere Systems Inc.
37
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
Table 24. Parts List L9215; Agere T7504 First-Generation Codec Resistive Termination; Nonmeter Pulse
Application
Name
Value
Tolerance
Rating
Function
Fault Protection
RPT
30 Ω
30 Ω
Agere L7591
1%
1%
—
Fusible or PTC Protection resistor.
Fusible or PTC Protection resistor.
RPR
Protector
Power Supply
CBAT1
CBAT2
DBAT1
CCC
—
Secondary protection.
0.1 µF
0.1 µF
1N4004
0.1 µF
0.22 µF
0.1 µF
20%
20%
—
20%
20%
20%
100 V
50 V
—
VBAT filter capacitor.
VBAT filter capacitor. |VBAT2| < |VBAT1|.
Reverse current.
10 V
100 V
100 V
VCC filter capacitor.
Filter capacitor.
Filter capacitor.
CF1
CF2
dc Profile
RVPROG
RVREF
Ring/Ring Trip
C1
23.7 kΩ
80.6 kΩ
1%
1%
1/16 W
1/16 W
With RVREF fixes dc current limit.
With RVPROG fixes dc current limit.
1.0 µF
0.47 µF
12 kΩ
0.1 µF
383 kΩ
20%
20%
1%
20%
1%
10 V
10 V
1/16 W
10 V
Ring filter for square wave.
ac-couple input ring signal.
Ring filter for square wave.
Ring trip filter capacitor.
Ring trip filter resistor.
C2
R1
CRT
RRT
1/16 W
ac Interface
RGX
4750 Ω
0.1 µF
0.1 µF
0.1 µF
69.8 kΩ
1%
20%
20%
20%
1%
1/16 W
10 V
10 V
10 V
1/16 W
Sets T/R to VITR transconductance.
ac/dc separation.
dc blocking capacitor.
dc blocking capacitor.
With RGP and RRCV, sets termination
impedance and receive gain.
CTX
CC1
CC2
RT3
RT6
49.9 kΩ
100 kΩ
100 kΩ
60.4 kΩ
1%
1%
1%
1%
1/16 W
1/16 W
1/16 W
1/16 W
With RX, sets transmit gain.
With RT6, sets transmit gain.
With RX, sets hybrid balance.
With RGP and RT3, sets termination
impedance and receive gain.
RX
RHB1
RRCV
RGP
26.7 kΩ
17.6 kΩ
1%
1%
1/16 W
1/16 W
With RRCV and RT3, sets termination
impedance and receive gain.
Optional. Compensates for input off-
set at RCVN/RCVP.
RGN Optional
Notes:
Termination impedance = 600 Ω.
Hybrid balance = 600 Ω.
T x = 0 dBm Rx = 0 dBm.
38
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Interface Using First-Generation Codec
ac Applications (continued)
Design Examples (continued)
RGX/RTGS/CGS (ZTG): these components give gain shap-
ing to get good gain flatness. These components are a
scaled version of the specified complex termination
impedance.
First-Generation Codec ac Interface Network—
Complex Termination
Note for pure (600 Ω) resistive terminations, compo-
nents RTGS and CGS are not used. Resistor RGX is used
and is still 4750 Ω.
The following reference circuit shows the complete
SLIC schematic for interface to the Agere T7504 first-
generation codec for the German complex termination
impedance. For this example, the ac interface was
designed for a 220 Ω + (820 Ω || 115 nF) complex ter-
mination and hybrid balance with transmit gain and
receive gain set to 0 dBm. For illustration purposes,
1 Vrms PPM injection was assumed in this example.
This implies the overhead voltage is increased to
7.24 V and no meter pulse rejection is required. Also,
this example illustrates the device using fixed overhead
and current limit.
RX/RT6: with other components set, the transmit gain
(for complex and resistive terminations) RX and RT6 are
varied to give specified transmit gain.
RT3/RRCV/RGP: for both complex and resistive termina-
tions, the ratio of these resistors sets the receive gain.
For resistive terminations, the ratio of these resistors
sets the return loss characteristic. For complex termi-
nations, the ratio of these resistors sets the low-fre-
quency return loss characteristic.
CN/RN1/RN2: for complex terminations, these compo-
nents provide high-frequency compensation to the
return loss characteristic.
Complex Termination Impedance Design Example
The gain shaping necessary for a complex termination
impedance may be done by shaping across the AX
amplifier at nodes ITR and VTX.
For resistive terminations, these components are not
used and RCVN is connected to ground via a resistor.
Complex termination is specified in the form:
RHB: sets hybrid balance for all terminations.
R2
Set ZTG—Gain Shaping
R1
ZTG = RGX || RTGS + CGS which is a scaled version of
ZT/R (the specified termination resistance) in the
R1´ || R2´ + C´ form.
C
5-6396(F)
To work with this application, convert termination to the
form:
RGX must be 4750 Ω to set SLIC transconductance to
300 V/A.
R1´
RGX = 4750 Ω
At dc, CGS and C´ are open.
RGX = M x R1´
R2´ C´
5-6398(F)
where M is the scale factor.
4750
where:
--------------
M =
R1′
R1´ = R1 + R2
R1
It can be shown:
-------
R2´ =
(R1 + R2)
R2
RTGS = M x R2´
2 C
R2
R1 + R2
and
---------------------
C´ =
C′
------
CTGS =
M
Agere Systems Inc.
39
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Set ZTG—Gain Shaping (continued)
RTGS CGS
Rx
RGX = 4750 Ω
–IT/R
318.25
0.1 µF
RT6
–
20
+
VTX
TXI
VITR
CODEC
OP AMP
CN
RT3
RHB
RN1
RCVN
RCVP
CODEC
OUTPUT
DRIVE
AMP
RRCV
RN2
RGP
5-6400.P (F)
Figure 24. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown)
Transmit Gain
TX (specified[dB]) is the specified transmit gain. 600 Ω is the
impedance at the PCM, and REQ is the impedance at
Transmit gain will be specified as a gain from T/R to
PCM, TX (dB). Since PCM is referenced to 600 Ω and
assumed to be 0 dB, and in the case of T/R being refer-
enced to some complex impedance other than 600 Ω
resistive, the effects of the impedance transformation
must be taken into account.
600
tip and ring. 20log
represents the power
----------
REQ
loss/gain due to the impedance transformation.
Note in the case of a 600 Ω pure resistive termination
600
REQ
600
= 0.
---------
Again, specified complex termination impedance at T/R
is of the form:
at T/R 20log
= 20log
----------
600
Thus, there is no power loss/gain due to impedance
transformation and TX (dB) = TX (specified[dB]).
R2
Finally, convert TX (dB) to a ratio, gTX:
TX (dB) = 20log gTX
R1
C
The ratio of RX/RT6 is used to set the transmit gain:
5-6396(F)
First, calculate the equivalent resistance of this network
at the midband frequency of 1000 Hz.
RX
RT6
318.25
20
1
M
----------
= gTX • ----------------- • ---- with a quad Agere codec
REQ =
such as T7504:
2
2
2
2
2
(2 πf) C1 R1R22 + R1 + R2
2 πfR2 C1
-----------------------------------------------------------------------------
--------------------------------------------------
2
+
RX < 200 kΩ
2
2
2
2
2
1 + (2 πf) R2 C1
1 + (2 πf) R2 C1
Using REQ, calculate the desired transmit gain, taking
into account the impedance transformation:
600
TX (dB) = TX (specified[dB]) + 20log ----------
REQ
40
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Hybrid Balance
ac Applications (continued)
Design Examples (continued)
Receive Gain
Set the hybrid cancellation via RHB.
RX
gRCV × gTX
------------------------------
RHB =
If a 5 V only codec such as the Agere T7504 is used,
dc blocking capacitors must be added as shown in
Figure 25. This is because the codec is referenced to
2.5 V and the SLIC to ground—with the ac coupling, a
dc bias at T/R is eliminated and power associated with
this bias is not consumed.
Ratios of RRCV, RT3, and RGP will set both the low-fre-
quency termination and receive gain for the complex
case. In the complex case, additional high-frequency
compensation, via CN, RN1, and RN2, is needed for the
return loss characteristic. For resistive termination, CN,
RN1, and RN2 are not used and RCVN is tied to ground
via a resistor.
Typically, values of 0.1 µF to 0.47 µF capacitors are
used for dc blocking. The addition of blocking capaci-
tors will cause a shift in the return loss and hybrid bal-
ance frequency response toward higher frequencies,
degrading the lower-frequency response. The lower
the value of the blocking capacitor, the more pro-
nounced the effect is, but the cost of the capacitor is
lower. It may be necessary to scale resistor values
higher to compensate for the low-frequency response.
This effect is best evaluated via simulation. A PSPICE®
model for the L9215 is available.
Determine the receive gain, gRCV, taking into account
the impedance transformation in a manner similar to
transmit gain.
REQ
RX (dB) = RX (specified[dB]) + 20log ----------
600
RX (dB) = 20log gRCV
Then:
4
-----------------------------------------------
RRCV RRCV
gRCV =
--------------- ---------------
1 +
+
Design equation calculations seldom yield standard
component values. Conversion from the calculated
value to standard value may have an effect on the ac
parameters. This effect should be evaluated and opti-
mized via simulation.
RT3
RGP
and low-frequency termination
2400
--------------------------------------------
ZTER(low) =
+ 2RP + 50 Ω
RT3
RT3
----------- ---------------
1 +
+
RGP RRCV
ZTER(low) is the specified termination impedance assum-
ing low frequency (C or C´ is open).
RP is the series protection resistor.
50 Ω is the typical internal feed resistance.
These two equations are best solved using a computer
spreadsheet.
Next, solve for the high-frequency return loss compen-
sation circuit, CN, RN1, and RN2:
2RP
CNRN2 = ------------ CG RTGP
2400
RTGS
-------------
2400
2RP
RN1 = RN2 ------------
– 1
RTGP
There is an input offset voltage associated with nodes
RCVN and RCVP. To minimize the effect of mismatch
of this voltage at T/R, the equivalent resistance to ac
ground at RCVN should be approximately equal to that
at RCVP. Refer to Figure 25 (with dc blocking capaci-
tors). To meet this requirement, RN2 = RGP || RT3.
Agere Systems Inc.
41
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Blocking Capacitors
RTGS
CGS
Rx
RGX = 4750 Ω
–IT/R
CB1
0.1 µF
318.25
RT6
RT3
–
+
20
VTX
TXI
VITR
CODEC
OP AMP
CN
RHB
RN1
RCVN
RCVP
CB2
RRCV
RGP
2.5 V
RN2
CODEC
OUTPUT
DRIVE
AMP
5-6401.M (F)
Figure 25. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex Termi-
nation Impedance
42
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Blocking Capacitors (continued)
VBAT1
VBAT2 VCC
CBAT1
CBAT2
CCC
DBAT1
VBAT1
0.1 µF 0.1 µF
0.1 µF
BGND VBAT2 VCC
AGND
ICM
TRGDET
ground key
not used
CRT
ITR
RTFLT
RTGS 1.74 kΩ
RGX
0.1 µF
4750 Ω
RRT
CGS 12 nF
383 kΩ
VTX
TXI
FUSIBLE
OR PTC
DCOUT
PR
CTX
0.1 µF
RX
115 kΩ
30 Ω
GSX
DX
AGERE
L7591
VBAT1
CC1
0.1 µF
RT6
40.6 kΩ
30 Ω
VITR
–
+
PT
L9215A
CN
VFXIN
FUSIBLE
OR PTC
120 pF
RT3
49.9 kΩ
PCM
HIGHWAY
RHB1
113 kΩ
+2.4 V
RVREF
80.6 kΩ
RRCV
VFRO
OVH
RCVP
DR
ROVH
10 kΩ
59.0 kΩ
CC2
0.1 µF
RN1
127
kΩ
FSE
FSEP
MCLK
SYNC
AND
CLOCK
VPROG (ILIMIT = 25 mA)
rate of battery
RCVN
RVPROG
20 kΩ
RGP
54.9 kΩ
reversal not
ramped
VREF
CF1
VREF
47.5 kΩ
RN2
CF2 FB1 FB2 NSTAT BR B2 B1 B0 RINGIN
PPMIN
CONTRO
INPUTS
ASEL
CF1
VREF
CRING
0.47 µF
CPPM
10 nF
0.22 µF
CF2
1/4 T7504
CODEC
FROM/TO CONTROL
RING
0.1 µF
PPM
0.5 VRMS
Figure 26. Agere T7504 First-Generation Codec Complex Termination; Meter Pulse Application
Agere Systems Inc.
43
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Applications (continued)
Design Examples (continued)
Blocking Capacitors (continued)
Table 25. Parts List L9215; Agere T7504 First-Generation Codec Complex Termination; Meter Pulse
Application
Termination impedance = 220 Ω + (820 Ω || 115 nF), hybrid balance = 220 Ω + (820 Ω || 115 nF) Tx = 0 dBm,
Rx = 0 dBm.
Name
Value Tolerance
Rating
Function
Fault Protection
RPT
RPR
Protector
30 Ω
30 Ω
Agere
L7591
1%
1%
—
Fusible or PTC Protection resistor.
Fusible or PTC Protection resistor.
—
Secondary protection.
Power Supply
CBAT1
CBAT2
DBAT1
CCC
0.1 µF
20%
20%
—
20%
20%
20%
100 V
50 V
—
10 V
100 V
100 V
VBAT filter capacitor.
VBAT filter capacitor. |VBAT2| < |VBAT1|.
Reverse current.
VCC filter capacitor.
Filter capacitor.
Filter capacitor.
0.1 µF
1N4004
0.1 µF
0.22 µF
0.1 µF
CF1
CF2
dc Profile
RVPROG
RVOVH
RVREF
20 kΩ
10 kΩ
80.6 kΩ
1%
1%
1%
1/16 W
1/16 W
1/16 W
With RVREF fixes dc current limit.
With RVREF fixes overhead voltage.
With RVPROG fixes dc current limit/overhead.
Ring/Ring Trip
CRING
CRT
RRT
0.47 µF
0.1 µF
383 kΩ
20%
20%
1%
10 V
10 V
1/16 W
ac-couple input ring signal.
Ring trip filter capacitor.
Ring trip filter resistor.
PPM
CPPM
ac Interface
RGX
RTGS
CGS
CTX
CC1
CC2
RT3
10 nF
20%
10 V
ac-couple PPM input.
4750 Ω
1.74 kΩ
12 nF
0.1 µF
0.1 µF
0.1 µF
49.9 kΩ
1%
1%
5%
20%
20%
20%
1%
1/16 W
1/16 W
10 V
10 V
10 V
Sets T/R to VITR transconductance.
Gain shaping for complex termination.
Gain shaping for complex termination.
ac/dc separation.
dc blocking capacitor.
dc blocking capacitor.
10 V
1/16 W
With RGP and RRCV, sets termination impedance and receive
gain.
RT6
RX
RHB1
RRCV
RGP
40.2 kΩ
115 kΩ
113 kΩ
59.0 kΩ
54.9 kΩ
1%
1%
1%
1%
1%
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
With RX, sets transmit gain.
With RT6, sets transmit gain.
With RX, sets hybrid balance.
With RGP and RT3, sets termination impedance and receive gain.
With RRCV and RT3, sets termination impedance and receive
gain.
CN
RN1
RN2
120 pF
127 kΩ
47.5 kΩ
20%
1%
1%
10 V
1/16 W
1/16 W
High frequency compensation.
High frequency compensation.
High frequency compensation, compensate for dc offset at
RCVP/RCVN.
44
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network—Complex Termination
The following reference circuit shows the complete SLIC schematic for interface to the Agere T8536 third-genera-
tion codec. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. For illustration
purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this
example illustrates the device using programmable overhead and current limit. Please see the T8535/6 data sheet
for information on coefficient programming.
VBAT1
VBAT2 VCC
CBAT1
CBAT2
CCC
DBAT1
VBAT1
0.1 µF 0.1 µF
0.1 µF
BGND VBAT2 VCC
AGND
ITR
CRT
RTFLT
RGX
4750 Ω
0.1 µF
RRT
383 kΩ
VTX
DCOUT
PR
CTX
FUSIBLE OR PTC
50 Ω
AGERE
0.1 µF
TXI
CC1
0.1 µF
VBAT2
L7591
VFXI
DX0
DR0
VITR
50 Ω
RCIN
20 MΩ
PT
L9215G
FUSIBLE OR PTC
PCM
HIGHWAY
DX1
DR1
VFROP
VFRON
RCVP
RCVN
OVH
CONTROL
VOLTAGE
VPROG
1/4
T8536/8
SYNC
AND
CLOCK
FS
VREF
SLIC4a
SLIC3a
SLIC2a
SLIC1a
SLIC0a
BCLK
B2
B1
CF1
CF1
CF2
NSTAT BR B2 B1 B0
RINGIN
PPMIN
CPPM
10 nF
CRING
0.47 µF
B0
0.22 µF
DGND
VDD
CF2
0.1 µF
FROM/TO T8536
CONTROL LATCHES
BR
NSTAT
VDD
PPM
0.5 Vrms
Figure 27. Third-Generation Codec ac Interface Network; Complex Termination
Agere Systems Inc.
45
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network—Complex Termination (continued)
Table 26. Parts List L9215; Agere T8536 Third-Generation Codec Meter Pulse Application ac and dc
Parameters; Fully Programmable
Name
Value
Tolerance
Rating
Function
Fault Protection
RPT
RPR
50 Ω
50 Ω
1%
1%
—
FusibleorPTC Protection resistor*.
FusibleorPTC Protection resistor*.
Protector
Agere L7591
—
Secondary protection.
Power Supply
CBAT1
0.1 µF
0.1 µF
1N4004
0.1 µF
0.22 µF
0.1 µF
20%
20%
—
100 V
50 V
—
VBAT filter capacitor.
CBAT2
VBAT filter capacitor. |VBAT2| < |VBAT1|.
Reverse current.
DBAT1
CCC
20%
20%
20%
10 V
100 V
100 V
VCC filter capacitor.
Filter capacitor.
CF1
CF2
Filter capacitor.
Ring/Ring Trip
CRING
CRT
0.47 µF
0.1 µF
20%
20%
1%
10 V
10 V
ac-couple input ring signal.
Ring trip filter capacitor.
Ring trip filter resistor.
RRT
383 kΩ
1/16 W
PPM
CPPM
10 nF
20%
10 V
ac-couple PPM input.
ac Interface
RGX
4750 Ω
20 MΩ
0.1 µF
0.1 µF
1%
5%
1/16 W
1/16 W
10 V
Sets T/R to VITR transconductance.
dc Bias
RCIN
CTX
20%
20%
ac/dc separation.
CC1
10 V
dc blocking capacitor.
* For loop stability, increase to 50 Ω minimum if synthesizing 900 Ω or 900 Ω + 2.16 µF termination impedance.
46
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Outline Diagrams
32-Pin PLCC
Dimensions are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Sales Representative.
12.446 ± 0.127
11.430 ± 0.076
PIN #1 IDENTIFIER
ZONE
4
1
30
5
29
13.970
± 0.076
14.986
± 0.127
13
21
14
20
3.175/3.556
SEATING PLANE
0.10
0.38 MIN
TYP
1.27 TYP
0.330/0.533
5-3813F
Agere Systems Inc.
47
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Outline Diagrams (continued)
48-Pin MLCC
Dimensions are in millimeters.
Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Sales Representative.
The exposed pad on the bottom of the package will be at VBAT1 potential.
C
C
7.00
CL
3.50
6.75
3.375
0.50 BSC
1
2
3
DETAIL A
VIEW FOR EVEN TERMINAL/SIDE
6.75
7.00
PIN #1
IDENTIFIER ZONE
0.18/0.30
0.00/0.05
SECTION C–C
DETAIL A
0.65/0.80
1.00 MAX
12°
SEATING PLANE
0.08
0.20 REF
0.01/0.05
11 SPACES @
0.50 = 5.50
0.24/0.60
0.18/0.30
0.24/0.60
5.10
± 0.15
3
2
1
0.30/0.45
EXPOSED PAD
0.50 BSC
0195mod
48
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Outline Diagrams (continued)
48-Pin MLCC, JEDEC MO-220 VKKD-2
Dimensions are in millimeters.
Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Sales Representative.
The exposed pad on the bottom of the package will be at VBAT1 potential.
7.00
CL
3.50
PIN #1
IDENTIFIER ZONE
0.50 BSC
3.50
INDEX AREA
DETAIL A
VIEW FOR EVEN TERMINAL/SIDE
(7.00/2 x 7.00/2)
7.00
0.18
0.23
0.18
TOP VIEW
SIDE VIEW
0.23
1.00 MAX
SEATING PLANE
0.08
0.20 REF
DETAIL B
0.02/0.05
11 SPACES @
0.50 = 5.50
DETAIL A
0.18/0.30
0.30/0.50
2.50/2.625
5.00/5.25
3
2
1
EXPOSED PAD
0.50 BSC
DETAIL B
BOTTOM VIEW
Agere Systems Inc.
49
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Ordering Information
Device Part No.
LUCL9215AAU-D
LUCL9215AAU-DT
LUCL9215GAU-D
LUCL9215GAU-DT
LUCL9215ARG-D
LUCL9215GRG-D
Description
SLIC Gain = 8
SLIC Gain = 8
SLIC Gain = 2
SLIC Gain = 2
SLIC Gain = 8
SLIC Gain = 2
Package
Comcode
108327214
108327222
108417932
108417940
108955451
108955444
32-Pin PLCC Dry Bag
32-Pin PLCC Tape & Reel
32-Pin PLCC Dry Bag
32-Pin PLCC Tape & Reel
48-Pin MLCC Dry Bag
48-Pin MLCC Dry Bag
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
PSPICE is a registered trademark of MicroSim Corporation.
Telcordia Technologies is a trademark of Bell Communications Research, Inc.
HP is a trademark of Hewlett-Packard Company.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
docmaster@agere.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
Tel. (44) 7000 624624, FAX (44) 1344 488 045
EUROPE:
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
September 2001
DS01-299ALC (Replaces DS01-104ALC)
相关型号：
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