EVAL-AD5429EBZ [ADI]
Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface; 双8位/ 10位/ 12位，高带宽，乘法DAC，串行接口
| 型号： | EVAL-AD5429EBZ |
| 厂家： | 
ADI |
| 描述： | Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface |
| 文件： | 总32页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 8-/10-/12-Bit, High Bandwidth,
Multiplying DACs with Serial Interface
AD5429/AD5439/AD5449
GENERAL DESCRIPTION
FEATURES
The AD5429/AD5439/AD54491 are CMOS, 8-, 10-, and 12-bit,
dual-channel, current output digital-to-analog converters (DAC),
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
10 MHz multiplying bandwidth
INL of 0.2ꢀ LSB ꢁ 8 bits
16-lead TSSOP package
2.ꢀ V to ꢀ.ꢀ V supply operation
10 V reference input
ꢀ0 MHz serial interface
As a result of being manufactured on a CMOS submicron process,
these parts offer excellent 4-quadrant multiplication character-
istics, with large signal multiplying bandwidths of 10 MHz.
2.47 MSPS update rate
Extended temperature range: −40°C to +12ꢀ°C
4-quadrant multiplication
Power-on reset
0.ꢀ μA typical current consumption
Guaranteed monotonic
Daisy-chain mode
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
Readback function
APPLICATIONS
Portable battery-powered applications
Waveform generators
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI, QSPI™, MICROWIRE™, and most DSP
interface standards. In addition, a serial data out (SDO) pin allows
daisy-chaining when multiple packages are used. Data readback
allows the user to read the contents of the DAC register via the
SDO pin. On power-up, the internal shift register and latches
are filled with 0s, and the DAC outputs are at zero scale.
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
The AD5429/AD5439/AD5449 DACs are available in 16-lead
TSSOP packages.
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
V
A
REF
RFB
R
AD5429/AD5439/AD5449
V
DD
R
A
FB
SYNC
I
I
1A
OUT
OUT
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
8-/10-/12-BIT
R-2R DAC A
SCLK
SDIN
2A
SDO
CLR
LDAC
I
I
1B
2B
OUT
INPUT
REGISTER
DAC
REGISTER
8-/10-/12-BIT
R-2R DAC B
POWER-ON
RESET
OUT
R
B
FB
RFB
R
LDAC
V
B
REF
Figure 1.
1 U.S. Patent Number 5,689,257.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2010 Analog Devices, Inc. All rights reserved.
AD5429/AD5439/AD5449
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital-to-Analog Converter .................................................... 15
Circuit Operation....................................................................... 15
Single-Supply Applications ....................................................... 17
Adding Gain................................................................................ 18
Divider or Programmable Gain Element................................ 18
Reference Selection .................................................................... 19
Amplifier Selection .................................................................... 19
Serial Interface............................................................................ 20
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling ........................... 24
Evaluation Board for the DAC ................................................. 24
Overview of AD54xx Devices....................................................... 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
REVISION HISTORY
Changes to Table 5.......................................................................... 15
Changes to Table 6.......................................................................... 16
Changes to Single-Supply Applications Section......................... 17
Changes to Divider or Programmable Gain Element Section.... 18
Changes to Table 7 Through Table 10 ......................................... 20
Added ADSP-BF5xx-to-AD5429/AD5439/AD5449
Interface Section........................................................................ 23
Change to PCB Layout and
Power Supply Decoupling Section .......................................... 25
Changes to Power Supplies for the Evaluation Board Section.... 25
Changes to Table 13 ....................................................................... 29
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide.......................................................... 30
4/10—Rev. B to Rev. C
Added to Figure 4 ............................................................................. 6
3/08—Rev. A to Rev. B
Added t13 and t14 Parameters to Table 2 ......................................... 5
Changes to Figure 2.......................................................................... 5
Changes to Figure 3.......................................................................... 6
Changes to Figure 38...................................................................... 16
Changes to Ordering Guide .......................................................... 30
7/05—Rev. 0 to Rev. A
Changes to Features List.................................................................. 1
Changes to Specifications................................................................ 3
Changes to Timing Characteristics................................................ 5
Changes to Absolute Maximum Ratings Section......................... 7
Changes to General Description Section .................................... 15
7/04—Revision 0: Initial Version
Rev. C | Page 2 of 32
AD5429/AD5439/AD5449
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with the OP177, and ac performance is measured with the AD8038, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
AD5429
Resolution
8
±±.5
±ꢀ
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5439
Guaranteed monotonic
Guaranteed monotonic
Resolution
ꢀ±
±±.5
±ꢀ
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5449
Resolution
ꢀ2
±ꢀ
Bits
LSB
Relative Accuracy
Differential Nonlinearity
Gain Error
−ꢀ/+2 LSB
±25
Guaranteed monotonic
mV
Gain Error Temperature
Coefficient
±5
ppm FSR/°C
Output Leakage Current
±5
±ꢀ5
nA
nA
Data = ±x±±±±, TA = 25°C, IOUTꢀ
Data = ±x±±±±, IOUTꢀ
REFERENCE INPUT
Reference Input Range
VREFA, VREFB Input Resistance
VREFA-to-VREFB Input Resistance
Mismatch
±ꢀ±
ꢀꢀ
ꢀ.6
V
kΩ
%
9
ꢀ3
2.5
Input resistance temperature coefficient = −5± ppm/°C
Typical = 25°C, maximum = ꢀ25°C
Input Capacitance
Code ±
Code 4±95
3.5
3.5
pF
pF
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
ꢀ.7
ꢀ.7
V
V
VDD = 3.6 V to 5.5 V
VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
±.8
±.7
V
V
V
V
V
V
μA
pF
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5.5 V, ISOURCE = 2±± μA
VDD = 2.5 V to 3.6 V, ISOURCE = 2±± μA
VDD = 4.5 V to 5.5 V, ISINK = 2±± μA
VDD = 2.5 V to 3.6 V, ISINK = 2±± μA
VDD − ꢀ
VDD − ±.5
±.4
±.4
ꢀ
Input Leakage Current, IIL
Input Capacitance
4
ꢀ±
DYNAMIC PERFORMANCE
Reference-Multiplying Bandwidth
Output Voltage Settling Time
ꢀ±
MHz
VREF = ±3.5 V p-p, DAC loaded all ꢀs
RLOAD = ꢀ±± Ω, CLOAD = ꢀ5 pF, VREF = ꢀ± V,
DAC latch alternately loaded with ±s and ꢀs
Measured to ±ꢀ mV of FS
Measured to ±4 mV of FS
Measured to ±ꢀ6 mV of FS
Digital Delay
8±
35
3±
2±
3
ꢀ2±
7±
6±
ns
ns
ns
ns
4±
Digital-to-Analog Glitch Impulse
nV-sec
ꢀ LSB change around major carry, VREF = ± V
Rev. C | Page 3 of 32
AD5429/AD5439/AD5449
Parameter1
Min
Typ
Max
Unit
Conditions
Multiplying Feedthrough Error
DAC latches loaded with all ±s, VREF = ±3.5 V
ꢀ MHz
ꢀ± MHz
DAC latches loaded with all ±s
DAC latches loaded with all ꢀs
Feedthrough to DAC output with CS high and
alternate loading of all ±s and all ꢀs
@ ꢀ kHz
7±
48
ꢀ7
3±
5
dB
dB
pF
pF
Output Capacitance
Digital Feedthrough
ꢀ2
25
3
nV-sec
Output Noise Spectral Density
Analog THD
Digital THD
25
8ꢀ
nV/√Hz
dB
VREF = 3. 5 V p-p, all ꢀs loaded, f = ꢀ kHz
Clock = ꢀ± MHz, VREF = 3.5 V
ꢀ±± kHz fOUT
5± kHz fOUT
6ꢀ
66
dB
dB
SFDR Performance (Wide Band)
Clock = ꢀ± MHz
5±± kHz fOUT
AD5449, 65k codes, VREF = 3.5 V
55
63
65
dB
dB
dB
ꢀ±± kHz fOUT
5± kHz fOUT
Clock = 25 MHz
5±± kHz fOUT
ꢀ±± kHz fOUT
5±
6±
62
dB
dB
dB
5± kHz fOUT
SFDR Performance (Narrow Band)
Clock = ꢀ± MHz
5±± kHz fOUT
AD5449, 65k codes, VREF = 3.5 V
73
8±
87
dB
dB
dB
ꢀ±± kHz fOUT
5± kHz fOUT
Clock = 25 MHz
5±± kHz fOUT
ꢀ±± kHz fOUT
7±
75
8±
dB
dB
dB
5± kHz fOUT
Intermodulation Distortion
fꢀ = 4± kHz, f2 = 5± kHz
fꢀ = 4± kHz, f2 = 5± kHz
POWER REQUIREMENTS
Power Supply Range
IDD
AD5449, 65k codes, VREF = 3.5 V
Clock = ꢀ± MHz
Clock = 25 MHz
72
65
dB
dB
2.5
5.5
±.7
ꢀ±
±.±±ꢀ
V
μA
μA
%/%
TA = 25°C, logic inputs = ± V or VDD
TA = −4±°C to +ꢀ25°C, logic inputs = ± V or VDD
∆VDD = ±5%
±.5
Power Supply Sensitivity
ꢀ Guaranteed by design and characterization, not subject to production test.
Rev. C | Page 4 of 32
AD5429/AD5439/AD5449
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
REF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
V
Table 2.
Parameter1
Limit at TMIN, TMAX
Unit
Conditions/Comments2
fSCLK
t1
t2
t3
t4
50
20
8
8
13
5
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
t5
t6
t7
4
5
t8
30
0
t9
SCLK falling edge to LDAC falling edge
LDAC pulse width
t10
t11
12
10
25
60
12
4.5
2.47
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
CLR pulse width
3
t12
t13
t14
SYNC rising edge to LDAC falling edge
Consists of cycle time, SYNC high time, data setup, and output voltage settling time
Update Rate
1 Guaranteed by design and characterization, not subject to production test.
2 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
3 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5.
TIMING DIAGRAMS
t1
SCLK
t2
t3
t4
t8
t7
SYNC
SDIN
t6
t5
DB0
DB15
t10
t9
1
LDAC
t11
2
LDAC
1
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
2
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram
Rev. C | Page 5 of 32
AD5429/AD5439/AD5449
t1
SCLK
t2
t3
t7
t4
SYNC
t6
t8
t5
DB0
(N + 1)
DB15
(N)
DB0
(N)
DB15
(N + 1)
SDIN
t12
DB0
(N)
DB15
(N)
SDO
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON THE FALLING
EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain Timing Diagram
SCLK
16
32
SYNC
SDIN
DB15
DB0
DB15
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB15
DB0
SDO
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
Figure 4. Readback Mode Timing Diagram
200μA
I
OL
V
(MIN) + V (MAX)
OL
OH
TO OUTPUT
PIN
2
C
L
50pF
200μA
I
OH
Figure 5. Load Circuit for SDO Timing Specifications
Rev. C | Page 6 of 32
AD5429/AD5439/AD5449
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
Table 3.
Parameter
Rating
VDD to GND
VREFx, RFBx to GND
IOUT1, IOUT2 to GND
Input Current to Any Pin Except Supplies
Logic Inputs and Output1
Operating Temperature Range
Extended (Y Version)
Storage Temperature Range
Junction Temperature
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
10 mA
−0.3 V to VDD + 0.3 V
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
16-Lead TSSOP, θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
150°C/W
300°C
235°C
1
SYNC
Overvoltages at SCLK,
, and SDIN are clamped by internal diodes.
Rev. C | Page 7 of 32
AD5429/AD5439/AD5449
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
I
1A
2A
I
1B
2B
OUT
OUT
I
I
OUT
OUT
R
A
A
R
B
FB
FB
AD5429/
AD5439/
V
V
B
REF
REF
DD
AD5449
GND
LDAC
SCLK
SDIN
V
TOP VIEW
CLR
(Not to Scale)
SYNC
SDO
NC = NO CONNECT
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
DAC A Current Output.
1
2
IOUT1A
IOUT2A
DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but it can be
biased to achieve single-supply operation.
3
RFBA
DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external
amplifier output.
4
5
6
VREF
GND
LDAC
A
DAC A Reference Voltage Input Pin.
Ground Pin.
Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling
edge when the device is in standalone mode, or on the rising edge of SYNC when in daisy-chain mode.
7
8
9
SCLK
SDIN
SDO
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked
into the shift register on the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, data is clocked at power-on into the shift register on the falling edge of SCLK. The control bits allow
the user to change the active edge to a rising edge.
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the
shift register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked
out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift
register makes the DAC register contents available for readback on the SDO pin, and they are clocked out on the
next 16 opposite clock edges to the active clock edge.
10
11
SYNC
Active Low Control Input. This pin provides the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded into the
shift register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the
clocks, and data is latched into the shift register on the 16th active clock edge.
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware CLR pin as a clear-to-zero scale or midscale, as required.
CLR
VDD
12
13
14
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC B Reference Voltage Input Pin.
DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external
amplifier output.
VREF
B
RFBB
15
16
IOUT2B
IOUT1B
DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but it can be
biased to achieve single-supply operation.
DAC B Current Output.
Rev. C | Page 8 of 32
AD5429/AD5439/AD5449
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.20
0.15
0.10
0.05
0
T
= 25°C
T = 25°C
A
A
V
V
= 10V
= 5V
V
V
= 10V
REF
REF
= 5V
DD
0.15
0.10
0.05
0
DD
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
0
50
100
150
200
250
0
50
100
150
200
250
CODE
CODE
Figure 7. INL vs. Code (8-Bit DAC)
Figure 10. DNL vs. Code (8-Bit DAC)
0.5
0.4
0.5
0.4
T
V
V
= 25°C
T
V
V
= 25°C
A
A
= 10V
= 10V
REF
= 5V
REF
= 5V
DD
DD
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
–0.5
0
–0.5
0
200
400
600
800
1000
200
400
600
800
1000
CODE
CODE
Figure 8. INL vs. Code (10-Bit DAC)
Figure 11. DNL vs. Code (10-Bit DAC)
1.0
0.8
1.0
0.8
T
V
V
= 25°C
T = 25°C
A
A
= 10V
V
= 10V
REF
= 5V
REF
= 5V
DD
V
DD
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
–1.0
0
–1.0
0
500
1000
1500
2000
2500
3000
3500
4000
500
1000
1500
2000
2500
3000
3500
4000
CODE
CODE
Figure 9. INL vs. Code (12-Bit DAC)
Figure 12. DNL vs. Code (12-Bit DAC)
Rev. C | Page 9 of 32
AD5429/AD5439/AD5449
8
7
6
5
4
3
2
1
0
0.6
0.5
0.4
T
= 25°C
A
MAX INL
0.3
V
= 5V
DD
0.2
0.1
0
T
V
= 25°C
= 5V
A
DD
MIN INL
–0.1
V
= 3V
DD
–0.2
–0.3
V
= 2.5V
DD
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
2
3
4
5
6
7
8
9
10
INPUT VOLTAGE (V)
REFERENCE VOLTAGE
Figure 13. INL vs. Reference Voltage
Figure 16. Supply Current vs. Logic Input Voltage
1.6
–0.40
T
= 25°C
A
V
= 5V
DD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
I
1 V = 5V
OUT DD
I
1 V = 3V
DD
OUT
MIN DNL
–40
–20
0
20
40
60
80
100
120
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
REFERENCE VOLTAGE
Figure 14. DNL vs. Reference Voltage
Figure 17. IOUT1 Leakage Current vs. Temperature
0.50
5
4
3
2
1
0
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
= 5V
V
= 5V
DD
DD
ALL 0s
ALL 1s
V
DD
= 2.5V
V
= 2.5V
DD
–1
–2
–3
–4
–5
ALL 1s
ALL 0s
V
= 10V
REF
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Supply Current vs. Temperature
Figure 15. Gain Error vs. Temperature
Rev. C | Page 10 of 32
AD5429/AD5439/AD5449
3
0
14
12
10
8
T
V
= 25°C
A
T
= 25°C
A
= 5V
DD
LOADING ZS TO FS
V
= 5V
DD
–3
–6
–9
6
V
V
= 3V
DD
DD
4
V
V
V
V
V
= ±2V, AD8038 C 1.47pF
REF
REF
REF
REF
REF
C
= 2.5V
= ±2V, AD8038 C 1pF
C
= ±0.15V, AD8038 C 1pF
C
2
= ±0.15V, AD8038 C 1.47pF
C
= ±3.51V, AD8038 C 1.8pF
C
0
10k
100k
1M
10M
100M
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Supply Current vs. Update Rate
Figure 22. Reference Multiplying Bandwidth vs. Frequency
and Compensation Capacitor
6
0
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
T
= 25°C
ALL ON
DB11
DB10
DB9
DB8
DB7
A
T
V
= 25°C
= 0V
0x7FF TO 0x800
A
LOADING
ZS TO FS
REF
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
AMP = AD8038
= 1.8pF
V
= 5V
DD
C
COMP
DB6
V
= 3V
DD
DB5
DB4
DB3
DB2
DB1
DB0
0x800 TO 0x7FF
= 3V
V
DD
T
V
= 25°C
A
= 5V
DD
V
= ±3.5V
= 1.8pF
REF
ALL OFF
C
–0.005
–0.010
COMP
AMP = AD8038
V
= 5V
DD
1
10
100
1k
10k
100k
1M 10M 100M
0
20
40
60
80
100 120 140 160 180 200
TIME (ns)
FREQUENCY (Hz)
Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 23. Midscale Transition, VREF = 0 V
0.2
0
–1.68
–1.69
–1.70
–1.71
–1.72
–1.73
–1.74
–1.75
–1.76
–1.77
T
V
= 25°C
= 3.5V
A
0x7FF TO 0x800
REF
AMP = AD8038
= 1.8pF
V
= 5V
DD
C
COMP
–0.2
–0.4
V
= 3V
DD
V
= 5V
V
DD
= 3V
DD
T
V
V
= 25°C
A
–0.6
–0.8
= 5V
DD
=
±
3.5V
REF
C
= 1.8pF
COMP
0x800 TO 0x7FF
20 40 60
AMP = AD8038
1
10 100
1k
10k
100k
1M
10M
100M
0
80
100 120 140 160 180 200
TIME (ns)
FREQUENCY (Hz)
Figure 21. Reference Multiplying Bandwidth—All 1s Loaded
Figure 24. Midscale Transition, VREF = 3.5 V
Rev. C | Page 11 of 32
AD5429/AD5439/AD5449
90
80
70
60
50
40
30
20
10
0
20
T
V
= 25°C
A
= 3V
DD
AMP = AD8038
0
–20
MCLK = 5MHz
MCLK = 10MHz
–40
FULL SCALE
ZERO SCALE
MCLK = 25MHz
–60
–80
–100
–120
T
V
= 25°C
= 3.5V
A
REF
AMP = AD8038
1
100
1k
10k
100k
1M
10M
10
0
100 200 300 400 500 600 700 800 900 1000
fOUT (kHz)
FREQUENCY (Hz)
Figure 25. Power Supply Rejection Ratio vs. Frequency
Figure 28. Wideband SFDR vs. fOUT Frequency
–60
–65
–70
–75
–80
–85
0
T
V
= 25°C
A
T
V
V
= 25°C
A
= 5V
DD
= 3V
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
AMP = AD8038
65k CODES
= 3.5V p-p
REF
–90
1
0
2
4
6
8
10
12
10
100
1k
10k
100k
1M
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 26. THD + Noise vs. Frequency
Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
100
80
60
40
20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
= 25°C
A
= 5V
DD
MCLK = 1MHz
AMP = AD8038
65k CODES
MCLK = 200kHz
MCLK = 0.5MHz
T
V
= 25°C
= 3.5V
A
REF
AMP = AD8038
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
20
40
60
80
100 120 140 160 180 200
FREQUENCY (MHz)
fOUT (kHz)
Figure 27. Wideband SFDR vs. fOUT Frequency
Figure 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Rev. C | Page 12 of 32
AD5429/AD5439/AD5449
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
V
= 25°C
T = 25°C
A
DD
AMP = AD8038
65k CODES
A
= 5V
V
= 3V
DD
AMP = AD8038
65k CODES
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
70
75
80
85
90
95
100 105 110 115 120
FREQUENCY (MHz)
FREQUENCY (kHz)
Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
Figure 34. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
T
V
= 25°C
DD
A
T
V
= 25°C
DD
A
= 3V
= 5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
AMP = AD8038
65k CODES
AMP = AD8038
65k CODES
250 300 350 400 450 500 550 600 650 700 750
0
50
100
150
200
250
300
350
400
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 32. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
20
300
T
V
= 25°C
DD
T
= 25°C
A
A
= 3V
ZERO SCALE LOADED TO DAC
MIDSCALE LOADED TO DAC
FULL SCALE LOADED TO DAC
AMP = AD8038
AMP = AD8038
65k CODES
0
–20
250
200
150
100
50
–40
–60
–80
–100
–120
0
50
60
70
80
90
100 110 120 130 140 150
100
1k
10k
FREQUENCY (Hz)
100k
FREQUENCY (kHz)
Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 36. Output Noise Spectral Density
Rev. C | Page 13 of 32
AD5429/AD5439/AD5449
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
Digital Crosstalk
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function.
It is measured after adjusting for zero and full scale and is typically
expressed in LSBs or as a percentage of the full-scale reading.
The glitch impulse transferred to the outputs of one DAC in
response to a full-scale code change (all 0s to all 1s, or vice versa)
in the input register of the other DAC. It is expressed in nV-sec.
Analog Crosstalk
Differential Nonlinearity
The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating temperature
range ensures monotonicity.
LDAC
(all 0s to all 1s, or vice versa) while keeping
high and
LDAC
then pulsing
low and monitoring the output of the DAC
whose digital code has not changed. The area of the glitch is
expressed in nV-sec.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
Channel-to-Channel Isolation
The portion of input signal from the reference input of a DAC
that appears at the output of another DAC. It is expressed in dB.
V
REF − 1 LSB. The gain error of the DACs is adjustable to zero
with an external resistance.
Output Leakage Current
Total Harmonic Distortion (THD)
The current that flows into the DAC ladder switches when they
are turned off. For the IOUT1x terminal, it can be measured by
loading all 0s to the DAC and measuring the IOUT1 current.
Minimum current flows into the IOUT2x line when the DAC is
loaded with all 1s.
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as the second to fifth harmonics.
2
2
2
2
V2 +V3 +V4 +V5
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
THD = 20 log
V1
Intermodulation Distortion (IMD)
Output Current Settling Time
The DAC is driven by two combined sine wave references of
Frequency fa and Frequency fb. Distortion products are produced
at sum and difference frequencies of mfa nfb, where m, n = 0, 1,
2, 3 … Intermodulation terms are those for which m or n is not
equal to 0. The second-order terms include (fa + fb) and (fa − fb),
and the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa + 2fb),
and (fa − 2fb). IMD is defined as
The amount of time for the output to settle to a specified level
for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
RMS Sum of the Sum and Diff Distortion Products
IMD = 20log
RMS Amplitude of the Fundamental
Digital Feedthrough
Compliance Voltage Range
When the device is not selected, high frequency logic activity
on the digital inputs of the device is capacitively coupled through
the device and produces noise on the IOUT pins and, subsequently,
on the circuitry that follows. This noise is digital feedthrough.
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1x terminal when all 0s are
loaded to the DAC.
Rev. C | Page 14 of 32
AD5429/AD5439/AD5449
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
When an output amplifier is connected in unipolar mode, the
output voltage is given by
The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit, dual-
channel, current output DACs consisting of a standard inverting
R-2R ladder configuration. Figure 37 shows a simplified diagram
for a single channel of the AD5449. The feedback resistor, RFBA,
has a value of R. The value of R is typically 10 kΩ (with a
minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT1A and
IOUT2A are kept at the same potential, a constant current flows
into each ladder leg, regardless of digital input code. Therefore,
the input resistance presented at VREFA is always constant.
VOUT = −VREF × D/2n
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)
n is the number of bits.
R
R
R
V
A
REF
With a fixed 10 V reference, the circuit shown in Figure 38 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
2R
S1
2R
S2
2R
S3
2R
2R
R
S12
R
A
FB
I
I
1A
2A
OUT
OUT
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation using the 8-bit
AD5429 DAC.
DAC DATA LATCHES
AND DRIVERS
Table 5. Unipolar Code Table
Figure 37. Simplified Ladder
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
Access is provided to the VREFx, RFBx, IOUT1x, and IOUT2x termi-
nals of the DACs, making the devices extremely versatile and
allowing them to be configured in several operating modes, such
as unipolar mode, bipolar output mode, or single-supply mode.
−VREF (255/256)
−VREF (128/256) = −VREF/2
−VREF (1/256)
−VREF (0/256) = 0
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 38.
V
DD
R2
C1
A1
V
R
A
DD
FB
I
1A
AD5429/
AD5439/
AD5449
OUT
V
V
x
REF
REF
I
2A
R1
OUT
V
= 0V TO –V
REF
OUT
SYNC SCLK SDIN GND
MICROCONTROLLER
AGND
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
3. DAC B OMITTED FOR CLARITY.
Figure 38. Unipolar Operation
Rev. C | Page 15 of 32
AD5429/AD5439/AD5449
Bipolar Operation
Stability
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can easily be accomplished by using another external
amplifier and three external resistors, as shown in Figure 39.
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as closely as possible, and
proper PCB layout techniques must be used. Because every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited gain bandwidth product (GBP) and
there is excessive parasitic capacitance at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in the closed-
loop applications circuit.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. When connected in bipolar mode, the output
voltage is
VOUT
=
(
V
REF ×D/2n − 1
− VREF
)
As shown in Figure 38 and Figure 39, an optional compensation
capacitor, C1, can be added in parallel with RFBx for stability.
Too small a value of C1 can produce ringing at the output,
whereas too large a value can adversely affect the settling time.
C1 should be found empirically, but 1 pF to 2 pF is generally
adequate for the compensation.
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)
n is the number of bits.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation with the AD5429.
Table 6. Bipolar Code
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
+VREF (255/256)
0
−VREF (255/256)
−VREF (256/256)
R3
20kΩ
V
V
DD
R2
R5
20kΩ
C1
R
A
DD
FB
R4
10kΩ
R1
I
1A
AD5429/
AD5439/
AD5449
OUT
V
x
V
±10V
A1
REF
REF
A2
I
2A
R1
OUT
V
= –V
REF
TO +V
REF
SYNC SCLK SDIN
GND
OUT
AGND
MICROCONTROLLER
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC.
OUT
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
4. DAC B AND ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. Bipolar Operation
Rev. C | Page 16 of 32
AD5429/AD5439/AD5449
Note that VIN is limited to low voltages because the switches
in the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, VIN must not go negative by
more than 0.3 V, or an internal diode turns on, causing the device
to exceed the maximum ratings. In this type of application, the
full range of multiplying capability of the DAC is lost.
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 40 shows the DACs operating in voltage-switching mode.
The reference voltage, VIN, is applied to the IOUT1A pin; IOUT2A
is connected to AGND; and the output voltage is available at the
VREFA terminal. In this configuration, a positive reference voltage
results in a positive output voltage, making single-supply operation
possible. The output from the DAC is voltage at a constant
impedance (the DAC ladder resistance). Therefore, an op amp
is necessary to buffer the output voltage. The reference input
no longer sees a constant input impedance; instead, it sees one
that varies with code. Therefore, the voltage input should be
driven from a low impedance source.
Positive Output Voltage
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier because
of the resistor tolerance errors. To generate a negative reference,
the reference can be level-shifted by an op amp such that the VOUT
and GND pins of the reference become the virtual ground and
−2.5 V, respectively, as shown in Figure 41.
V
V
DD
R1
R2
R
A
FB
DD
V
I
1A
IN
OUT
V
8-/10-/12-BIT
DAC
OUT
V
A
REF
I
2A
OUT
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 40. Single-Supply Voltage-Switching Mode
V
= +5V
DD
ADR03
V
V
IN
OUT
GND
+5V
C1
R
A
V
FB
DD
–2.5V
I
I
1A
2A
OUT
V
A
8-/10-/12-BIT
DAC
REF
OUT
V
= 0V TO +2.5V
OUT
GND
–5V
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 41. Positive Voltage Output with Minimum Components
Rev. C | Page 17 of 32
AD5429/AD5439/AD5449
As D is reduced, the output voltage increases. For small values of
the Digital Fraction D, it is important to ensure that the amplifier
does not saturate and the required accuracy is met. For example,
an 8-bit DAC driven with binary code of 0x10 (0001 0000)—that
is, 16 decimal—in the circuit of Figure 43 should cause the output
voltage to be 16 × VIN. However, if the DAC has a linearity speci-
fication of 0.5 LSB, D can have a weight in the range of 15.5/256
to 16.5/256, so that the possible output voltage is in the range of
15.5 VIN to 16.5 VIN. This range represents an error of 3%, even
though the DAC itself has a maximum error of 0.2%.
ADDING GAIN
In applications in which the output voltage must be greater than
VIN, gain can be added with an additional external amplifier, or
it can be achieved in a single stage. Consider the effect of temper-
ature coefficients of the thin film resistors of the DAC. Simply
placing a resistor in series with the RFB resistor causes mismatches
in the temperature coefficients, resulting in larger gain temper-
ature coefficient errors. Instead, the circuit in Figure 42 shows
the recommended method of increasing the gain of the circuit.
R1, R2, and R3 should have similar temperature coefficients,
but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits in which
gains of greater than 1 are required.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current into the VREFx terminal
is routed to the IOUT1 terminal, the output voltage changes as
follows:
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves
to many applications. If this type of DAC is connected as the
feedback element of an op amp and RFBA is used as the input
resistor, as shown in Figure 43, the output voltage is inversely
proportional to the digital input fraction, D.
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREFx terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
For D = 1 − 2−n, the output voltage is
− n
(
)
VOUT = −VIN /D = −VIN / 1−2
V
DD
C1
V
R
A
DD
FB
I
1A
2A
OUT
R1
8-/10-/12-BIT
DAC
V
V
V
A
IN
OUT
REF
I
OUT
R3
GND
R2 + R3
R2
GAIN =
R2
R2R3
R2 + R3
R1 =
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 42. Increasing Gain of Current Output DAC
V
DD
V
IN
R
A
V
FB
DD
I
1A
OUT
8-/10-/12-BIT
DAC
V
A
REF
I
2A
OUT
GND
V
OUT
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 43. Current-Steering DAC Used as a Divider or Programmable Gain Element
Rev. C | Page 18 of 32
AD5429/AD5439/AD5449
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity
error, which, if large enough, could cause the DAC to be non-
monotonic. The input bias current of an op amp also generates
an offset at the voltage output as a result of the bias current flowing
in the feedback resistor, RFB. Most op amps have input bias
currents low enough to prevent significant errors in 12-bit
applications.
REFERENCE SELECTION
When selecting a reference for use with the AD54xx series of
current output DACs, pay attention to the reference output voltage
temperature coefficient specification. This parameter affects not
only the full-scale error, but it can also affect the linearity (INL and
DNL) performance. The reference temperature coefficient should
be consistent with the system accuracy specifications. For example,
an 8-bit system required to hold its overall specification to within
1 LSB over the temperature range of 0°C to 50°C dictates that the
maximum system drift with temperature should be less than
78 ppm/°C. A 12-bit system with the same temperature range
to overall specification within 2 LSBs requires a maximum drift
of 10 ppm/°C. By choosing a precision reference with a low output
temperature coefficient, this error source can be minimized.
Table 7 lists some references available from Analog Devices, Inc.,
that are suitable for use with this range of current output DACs.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.
If the DAC switches are driven from true wideband low impedance
sources (VIN and AGND), they settle quickly. Consequently, the
slew rate and settling time of a voltage-switching DAC circuit
is determined largely by the output op amp. To obtain minimum
settling time in this configuration, minimize capacitance at the
AMPLIFIER SELECTION
VREF node (the voltage output node in this application) of the
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier input offset voltage. This output
DAC by using low input capacitance buffer amplifiers and careful
board design.
Most single-supply circuits include ground as part of the analog
signal range, which, in turn, requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a wide range of single-
supply amplifiers (see Table 8 and Table 9).
Table 7. Suitable Analog Devices Precision References
Part No. OutputVoltage (V) Initial Tolerance (%)
Temp Drift (ppm/°C)
ISS (mA)
Output Noise (μV p-p) Package
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
10
10
5
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
3
9
3
9
3
9
3
9
3
3
9
9
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
20
20
10
10
6
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
5
2.5
2.5
3
3
2.5
5
6
10
10
3.5
8
5
8
2.5
5
Table 8. Suitable Analog Devices Precision Op Amps
Part No. Supply Voltage (V)
VOS (Max) (μV)
IB (Max) (nA) 0.1 Hz to 10 Hz Noise (μV p-p) Supply Current (μA) Package
OP97
2 to 20
2.5 to 15
2.7 to 5
1.8 to 6
2.7 to 6
25
60
5
50
5
0.1
2
0.05
0.001
0.1
0.5
0.4
1
2.3
0.5
600
500
975
50
SOIC-8
OP1177
AD8551
AD8603
AD8628
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
850
TSOT, SOIC-8
Table 9. Suitable Analog Devices High Speed Op Amps
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V) BW ꢁ ACL (MHz) Slew Rate (V/μs)
VOS (Max) (μV) IB (Max) (nA)
Package
5 to 24
145
490
350
320
180
120
425
1300
1500
1000
3000
10,000
6000
10,500
750
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
2.5 to 12
3 to 12
3 to 6
7000
Rev. C | Page 19 of 32
AD5429/AD5439/AD5449
SDO Control (SDO1 and SDO2)
SERIAL INTERFACE
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an open-drain
driver. The strength of the SDO driver affects the timing of t12,
and, when stronger, allows a faster clock cycle.
The AD5429/AD5439/AD5449 have an easy-to-use, 3-wire
interface that is compatible with SPI, QSPI, MICROWIRE, and
most DSP interface standards. Data is written to the device in
16-bit words. Each 16-bit word consists of four control bits and
eight, 10, or 12 data bits, as shown in Figure 44 through Figure 46.
Table 10. SDO Control Bits
Low Power Serial Interface
SDO2
SDO1
Function Implemented
0
0
Full SDO driver
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
0
1
1
1
0
1
Weak SDO driver
SDO configured as open drain
Disable SDO output
SYNC
on the falling edge of
. The SCLK and SDIN input buffers
SYNC
are powered down on the rising edge of
.
DAC Control Bit C3 to Control Bit C0
Daisy-Chain Control (DSY)
Control Bit C3 to Control Bit C0 allow control of various functions
of the DAC, as shown in Table 11. The default settings of the DAC
at power-on are such that data is clocked into the shift register
on falling clock edges and daisy-chain mode is enabled. The device
powers on with a zero-scale load to the DAC register and IOUT lines.
The DAC control bits allow the user to adjust certain features at
power-on. For example, daisy-chaining can be disabled if not in
use, an active clock edge can be changed to a rising edge, and DAC
output can be cleared to either zero scale or midscale. The user
can also initiate a readback of the DAC register contents for veri-
fication.
DSY allows the enabling or disabling of daisy-chain mode.
A 1 enables daisy-chain mode; a 0 disables daisy-chain mode.
When disabled, a readback request is accepted; SDO is auto-
matically enabled; the DAC register contents of the relevant
DAC are clocked out on SDO; and, when complete, SDO is
disabled again.
CLR
Hardware
The default setting for the hardware
and DAC output to zero code. A 1 in the HCLR bit allows the
CLR
Bit (HCLR)
CLR
bit is to clear the registers
pin to clear the DAC outputs to midscale, and a 0 clears to
zero scale.
Control Register (Control Bits = 1101)
Active Clock Edge (SCLK)
While maintaining software compatibility with single-channel
current output DACs (AD5426/AD5432/AD5443), these DACs
also feature additional interface functionality. Set the control bits
to 1101 to enter control register mode. Figure 47 shows the
contents of the control register, the functions of which are
described in the following sections.
The default active clock edge is a falling edge. Write a 1 to this
bit to clock data in on the rising edge, or a 0 to clock it in on the
falling edge.
DB15 (MSB)
DB0 (LSB)
C3
C2
C1
C0
C0
C0
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
CONTROL BITS
DATA BITS
Figure 44. AD5429 8-Bit Input Shift Register Contents
DB15 (MSB)
C3 C2
DB0 (LSB)
0 0
C1
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB2
X
CONTROL BITS
DATA BITS
Figure 45. AD5439 10-Bit Input Shift Register Contents
DB15 (MSB)
C3 C2
DB0 (LSB)
C1
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB1
DB0
CONTROL BITS
DATA BITS
Figure 46. AD5449 12-Bit Input Shift Register Contents
DB15 (MSB)
1
DB0 (LSB)
X X
1
0
SDO2 SDO1
DSY HCLR SCLK
X
X
X
X
CONTROL BITS
Figure 47. Control Register Loading Sequence
Rev. C | Page 20 of 32
AD5429/AD5439/AD5449
When control bits = 0000, the device is in no operation mode.
This may be useful in daisy-chain applications in which the user
does not want to change the settings of a particular DAC in the
chain. Write 0000 to the control bits for that DAC; subsequent
data bits are ignored.
SYNC
Function
SYNC
is an edge-triggered input that acts as a frame synchron-
ization signal and chip enable. Data can be transferred into the
device only while
SYNC
SYNC
is low. To start the serial data transfer,
SYNC
should be taken low, observing the minimum
Standalone Mode
falling edge to SCLK falling edge setup time, t4.
After power-on, write 1001 to the control word to disable daisy-
Daisy-Chain Mode
SYNC
chain mode. The first falling edge of
clock counter to ensure that the correct number of bits are
SYNC
resets the serial
Daisy-chain mode is the default power-on mode. To disable the
daisy-chain function, write 1001 to the control word. In daisy-
chain mode, the internal gating on SCLK is disabled. SCLK is
shifted in and out of the serial shift registers. A
edge
during the 16-bit write cycle causes the device to abort the
current write cycle.
SYNC
continuously applied to the input shift register when
is
low. If more than 16 clock pulses are applied, the data ripples
out of the shift register and appears on the SDO line. This data
is clocked out on the rising edge of SCLK (this is the default; use
the control word to change the active edge) and is valid for the
next device on the falling edge of SCLK (default). By connecting
this line to the SDIN input on the next device in the chain,
a multidevice interface is constructed. For each device in the
system, 16 clock pulses are required. Therefore, the total number
of clock cycles must equal 16n, where n is the total number of
devices in the chain. See Figure 4.
After the falling edge of the 16th SCLK pulse, data is automat-
ically transferred from the input shift register to the DAC. For
another serial transfer to take place, the counter must be reset
SYNC
by the falling edge of
.
LDAC
Function
LDAC
The
function allows asynchronous and synchronous
updates to the DAC output. The DAC is asynchronously updated
when this signal goes low. Alternatively, if this line is held perma-
nently low, an automatic or synchronous update mode is selected,
whereby the DAC is updated on the 16th clock falling edge when
SYNC
When the serial transfer to all devices is complete,
should
be taken high. This prevents additional data from being clocked
into the input shift register. A burst clock containing the exact
SYNC
the device is in standalone mode, or on the rising edge of
when the device is in daisy-chain mode.
SYNC
number of clock cycles can be used, after which
can be
, data is automatically
LDAC
Software
Load-and-update mode can also serve as a software update func-
LDAC
Function
SYNC
taken high. After the rising edge of
transferred from the input shift register of each device to the
addressed DAC.
tion, irrespective of the voltage level on the
pin.
Table 11. DAC Control Bits
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC
A and B
A
A
A
B
B
B
A and B
A and B
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Function Implemented
No operation (power-on default)
Load and update
Initiate readback
Load input register
Load and update
Initiate readback
Load input register
Update DAC outputs
Load input registers
Disable daisy-chain
Clock data to shift register on rising edge
Clear DAC output to zero scale
Clear DAC output to midscale
Control word
Reserved
No operation
Rev. C | Page 21 of 32
AD5429/AD5439/AD5449
See the ADSP-21xx user manual at www.analog.com for details
SYNC
Table 12 shows the setup for the SPORT control register.
MICROPROCESSOR INTERFACING
on clock and frame
frequencies for the SPORT register.
Microprocessor interfacing to the AD54xx family of DACs is
through a serial bus that uses standard protocol and is compatible
with microcontrollers and DSP processors. The communication
channel is a 3-wire interface consisting of a clock signal, a data
signal, and a synchronization signal. The AD5429/AD5439/
AD5449 require a 16-bit word, with the default being data valid
on the falling edge of SCLK; however, this is changeable using
the control bits in the data-word.
Table 12. SPORT Control Register Setup
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
Setting
Description
1
1
00
1
1
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
ADSP-21xx-to-AD5429/AD5439/AD5449 Interface
ITFS
SLEN
1
The ADSP-21xx family of DSPs is easily interfaced to an AD5429/
AD5439/AD5449 DAC without the need for extra glue logic.
Figure 48 is an example of a serial peripheral interface (SPI)
between the DAC and the ADSP-2191. The MOSI (master output,
slave input) pin of the DSP drives the serial data line, SDIN.
1111
ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface
The ADSP-BF5xx family of processors has an SPI-compatible port
that enables the processor to communicate with SPI-compatible
devices. A serial interface between the BlackFin® processor and
the AD5429/AD5439/AD5449 DAC is shown in Figure 50. In
this configuration, data is transferred through the MOSI pin.
SYNC
SPIxSEL
is driven from a port line, in this case
.
AD5429/AD5439/
AD5449
ADSP-2191*
SPIxSEL
*
SYNC
SDIN
SCLK
SYNC
SPIxSEL
is driven by the
pin, which is a reconfigured
MOSI
SCK
programmable flag pin.
AD5429/AD5439/
AD5449*
ADSP-BF5xx*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
SDIN
SCLK
SPIxSEL
MOSI
Figure 48. ADSP-2191 SPI-to-AD5429/AD5439/AD5449 Interface
The ADSP-2101/ADSP-2103/ADSP-2191 processor incorporates
channel synchronous serial ports (SPORT). A serial interface
between the DAC and DSP SPORT is shown in Figure 49. In this
interface example, SPORT0 is used to transfer data to the DAC
shift register. Transmission is initiated by writing a word to the Tx
register after SPORT has been enabled. In a write sequence, data
is clocked out on each rising edge of the DSP serial clock and
clocked into the DAC input shift register on the falling edge of
its SCLK. Updating of the DAC output takes place on the rising
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 50. ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface
A serial interface between the DAC and the DSP SPORT is shown
in Figure 51. When SPORT is enabled, initiate transmission by
writing a word to the Tx register. The data is clocked out on each
rising edge of the DSP serial clock and clocked into the DAC
input shift register on the falling edge of its SCLK. The DAC
output is updated by using the transmit frame synchronization
SYNC
edge of the
signal.
AD5429/AD5439/
AD5449*
ADSP-2101/
ADSP-2103/
SYNC
(TFS) line to provide a
signal.
ADSP-2191
*
TFS
DT
SYNC
AD5429/AD5439/
AD5449*
ADSP-BF5xx*
SDIN
TFS
DT
SYNC
SCLK
SCLK
SDIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 49. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-
AD5429/AD5439/AD5449 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 51. ADSP-BF5xx SPORT-to-AD5429/AD5439/AD5449 Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible: frame
SYNC
SYNC
delay and frame
data setup-and-hold, and SCLK width. The DAC interface expects
SYNC
setup-and-hold, data delay and
a t4 (
minimum.
falling edge to SCLK falling edge setup time) of 13 ns
Rev. C | Page 22 of 32
AD5429/AD5439/AD5449
80C51/80L51-to-AD5429/AD5439/AD5449 Interface
valid on the falling edge of SCK. Serial data from the 68HC11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 52. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line, SDIN.
P1.1 is a bit-programmable pin on the serial port and is used to
To load data to the DAC, leave PC7 low after the first eight bits
are transferred and perform a second serial write operation to
the DAC. PC7 is taken high at the end of this procedure.
SYNC
drive
. When data is to be transmitted to the switch, P1.1
is taken low. The 80C51/80L51 transmit data in 8-bit bytes only;
therefore, only eight falling clock edges occur in the transmit cycle.
If the user wants to verify the data previously written to the input
shift register, the SDO line can be connected to MISO of the
SYNC
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and then a second write cycle is initiated
to transmit the second byte of data. Data on RxD is clocked out
of the microcontroller on the rising edge of TxD and is valid on
the falling edge of TxD. As a result, no glue logic is required
between the DAC and microcontroller interface. P1.1 is taken
high following the completion of this cycle. The 80C51/80L51
provide the LSB of the SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
requirement into account.
MC68HC11, and, with
low, the shift register clocks data
out on the rising edges of SCLK.
MICROWIRE-to-AD5429/AD5439/AD5449 Interface
Figure 54 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC SCLK.
MICROWIRE*
AD5429/AD5439/
AD5449*
SK
SO
CS
SCLK
AD5429/AD5439/
80C51
*
SDIN
AD5449*
SYNC
TxD
RxD
P1.1
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 54. MICROWIRE-to-AD5429/AD5439/AD5449 Interface
PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 52. 80C51/80L51-to-AD5429/AD5439/AD5449 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 microcontroller user manual for
more information. In this example, the I/O port, RA1, is used to
MC68HC11-to-AD5429/AD5439/AD5449 Interface
Figure 53 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The SPI on the MC68HC11
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured
by writing to the SPI control register (SPCR); see the MC68HC11
user manual. The SCK of the MC68HC11 drives the SCLK of
the DAC interface; the MOSI output drives the serial data line
(SDIN) of the AD5429/AD5439/AD5449.
SYNC
provide a
signal and enable the serial port of the DAC. This
microcontroller transfers only eight bits of data during each serial
transfer operation; therefore, two consecutive write operations
are required. Figure 55 shows the connection diagram.
PIC16C6x/7x*
SCK/RC3
AD5429/AD5439/
AD5449*
SCLK
MC68HC11*
AD5429/AD5439/
AD5449*
SDI/RC4
RA1
SDIN
PC7
SCK
SYNC
SCLK
SDIN
SYNC
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 55. PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 53. MCH68HC11/68L11-to-AD5429/AD5439/AD5449 Interface
SYNC
The
is being transmitted to the AD5429/AD5439/AD5449, the
line is taken low (PC7). Data appearing on the MOSI output is
signal is derived from a port line (PC7). When data
SYNC
Rev. C | Page 23 of 32
AD5429/AD5439/AD5449
layout reduces the effects of feedthrough on the board. A micro-
strip technique is by far the best method, but its use is not always
possible with a double-sided board. In this technique, the compo-
nent side of the board is dedicated to the ground plane, and
signal traces are placed on the soldered side.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5429/AD5439/AD5449 is mounted should be
designed so that the analog and digital sections are separate
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
It is good practice to use compact, minimum lead-length PCB
layout design. Leads to the input should be as short as possible
to minimize IR drops and stray inductance.
The PCB metal traces between VREFx and RFBx should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close as
possible to the device.
The DAC should have ample supply bypassing of 10 μF in parallel
with 0.1 μF on the supply, located as close as possible to the
package, ideally right up against the device. The 0.1 μF capacitor
should have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types of
capacitors that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR, 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
EVALUATION BOARD FOR THE DAC
The evaluation board consists of an AD5429/AD5439/AD5449
DAC and a current-to-voltage amplifier, the AD8065. Included
on the evaluation board is a 10 V reference, the ADR01. An
external reference can also be applied via an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software allows the user
to write a code to the device.
Components, such as clocks, that produce fast-switching signals,
should be shielded with digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Power Supplies for the Evaluation Board
The board requires 12 V and +5 V supplies. The +12 V VDD
and −12 V VSS are used to power the output amplifier; the +5 V
supply is used to power the DAC (VDD) and transceivers (VCC).
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
Both supplies are decoupled to their respective ground plane
with 10 μF tantalum and 0.1 μF ceramic capacitors.
Rev. C | Page 24 of 32
AD5429/AD5439/AD5449
Evaluation Board Schematic and Artwork
Figure 56. Schematic of the Evaluation Board
Rev. C | Page 25 of 32
AD5429/AD5439/AD5449
Figure 57. Component-Side Artwork
Figure 58. Silkscreen—Component-Side View (Top)
Rev. C | Page 26 of 32
AD5429/AD5439/AD5449
Figure 59. Solder-Side Artwork
Rev. C | Page 27 of 32
AD5429/AD5439/AD5449
OVERVIEW OF AD54xx DEVICES
Table 13.
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
Resolution
No. DACs
INL (LSB)
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package1
RU-16, CP-20
RM-10
RU-20
Features
8
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
0.25
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
0.25
1
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
8
8
8
8
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
RU-24
UJ-8
RM-10
RM-8
RU-24
CP-40
0.5
1
1
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
1
RU-20, CP-20
RU-24
1
1
0.5
1
2
1
RU-16
UJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
10 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
1
1
1
RM-8
RU-38
2
2
RM-8
RU-28
2
2
RU-16
RU-38
1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. C | Page 28 of 32
AD5429/AD5439/AD5449
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 60. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Resolution
INL (LSB)
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation Board
Evaluation Board
Evaluation Board
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
AD5429YRU
8
8
8
8
8
8
AD5429YRU-REEL
AD5429YRU-REEL7
AD5429YRUZ
AD5429YRUZ-REEL
AD5429YRUZ-REEL7
AD5439YRU
AD5439YRU-REEL
AD5439YRU-REEL7
AD5439YRUZ
AD5439YRUZ-REEL
AD5439YRUZ-REEL7
AD5449YRU
AD5449YRU-REEL
AD5449YRU-REEL7
AD5449YRUZ
AD5449YRUZ-REEL
AD5449YRUZ-REEL7
EVAL-AD5429EBZ
EVAL-AD5439EB
EVAL-AD5449EBZ
10
10
10
10
10
10
12
12
12
12
12
12
1
1
1
1
1
1 Z = RoHS Compliant Part.
Rev. C | Page 29 of 32
AD5429/AD5439/AD5449
NOTES
Rev. C | Page 30 of 32
AD5429/AD5439/AD5449
NOTES
Rev. C | Page 31 of 32
AD5429/AD5439/AD5449
NOTES
©2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04464-0-4/10(C)
Rev. C | Page 32 of 32
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