EVAL-AD5504EBZ [ADI]
High Voltage, Quad-Channel 12-Bit Voltage Output DAC; 高压，四通道12位电压输出DAC
| 型号： | EVAL-AD5504EBZ |
| 厂家： | 
ADI |
| 描述： | High Voltage, Quad-Channel 12-Bit Voltage Output DAC |
| 文件： | 总20页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage, Quad-Channel
12-Bit Voltage Output DAC
Data Sheet
AD5504
FEATURES
GENERAL DESCRIPTION
Quad-channel high voltage DAC
12-bit resolution
The AD5504 is a quad-channel, 12-bit, serial input, digital-to-
analog converter with on-chip high voltage output amplifiers
and an integrated precision reference. The DAC output voltage
Pin selectable 30 V or 60 V output range
Integrated precision reference
Low power serial interface with readback capability
Integrated temperature sensor alarm function
Power-on reset
R_SEL
ranges are programmable via the range select pin (
). If
R_SEL
is held high, the DAC output ranges are 0 V to 30 V. If
R_SEL
is held low, the DAC output ranges are 0 V to 60 V. The
on-chip output amplifiers allow an output swing within the
range of AGND + 0.5 V to VDD − 0.5 V.
LDAC
Simultaneous updating via
Wide operating temperature: −40°C to +105°C
The AD5504 has a high speed serial interface, which is com-
patible with SPI®-, QSPI™-, MICROWIRE™-, and DSP-interface
standards and can handle clock speeds of up to 16.667 MHz.
APPLICATIONS
Programmable voltage sources
High voltage LED drivers
Receiver bias in optical communications
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
CLR R_SEL
LOGIC
LDAC
1713kΩ
REFERENCE
122.36kΩ
–
V
V
V
V
SDI
SDO
INPUT
REGISTER
A
DAC
REGISTER
A
OUTA
OUTB
OUTC
OUTD
DACA
+
12
12
12
12
12
1713kΩ
INPUT
SCLK
SYNC
ALARM
CONTROL
LOGIC
122.36kΩ
–
INPUT
REGISTER
B
DAC
REGISTER
B
DAC B
+
1713kΩ
122.36kΩ
–
POWER-ON
RESET
INPUT
REGISTER
C
DAC
REGISTER
C
DAC C
+
1713kΩ
122.36kΩ
–
+
INPUT
REGISTER
D
DAC
REGISTER
D
DAC D
POWER-DOWN
CONTROL LOGIC
AD5504
TEMPERATURE
SENSOR
DGND
AGND
Figure 1.
Rev. B
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2009-2012 Analog Devices, Inc. All rights reserved.
www.analog.com
AD5504
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power-Down Mode.................................................................... 14
DAC Channel Architecture....................................................... 14
Selecting the Output Range ...................................................... 14
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 14
Power-Up State ........................................................................... 14
CLR
Function.............................................................................. 14
LDAC
Function .......................................................................... 14
Temperature Sensor ................................................................... 15
Power Dissipation....................................................................... 15
Power Supply Sequencing ......................................................... 15
Serial Interface ................................................................................ 16
Write Mode ................................................................................. 16
Read Mode .................................................................................. 16
Writing to the Control Register................................................ 16
Interfacing Examples ................................................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
12/12—Rev. A to Rev. B
Changes to t4 Parameter, Table 4 .................................................... 6
Changes to Figure 3 and Figure 4................................................... 7
Changes to Pin 3 Description, Table 7 and Pin 4 Description,
Table 7 ................................................................................................ 9
Changes to Write Mode Section ................................................... 16
Changes to Table 10........................................................................ 17
10/10—Rev. 0 to Rev. A
Changes to Figure 3 and Figure 4................................................... 7
7/09—Revision 0: Initial Version
Rev. B | Page 2 of 20
Data Sheet
AD5504
The serial interface offers the user the capability of both writing
to, and reading from, most of the internal registers. To reduce
power consumption at power up, only the digital section of the
AD5504 is powered up initially. This gives the user the ability to
program the DAC registers to the required value while typically
only consuming 30 μA of supply current. The AD5504 incor-
porates power-on reset circuitry that ensures the DAC registers
power up in a known condition and remain there until a valid
write to the device has taken place. The analog section is
powered up by issuing a power-up command via the SPI
interface. The AD5504 provides software-selectable output
loads while in the power-down mode.
The AD5504 has an on-chip temperature sensor. When the
ALARM
active low CMOS output pin) flags an alarm and the AD5504
enters a temperature power-down mode disconnecting the
output amplifier thus removing the short-circuit condition. The
AD5504 remains in power-down mode until a software power-up
command is executed.
temperature on the die exceeds 110°C, the
pin (an
The AD5504 is available in a compact 16-lead TSSOP. The AD5504
is guaranteed to operate over the extended temperature range of
−40°C to +105°C.
Table 1. Related Device
Part No.
Description
AD5501
High Voltage, 12-Bit Voltage Output DAC
Rev. B | Page 3 of 20
AD5504
Data Sheet
SPECIFICATIONS
VDD = 10 V to 62 V; VLOGIC = 2.3 V to 5.5 V; RL = 60 kΩ; CL = 200 pF; −40°C < TA < +105°C, unless otherwise noted.
Table 2.
Parameter
Symbol Min
Typ1 Max
Unit
Test Conditions/Comments
ACCURACY2
Resolution
12
Bits
LSB
Differential Nonlinearity
Integral Nonlinearity
60 V Mode
DNL
INL
−1
1
−2
−3
+2
+3
LSB
LSB
VDD = 62 V
30 V Mode
VDD = 62 V
VOUTX Temperature Coefficient3, 4, 5
Zero-Scale Error
Zero-Scale Error Drift4
Offset Error6
Offset Error Drift4
Full-Scale Error
Full-Scale Error Drift4
50
ppm/°C
mV
µV/°C
mV
µV/°C
mV
mV/°C
µV/°C
% of FSR
DAC code = half scale
DAC code = 0
60 V mode
VZSE
VOE
VFSE
100
60
+120
60
+275
1
350
+0.6
10
−80
60 V mode
−325
−40°C to +25°C; 60 V mode
+25°C to +105°C; 60 V mode
Gain Error
Gain Temperature Coefficient4
DC Crosstalk4
Due to Single Channel Full-Scale
Output Change
−0.6
ppm of FSR/°C 60 V mode
RL = 60 kΩ to AGND or VDD
60 V mode
3
4
mV
mV
Due to Powering Down (Per Channel)
OUTPUT CHARACTERISTICS
Output Voltage Range7
Short-Circuit Current4, 8
Capacitive Load Stability4
RL = 60 kΩ to ∞
60 V mode
AGND + 0.5
VDD − 0.5
V
mA
2
On any single channel
1 V to 4 V step
1
+1
nF
mA
Ω
Load Current4
−1
On any single channel
DC Output Impedance4
DC Output Leakage4
DIGITAL INPUTS
3
10
µA
Input Logic High
VIH
2.0
1.8
V
V
V
µA
pF
VLOGIC = 4.5 V to 5.5 V
VLOGIC = 2.3 V to 3.6 V
VLOGIC = 2.3 V to 5.5 V
Input Logic Low
Input Current
Input Capacitance4
VIL
IIL
IIC
0.8
1
5
5
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
Three-State Leakage Current
SDI, SDO, SCLK, LDAC, CLR, R_SEL
ALARM
VOH
VOL
VLOGIC − 0.4 V
V
V
ISOURCE = 200 µA
ISINK = 200 µA
DGND + 0.4 V
−1
+1
µA
µA
pF
−10
+10
Output Capacitance4
Rev. B | Page 4 of 20
Data Sheet
AD5504
Parameter
Symbol Min
Typ1 Max
Unit
Test Conditions/Comments
POWER SUPPLIES
VDD
10
62
V
VLOGIC
2.3
5.5
V
Quiescent Supply Current (IQUIESCENT
)
2
3
mA
Static conditions; DAC
outputs = midscale
Logic Supply Current (ILOGIC
DC PSRR4
)
0.4
2
µA
VIH = VLOGIC; VIL = DGND
DAC output = full-scale
60 V Mode
30 V Mode
68
76
dB
dB
POWER-DOWN MODE
Supply Current
Software Power-Down Mode
Junction Temperature8
IDD_PWD
TJ
30
50
130
µA
°C
TJ = TA + PTOTAL × θJA
1 Typical specifications represent average readings at 25°C, VDD = 62 V and VLOGIC = 5 V.
2 Valid in output voltage range of (VDD − 0.5 V) to (AGND + 0.5 V). Outputs are unloaded.
3 Includes linearity, offset, and gain drift.
4 Guaranteed by design and characterization. Not production tested.
5 VOUTX refers to VOUTA, VOUTB, VOUTC, or VOUTD
.
6 DAC code = 32 for 60 V mode; DAC code = 64 for 30 V mode.
7
R_SEL
R_SEL
is held low. As the output voltage range is
The DAC architecture gives a fixed linear voltage output range of 0 V to 30 V if
is held high and 0 V to 60 V if
limited by output amplifier compliance, VDD should be set to at least 0.5 V higher than the maximum output voltage to ensure compliance.
8 If the die temperature exceeds 110°C, the AD5504 enters a temperature power-down mode putting the DAC outputs into a high impedance state thereby removing
the short-circuit condition. Overheating caused by long term short-circuit condition(s) is detected by an integrated thermal sensor. After power-down, the AD5504
stays powered down until a software power-up command is executed.
AC CHARACTERISTICS
VDD = 10 V to 62 V; VLOGIC = 2.3 V to 5.5 V; RL = 60 kΩ; CL = 200 pF; −40°C < TA < +105°C, unless otherwise noted.
Table 3.
Parameter1, 2
Min Typ
Max
Unit
Test Conditions/Comments3
AC CHARACTERISTICS
Output Voltage Settling Time
60 V Mode
¼ to ¾ scale settling to 1 LSB, RL = 60 kΩ
45
25
55
35
µs
µs
30 V Mode
Slew Rate
0.65
300
170
40
V/µs
nV-s
mV
nV-s
nV-s
nV-s
nV-s
μV p-p
mV p-p
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Peak-to-Peak Noise
1 LSB change around major carry in 60 V mode
60 V mode
5
600
600
140
4
0.1 Hz to 10 Hz; DAC code = 0x800
0.1 Hz to 10 kHz; DAC code = 0x800
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to + 105°C, typical at 25°C.
Rev. B | Page 5 of 20
AD5504
Data Sheet
TIMING CHARACTERISTICS
VDD = 30 V, VLOGIC = 2.3 V to 5.5 V and −40°C < TA < +105°C; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Limit1
60
10
10
25
15
5
Unit
Test Conditions/Comments
SCLK cycle time
2
t1
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
μs typ
ns min
ns max
ns min
μs max
μs max
μs typ
t2
t3
t4
SCLK high time
SCLK low time
SYNC falling edge to SCLK rising edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width low
t5
t6
t7
0
t8
20
20
50
15
100
20
110
55
25
50
50
5
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
SCLK falling edge to LDAC rising edge
CLR pulse width low
CLR pulse activation time
ALARM clear time
SCLK cycle time in read mode
SCLK rising edge to SDO valid
SCLK to SDO data hold time
Power-on reset time (this is not shown in the timing diagrams)
Power-on time (this is not shown in the timing diagrams)
3
3
4
5
t19
ALARM
clear to output amplifier turn on (this is not shown in the timing
diagrams)
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 16.667 MHz.
3 Under load conditions shown in Figure 2.
4 Time from when the VDD/VLOGIC supplies are powered-up to when a digital interface command can be executed.
5 Time required from execution of power-on software command to when the DAC outputs have settled to 1 V.
200µA
I
OL
V
(MIN) – V (MAX)
OL
OH
TO OUTPUT
PIN
2
C
L
50pF
200µA
I
OH
Figure 2. Load Circuit for SDO Timing Diagram
Rev. B | Page 6 of 20
Data Sheet
AD5504
t1
t4
SCLK
t2
t8
t7
t3
SYNC
SDI
t6
t5
R/W
D0
t9
1
LDAC
t10
2
LDAC
t11
CLR
3
t13
ALARM
t12
4
V
OUTx
1
2
3
4
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
IN THE EVENT OF OVERTEMPERATURE CONDITION.
V
REFERS TO ANY OF V
, V
V
OR V
.
OUTx
OUTA OUTB, OUTC
OUTD
Figure 3. Write Timing Diagram
t14
SCLK
SYNC
SDI
X
A2
X
X
X
X
X
X
R/W
A1
A0
t16
t15
D8
D11
D10
D9
D0
D2
D1
SDO
Figure 4. Read Timing Diagram
Rev. B | Page 7 of 20
AD5504
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Thermal resistance is for a JEDEC 4-layer(2S2P) board.
Table 5.
Parameter
Rating
Table 6. Thermal Resistance
Package Type
16-Lead TSSOP
VDD to AGND
VLOGIC to DGND
−0.3 V, + 64 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to +0.3 V
150°C
θJA
Unit
VOUTX to AGND1
Digital Input to DGND
SDO Output to DGND
AGND to DGND
Maximum Junction Temperature
(TJ Maximum)
112.60
°C/W
ESD CAUTION
Storage Temperature Range
Reflow Soldering
−65°C to +150°C
Peak Temperature
260°C
Time at Peak Temperature Range
20 sec to 40 sec
1 VOUTX refers to VOUTA, VOUTB, VOUTC, or VOUTD
.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 8 of 20
Data Sheet
AD5504
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
SYNC
SCLK
SDI
V
LOGIC
ALARM
V
AD5504
TOP VIEW
(Not to Scale)
DD
R_SEL
SDO
V
V
V
V
OUTA
OUTB
OUTC
OUTD
DGND
AGND
LDAC
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the input register and the DAC register are set to 0x000 and the outputs to zero scale.
SYNC
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes
low, it enables the input shift register and data is transferred in on the rising edges of the following clocks. The
selected DAC register is updated on the 16th falling SCLK, unless SYNC is taken high before this edge, in which case, the
rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
3
4
5
SCLK
SDI
Serial Clock Input. Data is clocked into the input shift register on the rising edge of the serial clock input. Data can
be transferred at rates up to 16 MHz.
Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the rising edge of the
serial clock input.
Serial Data Output. CMOS output. This pin serves as the readback function for all DAC and control registers. Data
is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
SDO
6
7
8
DGND
AGND
LDAC
Digital Ground Pin.
Analog Ground Pin.
Load DAC Input. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new
data. This allows all DAC outputs to update simultaneously. Alternatively, this pin can be tied permanently low.
9
VOUTD
VOUTC
VOUTB
VOUTA
R_SEL
Buffered Analog Output Voltage from DAC D.
Buffered Analog Output Voltage from DAC C.
Buffered Analog Output Voltage from DAC B.
Buffered Analog Output Voltage from DAC A.
10
11
12
13
Range Select Pin. Tying this pin to DGND selects a DAC output range of 0 V to 60 V, alternatively tying R_SEL to
V
LOGIC selects a DAC output range of 0 V to 30 V.
14
VDD
Positive Analog Power Supply. 10 V to 62 V for the specified performance. This pin should be decoupled with 0.1 µF
ceramic capacitors and 10 µF capacitors.
15
16
ALARM
VLOGIC
Active Low CMOS Output Pin. This pin flags an alarm if the temperature on the die exceeds 110°C.
Logic Power Supply; 2.3 V to 5.5 V. Decouple this pin with 0.1µF ceramic capacitors and 10 µF capacitors.
Rev. B | Page 9 of 20
AD5504
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.8
45.0025
45.0000
44.9975
44.9950
44.9925
0.4
0
–0.4
–0.8
32
1008
2048
3056
4064
0
0.05
0.10
0.15
0.20
CODE
TIME (ms)
Figure 6. Typical INL
Figure 9. Output Settling Time (Low to High)
0.50
0.25
200
100
0
V
V
= 62V
DD
OUTx
= 30V
0
–0.25
–0.50
–100
–200
0
32
1008
2048
3056
4064
2.5
5.0
7.5
10.0
CODE
TIME (Seconds)
Figure 10. Output Noise
Figure 7. Typical DNL
15.0050
15.0025
15.0000
14.9975
14.9950
0.70
0.65
0.60
0.55
V
V
= 62V
, V
DD
OUTB OUTC
, AND V POWERED DOWN
OUTD
0.50
0
0
0.05
0.10
0.15
0.20
15
30
45
60
TIME (ms)
V
(V)
OUTA
Figure 8. Output Settling Time (High to Low)
Figure 11. IDD vs. VOUTA
Rev. B | Page 10 of 20
Data Sheet
AD5504
2.2
0.20
0.15
0.10
0.05
0
V
V
= 62V
DD
= V
= V
OUTC
= V
OUTD
OUTA
OUTB
2.1
2.0
1.9
–0.05
–0.10
–0.15
–0.20
V
V
V
V
= 30V; V SWITCHING
OUTB
OUTA
OUTB
OUTB
OUTB
= 0V TO 30V
= 0V TO 45V
= 0V TO 60V
1.8
0
15
30
OUTPUT VOLTAGE (V)
45
60
15
15
0
2
4
6
8
10
TIME (µs)
Figure 12. IDD vs. VOUTA to VOUTD
Figure 15. DAC-to-DAC Crosstalk
2
0
6
5
4
3
2
1
0
V
OUTD
OUTB
–2
–4
–6
–8
V
V
V
OUTC
OUTA
–10
0
5
10
–1.0
–0.5
0
0.5
1.0
TIME (ms)
LOAD CURRENT (mA)
Figure 13. Digital-to-Analog Negative Glitch Impulse
Figure 16. DAC-to-DAC Mismatch
12
10
8
6
4
2
0
–2
–4
0
5
10
TIME (ms)
Figure 14. Digital-to-Analog Positive Glitch Impulse
Rev. B | Page 11 of 20
AD5504
Data Sheet
TERMINOLOGY
Gain Temperature Coefficient
Relative Accuracy
The gain temperature coefficient is a measure of the change in
gain with changes in temperature. It is expressed in (ppm of
full-scale range)/°C.
For the DAC, relative accuracy, or integral nonlinearity (INL),
is a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer function.
Digital-to-Analog Glitch Impulse
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition.
Zero-Code Error
DC and AC Power Supply Rejection Ratio (PSRR)
Zero-code error is a measure of the output error when zero
code (0x000) is loaded into the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5504 because the output of the DAC cannot go below 0 V.
It is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in millivolts.
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUTA
,
V
OUTB, VOUTC, or VOUTD to a change in VDD for full-scale output of
the DAC. It is measured in decibels. For dc PSRR, VDD is dc
varied 10%. For ac PSRR, VDD is ac varied 10%.
DC Crosstalk
Zero-Code Error Drift
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in millivolts.
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Offset Error
A measure of the difference between VOUT (actual) and VOUT
(ideal) expressed in millivolts in the linear region of the transfer
function. Offset error is measured on the AD5504 with Code 32
loaded in the DAC registers for 60 V mode and with Code 64
loaded in the DAC registers for 30 V mode. Offset error is
expressed in millivolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in μV/mA.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to
Offset Error Drift
Offset error drift is a measure of the change in offset error with
a change in temperature. It is expressed in μV/°C.
SYNC
(
held high). It is specified in nV-s and measured with a
full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFF) is loaded into the DAC register. Full-scale error is
expressed in millivolts.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping
high, and then pulsing
Full-Scale Error Drift
Full-scale error drift is a measure of the change in full-scale
error with a change in temperature. It is expressed in μV/°C.
LDAC
LDAC
low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Rev. B | Page 12 of 20
Data Sheet
AD5504
DAC-to-DAC Crosstalk
Capacitive Load Stability
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
Capacitive load stability refers to the ability of the amplifier to
drive a capacitive load. An amplifier output is considered stable
if any overshoot or ringing has stopped before approximately
1.5 times the settling time of the DAC has elapsed.
LDAC
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-s.
Rev. B | Page 13 of 20
AD5504
Data Sheet
THEORY OF OPERATION
The AD5504 contains four DACs, four output amplifiers, and a
precision reference in a single package. The architecture of a
single DAC channel consists of a 12-bit resistor string DAC
followed by an output buffer amplifier. The part operates from
a single-supply voltage of 10 V to 62 V. The DAC output voltage
format for the AD5501 is straight binary and the output voltage
follows the formula
D
4096
VOUT
=
× Range
where:
D is the code loaded to the DAC.
R_SEL
range is selected via the range select,
, pin. The DAC
is held high and 0 V to
is held low. Data is written to the AD5504 in a
R_SEL
output range is 0 V to 30 V if
R_SEL
R_SEL
R_SEL
is low.
Range = 30, if
is high, and 60 if
60 V if
PRECISION
REFERENCE
16-bit word format (see Table 8), via a serial interface.
POWER-UP STATE
INPUT
DAC
REGISTER
On power-up, the power-on reset circuitry clears the bits of the
control register to 0x40 (see Table 10). This ensures that the
analog section is initially powered down, which helps reduce
power consumption. The user can program the DAC registers
to the required values while typically consuming only 30 µA of
supply current. The power-on reset circuitry also ensures that
all the input and DAC registers power up in a known condition,
0x000, and remain there until a valid write to the device has
taken place. The analog section can be powered up by setting
any or all of Bit C2 to Bit C5 of the control register to 1.
GAIN
DAC
V
OUTx
REGISTER
12
12
AGND
Figure 17. DAC Channel Architecture (Single-Channel Shown)
SELECTING THE OUTPUT RANGE
R_SEL
The output range of the DACs is selected by the
pin.
pin is connected to Logic 1, the DAC output
R_SEL
R_SEL
When the
voltages can be set between 0 V and 30 V. When the
is connected to Logic 0, the DAC output voltages can be set
R_SEL
pin
POWER-DOWN MODE
Each DAC channel can be individually powered up or powered
down by programming the control register (see Table 10).
When the DAC channel is powered down, the associated analog
circuitry turns off to reduce power consumption. The digital
section of the AD5504 remains powered up. The output of the
DAC amplifier can be three-stated or connected to AGND via
an internal 20 kΩ resistor, depending on the state of Bit C6 in
the control register. The power-down mode does not change the
contents of the DAC register to ensure that the DAC channel
returns to its previous voltage when the power-down bit is set to 1.
The AD5504 also offers the user the flexibility of updating the
DAC registers during power-down. The control register can be
read back at any time to check the status of the bits.
between 0 V and 60 V. The state of
time when the serial interface is not being used, that is, not
R_SEL
can be changed any
during a read or write operation. When the
changed, the voltage on the output pin remains the same until
LDAC
pin is
the next write to the DAC register (and
For example, if the user writes 0x800 to the DAC register when
R_SEL
is brought low).
in 30 V mode (
= 1), the output voltage is 15 V (assuming
LDAC
is low or has been pulsed low). When the user switches
R_SEL
to 60 V mode (
user writes a new value to the DAC register.
or be pulsed low for the output to change.
= 0), the output stays at 15 V until the
LDAC
must be low
CLR FUNCTION
DAC CHANNEL ARCHITECTURE
CLR
The AD5504 has a hardware
pin that is an asynchronous
input is falling edge sensitive. Bringing the
line low clears the contents of the input register and the
The architecture of a single DAC channel consists of a 12-bit
resistor string DAC followed by an output buffer amplifier (see
Figure 17). The resistor string section is simply a string of
resistors, each of Value R from VREF generated by the precision
reference to AGND. This type of architecture guarantees DAC
monotonicity. The 12-bit binary digital code loaded to the DAC
register determines at which node on the string the voltage is
tapped off before being fed into the output amplifier. The
output amplifier multiplies the DAC output voltage to give a
CLR
clear input. The
CLR
CLR
DAC registers to 0x000. The
pulse activation time, that is,
CLR
the falling edge of
typically 100 ns.
to when the output starts to change, is
LDAC FUNCTION
LDAC
The DAC outputs can be updated using the hardware
LDAC
LDAC
is normally high. On the falling edge of , data
is copied from the input registers to the DAC registers, and the
DAC outputs are updated simultaneously (asynchronous update
pin.
R_SEL
fixed linear voltage output range of 0 V to 60 V if
= 0
R_SEL
or 0 V to 30 V if
= 1. Each output amplifier is capable
of driving a 60 kΩ load while allowing an output swing within
the range of AGND + 0.5 V and VDD − 0.5 V.
Because the DAC architecture gives a fixed voltage output range
of 0 V to 30 V or 0 V to 60 V, the user should set VDD to at least
30.5 V or 60.5 V to use the maximum DAC resolution. The data
LDAC
mode, see Figure 3). If the
is kept low, or is low on the
falling edge of the 16th SCLK, the appropriate DAC register and
DAC output are updated automatically (synchronous update
mode, see Figure 3).
Rev. B | Page 14 of 20
Data Sheet
AD5504
The amount of heat generated can be calculated using the
formula
TJ = TA + (PTOTAL × θJA)
TEMPERATURE SENSOR
The AD5504 has an integrated temperature sensor that causes
the part to enter thermal shutdown mode when the temperature
on the die exceeds 110°C. In thermal shutdown mode, the
analog section of the device powers down and the DAC outputs
are disconnected, but the digital section remains operational,
which is equivalent to setting the power-down bit in the control
register. To indicate that the AD5504 has entered temperature
shutdown mode, Bit 0 of the control register is set to 1 and the
where:
TJ is the package junction temperature.
TA is the ambient temperature.
P
TOTAL is the total power being consumed by the AD5504.
θ
JA is the thermal impedance of the AD5504 package (see the
Absolute Maximum Ratings section for this value).
ALARM
pin goes low. The AD5504 remains in temperature
POWER SUPPLY SEQUENCING
ALARM
shutdown mode with Bit 0 set to 1 and the
pin low, even
if the die temperature falls, until Bit 0 in the control register is
cleared to 0.
The power supplies for the AD5504 can be applied in any order
without affecting the device. However, the AGND and DGND
pins should be connected to the relevant ground plane before
the power supplies are applied. None of the digital input pins
POWER DISSIPATION
Drawing current from any of the voltage output pins causes a
temperature rise in the die and package of the AD5504. The
package junction temperature (TJ) should not exceed 130°C for
normal operation. If the die temperature exceeds 110°C, the
AD5504 enters thermal shutdown mode as described in the
Temperature Sensor section.
SYNC R_SEL CLR
(SCLK, SDI,
,
and ) should be allowed to float
during power up. The digital input pins can be connected to
pull-up (to VLOGIC) or pull-down (to DGND) resistors as
required.
Rev. B | Page 15 of 20
AD5504
Data Sheet
SERIAL INTERFACE
SYNC
The AD5504 has a serial interface (
, SCLK, SDI, and
READ MODE
SDO), which is compatible with SPI interface standards, as well
with as most DSPs. The AD5504 allows writing of data, via the
serial interface, to the input and control registers. The DAC
registers are not directly writeable or readable.
The AD5504 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the DAC registers. To read back a register, it
is first necessary to tell the AD5504 that a readback is required.
W
The input shift register is 16 bits wide (see Table 8). The 16-bit
This is achieved by setting the R/ bit to 1. The three address
W
word consists of one read/write (R/ ) control bit, followed by
bits then determine the register from which data is to be read
back. Data from the selected register is then clocked out of the
SDO pin on the next twelve clocks of the same frame.
three address bits and 12 DAC data bits. Data is loaded MSB first.
WRITE MODE
The SDO pin is normally three-stated but becomes driven on
the rising edge of the fifth clock pulse. The pin remains driven
until the data from the register has been clocked out or the
W
To write to a register, the R/ bit should be 0. The three
address bits in the input register (see Table 9) then determine
the register to update. The address bits (A2 to A0) are used for
either DAC register selection or for writing to the control
register. Data is clocked into the selected register during the
remaining 12 clocks of the same frame. Figure 3 shows a timing
diagram of a typical AD5504 write sequence. The write
SYNC
pin is returned high. Figure 4 shows the timing
requirements during a read operation. Note that due to timing
requirements of t14 (110 ns), the maximum speed of the SPI
interface during a read operation should not exceed 9 MHz.
SYNC
WRITING TO THE CONTROL REGISTER
sequence begins by bringing the
line low. Data on the
SDI line is clocked into the 16-bit shift register on the rising
edge of SCLK. On the 16th falling clock edge, the last data bit is
clocked in and the programmed function is executed (that is, a
change in the selected DAC/DACs input register/registers or a
change in the mode of operation). The AD5504 does not
require a continuous SCLK and dynamic power can be saved by
transmitting clock pulses during a serial write only. At this
The control register is written when Bits[DB14:DB12] are 1.
The control register sets the power-up state of the DAC outputs.
A write to the control register must be followed by another
write operation. The second write operation can be a write to a
DAC input register or a NOP write. Figure 18 shows some
typical combinations.
SYNC
stage, the
either case, it must be brought high for a minimum of 20 ns
SYNC
line can be kept low or be brought high. In
before the next write sequence for a falling edge of
to
initiate the next write sequence. Operate all interface pins close
to the supply rails to minimize power consumption in the
digital input buffers.
Table 8. Input Register Bit Map
DB15
DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
Data
DB4
DB3
DB2
DB1
DB0
W
A2 A1 A0
R/
Table 9. Input Register Bit Functions
Bit Description
Indicates a read from or a write to the addressed register.
These bits determine if the input registers or the control register are to be accessed.
W
R/
A2, A1, A0
A2
A1
0
A0
0
Function/Address
No operation
0
0
0
0
1
0
1
1
0
1
0
1
0
DAC A input register
DAC B input register
DAC C input register
DAC D input register
1
0
1
Write data contents to all four DAC input registers
1
1
0
Reserved
1
1
1
Control register
D11:D0
Data bits
Rev. B | Page 16 of 20
Data Sheet
AD5504
Table 10. Control Register Functions
DB15
DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
C1
DB01
W
1
1
1
0
0
0
0
0
C6
C5
C4
C3
C2
C0
R/
1 Read-only bit. This bit should be 0 when writing to the control register.
Table 11. Control Register Function Bit Descriptions
Bit No.
Bit Name
Description
DB0
C0
C0 = 0: the device is not in thermal shutdown mode.
C0 = 1: the device is in thermal shutdown mode.
DB1
DB2
C1
C21
C1 = 0: reserved. This bit should be 0 when writing to the control register.
C2 = 0: DAC Channel A power-down (default).
C2 = 1: DAC Channel A power-up.
DB3
DB4
DB5
DB6
C31
C41
C51
C6
C3 = 0: DAC Channel B power-down (default).
C3 = 1: DAC Channel B power-up.
C4 = 0: DAC Channel C power-down (default).
C4 = 1: DAC Channel C power-up.
C5 = 0: DAC Channel D power-down (default).
C5 = 1: DAC Channel D power-up.
C6 = 0: outputs connected to AGND through a 20 kΩ resistor (default).
C6 = 1: outputs are three-stated.
1 If Bit C2 to Bit C5 are set to 0, the part is placed in power-down mode.
WRITE TO
CONTROL REGISTER
NOP
WRITE TO
CONTROL REGISTER
WRITE TO
DAC REGISTER
WRITE TO
CONTROL REGISTER
WRITE TO
CONTROL REGISTER
NOP
WRITE TO
CONTROL REGISTER
WRITE TO
CONTROL REGISTER
WRITE TO
DAC REGISTER
WRITE N
WRITE N + 1
WRITE N + 2
Figure 18. Control Register Write Sequences
Rev. B | Page 17 of 20
AD5504
Data Sheet
The Analog Devices ADSP-21065L is a floating point DSP with
two serial ports (SPORTs). Figure 20 shows how one SPORT
can be used to control the AD5504. In this example, the transmit
frame synchronization (TFS) pin is connected to the receive
frame synchronization (RFS) pin. The transmit and receive
clocks (TCLK and RCLK) are also connected together. The user
can write to the AD5504 by writing to the transmit register. When a
read operation is performed, the data is clocked out of the AD5504
on the last 12 SCLKs. The DSP receive interrupt can be used to
indicate when the read operation is complete.
INTERFACING EXAMPLES
The SPI interface of the AD5504 is designed to allow it to be
easily connected to industry-standard DSPs and microcon-
trollers. Figure 19 shows how the AD5504 can be connected to
the Analog Devices, Inc., Blackfin® D S P. The Blackfin has an
integrated SPI port that can be connected directly to the SPI
pins of the AD5504. Programmable input/output pins are also
available and can be used to read or set the state of the digital
input or output pins associated with the interface.
AD5504
ADSP-21065L
TFSx
AD5504
SYNC
SPISELx
SYNC
RFSx
SCLK
SCK
TCLKx
RCLKx
MOSI
SDI
SCLK
SDI
SDO
MISO
DTxA
DRxA
PF10
PF9
PF8
PF7
R_SEL
SDO
ADSP-BF531
LDAC
CLR
FLAG
0
R_SEL
FLAG
1
LDAC
CLR
ALARM
FLAG
2
3
ALARM
FLAG
Figure 19. Interfacing to a Blackfin DSP
Figure 20. Interfacing to an ADSP-21065L DSP
Rev. B | Page 18 of 20
Data Sheet
AD5504
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 21. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
AD5504BRUZ
AD5504BRUZ-REEL
EVAL-AD5504EBZ
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
RU-16
RU-16
1 Z = RoHS Compliant Part..
Rev. B | Page 19 of 20
AD5504
NOTES
Data Sheet
©2009-2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07994-0-12/12(B)
Rev. B | Page 20 of 20
相关型号：
EVAL-AD5535BEBZ
32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V
ADI
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