EVAL-AD5560EBUZ [ADI]
1.2 A Programmable Device Power Supply; 1.2可编程器件电源
| 型号： | EVAL-AD5560EBUZ |
| 厂家： | 
ADI |
| 描述： | 1.2 A Programmable Device Power Supply |
| 文件： | 总68页 (文件大小：1748K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.2 A Programmable Device Power Supply
with Integrated 16-Bit Level Setting DACs
Data Sheet
AD5560
On-chip comparators
Gangable for higher current
Guard amplifier
System PMU connections
Current clamps
FEATURES
Programmable device power supply (DPS)
FV, MI, MV, FNMV functions
5 internal current ranges (on-chip RSENSE
5 µA, 25 µA, 250 µA, 2.5 mA, 25 mA
2 external high current ranges (external RSENSE
EXTFORCE1: 1.2 A maximum
)
Die temperature sensor and shutdown feature
On-chip diode thermal array
)
Diagnostic register allows access to internal nodes
Open-drain alarm flags (temperature, current clamp, Kelvin
alarm)
SPI-/MICROWIRE-/DSP-compatible interface
64-lead (10 mm × 10 mm) TQFP with exposed pad (on top)
72-ball (8 mm × 8 mm) flip-chip BGA
EXTFORCE2: 500 mA maximum
Integrated programmable levels
All 16-bit DACs: force DAC, comparator DACs, clamp DACs,
offset DAC, OSD DAC, DGS DAC
Programmable Kelvin clamp and alarm
Offset and gain correction registers on-chip
Ramp mode on force DAC for power supply slewing
Programmable slew rate feature, 1 V/μs to 0.3 V/μs
DUTGND Kelvin sense and alarm
APPLICATIONS
Automatic test equipment (ATE)
Device power supply
25 V FV span with asymmetrical operation within −22 V/+25 V
GENERAL DESCRIPTION
The AD5560 is a high performance, highly integrated device
power supply consisting of programmable force voltages and
measure ranges. This part includes the required DAC levels to
set the programmable inputs for the drive amplifier, as well as
clamping and comparator circuitry. Offset and gain correction
is included on-chip for DAC functions. A number of program-
mable measure current ranges are available: five internal fixed
ranges and two external customer-selectable ranges (EXTFORCE1
and EXTFORCE2) that can supply currents up to 1.2 A and
500 mA, respectively. The voltage range possible at this high
current level is limited by headroom and the maximum power
dissipation. Current ranges in excess of 1.2 A or at high
current and high voltage combinations can be achieved by
paralleling or ganging multiple DPS devices. Open-drain
alarm outputs are provided in the event of overcurrent,
overtemperature, or Kelvin alarm on either the SENSE or
DUTGND line.
The DPS functions are controlled via a simple 3-wire serial
interface compatible with SPI, QSPI™, MICROWIRE™, and DSP
interface standards running at clock speeds of up to 50 MHz.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008-2012 Analog Devices, Inc. All rights reserved.
AD5560
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Adjusting the Autocompensation Mode................................. 39
Dealing with Parallel Load Capacitors .................................... 39
DAC Levels.................................................................................. 39
Force and Comparator DACs ................................................... 39
Clamp DACs ............................................................................... 39
OSD DAC .................................................................................... 40
DUTGND DAC.......................................................................... 40
Offset DAC.................................................................................. 40
Offset and Gain Registers.......................................................... 40
Reference Selection .................................................................... 41
Choosing AVDD/AVSS Power Supply Rails............................... 41
Choosing HCAVSSx and HCAVDDx Supply Rails ................... 41
Power Dissipation....................................................................... 41
Package Composition and Maximum Vertical Force............ 42
Slew Rate Control....................................................................... 42
Serial Interface ................................................................................ 44
SPI Interface................................................................................ 44
SPI Write Mode .......................................................................... 44
SDO Output ................................................................................ 44
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
Timing Characteristics .............................................................. 13
Timing Diagrams........................................................................ 13
Absolute Maximum Ratings.......................................................... 15
ESD Caution................................................................................ 15
Pin Configurations and Function Descriptions ......................... 16
Typical Performance Characteristics ........................................... 20
Terminology .................................................................................... 28
Theory of Operation ...................................................................... 29
Force Amplifier........................................................................... 29
DAC Reference Voltage (VREF)............................................... 29
Open-Sense Detect (OSD) Alarm and Clamp ....................... 29
Device Under Test Ground (DUTGND)................................. 29
GPO.............................................................................................. 30
Comparators................................................................................ 30
Current Clamps .......................................................................... 30
Short-Circuit Protection............................................................ 30
Guard Amplifier ......................................................................... 30
Compensation Capacitors ......................................................... 30
Current Range Selection............................................................ 31
High Current Ranges ................................................................. 31
Ideal Sequence for Gang Mode................................................. 32
Compensation for Gang Mode................................................. 32
System Force/Sense Switches.................................................... 32
Die Temperature Sensor and Thermal Shutdown.................. 33
Measure Output (MEASOUT) ................................................. 33
VMID Voltage ................................................................................ 33
Force Amplifier Stability............................................................ 36
Poles and Zeros in a Typical System ........................................ 37
RESET
Function ......................................................................... 44
Function........................................................................... 44
Function.......................................................................... 44
BUSY
LOAD
Register Update Rates................................................................ 45
Control Registers............................................................................ 46
DPS and DAC Addressing ........................................................ 46
Readback Mode .......................................................................... 57
DAC Readback............................................................................ 57
Power-On Default ...................................................................... 57
Using the HCAVDDx and HCAVSSx Supplies .......................... 59
Power Supply Sequencing ......................................................... 59
Required External Components............................................... 60
Power Supply Decoupling ......................................................... 61
Applications Information .............................................................. 62
Thermal Considerations............................................................ 62
Temperature Contour Map on the Top of the Package......... 63
Outline Dimensions....................................................................... 64
Ordering Guide .......................................................................... 65
Minimizing the Number of External Compensation
Components................................................................................ 37
Extra Poles and Zeros in the AD5560...................................... 37
Compensation Strategies ........................................................... 38
Optimizing Performance for a Known Capacitor Using
Autocompensation Mode.......................................................... 38
Rev. D | Page 2 of 68
Data Sheet
AD5560
REVISION HISTORY
8/12—Rev. C to Rev. D
12/08—Rev. 0 to Rev. A
Added 72-Ball Flip-Chip BGA (Throughout)...............................1
Added Figure 7 and Table 5 (Renumbered Sequentially)..........18
Added Applications Information Section ....................................62
Updated Outline Dimensions........................................................64
Changes to Ordering Guide...........................................................65
Changes to Figure 1 ..........................................................................4
Changes to Table 1 ............................................................................4
Changes to Table 2 ..........................................................................13
Changes to Table 3 ..........................................................................15
Changes to Open-Sense Detect (OSD) Alarm and Clamp .......27
Changes to Figure 53 ......................................................................30
Change to gm Maximum Rating, Table 13..................................34
Changes to Table 19 ........................................................................46
Changes to Bit 7, Bit 8 Functions, Table 21 .................................48
Changes to Power Supply Decoupling Section ...........................59
10/10—Rev. B to Rev. C
Changes to Force Output Voltage Parameter and Load Transient
Response Parameter, Table 1............................................................5
Changes to Figure 52 ......................................................................29
Changes to Table 9 ..........................................................................32
11/08—Revision 0: Initial Version
9/09—Rev. A to Rev. B
Changes to Table 1, Measure Current and Measure Voltage
Parameters..........................................................................................6
Changes to Die Temperature Sensor and Thermal
Shutdown Section............................................................................31
Changes to Table 10 and Table 11 .................................................32
Changes to Table 18, Bit 15 ............................................................45
Changes to Table 23, Bits[15:12] ...................................................50
Changes to Table 25 ........................................................................54
Rev. D | Page 3 of 68
AD5560
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
0 0 1 0 7
1 0 0 k Ω
2 5 k Ω
6 k Ω
Figure 1.
Rev. D | Page 4 of 68
Data Sheet
AD5560
SPECIFICATIONS
HCAVDDx ≤ (AVSS + 33 V), HCAVDDx ≤ AVDD, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, DVCC
2.3 V to 5.5 V, VREF = 5 V, gain (m), offset (c), and DAC offset registers are at default values; AGND = DGND = 0 V; TJ = 25°C to 90°C,
=
maximum specifications, unless otherwise noted. FSV is full-scale voltage, FSVR is full-scale voltage range, FSC is full-scale current, FSCR is
full-scale current range.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
FORCE VOLTAGE
Force Output Voltage1
EXTFORCE1
AVSS + 2.25
HCAVSS1x + 1.75
HCAVSS1x + 1.25
AVDD − 2.25
HCAVSS1x − 1.75
HCAVDD1x − 1.25
V
V
V
Allow 500 mV for external RSENSE voltage drop.
Allow 500 mV for external RSENSE voltage drop.
Allow 500 mV for external RSENSE voltage drop.
Reduced headroom/footroom, clamps must be
enabled.2
EXTFORCE2
AVSS + 2.25
HCAVSS2x + 1.75
HCAVSS2x + 1.25
AVDD − 2.25
HCAVDD2x − 1.75
HCAVDD2x − 1.25
V
V
V
Allow 500 mV for external RSENSE voltage drop
Allow 500 mV for external RSENSE voltage drop
Allow 500 mV for external RSENSE voltage drop.
Reduced headroom/footroom, clamps must be
enabled.2
FORCE
AVSS + 2.75
−2.75
AVDD − 2.75
+2.75
V
V
V
Internal current ranges, includes 500 mV for
internal RSENSE voltage drop
Internal current ranges to AVDD/AVSS, includes
500 mV for internal RSENSE voltage drop.
Headroom/Footroom1
Headroom/Footroom1
−2.25
+2.25
External current ranges, EXTFORCE1/
EXTFORCE2 to HCAVDDx and HCAVSSx supplies;
includes 500 mV for external RSENSE voltage drop.
Force Output Voltage Span
−22
+25
V
May be a skewed range but within headroom
requirements and maximum power dissipation
for current range.
Forced Voltage Linearity Error
Forced Voltage Offset Error
−2
−50
+2
+50
mV
mV
Uncalibrated, use c register to calibrate, meas-
ured at midscale.
Forced Voltage Offset Error Tempco1
Forced Voltage Gain Error
Forced Voltage Gain Error Tempco1
Short-Circuit Current Limit3
EXTFORCE1
27
4
μV/°C
mV
ppm/°C
Standard deviation = 23 μV/°C.
−25
+25
Uncalibrated, use m register to calibrate.
Standard deviation = 3 ppm/°C.
Clamps off.
Positive and negative dc short-circuit current.
Positive and negative dc short-circuit current.
−3.5
−1.25
−75
2.7
0.9
50
+3.5
+1.25
+75
A
A
mA
EXTFORCE2
FORCE
25 mA range, positive and negative dc short-
circuit current.
−20
10
+20
mA
All other ranges, positive and negative dc
short-circuit current.
Active CFx Buffer
−64
−1
−0.4
+64
+1
+0.4
mA
mV
mV
mV
DC Load Regulation1
EXTFORCE1 range, 1 A load current change.
EXTFORCE2 range, 0.5 A load current change.
1.2 A load step into 100 μF DUT capacitance
(10 mΩ ESR), autocompensation mode.
Load Transient Response1
70
140
350
mV
1.2 A load step into 30 µF DUT capacitance
(10 mΩ ESR), autocompensation mode.
NSD1
nV/√Hz
Measured at 1 kHz, at output of FORCE.
MEASURE CURRENT RANGES
Sense resistors are trimmed to within 1%,
nominal 500 mV VRSENSE
5 µA current range.
25 µA current range.
250 µA current range.
2.5 mA current range.
25 mA current range.
.
Internal Sense Resistors1
100
20
2
200
20
kΩ
kΩ
kΩ
Ω
Ω
Rev. D | Page 5 of 68
AD5560
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Measure Current Ranges
Specified current ranges with VREF = 5 V and MI
gain = 20, or with VREF = 2.5 V and MI gain = 5.
5
25
250
2.5
25
µA
µA
µA
mA
mA
mA
Set using internal sense resistor.
Set using internal sense resistor.
Set using internal sense resistor.
Set using internal sense resistor.
Set using internal sense resistor.
EXTFORCE2, set by user with external sense
resistor, limited by headroom requirements
and maximum power dissipation.
500
120
mA
EXTFORCE1, set by user with external sense
resistor, limited by headroom requirements
and maximum power dissipation.
0
MEASURE CURRENT
All offset DAC/supply combinations settings, all
gain settings are measure current = (IDUT
×
R
SENSE × MI gain), unless otherwise noted.
Differential Input Voltage Range1
−0.64
−0.7
+0.64
+0.7
V
V
V
Maximum voltage across RSENSE, MI gain = 20.
Maximum voltage across RSENSE, MI gain = 10.
Measure current block alone (internal node).
At 0 A, MI gain = 20, MEASOUT gain = 1.
Output Voltage Span1
Offset Error
Offset Error Tempco1
Offset Error
Offset Error Tempco1
Offset Error
Offset Error Tempco1
Offset Error
Offset Error Tempco1
Gain Error
Gain Error1
Gain Error Tempco1
MEASOUT Gain = 1
Linearity Error
25
−1
−1
3
−1
+1
% FSC
ppm of FSC/°C Standard deviation = 13 ppm/°C.
% FSC At 0 A, MI gain = 10, MEASOUT gain = 1.
ppm of FSC/°C Standard deviation = 13 ppm/°C.
% FSC At 0 A, MI gain = 20, MEASOUT gain = 0.2.
ppm of FSC/°C Standard deviation = 13 ppm/°C.
% FSC At 0 A, MI gain = 10, MEASOUT gain = 0.2.
ppm of FSC/°C Standard deviation = 15 ppm/°C.
−1.5
−1.5
−3
+1.5
+1.5
+3
8
−2
−1
+2
+1
% FSC
% FSC
ppm/°C
Internal current ranges, all gain settings.
External current ranges, excluding RSENSE
Standard deviation = 5 ppm/°C.
All supply conditions.
.
20
−0.01
+0.01
% FSCR
MI gain = 20 and 10.
MEASOUT Gain = 0.2
Linearity Error
Linearity Error
Nominal supply ( 16.5 V, 0x8000 offset DAC).
MI gain = 20.
MI gain = 10.
−0.06
−0.05
+0.06
+0.05
% FSCR
% FSCR
MEASOUT Gain = 0.2
Linearity Error
Linearity Error
Low supply (−25 V/+8 V, 0xD4EB offset DAC).
MI gain = 20.
MI gain = 10.
−0.125
−0.175
+0.125
+0.175
% FSCR
% FSCR
MEASOUT Gain = 0.2
Linearity Error
High supply (−5 V/+28 V, 0xD1D offset DAC).
MI gain = 20.
−0.0875
−0.1
−0.005
+0.0875
+0.1
+0.005
% FSCR
% FSCR
%FSVR/V
Linearity Error
Common-Mode Error
MI gain = 10.
% of FS change at measure output per volts
change in DUT voltage.
MI gain = 20, MEASOUT gain = 1, measured at
MEASOUT @ 1 kHz, inputs grounded.
MI gain = 10, MEASOUT gain = 1, measured at
MEASOUT @ 1 kHz, inputs grounded.
MI gain = 20, MEASOUT gain = 0.2, measured at
MEASOUT @ 1 kHz, inputs grounded.
MI gain = 10, MEASOUT gain = 0.2, measured at
MEASOUT @ 1 kHz, inputs grounded.
NSD1
900
550
170
110
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
MEASURE VOLTAGE
Measure Voltage Range1
Gain Error
Gain Error Tempco1
MEASOUT Gain = 1
Linearity Error
MEASOUT Gain 1 and MEASOUT Gain 0.2.
All voltage ranges.
AVSS + 2.75
−0.1
AVDD − 2.75
+0.1
V
% FS
ppm/°C
3
Standard deviation = 2 ppm/°C.
−2
+2
mV
Offset Error
−12
+12
mV
Offset Error Tempco1
NSD1
2
100
µV/°C
nV/√Hz
Standard deviation = 12 µV/°C.
@ 1 kHz, at MEASOUT, inputs grounded.
Rev. D | Page 6 of 68
Data Sheet
AD5560
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
MEASOUT Gain = 0.2
Linearity Error
−5.5
−9
+5.5
+24
+13
+20
mV
mV
mV
Referred to MV input, nominal supply ( 16.5 V,
0x8000 offset DAC).
Referred to MV input, low supply (−25 V/+8 V,
0xD4EB offset DAC).
Referred to MV input, high supply (−5 V/+28 V,
0xD1D offset DAC).
−4
Offset Error
Offset Error Tempco1
−30
mV
µV/°C
Referred to MV output.
Standard deviation = 12 µV/°C, referred to MV
output.
10
50
NSD1
nV/√Hz
@ 1 kHz, at MEASOUT, inputs grounded.
COMBINED LEAKAGE
Includes SYS_SENSE, SYS_FORCE, EXTFORCE1,
EXTFORCE2, EXTMEASIH1, EXTMEASIH2,
EXTMEASIL, FORCE, and SENSE; measured with
PD
SW-INH
= 0 (power up and tristate).
= 1,
Leakage Current
−37.5
−30
+37.5
+30
0.4
nA
nA
nA/°C
TJ = 25°C to 70°C.
Leakage Current Tempco1
SENSE INPUT
0.1
Leakage Current
−2.5
+2.5
nA
PD
SW-INH
SW-INH
Measured with
and tristate).
= 1,
= 1,
= 0 (power-up
= 0 (power-up
Leakage Current Tempco1
0.0
1
nA/°C
pF
Pin Capacitance1
10
EXTMEASIH1, EXTMEASIH2, EXTMEASIL
Leakage Current
−2.5
+2.5
nA
PD
PD
Measured with
and tristate).
Leakage Current Tempco1
0.0
1
5
nA/°C
pF
Pin Capacitance1
FORCE OUTPUT, FORCE
Maximum Current Drive1
Leakage Current
−30
−10
+30
+10
mA
nA
SW-INH
Measured with
and tristate).
= 1,
= 0 (power-up
Leakage Current Tempco1
0.0
3
nA/°C
pF
Pin Capacitance1
120
EXTFORCE1 OUTPUTS
Maximum Current Drive1
−1200
−7.5
+1200
+7.5
mA
nA
Set with external sense resistor, limited by
headroom and power dissipation.
Leakage Current
PD
SW-INH
= 1, = 0 (power-up
Measured with
and tristate).
Leakage Current Tempco1
0.0
3
0.06
nA/°C
pF
Pin Capacitance1
275
EXTFORCE2 OUTPUTS
Maximum Current Drive1
−500
−5
+500
+5
mA
nA
Set with external sense resistor, limited by
headroom and power dissipation.
Leakage Current
PD
SW-INH
= 1, = 0 (power-up
Measured with
and tristate).
Leakage Current Tempco1
0.0
2
0.05
nA/°C
pF
Pin Capacitance1
SYS_SENSE
100
Voltage Range
Leakage Current
Leakage Current Tempco1
AVSS
−2.5
AVDD
+2.5
0.025
V
nA
nA/°C
SYS_SENSE high-Z, force amplifier inhibited.
AVDD = 16.5 V, AVSS = −16.5 V.
0.0
05
Path On Resistance
Pin Capacitance1
280
Ω
pF
5
Rev. D | Page 7 of 68
AD5560
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SYS_FORCE
Voltage Range
AVSS
−25
−2.5
AVDD
+25
+2.5
V
Current Carrying Capability1
Leakage Current
Leakage Current Tempco1
mA
nA
nA/°C
SYS_FORCE high-Z, force amplifier inhibited.
AVDD = 16.5 V, AVSS = −16.5 V.
0.00
0.025
5
5
Path On Resistance
Pin Capacitance1
SYS_DUTGND
35
Ω
pF
Voltage Range
AVSS
AVDD
400
V
Path On Resistance
CURRENT CLAMP
Clamp Accuracy
300
Ω
AVDD = 16.5 V, AVSS = −16.5 V.
Programmed
clamp value
Programmed clamp % of FS
value + 10
MI gain = 20, with clamp separation of 2 V, and
1 V separation from AGND/0 A.
Programmed
clamp value
Programmed clamp % of FS
value + 20
MI gain = 10, with clamp separation of 2 V, and
1 V separation from AGND/0 A.
10% of FSCR (MI gain = 20), 20% of FSCR (MI
gain = 10), restriction to prevent both clamps
activating together.
5% of FSCR (MI gain = 20), 10% of FSCR (MI gain
= 10), restriction to avoid impinging on FV
before programmed level.
5% of FSCR (MI gain 20), 10% of FSCR (MI gain =
10), restriction to avoid impinging on FV before
programmed level.
VCLL to VCLH1
VCLL to 0 A1
VCLH to 0 A1
2
1
1
V
V
V
Clamp Activation Response Time1
Clamp Recovery1
20
2
100
5
μs
μs
μs
BUSY
Measured from
clamping.
going low to visible
BUSY
Measured from
recovery.
going low to visible
Alarm Delay 1
50
CLALM
Time for to flag.
FORCE AMPLIFER
Slew Rate1
1
V/µs
V/µs
µF
Fastest slew rate, controlled via serial interface.
Slowest slew rate, controlled via serial interface.
0.312
Maximum Stable Load Capacitance1
Voltage Overshoot/Undershoot1
SETTLING TIME (FORCE AMPLIFER)
160
5
%
Of programmed value (≥1 V).
Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
To within 10 mV of programmed value.
FV (1200 mA EXTFORCE1 Range)1
FV (900 mA EXTFORCE1 Range)1
16
18
25
30
µs
µs
3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc
load.
15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc
load.
FV (500 mA EXTFORCE2 Range)1
34
53
µs
FV (300 mA EXTFORCE2 Range)1
FV (25 mA Range)1, 3
FV (2.5 mA Range)1, 3
FV (250 µA Range)1, 3
FV (25 µA Range)1, 3
25
50
µs
µs
µs
µs
µs
µs
10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 400 kΩ, CDUT = 0.22 µF, full dc load.
1 V step, RDUT = 200 kΩ, CDUT = 0.22 µF, full dc load.
125
300
300
400
20
180
500
500
600
40
FV (5 µA Range)1, 3
Compensation Register 1 = 0x8880 (1.7 μF to
2.9 μF, ESR 74 to 140 mΩ)
FV (180 mA EXTFORCE1 Range)1
FV (100 mA EXTFORCE2 Range)1
16
60
25
80
µs
µs
3 V step, CDUT = 2.2 µF, full dc load.
8 V step, CDUT = 2.2 µF, full dc load.
Compensation Register 1 = 0xB880 (7.9μF to
13 μF, ESR 74 to 140 mΩ)
FV (180 mA EXTFORCE1 Range)1
FV (100 mA EXTFORCE2 Range)1
55
70
µs
µs
3 V step, CDUT = 10 µF, full dc load.
8 V step, CDUT = 10 µF, full dc load.
210
260
Compensation Register 1 = 0xC880 (13 μF to
22 μF, ESR 74 to 140 mΩ)
FV (180 mA EXTFORCE1 Range)1
FV (100 mA EXTFORCE2 Range)1
65
80
µs
µs
3 V step, CDUT = 20 µF, full dc load.
8 V step, CDUT = 20 µF, full dc load.
310
370
Rev. D | Page 8 of 68
Data Sheet
AD5560
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SETTLING TIME (FV, MEASURE CURRENT) Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
To within 10 mV of programmed value.
MI (1200 mA EXTFORCE1 Range)1
MI (900 mA EXTFORCE1 Range)1
MI (500 mA EXTFORCE2 Range)1
30
32
69
40
42
95
µs
µs
µs
3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load.
15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc
load.
MI (300 mA EXTFORCE2 Range)1
MI (25 mA Range)1, 3
70
100
µs
µs
µs
10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc
load.
0.5 V step using MEASOUT high-Z to within
10 mV of final value.
650
6400
MI (2.5 mA Range)1, 3
MI Buffer Alone1
10
15
µs
SETTLING TIME (FV, MEASURE VOLTAGE) Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
To within 10 mV of programmed value.
MV (1200 mA Range)1
MV (900 mA Range)1
MV (500 mA Range)1
16
20
34
µs
µs
µs
3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load.
15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc
load.
MV (300 mA Range)1
MV (25 mA Range)1, 3
MV (2.5 mA Range)1, 3
25
125
300
µs
µs
µs
10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc
load.
180
500
MV (250 µA Range)1, 3
MV Buffer Alone1
300
2
500
5
µs
µs
10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load.
10 V step using MEASOUT high-Z to within
10 mV of final value.
SETTLING TIME (FV) SAFE MODE
FV (1200 mA EXTFORCE1 Range1
FV (180 mA EXTFORCE1 Range)1
To within 100 mV of programmed value.
3.7 V step, RDUT = 3.1 Ω, CDUT = 0.22 µF, full dc load.
3 V step, RDUT = 16 Ω, CDUT = 0. 22 µF to 20 μF, full
dc load.
8 V step, RDUT = 33.3 Ω, CDUT = 0. 22 µF to 20 μF,
full dc load.
25
303
µs
µs
FV (100 mA EXTFORCE2 Range)1
660
760
µs
µs
FV (25 mA Range)1, 3
SWITCHING TRANSIENTS
Range Change Transient1
1000
0.5
20 V step, RDUT = 400 Ω, CDUT = 0.22 µF, full dc load.
% of FV
mV
CDUT = 10 μF, changing from higher to adjacent
lower ranges (except EXTFORCE1 to EXTFORCE2).
CDUT = 10 μF, changing from lower (5 µA) to
20
higher range (EXTFORCE1).
0.5
% of FV
CDUT = 100 μF, changing between all ranges.
DAC SPECIFICATIONS
Force/Comparator/Offset DACs
Resolution
16
16
Bits
V
Voltage Output Span
−22
−1
+25
+1
VREF = 5 V, minimum and maximum values set
by offset DAC.
Guaranteed monotonic.
Differential Nonlinearity1
Offset DAC
Gain Error
Clamp DAC
LSB
mV
−20
+20
CLL < CLH.
Resolution
Voltage Output Span
Bits
V
−22
−1
+25
+1
VREF = 5 V, minimum and maximum values set
by offset DAC.
Differential Nonlinearity1
OSD DAC
LSB
Guaranteed monotonic.
Resolution
16
16
Bits
V
LSB
Voltage Output Span
Differential Nonlinearity1
DGS DAC
0.62
−2
5
+2
VREF = 5 V.
VREF = 5 V.
Resolution
Bits
V
LSB
Voltage Output Span
Differential Nonlinearity1
0
−2
5
+2
Rev. D | Page 9 of 68
AD5560
Data Sheet
Parameter
Min
Typ
3.5
Max
Unit
Test Conditions/Comments
Comparator DAC Dynamic
Output Voltage Settling Time1
Slew Rate1
Digital-to-Analog Glitch Energy1
Glitch Impulse Peak Amplitude1
REFERENCE INPUT
6
µs
1 V change to 1 LSB.
1
10
40
V/µs
nV-s
mV
VREF DC Input Impedance
VREF Input Current
VREF Range1
1
−10
2
MΩ
µA
V
Typically 100 MΩ.
Per input; typically 30 nA.
+10
5
COMPARATOR
Measured directly at comparator; does not
include measure block errors.
Error
−7
+7
mV
Uncalibrated.
VOLTAGE COMPARATOR
Propagation Delay1
Error1
With respect to the measured voltage.
0.25
0.25
µs
mV
−12
+12
Uncalibrated.
CURRENT COMPARATOR
Propagation Delay1
Error1
1
µs
%
−1.5
+1.5
Of programmed current range, uncalibrated.
MEASURE OUTPUT, MEASOUT
Measure Output Voltage Span1
−12.81
+12.81
V
MEASOUT gain = 1, VREF = 5 V, offset DAC =
0x8000.
Measure Output Voltage Span1
Measure Output Voltage Span1
−6.405
0
+6.405
5.125
V
V
MEASOUT gain = 1, VREF = 2.5 V.
MEASOUT gain = 0.2, VREF = 5 V, offset DAC =
0x8000.
Measure Output Voltage Span1
Measure Pin Output Impedance
Output Leakage Current
Output Capacitance1
Short-Circuit Current1
OPEN-SENSE DETECT/CLAMP/ALARM
Measurement Accuracy
Clamp Accuracy
0
2.56
115
+100
V
Ω
nA
pF
mA
MEASOUT gain = 0.2, VREF = 2.5 V.
−100
−10
−200
HW_INH
When is low.
5
+10
+200
900
mV
mV
μs
600
50
Alarm Delay1
DUTGND
Voltage Range1
Pull-Up Current
−1
−1
+1
+70
V
μA
+50
Pull-up for purpose of detecting open circuit on
DUTGND, can be disabled.
When pull-up disabled, DGS DAC = 0x3333 (1 V
with VREF = 5 V). If DUTGND voltage is far away
from one of comparator thresholds, more
leakage may be present.
Leakage Current
+1
μA
Trip Point Accuracy
Alarm Delay1
−30
+10
mV
μs
50
GUARD AMPLIFIER
Voltage Range1
Voltage Span1
AVSS + 2.25
AVDD − 2.25
25
V
V
Output Offset
−10
−20
+10
mV
mA
nF
Ω
Short-Circuit Current1
Load Capacitance1
Output Impedance
Alarm Delay1
+20
100
100
200
μs
If it moves 100 mV away from input level.
Relative to a temperature change.
DIE TEMPERATURE SENSOR
Accuracy1
Output Voltage at 25°C
Output Scale Factor1
Output Voltage Range1
−10
1
+10
2
%
V
mV/°C
V
1.54
4.7
Rev. D | Page 10 of 68
Data Sheet
AD5560
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SPI INTERFACE LOGIC
Logic Inputs
Input High Voltage, VIH
1.7/2.0
V
V
(2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant
input levels.
(2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant
input levels.
Input Low Voltage, VIL
0.7/0.8
Input Current, IINH, IINL
−1
+1
10
µA
pF
1
Input Capacitance, CIN
CMOS Logic Outputs
Output High Voltage, VOH
Output Low Voltage, VOL
Tristate Leakage Current
Output Capacitance1
Open-Drain Logic Outputs
Output Low Voltage, VOL
Output Capacitance1
POWER SUPPLIES
SDO, CPOL, CPOH, GPO, CPO.
DVCC − 0.4
V
V
μA
pF
0.4
+1
10
IOL = 500 µA.
SDO, CPOL, CPOH, CPO.
SDO, CPOL, CPOH, CPO.
−1
10
10
BUSY TMPALM CLALM KELALM
.
,
,
,
0.4
10
V
pF
IOL = 500 µA, CL = 50 pF, RPULLUP = 1 kΩ.
HCAVDD1x
4
28
V
|HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS,
HCAVDDx ≤ AVDD
.
HCAVSS1x
HCAVDD2x
−25
4
−5
28
V
V
|HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS,
HCAVDDx ≤ AVDD
.
HCAVSS2x
AVDD
AVSS
−25
8
−25
2.3
−5
28
−5
5.5
30
V
V
V
V
mA
mA
mA
mA
|AVDD – AVSS| < 33 V.
DVCC
4
AIDD
AISS
All ranges.
All ranges.
4
−30
−27
DICC
AIDD
3
27
4
HW_INH
HW_INH
Channel inhibited/tristate,
or
or
SW-INH
low.
Channel inhibited/tristate,
SW-INH
4
AISS
mA
low.
HCAVDDx and HCAVSSx supply currents shown
are excluding load currents; however, for
power budget calculations, the supply currents
here are consumed by the load.
HCAIDD
HCAIDD
HCAISS1
HCAISS1
HCAIDD
HCAIDD
HCAISS2
1
1
20
0.5
mA
mA
mA
mA
mA
mA
mA
mA
When enabled, excluding load conditions.
When disabled.
When enabled, excluding load condition.
When disabled.
When enabled, excluding load conditions.
When disabled.
When enabled, excluding load conditions.
When disabled.
−20
−0.5
2
2
15
0.25
−15
−0.25
HCAISS2
POWER-DOWN CURRENTS
Supply currents on power-up or during a
power-down condition.
HCAIDD
HCAISS
HCAIDD
HCAISS
AIDD
AISS
DICC
250
250
5
μA
μA
μA
μA
mA
mA
mA
−250
−250
−5
3
Maximum Power Dissipation
EXTFORCE1
EXTFORCE2
Power-Up Overshoot1
10
5
W
W
%
5
Of programmed value.
Rev. D | Page 11 of 68
AD5560
Data Sheet
Parameter
Min
Typ
−65
Max
Unit
Test Conditions/Comments
Power Supply Sensitivity1
ΔForced Voltage/ΔAVDD
ΔForced Voltage/ΔAVSS
ΔForced Voltage/ΔHCAVDD
DC to 1 kHz.
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
−30 dB at 100 kHz.
−25 dB at 100 kHz.
−60 dB at 100 kHz.
−62 dB at 100 kHz.
−25 dB at 100 kHz.
−20 dB at 100 kHz.
−60 dB at 100 kHz.
−60 dB at 100 kHz.
−30 dB at 100 kHz.
−25 dB at 100 kHz.
−60 dB at 100 kHz.
−65 dB at 100 kHz.
−46 dB at 100 kHz.
−36 dB at 100 kHz.
−46 dB at 100 kHz.
−65
−90
−90
−50
−43
−90
−90
−65
−65
−90
−90
−80
−80
−80
x
ΔForced Voltage/ΔHCAVSSx
ΔMeasured Current/ΔAVDD
ΔMeasured Current/ΔAVSS
ΔMeasured Current/ΔHCAVDD
ΔMeasured Current/ΔHCAVSSx
ΔMeasured Voltage/ΔAVDD
ΔMeasured Voltage/ΔAVSS
ΔMeasured Voltage/ΔHCAVDD
ΔMeasured Voltage/ΔHCAVSSx
ΔForced Voltage/ΔDVCC
ΔMeasured Current/ΔDVCC
ΔMeasured Voltage/ΔDVCC
x
x
1 Guaranteed by design and characterization, not subject to production test.
2 Programmable clamps must be enabled if taking advantage of reduced headroom/footroom.
3 Clamps disabled.
4 Not including internal pull-up current between AVDD/AVSS and HCAVDDx/HCAVSSx pins.
Rev. D | Page 12 of 68
Data Sheet
AD5560
TIMING CHARACTERISTICS
HCAVDDx ≤ AVSS + 33 V, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, VREF = 5 V (TJ = 25°C to 90°C,
maximum specifications, unless otherwise noted).
Table 2. SPI Interface
DVCC = 2.3 V
to 2.7 V
DVCC = 2.7 V
to 3.3 V
DVCC = 4.5 V
to 5.5 V
Parameter1, 2, 3
Unit
Description
tUPDATE
t1
t2
t3
t4
600
25
10
10
10
15
5
600
20
8
600
20
8
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs max
ns max
ns min
µs max
ns min
ns max
ns max
Channel update cycle time
SCLK cycle time; 60/40 duty cycle
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
8
8
10
15
5
10
15
5
t5
Minimum SYNC high time
t6
24th SCLK falling edge to SYNC rising edge
Data setup time
t7
5
5
5
t8
t9
4.5
40
1.5
280
25
400
250
45
30
4.5
35
1.5
280
20
400
250
35
30
4.5
30
1.5
280
10
400
250
25
30
Data hold time
4
SYNC rising edge to BUSY falling edge
BUSY pulse width low for DAC x1 write
BUSY pulse width low for other register write
RESET pulse width low
t10
t11
t12
t13
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid
SYNC rising edge to SDO high-Z
5, 6
t14
t15
LOAD TIMING
t16
t17
t18
t19
20
20
20
ns min
ns min
ns min
ns min
ns min
LOAD pulse width low
150
0
150
0
150
0
BUSY rising edge to force output response time
BUSY rising edge to LOAD falling edge
LOAD rising edge to FORCE output response time
LOAD rising edge to current range response
150
150
150
150
150
150
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 4 and Figure 5.
4 This is measured with the load circuit shown in Figure 2.
5 This is measured with the load circuit shown in Figure 3.
6 Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications.
TIMING DIAGRAMS
DV
CC
200µA
I
OL
R
LOAD
2.2kΩ
TO OUTPUT
PIN
V
(MIN) – V (MAX)
OL
OH
2
C
LOAD
50pF
TO OUTPUT
PIN
V
OL
C
LOAD
50pF
200µA
I
OL
Figure 2. Load Circuit for Open Drain
Figure 3. Load Circuit for CMOS
Rev. D | Page 13 of 68
AD5560
Data Sheet
t1
SCLK
1
24
2
t2
t3
t4
t6
SYNC
SDI
t5
t
7
t
8
DB0
DB2
3
t9
t10
BUSY
1,3
t16
LOAD
FORCE
t17
t18
EXTFORCE1
1
EXTFORCE2
t16
2,3
LOAD
FORCE
EXTFORCE1
t19
2,3
EXTFORCE2
t11
RESET
BUSY
t12
1
LOAD ACTIVE DURING BUSY.
2
LOAD ACTIVE AFTER BUSY.
3
LOAD FUNCTION IS AVAILABLE VIA CLEN OR HW_INH AS DETERMINED BY DPS REGISTER 2.
Figure 4. SPI Write Timing
SCLK
48
24
t
14
t
13
SYNC
SDI
t
15
DB23
D0B
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
SDO
DB23
DB0
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. SPI Read Timing
Rev. D | Page 14 of 68
Data Sheet
AD5560
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVDD to AVSS
34 V
AVDD to AGND
AVSS to AGND
HCAVDDx to HCAVSSx
HCAVDDx to AGND
HCAVSSx to AGND
HCAVDDx to AVSS
HCAVDDx to AVDD
HCAVSSx to AVSS
DVCC to DGND
−0.3 V to +34 V
−34 V to +0.3 V
34 V
−0.3 V to +34 V
−34 V to +0.3 V
−0.3 V to AVSS + 34 V
−0.3 V to AVDD + 0.3 V
+0.3 V to AVSS − 0.3 V
−0.3 V to +7 V
ESD CAUTION
AGND to DGND
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to DVCC + 0.3 V
AVSS − 0.3 V to AVDD + 0.3 V
AVDD − 28 V
−65°C to +125°C
25°C to 90°C
J-STD 20 (JEDEC)
150°C max
REFGND to AGND
Digital Inputs to DGND
Analog Inputs to AGND
EXTFORCE1 and EXTFORCE2 to AGND1
Storage Temperature
Operating Junction Temperature
Reflow Profile
Junction Temperature
Power Dissipation
10 W max (EXTFORCE1 stage)
5 W max (EXTFORCE2 stage)
ESD
HBM
FICDM
1500 V
500 V
1 When an EXTFORCE1 or EXTFORCE2 stage is enabled and the supply differ-
ential |AVDD − AVSS| > 28 V, take care to ensure that these pins are not directly
shorted to AVSS voltage at any time because this can cause damage to the device.
Rev. D | Page 15 of 68
AD5560
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
EXTMEASIH2
EXTMEASIH1
CLALM
PIN 1
KELALM
2
3
AV
DD
TMPALM
4
CPOH/CPO
AV
SS
5
AGND
CPOL
BUSY
SDO
6
GUARD/SYS_DUTGND
EXTMEASIL
SENSE
7
AD5560
TOP VIEW
(Not to Scale)
8
DV
CC
9
DGND
SCLK
SDI
DUTGND
EXPOSED PAD ON TOP
10
11
C
F0
C
C
C
C
F1
F2
F3
F4
SYNC 12
13
14
15
16
RCLK
RESET
CLEN/LOAD
NC
AV
HW_INH/LOAD
DD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD ON TOP OF PACKAGE. EXPOSED PAD IS INTERNALLY CONNECTED TO
MOST NEGATIVE POINT, AV
.
SS
Figure 6. TQFP_EP Pin Configuration
Table 4. TQFP_EP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLALM
Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
2
3
Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either
latched or unlatched.
Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
KELALM
TMPALM
4
5
6
7
CPOH/CPO
CPOL
Comparator High Output (CPOH) or Window Comparator Output (CPO).
Comparator Low Output.
Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
BUSY
SDO
Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic
purposes.
8
9
10
11
12
13
DVCC
DGND
SCLK
SDI
Digital Supply Voltage.
Digital Ground Reference Point.
Clock Input, Active Falling Edge.
Serial Data Input.
Frame Sync, Active Low.
SYNC
RCLK
Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to
this input to drive the ramp circuitry. Tie RCLK low if it is unused.
14
15
Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
RESET
Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured
as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as
LOAD input (see the system control register, Address 0x1).
CLEN/LOAD
16
17
LOAD
function to allow
HW_INH/LOAD
REFGND
Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a
synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system
control register, Address 0x1).
Accurate Ground Reference for Applied Voltage Reference.
Rev. D | Page 16 of 68
Data Sheet
AD5560
Pin No.
18
19, 44
20, 30, 45
Mnemonic
Description
VREF
AGND
AVSS
Reference Input for DAC Channels, Input Range 2 V to 5 V.
Analog Ground.
Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
21, 33, 46
AVDD
Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
22
23
24
25
26
27
28
29
31
32
34
35
36
37
38
39
40
41
42
43
MEASOUT
CC3
CC0
CC1
CC2
SLAVE_IN
MASTER_OUT
SYS_SENSE
SYS_FORCE
FORCE
NC
CF4
CF3
CF2
CF1
CF0
Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND.
Compensation Capacitor Input 3.
Compensation Capacitor Input 0.
Compensation Capacitor Input 1.
Compensation Capacitor Input 2.
Slave Input When Ganging Multiple DPS Devices.
Master Output When Ganging Multiple DPS Devices.
External Sense Signal Output.
External Force Signal Input.
Output Force Pin for Internal Current Ranges.
No Connect.
Feedforward Capacitor 4.
Feedforward Capacitor 3.
Feedforward Capacitor 2.
Feedforward Capacitor 1.
Feedforward Capacitor 0.
Device Under Test Ground.
Input Sense Line.
Low Side Measure Current Line for External High Current Ranges.
DUTGND
SENSE
EXTMEASIL
GUARD/SYS_DUTGND
Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19
for addressing details.
47
48
49, 55, 61
EXTMEASIH1
EXTMEASIH2
HCAVDD1A,
HCAVDD1B,
HCAVDD1C
Input High Measure Line for External High Current Range 1.
Input High Measure Line for External High Current Range 2.
High Current Positive Analog Supply Voltage, for EXTFORCE1 Range.
50, 56, 62
51, 57, 63
EXTFORCE1A,
EXTFORCE1B,
EXTFORCE1C
HCAVSS1A,
HCAVSS1B,
HCAVSS1C
Output Force. This pin is used for high Current Range 1, up to a maximum of 1.2 A.
High Current Negative Analog Supply Voltage, for EXTFORCE1 Range.
52, 58
53, 59
HCAVSS2A, HCAVSS2B
EXTFORCE2A,
EXTFORCE2B
High Current Negative Analog Supply Voltage, for EXTFORCE2 Range.
Output Force. This pin is used for high Current Range 2, up to a maximum of 500 mA.
54, 60
HCAVDD2A,
HCAVDD2B
High Current Positive Analog Supply Voltage, for EXTFORCE2 Range.
64
65
GPO
EP
Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT.
The exposed pad is internally connected to AVSS.
Rev. D | Page 17 of 68
AD5560
Data Sheet
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
EXTFORCE1A EXTFORCE1A EXTFORCE2A EXTFORCE1B EXTFORCE1B EXTFORCE2B EXTFORCE1C EXTFORCE1C
GPO
CLALM
KELALM
TMPALM
BUSY
HCAV 1A
DD
HCAV 1A
SS
HCAV 2A
DD
HCAV 1B
DD
HCAV 1B
SS
HCAV 2B
DD
HCAV 1C
DD
HCAV 1C
SS
HCAV 1A
DD
HCAV 1A
SS
HCAV 2A
SS
HCAV 1B
DD
HCAV 1B
SS
HCAV 2B
SS
HCAV 1C
DD
HCAV 1C
SS
AV
DD
EXTMEASIH1
AGND
EXTMEASIH2
CPOL
CPOH/CPO
GUARD/
SYS_DUTGND
3 × 3 ARRAY IS VOID OF BALLS
AV
SS
DV
CC
SDO
DUTGND
EXTMEASIL
SENSE
SYS_FORCE
SLAVE_IN
FORCE
SDI
SCLK
DGND
C
C
SYS_SENSE
C
C
AV
RESET
RCLK
SYNC
G
H
J
F0
F2
C0
SS
CLEN/
LOAD
C
C
MASTER_OUT
MEASOUT
AV
DD
VREF
F1
F3
C1
HW_INH/
LOAD
C
AV
DD
C
CC3
AV
SS
AGND
REFGND
F4
C2
Figure 7. Flip-Chip BGA Pin Configuration, Bottom Side (BGA Balls Are Visible)
Table 5. Flip-Chip BGA Pin Function Descriptions
Pin No.
Mnemonic
Description
A1
A2, A3
A4
A5, A6
A7
A8, A9
B1
GPO
Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT.
Output Force. These pins are used for high Current Range 1, up to a maximum of 1.2 A.
Output Force. This pin is used for high Current Range 2, up to a maximum of 500 mA.
Output Force. These pins are used for high Current Range 1, up to a maximum of 1.2 A.
Output Force. This pin is used for high Current Range 2, up to a maximum of 500 mA.
Output Force. These pins are used for high Current Range 1, up to a maximum of 1.2 A.
EXTFORCE1C
EXTFORCE2B
EXTFORCE1B
EXTFORCE2A
EXTFORCE1A
CLALM
Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
B2, C2
B3, C3
B4
B5, C5
B6, C6
B7
B8, C8
B9, C9
C1
HCAVSS1C
HCAVDD1C
HCAVDD2B
HCAVSS1B
HCAVDD1B
HCAVDD2A
HCAVSS1A
HCAVDD1A
KELALM
High Current Negative Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE2 Range.
High Current Negative Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE2 Range.
High Current Negative Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE1 Range.
Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either
latched or unlatched.
C4
C7
HCAVSS2B
HCAVSS2A
High Current Negative Analog Supply Voltage for EXTFORCE2 Range.
High Current Negative Analog Supply Voltage for EXTFORCE2 Range.
Rev. D | Page 18 of 68
Data Sheet
AD5560
Pin No.
Mnemonic
Description
D1
Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched
or unlatched.
TMPALM
D2
D3
D7
D8
CPOH/CPO
CPOL
EXTMEASIH2
EXTMEASIH1
Comparator High Output (CPOH) or Window Comparator Output (CPO).
Comparator Low Output.
Input High Measure Line for External High Current Range 2.
Input High Measure Line for External High Current Range 1.
D9,H3, J8 AVDD
Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
E1
E2
Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
BUSY
SDO
Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic
purposes.
E3
E7
DVCC
Digital Supply Voltage.
GUARD/SYS_DUTGND
Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19
for addressing details.
E8
AGND
Analog Ground.
E9, G4, J4 AVSS
Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
F1
F2
F3
F7
F8
F9
G1
G2
DGND
SCLK
SDI
SENSE
EXTMEASIL
DUTGND
SYNC
Digital Ground Reference Point.
Clock Input, Active Falling Edge.
Serial Data Input.
Input Sense Line.
Low Side Measure Current Line for External High Current Ranges.
Device Under Test Ground.
Frame Sync, Active Low.
RCLK
Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied
to this input to drive the ramp circuitry. Tie RCLK low if it is unused.
G3
G5
G6
G7
G8
G9
H1
Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
RESET
CC0
Compensation Capacitor Input 0.
External Sense Signal Output.
External Force Signal Input.
Feedforward Capacitor 2.
SYS_SENSE
SYS_FORCE
CF2
CF0
Feedforward Capacitor 0.
Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured
as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as
LOAD input (see the system control register, Address 0x1).
CLEN/LOAD
H2
H4
H5
H6
H7
H8
H9
J1
VREF
MEASOUT
CC1
MASTER_OUT
SLAVE_IN
CF3
Reference Input for DAC Channels, Input Range is 2 V to 5 V.
Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND.
Compensation Capacitor Input 1.
Master Output When Ganging Multiple DPS Devices.
Slave Input When Ganging Multiple DPS Devices.
Feedforward Capacitor 3.
CF1
Feedforward Capacitor 1.
HW_INH/LOAD
Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a
LOAD
function to allow
synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system
control register, Address 0x1).
J2
J3
J5
J6
J7
J9
REFGND
AGND
CC3
CC2
FORCE
CF4
Accurate Ground Reference for Applied Voltage Reference.
Analog Ground.
Compensation Capacitor Input 3.
Compensation Capacitor Input 2.
Output Force Pin for Internal Current Ranges.
Feedforward Capacitor 4.
Rev. D | Page 19 of 68
AD5560
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
0.2
0
12
10
8
T
= 25°C
J
AV = 8V
AV = –25V
SS
DD
V
= 5V
REF
OFFSET DAC = 0xD4EB
6
MEASOUT GAIN = 0.2
4
2
0
MEASOUT GAIN = 1
–2
–4
–0.2
0
10,000
20,000
30,000
CODE
40,000
50,000
60,000
0
10,000
20,000
30,000
CODE
40,000
50,000
60,000
Figure 8. Force Voltage Linearity vs. Code, VREF = 5 V, No Load
Figure 11. Measure Voltage Linearity vs. Code (MEASOUT Gain 1,
MEASOUT Gain = 0.2, Negative Skew Supply)
2.0
0.0100
T
= 25°C
HIGH: AV = 28V, AV = –5V, OFFSET DAC = 0xD1D
DD SS
J
AV = 16.25V
AV = –16.25V
SS
LOW: AV = 5V, AV = –25V OFFSET DAC = 0xD4EB
NOM: AV /AV = ±16.25V, OFFSET DAC = 0x8000
DD SS
DD
DD SS
1.5
1.0
0.0075
0.0050
0.0025
V
= 5V
V
= 5V
REF
REF
0.5
MEASOUT GAIN = 0.2
0
0
–0.0025
–0.0050
–0.0075
–0.0100
LOW SUPPLIES
–0.5
–1.0
–1.5
–2.0
NOMINAL SUPPLIES
MEASOUT GAIN = 1
HIGH SUPPLIES
0
10,000
20,000
30,000
CODE
40,000
50,000
60,000
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE
Figure 9. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1,
MEASOUT Gain = 0.2, Nominal Supplies)
Figure 12. Measure Current Linearity vs. Code (MEASOUT Gain = 1,
MI Gain = 20), TJ = 25°C
0.010
5
T
= 25°C
HIGH: AV = 28V, AV = –5V, OFFSET DAC = 0xD1D
J
DD
SS
AV = 28V
AV = –5V
SS
LOW: AV = 5V, AV = –25V OFFSET DAC = 0xD4EB
DD
DD SS
4
3
NOM: AV /AV = ±16.25V, OFFSET DAC = 0x8000
SS
DD
= 5V
V
= 5V
V
REF
REF
OFFSET DAC = 0xD1D
0.005
MEASOUT GAIN = 0.2
LOW SUPPLIES
2
0
1
0
–0.005
–0.010
MEASOUT GAIN = 1
–1
–2
NOMINAL SUPPLIES
HIGH SUPPLIES
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE
0
10,000
20,000
30,000
CODE
40,000
50,000
60,000
Figure 10. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1,
MEASOUT Gain = 0.2, Positive Skew Supply)
Figure 13. Measure Current Linearity vs. Code (MEASOUT Gain = 1,
MI Gain = 10)
Rev. D | Page 20 of 68
Data Sheet
AD5560
0.0500
0.0500
0.0375
0.0250
0.0125
0
HIGH: AVDD = 28V, AV
= –5V, OFFSET DAC = 0xD1D
= –25V OFFSET DAC = 0xD4EB
SS
AV
= +16.25V
DD
AV = –16.25V
LOW: AVDD = 5V, AV
NOM: AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000
SS
SS
0.0375
0.0250
0.0125
0
V
= 5V
VREF = 5V
±25mA RANGE
REF
OFFSET DAC = 0x8000
MI GAIN = 20
MEASOUT GAIN = 0.2
25µA RANGE
NOMINAL SUPPLIES
LOW SUPPLIES
–0.0125
–0.0250
–0.0375
–0.0500
–0.0125
–0.0250
–0.0375
–0.0500
2.5mA
25mA RANGE
HIGH SUPPLIES
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE
0
10,000
20,000
30,000
CODE
40,000
50,000
60,000
Figure 14. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2,
MI Gain = 20)
Figure 17. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 0.2,
MI Gain = 20)
1.5
0.100
HIGH: AV = 28V, AV
DD
= –5V, OFFSET DAC = 0xD1D
SS
= –25V OFFSET DAC = 0xD4EB
SS
T
= 25°C
J
LOW : AV = 5V, AV
DD
NOM : AV /AV = ±16.25V, OFFSET DAC = 0x8000
1.0
0.5
DD SS
0.075
0.050
0.025
V
= 5V ±25mA RANGE
REF
HIGH SUPPLIES
0
EXTFORCE1A
EXTFORCE2B
FORCE
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
COMBINED LEAKAGE
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
–0.025
–0.050
–0.075
–0.100
NOMINAL SUPPLIES
LOW SUPPLIES
–10
5
0
5
10
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE
STRESS VOLTAGE (V)
Figure 18. Leakage Current vs. Stress Voltage (Force and Combined Leakage)
Figure 15. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2,
MI Gain = 10)
7
0.0100
AV
= +16.25V
DD
AV = –16.25V
V
= 9V
STRESS
SS
0.0075
0.0050
0.0025
0
V
= 5V
6
5
4
3
2
1
0
REF
OFFSET DAC = 0x8000
MI GAIN = 20
MEASOUT GAIN = 1
25µA RANGE
EXTFORCE1A
EXTFORCE2B
FORCE
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
COMBINED LEAKAGE
–0.0025
–0.0050
–0.0075
–0.0100
2.5mA
25mA RANGE
25
35
45
55
65
75
85
95
0
10,000
20,000
30,000
CODE
40,000
50,000
60,000
TEMPERATURE (°C)
Figure 19. Leakage Current vs. Temperature (Force and Combined Leakage),
STRESS = 9 V
Figure 16. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 1,
MI Gain = 20)
V
Rev. D | Page 21 of 68
AD5560
Data Sheet
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
0.15
0.10
0.05
0
EXTFORCE1A
EXTFORCE2B
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
T
= 25°C
J
HIGH
NOMINAL
LOW
–0.05
–0.10
–0.15
25
35
45
55
65
75
85
–0.20
–10
5
0
5
10
TEMPERATURE (°C)
STRESS VOLTAGE (V)
Figure 23. MI Positive Gain Error vs. Temperature, MI Gain = 20,
MEASOUT Gain = 1
Figure 20. Leakage Current vs. Stress Voltage
0.8
1.8
0
AV
= ±16.25V
DD
V
= 9V
STRESS
AV = –16.25V
SS
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 5V
REF
OFFSET DAC = 0x8000
–0.5
–1.0
–1.5
–2.0
–2.5
EXTFORCE1A
EXTFORCE2B
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
25
35
45
55
65
75
85
95
25
35
45
55
65
75
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Leakage Current vs. Temperature, VSTRESS = 9 V
Figure 24. FV Gain Error vs. Temperature
0.10
23.0
22.5
22.0
21.5
21.0
20.5
20.0
HIGH 0.2
LOW
0.05
0
NOMINAL
NOMINAL 0.2
HIGH
–0.05
–0.10
–0.15
–0.20
LOW 0.2
HIGH: AV = 28V, AV
DD
= –5V, OFFSET DAC = 0xD1D
= –25V OFFSET DAC = 0xD4EB
NOM : AV /AV = ±16.25V, OFFSET DAC = 0x8000
SS
SS
LOW : AV = 5V, AV
DD
DD SS
= 5V
V
REF
LOW0.2/HIGH0.2/NOM0.2 MEAN FOR MEASOUT GAIN = 0.2
25
35
45 55 65 75 85
TEMPERATURE (°C)
25
35
45
55
65
75
85
TEMPERATURE (°C)
Figure 22. MI Offset Error vs. Temperature, MI Gain = 20,
MEASOUT Gain = 1 and 0.2
Figure 25. FV Offset Error vs. Temperature
Rev. D | Page 22 of 68
Data Sheet
AD5560
0
–0.001
–0.002
–0.003
–0.004
–0.005
–0.006
–0.007
5
4
HIGH
3
2
1
LOW
NOMINAL
HIGH
0
NOMINAL
–1
–2
–3
–4
–5
LOW
55
25
35
45
55
65
75
85
25
35
45
65
75
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 26. MV Gain Error vs. Temperature, MEASOUT Gain = 1
Figure 29. MV Offset Error vs. Temperature, MEASOUT Gain = 0.2
1.0
CH1 p-p
27mV
0.9
HIGH
CH1 AREA
10.92µVs
0.8
NOMINAL
LOW
0.7
0.6
FORCE
1
0.5
0.4
0.3
0.2
0.1
0
SYNC
3
25
35
45
55
65
75
85
B
B
CH1 50mV
CH3 5V
M200µs
10.4%
A CH3
1.5V
W
W
T
TEMPERATURE (°C)
Figure 27. MV Offset Error vs. Temperature, MEASOUT Gain = 1
Figure 30. Range Change 2.5 mA to 25 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load
0.030
CH1 p-p
16mV
CH1 AREA
–5.336µVs
NOMINAL
LOW
0.025
0.020
HIGH
FORCE
0.015
0.010
0.005
0
1
SYNC
3
25
35
45
55
65
75
85
B
CH1 50mV
CH3 5V
M200µs
10.4%
A CH3
1.5V
W
B
T
TEMPERATURE (°C)
W
Figure 28. MV Gain Error vs. Temperature, MEASOUT Gain = 0.2
Figure 31. Range Change 25 mA to 2.5 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load
Rev. D | Page 23 of 68
AD5560
Data Sheet
CH1 p-p
159mV
CH1 p-p
84mV
CH1 AREA
14.31µVs
TRIGGER
FORCE
2
1
FORCE
1
SYNC
3
B
B
B
W
CH1 50mV
CH3 5V
M200µs
10.4%
A CH3
1.5V
CH2 5V
CH1 100mV
M40µs
120.4µs
A CH2
1.6V
W
W
T
T
Figure 35. Autocompensation Mode 90% to 10% ILOAD Change,
EXTFORCE2 Range, 10 µF Load
Figure 32. Range Change 25 mA to EXTFORCE2, Safe Mode,
25 mA ILOAD, 10 μF Load
CH1 p-p
86mV
CH1 p-p
36mV
TRIGGER
CH1 AREA
–9.738µVs
2
1
FORCE
FORCE
1
SYNC
3
B
CH2 5V
CH1 100mV
M40µs
120.4µs
A CH2
4V
CH1 50mV
CH3 5V
M200µs
10.4%
A CH3
1.5V
W
T
T
Figure 36. Autocompensation Mode 10% to 90% ILOAD Change,
EXTFORCE2 Range, 10 µF Load
Figure 33. Range Change EXTFORCE2 to 25 mA, Safe Mode,
25 mA ILOAD, 10 µF Load
350
10µF LOAD
30µF LOAD
100µF LOAD
CH1 p-p
172mV
300
TRIGGER
250
200
150
100
50
2
FORCE
1
0
EXT RANGE 1
EXT RANGE 2
25mA RANGE
B
CH2 5V
CH1 100mV
M40µs
120.4µs
A CH2
1.6V
W
SAFE
AUTO
COMP
SAFE
AUTO
COMP
SAFE
AUTO
COMP
T
MODE
MODE
MODE
Figure 34. Kick/Droop Response vs. IRANGE, Compensation, and CLOAD,
10% to 90% to 10% ILOAD Change
,
Figure 37. Safe Mode 80% to 10%, EXTFORCE2 Range, 10 µF Load
Rev. D | Page 24 of 68
Data Sheet
AD5560
CH1 p-p
174mV
TRIGGER
FORCE
MEASOUT – MI
2
1
T
AV
= 25°C
A
= +16.25V
DD
AV = –16.25V
SS
FORCE
1
V
= 5V
REF
OFFSET DAC = 0x8000
/I = 25mA
I
RANGE LOAD
0 TO 10V STEP
R
C
= 40kΩ
= 220nF
LOAD
LOAD
2
4
AUTOCOMP MODE 0x4480
MEASOUT GAIN 1, MI GAIN 20
BUSY
3
B
B
CH2 5V
CH1 100mV
M40µs
120.4µs
A CH2
4.6V
CH1 5V
CH3 5V
CH2 2V
M20µs
1.4%
A CH3
2.9V
W
W
T
T
CH4 10V
Figure 38. Safe Mode 10% to 90%, EXTFORCE2 Range, 10 µF Load
Figure 41. Transient Response FVMI Mode, 25 mA Range,
Autocompensation Mode
2.0
AV
= +16.5V
DD
FORCE
AV = –16.5V
SS
1.9
1.8
1.7
1.6
1.5
1.4
MEASOUT – MI
T
AV
= 25°C
A
= +16.25V
DD
AV = –16.25V
1
SS
V
= 5V
REF
OFFSET DAC = 0x8000
/I = 250µA
I
RANGE LOAD
0 TO 10V STEP
R
C
= 40kΩ
= 220nF
SAFE MODE
MEASOUT GAIN 1, MI GAIN 20
LOAD
LOAD
2
4
BUSY
3
25
35
45
55
65
75
85
B
CH1 5V
CH3 5V
CH2 2V
M100µs
7.2%
A CH3
2.9V
W
T
CH4 10V
FORCED TEMPERATURE (°C)
Figure 42. Transient Response FVMI Mode, 25mA Range, Safe Mode
Figure 39. MEASOUT TSENSE Temperature Sensor vs. Temperature
(Multiple Devices)
FORCE
MEASOUT – MI
MEASOUT – MI
FORCE
T
= 25°C
= +16.25V
A
AV
DD
AV = –16.25V
SS
T = 25°C
A
V
= 5V
REF
OFFSET DAC = 0x8000
/I = 250µA
AV
= +16.25V
1
1
2
DD
AV = –16.25V
SS
I
RANGE LOAD
0 TO 10V STEP
V
= 5V
REF
OFFSET DAC = 0x8000
I /I = EXTFORCE1/1.2A
R
C
= 40kΩ
= 220nF
LOAD
LOAD
RANGE LOAD
0 TO 3.7V STEP
= 10µF CERAMIC
2
4
AUTOCOMP MODE 0x4880
MEASOUT GAIN 1, MI GAIN 20
C
LOAD
AUTOCOMP MODE 0x9680
MEASOUT GAIN 1, MI GAIN 20
BUSY
BUSY
4
3
3
B
B
CH1 5V
CH3 5V
CH2 1V
M4µs
3%
A CH3
2.9V
CH1 5V
CH3 5V
CH2 2V
M400µs
10.2%
A CH3
2.9V
W
W
T
T
CH4 10V
CH4 10V
Figure 40. Transient Response FVMI Mode, 250 µA Range,
Autocompensation Mode
Figure 43. Transient Response FVMI Mode, EXTFORCE1 Range,
Autocompensation Mode
Rev. D | Page 25 of 68
AD5560
Data Sheet
1000
900
800
700
600
500
400
300
200
100
0
PART H1
PART H2
PART H3
MEASOUT – MI
T
AV
= 25°C
A
1
2
= +16.25V
DD
AV = –16.25V
SS
V
= 5V
REF
OFFSET DAC = 0x8000
/I = EXTFORCE1/1.2A
I
RANGE LOAD
0 TO 3.7V STEP
= 10µF CERAMIC
FORCE
BUSY
C
LOAD
SAFE MODE
MEASOUT GAIN 1, MI GAIN 20
FVMN
FVMV
FNMV
FVMI
4
3
B
CH1 5V
CH3 5V
CH2 1V
M20µs
4.6%
A CH3
2.9V
W
T
CH4 10V
Figure 44. Transient Response FVMI Mode, EXTFORCE1 Range, Safe Mode
Figure 47. NSD vs. Amplifier Stage and Gain Setting at 1 kHz
20
DV
= +5.25V, AV = +16.5V, AV = –16.5V
DD SS
CC
0
–20
T
= 25°C
= +16.25V
A
AV
DD
AV = –16.25V
MEASOUT – MI
1
SS
V
= 5V
–40
REF
OFFSET DAC = 0x8000
I
/I
= EXTFORCE2/
300mA
RANGE LOAD
FOH
MV: GAIN 0
MV: GAIN 1
MV: GAIN 2
MV: GAIN 3
MI: GAIN 0
MI:GAIN 1
MI: GAIN 2
MI: GAIN 3
–60
FORCE
BUSY
0 TO 10V STEP
= 220nF
2
4
C
LOAD
AUTOCOMP MODE 0x4880
MEASOUT GAIN 1, MI GAIN 20
–80
3
B
–100
CH1 5V
CH3 5V
CH2 2V
M10µs
9.8%
A CH3
2.9V
W
10
100
1k
10k
100k
1M
10M
T
CH4 10V
FREQUENCY (Hz)
Figure 45. Transient Response FVMI Mode, EXTFORCE2 Range,
Autocompensation Mode
Figure 48. ACPSRR of AVDD vs. Frequency
0
–20
FORCE
MEASOUT – MI
–40
T
= 25°C
= +16.25V
A
–60
AV
1
DD
AV = –16.25V
SS
FOH
V
= 5V
REF
OFFSET DAC = 0x8000
/I = EXTFORCE2/300mA
MV: GAIN 0
MV: GAIN 1
MV: GAIN 2
MV: GAIN 3
MI: GAIN 0
MI:GAIN 1
MI: GAIN 2
MI: GAIN 3
–80
I
RANGE LOAD
0 TO 10V STEP
= 220nF
2
4
–100
–120
–140
C
LOAD
SAFE MODE
MEASOUT GAIN 1, MI GAIN 20
BUSY
DV
= +5.25V, AV = +16.5V, AV = –16.5V
CC
DD
SS
3
B
CH1 5V
CH3 5V
CH2 2V
M100µs
9.8%
A CH3
2.9V
W
10
100
1k
10k
100k
1M
10M
T
CH4 10V
FREQUENCY (Hz)
Figure 46. Transient Response FVMI Mode, EXTFORCE2 Range, Safe Mode
Figure 49. ACPSRR of AVSS vs. Frequency
Rev. D | Page 26 of 68
Data Sheet
AD5560
0
0
–20
MI: GAIN 0
–20
FOH
MI: GAIN 0
–40
–40
–60
–60
MV: GAIN 0
–80
MV: GAIN 0
–80
–100
–120
–140
–100
FOH
DV
CC
= +5.25V, AV = +16.5V, AV = –16.5V
DV
= +5.25V, AV = +16.5V, AV = –16.5V
DD
SS
CC
DD
SS
–120
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 50. ACPSRR of DVCC vs. Frequency
Figure 52. ACPSRR of HCAVSSx vs. Frequency
1600
1400
1200
1000
800
600
400
200
0
0
–20
CABLE L = 2µH, CLAMP AT 1.2A
CABLE L = 1µH, CLAMP AT 1.2A
CABLE L = 0.2µH, CLAMP AT 1.2A
CABLE L = 0µH, CLAMP AT 1.2A
MI: GAIN 0
–40
CABLE L = 2µH, CLAMP AT 800mA
CABLE L = 1µH, CLAMP AT 800mA
CABLE L = 0.2µH, CLAMP AT 800mA
CABLE L = 0µH, CLAMP AT 800mA
MV: GAIN 0
–60
CABLE L = 2µH, CLAMP AT 400mA
CABLE L = 1µH, CLAMP AT 400mA
CABLE L = 0.2µH, CLAMP AT 400mA
CABLE L = 0µH, CLAMP AT 400mA
–80
–100
–120
–140
CABLE L = 2µH, CLAMP AT 100mA
CABLE L = 1µH, CLAMP AT 100mA
CABLE L = 0.2µH, CLAMP AT 100mA
CABLE L = 0µH, CLAMP AT 100mA
FOH
DV
= +5.25V, AV = +16.5V, AV = –16.5V
CC
DD
SS
0.001
0.01
0.1
1
10
10
100
1k
10k
100k
1M
10M
R
(Ω)
FREQUENCY (Hz)
LOAD
Figure 51. ACPSRR of HCAVDDx vs. Frequency
Figure 53. ICLAMP Value vs. RLOAD – Cal at 1Ohm
Rev. D | Page 27 of 68
AD5560
Data Sheet
TERMINOLOGY
Slew Rate
Offset Error
The slew rate is the rate of change of the output voltage
expressed in volts per microsecond (V/μs).
Offset error is a measure of the difference between the actual
voltage and the ideal voltage at midscale or at zero current
expressed in millivolts (mV) or percentage of full-scale range
(%FSR).
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of 1 LSB maximum ensures monotonicity.
Gain Error
Gain error is the difference between full-scale error and zero-
scale error. It is expressed in percentage of full-scale range
(%FSR).
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a full-scale
input change.
Gain Error = Full-Scale Error − Zero-Scale Error
where:
Digital-to-Analog Glitch Energy
Full-Scale Error is the difference between the actual voltage and
the ideal voltage at full scale.
Zero-Scale Error is the difference between the actual voltage and
the ideal voltage at zero scale.
Digital-to-analog glitch energy is the amount of energy that is
injected into the analog output at the major code transition. It
is specified as the area of the glitch in nanovolts per second
(nV-sec). It is measured by toggling the DAC register data
between 0x7FFF and 0x8000.
Linearity Error
Linearity error, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the full-scale range. It is measured after adjusting
for offset error and gain error and is expressed in millivolts (mV).
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the part’s ability to avoid coupling
noise and spurious signals that appear on the supply voltage
pin to the output of the switch. The dc voltage on the device
is modulated by a sine wave of 0.2 V p-p. The ratio of the
amplitude of the signal on the output to the amplitude of the
modulation is the ACPSRR. It is expressed in decibels (dB).
Common-Mode (CM) Error
CM error is the error at the output of the amplifier due to the
common-mode input voltage. It is expressed in percentage of
full-scale voltage range per volt (%FSVR/V).
VSTRESS
Clamp Limit
V
STRESS is the stress voltage applied to each pin during leakage
Clamp limit is a measure of where the clamps begin to function
fully and limit the clamped voltage or current.
testing.
Leakage Current
Leakage current is the current measured at an output pin when
the circuit connected to that pin is in high impedance state.
Rev. D | Page 28 of 68
Data Sheet
AD5560
THEORY OF OPERATION
The AD5560 is a single-channel, device power supply for use
in semiconductor automatic test equipment. All the DAC levels
required to operate the device are available on chip.
This block performs three functions related to the force and
sense lines.
•
It clamps the sense line to within a programmable
This device contains programmable modes to force a pin vol-
tage and measure the corresponding current (FVMI) covering
a wide current measure range of up to 1.2 A. A voltage sense
amplifier allows measurement of the DUT voltage. Measured
current or voltage is available on the MEASOUT pin.
threshold level (plus a VBE) of the force line, where the
programmable threshold is set by the OSD DAC voltage
level. This limits the maximum or minimum voltage that
can appear on the FORCE pin; it can be driven no higher
than [V(FIN DAC) + threshold + VBE] and no lower than
[V(FIN DAC) − threshold − VBE].
FORCE AMPLIFIER
KELALM
if the force line goes more
•
•
It triggers an alarm on
The force amplifier is a unity gain amplifier forcing voltage
directly to the device under test (DUT). This high bandwidth
amplifier allows suppression of load transient induced glitching
on the amplifier output. Headroom and footroom requirements
for the amplifier are 2.25 V and an additional 500 mV dropped
across the selected sense resistor with full-scale current flowing.
than the threshold voltage away (OSD DAC level) from the
sense line.
It translates the V(force − sense) voltage to a level
relative to AGND so that it can be measured through
the MEASOUT pin.
The open-sense detect level is programmable over the range
0.62 V to 5 V (16-bit OSD DAC plus one diode drop). The 5 V
OSD DAC can be accessed through the serial interface (see the
DAC register addressing portion of Table 24). There is a 10 kΩ
resistor that can be connected between the FORCE and SENSE
pins by use of SW11. This 10 kΩ resistor is intended to
maintain a force/sense connection when a DUT is not in place.
It is not intended to be connected when measurements are
being made because this defeats the purpose of the OSD circuit
in identifying an open circuit between FORCE and SENSE. In
addition, the sense path has a 2.5 kΩ resistor in series; there-
fore, if the 10 kΩ switch is closed, errors may become apparent
when in high current ranges.
The amplifier is designed to drive high currents up to 1.2 A
with the capability of ganging together outputs of multiple
AD5560 devices for currents in excess of 1.2 A.
The force amplifier can be compensated to ensure stability
when driving DUT capacitances of up to 160 μF.
The device is capable of supplying transient currents in excess
of 1.2 A when powering a DUT with a large decoupling
capacitor. A clamp enable pin (CLEN) allows disabling of the
clamp circuitry to allow the amplifier to quickly charge this
large capacitance.
An extra control bit (GPO) is available to switch out DUT
decoupling when making low current measurements.
DEVICE UNDER TEST GROUND (DUTGND)
DUTGND is the ground level of the DUT.
DUTGND Kelvin Sense
HW_INH
Function
HW_INH LOAD
) allows disabling of
A hardware inhibit pin (
the force amplifier, making the output high impedance. This
function is also available through the serial interface (see the
/
KELALM
flags when the voltage at the DUTGND pin moves
SW-INH
bit in the DPS Register 1, Address 0x2).
too far away from the AGND line (>1 V default setting of the
DGS DAC). This alarm trigger is programmable via the serial
interface. The threshold for the alarm function is program-
mable using the DUTGND SENSE DAC (DGS DAC) (see
Table 24).
LOAD
This pin can also be configured as a
function to allow
multiple devices to be synchronized. Note that either CLEN
HW_INH LOAD
or
can be chosen as a
function.
DAC REFERENCE VOLTAGE (VREF)
The DUTGND pin has a 50 μA pull-up resistor that allows
the alarm function to detect whether DUTGND is open. Setting
One analog reference input, VREF, supplies all DAC levels with
the necessary reference voltage to generate the required dc levels.
DUTALM
the disable
bit high (Register 0x6, Bit 10) disables the
OPEN-SENSE DETECT (OSD) ALARM AND CLAMP
50 μA pull-up resistor and also disables the alarm feature. The
alarm feature can also be set to latched or unlatched (Register 0x6,
Bit 11).
The open-sense detect (OSD) circuitry protects the DUT from
overvoltage when the force and sense lines of the force
amplifier becoming disconnected from each other.
KELALM
Kelvin Alarm (
)
The open-drain active low Kelvin alarm pin flags the user when
an open occurs in either the sense or DUTGND line; it can be
programmed to be either latched or unlatched (Register 0x6,
Bit 13, Bit 11, Bit 7). The delay in the alarm flag is 50 μs.
Rev. D | Page 29 of 68
AD5560
Data Sheet
If a clamp level is exceeded, this is flagged via the latched open-
GPO
CLALM
drain
pin, and the resulting alarm information can be
The GPO pin can be used as an extra control bit for external
switching functions, such as for switching out DUT decoupling
when making low current measurements.
read back via the SPI interface.
The clamp levels should not be set to the same level; instead,
they should be set a minimum of 2 V apart (irrespective of the
MI gain setting). This equates to 10% of FSCR (MI gain = 20)
(20% of FSCR, MI gain of 10) apart. They should also be 1 V
away from the 0 A level.
The GPO pin is also internally connected to an array of thermal
diodes scattered across the AD5560. The diagnostic register
(Address 0x7) details the addressing and location of the diodes.
These can be used for diagnostic purposes to determine the
thermal gradients across the die and across a board containing
many AD5560 devices. When selected, the anode of these
diodes is connected to GPO and the cathode to AGND. The
AD5560 evaluation board uses the ON Semiconductor®
ADT7461 temperature sensor for the purpose of analyzing the
temperature at different points across the die.
The clamp register limits the CLL clamp to the range 0x0000 to
0x7FFF; any code in excess of this is seen as 0x7FFF. Similarly,
the CLH clamp registers are limited to the range 0x8000 to
0xFFFF (see Table 24).
CLALM
Clamp Alarm Function (
CLALM
)
The
open-drain output flags the user when a clamp
COMPARATORS
limit has been hit; it can be programmed to be either latched or
unlatched.
The DUT measured value is monitored by two comparators
(CPOL, CPOH). These comparators give the advantage of
speed for go-no-go testing.
LOAD
Clamp Enable Function (CLEN/
)
Pin 15 (CLEN) allows the user to disable the clamping function
when powering a device with large DUT capacitance, thus allowing
increased current drive to the device and, therefore, speeding
up the charging time of the load capacitance. CLEN is active high.
Table 6. Comparator Output Function
Test Condition
CPOL
CPOH
(VDUT or IDUT) > CPH
(VDUT or IDUT) < CPH
(VDUT or IDUT) > CPL
(VDUT or IDUT) < CPL
CPH > (VDUT or IDUT) > CPL
0
1
LOAD
This pin can also be configured as
to be synchronized. Note that either CLEN or
LOAD
to allow multiple devices
1
0
1
HW_INH
can be
chosen as a
function.
1
SHORT-CIRCUIT PROTECTION
To minimize the number of comparator output lines routed
back to the controller, it is possible to change the comparator
function to a window comparator that outputs on one single
pin, CPO. This pin is shared with CPOH and, when configured
through the serial interface, it provides information on whether
the measured DUT current or voltage is inside or outside the
window set by the CPL and CPH DAC levels (see Table 24).
The AD5560 force amplifier stage has built-in short-circuit
protection per stage as noted in the Specifications section.
When the current clamps are disabled, the user must minimize
the duration of time that the device is left in a short-circuit
condition (for all current ranges).
GUARD AMPLIFIER
A guard amplifier allows the user to force the shield of the
coaxial cable to be driven to the same forced voltage at the
DUT, ensuring minimal voltage drops across the cable to
minimize errors from cable insulation leakage.
Table 7. Comparator Output Function in CPO Mode
Test Condition
CPO Output
(VDUT or IDUT) > CPL and < CPH
(VDUT or IDUT) < CPL or > CPH
1
0
The guard amplifier also has an alarm function that flags the
CURRENT CLAMPS
KELALM
open-drain
pin when the guard output is shorted.
The delay in the alarm flag is 200 μs.
High and low current clamps are included on chip. These protect
the DUT in the event of a short circuit. The CLH and CLL
levels are set by the 16-bit DAC levels. The clamp works to
limit the current supplied by the force amplifier to within the
set levels. The clamp circuitry compares the voltage across the
sense resistor (multiplied by an in-amp gain of 10 or 20) to
compare to the programmed clamp limit and activates the
clamp circuit if either the high level or low level is exceeded,
thus ensuring that the DUT current can never exceed the
programmed clamp limit + 10% of full-scale current.
The guard amplifier output (GUARD/SYS_DUTGND, Pin 43)
can also be configured to function as a SYS_DUTGND pin; to
do this, the guard amplifier must be tristated via software (see
DPS Register 2, Table 19).
COMPENSATION CAPACITORS
The force amplifier is capable of driving DUT capacitances up
to 160 μF. Four external compensation capacitor (CCx) inputs
are provided to ensure stability into the maximum load capacit-
ance while ensuring that settling time is optimized. In addition,
five CFx capacitor inputs are provided to switch across the sense
Rev. D | Page 30 of 68
Data Sheet
AD5560
resistors to further optimize stability and settling time perform-
ance. The AD5560 has three compensation modes: safe mode,
autocompensation mode, and manual compensation mode, all
of which are described in more detail in the Force Amplifier
Stability section.
HIGH CURRENT RANGES
For currents in excess of 1200 mA, a gang mode is available
whereby multiple devices are ganged together for higher currents.
There are two methods of ganging channels together; these are
discussed in the following two sections.
The range of suggested compensation capacitors allows
optimum performance for any capacitive load from 0 pF
to 160 μF using one of the modes previously listed.
Master and Slaves in Force Voltage (FV) Mode
All devices are placed in force voltage (FV) mode. One device
acts as the master device and the other devices act as slaves. By
connecting in this manner, any device can be configured as the
master. Here, the MASTER_OUT pin of the master device is
connected to the output of the force amplifier, and it feeds the
inputs of each slave force amplifier (via the SLAVE_IN pin ).
All devices are connected externally to the DUT. For current
to be shared equally, there must be good matching between
each of the paths to the DUT. Settings for DPS Register 2 are
master = 0x0000, slave = 0x0400. Clamps should be disabled in
the slave devices.
Although there are four compensation input pins and five feed-
forward capacitor inputs pins, all capacitor inputs may be used
only if the user intends to drive large variations of DUT load
capacitances. If the DUT load capacitance is known and does
not change for all combinations of voltage ranges and test
conditions, then it is possible only one set of CCx and CFx
capacitors may be required.
Table 8. Suggested Compensation Capacitor Selection
Capacitor
Value
100 pF
100 pF
330 pF
3.3 nF
4.7 nF
22 nF
CC0
CC1
CC2
CC3
MASTER DPS
SLAVE IN
SW6
SW5-a
MASTER OUT
SW16
EXTFORCE1
EXTFORCE2
SW5-b
SW5-a
FIN
DAC
CF0
CF1
×20
OR
×W
LOCAL
EXTMEASIH1
EXTMEASIL
FEEDBACK
CF2
CF3
CF4
100 nF
470 nF
2.2 μF
R
SENSE
I
SENSE
AMP
SENSE
×1
V
SENSE
AMP
The voltage range for the CCx and CFx pins is the same as the
voltage range expected on FORCE; therefore, choice of capa-
citors should take this into account. CFx capacitors can have
10% tolerance; this extra variation directly affects settling
times, especially when measuring current in the low current
ranges. Selection of CCx should be at ≤5% tolerance.
SLAVE DPS 1
SLAVE IN
SW6
MASTER OUT
SW5-a
SW16
EXTFORCE1
EXTFORCE2
SW5-b
SW5-a
FIN
DAC
×20
OR
×W
CURRENT RANGE SELECTION
LOCAL
EXTMEASIH1
EXTMEASIL
FEEDBACK
Integrated thin film resistors minimize external components
and allow easy selection of current ranges from 5 µA to
25 mA. Using external current sense resistors, two higher
current ranges are possible: EXTFORCE1 can drive currents
up to 1.2 A, while EXTFORCE2 is designed to drive currents
up to 500 mA. The voltage drop across the selected sense resistor
is 500 mV when full-scale current is flowing through it.
I
SENSE
AMP
SENSE
×1
V
SENSE
AMP
SLAVE DPS 2
SLAVE IN
SW6
MASTER OUT
SW5-a
The measure current amplifier has two gain settings, 10 and
20. The two gain settings allow users to achieve the quoted/
specified current ranges with large or small voltage swings.
The gain of 20 setting is intended for use with a 5 V reference,
and the gain of 10 setting is for use with a 2.5 V reference. Both
combinations ensure the specified current ranges. Other
VREF/gain setting combinations should only be used to
achieve smaller current ranges. Attempting to achieve greater
current ranges than the specified ranges is outside the intended
operation of the AD5560. The maximum guaranteed voltage
across RSENSE is 0.64 V (gain of 20) or 0.7 V (gain of 10).
SW16
EXTFORCE1
EXTFORCE2
SW5-b
SW5-a
FIN
DAC
×20
OR
×W
LOCAL
EXTMEASIH1
EXTMEASIL
FEEDBACK
I
SENSE
AMP
SENSE
×1
V
SENSE
AMP
DUT
DUTGND
Figure 54. Simplified Block Diagram of High Current Ganging Mode
Rev. D | Page 31 of 68
AD5560
Data Sheet
Master in FV Mode, Slaves in Force Current (FI) Mode
The EXTFORCE1, EXTFORCE2, or 25 mA ranges can be
used for the gang mode. Therefore, it is possible to gang devices
to get a high voltage/high current combination, or a low
voltage/high current combination.
The master device is placed into FV mode, and all slave devices
into force current (FI) mode. The measured current of the
master device (MASTER_OUT) is applied to the input of all
slave devices (SLAVE_IN), and the slaves act as followers. All
channels work to share the current equally among all devices
in the gang. Because the slaves force current, matching the
DUT paths is not so critical. Settings for DPS Register 2 are
master = 0x0200, slave = 0x0600. Clamps should be disabled in
the slave devices.
For example, ganging five 25 V/25 mA devices using the 25 mA
range achieves a 25 V/625 mA range, whereas five 15 V/200 mA
devices using the EXTFORCE2 path can achieve a 15 V/1 A
range. Similarly, ganging four 3.5 V/1.2 A devices using the
EXTFORCE1 path results in a 3.5 V/4.8 A DPS.
IDEAL SEQUENCE FOR GANG MODE
MASTER DPS
SLAVE IN
Use the following steps to bring devices into and out of gang mode:
SW6
SW5-a
MASTER OUT
EXTFORCE1
1. Choose the master device and force 0 V output, corres-
ponding to zero current.
2. Select slave DPS 1 and place it in slave mode (keep slaves in
SW16
SW5-b
SW5-a
FIN
DAC
EXTFORCE2
SENSE
SW-INH HW_INH
high-Z mode via
or
until ready to gang).
3. Select to gang in either current or voltage mode.
4. Repeat Step 2 and Step 3 one at a time through the chain of
slaves.
5. Load the required voltage to the master device. The other
devices copy either voltage or current as programmed.
EXTMEASIH1
EXTMEASIL
MEASOUT
BUFFER
R
×20
SENSE
AND GAIN
I
I
I
SENSE
AMP
SLAVE DPS 1
SLAVE IN
To remove devices from the gang, the master device should
be programmed to force 0 V out again. The procedure for
removing devices should be the reverse of Step 1 through Step 5.
SW5-a
SW6
MASTER OUT
SW16
EXTFORCE1
EXTFORCE2
SENSE
SW5-b
SW5-a
FIN
DAC
Note that this may not always be possible in practice; therefore,
it is also possible to gang and ungang while driving a load. Just
ensure that the slave devices are in high-Z mode while confi-
guring them into the required range and gang setting.
EXTMEASIH1
EXTMEASIL
MEASOUT
BUFFER
AND GAIN
×20
SENSE
AMP
Gang mode extends only to the 25 mA range and the two high
current ranges, EXTFORCE1 and EXTFORCE2. Therefore, where
an accurate measurement is required at a low current, the user
should remove slaves from the gang to move to the appropriate
lower current range to make the measurement. Similarly, slaves
can be brought back into the gang if needed.
SLAVE DPS 2
SLAVE IN
SW5-a
SW6
MASTER OUT
SW16
EXTFORCE1
SW5-b
SW5-a
FIN
DAC
EXTFORCE2
SENSE
COMPENSATION FOR GANG MODE
When ganging, the slave devices should be set to the fastest
response.
EXTMEASIH1
EXTMEASIL
MEASOUT
BUFFER
AND GAIN
×20
When slaves are in FI mode, the AD5560 force amplifier over-
rides other compensation settings to enforce CFx = 0, RZ = 0,
and gmx ≤ 1. This is done internally to the force amplifier;
therefore, readback will not show that the signals inside the
force amplifier actually change.
SENSE
AMP
DUT
DUTGND
SYSTEM FORCE/SENSE SWITCHES
Figure 55. Simplified Block Diagram of Gang Mode,
Using an FV/FI Combination
System force/sense switches allow easy connection of a central
or system parametric measurement unit (PMU) for calibration
or additional measurement purposes.
The system device under test ground (SYS_DUTGND) switch
is shared with the GUARD/SYS_DUTGND pin (Pin 43). See
the DPS Register 2 in Table 19 for addressing details.
Rev. D | Page 32 of 68
Data Sheet
AD5560
These diodes can be muxed out onto the GPO pin. The
DIE TEMPERATURE SENSOR AND THERMAL
SHUTDOWN
diagnostic register (Address 0x7) details the addressing and
location of the diodes. These can be used for diagnostic
purposes to determine the thermal gradients across the die
and across a board containing many AD5560 devices. When
selected, the anode of each diode is connected to GPO and
the cathode to AGND. The AD5560 evaluation board uses
the ON Semiconductor ADT7461 temperature sensor for
the purpose of analyzing the temperature at different
points across the die.
There are three types of temperature sensors in the AD5560.
•
The first is a temperature sensor available on the MEASOUT
pin and expressed in voltage terms. Nominally at 25°C, this
sensor reads 1.54 V. It has a temperature coefficient of
4.7 mV/°C. This sensor is active during power-down mode.
Die Temp = (VMEASOUT(TSENSE) − 1.54)/0.0047 + 25°C
Based on typical temperature sensor output voltage at
25°C and output scaling factor.
Note that, when a thermal shutdown occurs, as the force
amplifier is inhibited or tristated, user intervention is required
to reactivate the device. It is necessary to clear the temperature
alarm flag by issuing a read command of Register Address 0x44
(alarm status and clear alarm status register, Table 25), and
•
The second type of temperature sensor is related to the
thermal shutdown feature in the device. Here, there are
sensors located in the middle of the enabled power stage,
which are used to trip the thermal shutdown. The thermal
shutdown feature senses only the power stages, and the power
stage that it senses is determined by the active stage.
SW-INH
then issuing a new write to the DPS Register 1 (
to reenable the force amplifier.
= 1)
See also the Thermal Considerations section.
If ranges of <25 mA are selected, the EXTFORCE1 sensor is
monitored. The EXTFORCE1 power stage itself is made
up of three identical stages, but the thermal shutdown is
activated by only one stage (EXTFORCE1B). Similarly, the
EXTFORCE2 stage is made up of two identical output
stages, but the thermal shutdown can be activated by only
one stage (EXTFORCE2A).
MEASURE OUTPUT (MEASOUT)
The measured DUT voltage, current (voltage representation
of DUT current), KSENSE, or die temperature is available on
MEASOUT with respect to AGND. The default MEASOUT
range is the forced voltage range for voltage measure and
current measure (nominally 12.81 V, depending on reference
voltage and offset DAC) and includes overrange to allow for
system error correction.
The thermal shutdown circuit monitors these sensors and,
in the event of the die temperature exceeding the program-
mable threshold temperature (100°C, 110°C, 120°C, 130°C
(default)), the device protects itself by inhibiting the force
The serial interface allows the user to select another MEASOUT
range of (1.025 × VREF) to AGND; this range is suitable for use
with an ADC with a smaller input range.
SW-INH
amplifier stage, clearing
flagging the overtemperature event via the open-drain
TMPALM
in DPS Register 1 and
To allow for system error correction, there is additional gain
for the force function. If this overrange is used as intended,
the output range on MEASOUT scales accordingly.
pin, which can be programmed to be either
latched or unlatched. These temperature sensors can be
read via the MEASOUT pin by selecting them in the
diagnostic register (Table 23, VPTAT low and VPTAT
high). They are expressed in voltage and to scale to
temperature. They must be referred to the VTSD reference
voltage levels (see Table 23) also available on MEASOUT.
This set of sensors is not active in power-down mode.
The MEASOUT line can be tristated via the serial interface.
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the required force voltage range.
VMID VOLTAGE
The midcode voltage (VMID) is used in the measure current
amplifier block to center the current ranges at about 0 A.
This is required to ensure that the quoted current ranges can
be achieved when using offset DAC settings other than the
default. VMID corresponds to 0x8000 or the DAC midcode
value, that is, the middle of the voltage range set by the offset
DAC setting (see Table 15 and Figure 56).
Die Temp_y = {(VPTAT_x − VTSD_low)/[(VTSD_high −
VTSD_low)/(Temp_high – Temp_low)]} + Temp_low
where:
x, y are (high, NPN) and (low, PNP).
Temp_low = −273°C.
Temp_high = +130°C.
V
MID = 5.125 × VREF × (32,768/216) − (5.125 × VREF ×
(OFFSET_DAC_CODE/216))
•
The third set of temperature sensors is an array of thermal
diodes scattered across the die. These diodes allow the user
to evaluate the temperature of different parts of the die and
are of great use to determine the temperature gradients
across the die and the temperature of the accurate portions
of the die when the device is dissipating high power. For
further details on the thermal array and locations, see the
diagnostic register section in Table 23.
or
V
MID = 5.125 × VREF × ((32,768 − Offset DAC)/216)
Rev. D | Page 33 of 68
AD5560
Data Sheet
VMIN is another inportant voltage level that is used in other
parts of the circuit. When using a MEASOUT gain of 0.2, the
on (the high voltage DAC amplifiers used here require
approximately 2 V footroom to AVSS). See the Choosing
AVDD/AVSS Power Supply Rails section for more information.
V
MIN level is used to scale the voltage range; therefore, when
choosing supply rails, it is very important to ensure that there
is sufficient footroom so that the VMIN level is not impinged
VMIN = −5.125 × VREF × (OFFSET_DAC_CODE/216)
Table 9. MEASOUT Output Ranges
Output Voltage Range1
Offset DAC =
MEASOUT Function
GAIN1 = 0, MEASOUT Gain = 1
Transfer Function
VDUT
0x0
Offset DAC = 0x8000 Offset DAC = 0xE000
Measure Voltage (MV)
0 V to 25.62 V
0 V to 25.62 V
12.81 V
12.81 V
−22.42 V to +3.2 V
−22.42 V to +3.2 V
Measure GAIN0 = 0
MI gain = 20
MI gain = 10
(IDUT × RSENSE × 20) + VMID
(IDUT × RSENSE × 10) + VMID
Current
(MI)
GAIN0 = 1
0 V to 12.81 V
(VREF = 2.5 V)
6.4 V
(VREF = 2.5 V)
−11.2 V to +1.6 V
(VREF = 2.5 V)
1 VREF = 5 V, unless otherwise noted.
Table 10.
MEASOUT Function
GAIN1 = 1, MEASOUT Gain = 0.2
Transfer Function
Output Voltage Range1, 2
Measure Voltage (MV)
MV = 0.2 × (VDUT − VMIN
)
0 V to 5.12 V ( 2.56 V centered around 2.56 V)
(includes overrange)
Measure GAIN0 = 0
Current
MI gain = 20
MI gain = 10
(IDUT × RSENSE × 20 × 0.2) + 0.5125 × VREF
(IDUT × RSENSE × 10 × 0.2) + 0.5125 × VREF
0 V to 5.12 V ( 2.56 V centered around 2.56 V)
(includes overrange)
(MI)
GAIN0 = 1
1.28 V to 3.84 V ( 1.28 V, centered around 2.56 V)
0 V to 2.56 V ( 1.28 V, centered around 1.28 V)
(VREF = 2.5 V)
1 VREF = 5 V, unless otherwise noted.
2 The offset DAC setting has no effect on the output voltage range.
Table 11. Possible ADCs and ADC Drivers for Use with AD55601
Part
No.
Sample
250 kSPS
500 kSPS
500 kSPS
Resolution Rate
Channels AIN Range2
Interface
ADC Driver
Multiplexer3
Package
AD7685 16
AD7686 16
AD7693 16
1
1
1
0 to VREF
Serial, SPI
ADA4841-x
ADG704, ADG708
M S O P,
LFCSP
M S O P,
LFCSP
M S O P,
LFCSP
0 to VREF
Serial, SPI
Serial, SPI
ADA4841-x
ADG704, ADG708
−VREF to +VREF
ADA4841-x,
ADA4941-1
ADG1404,
ADG1408,
ADG1204
AD7610 16
AD7655 16
250 kSPS
1 MSPS
1
4
Bipolar 10 V, bipolar
5 V, unipolar 10 V,
unipolar 5 V
Serial, parallel AD8021
AD1404, ADG1408,
ADG1204
LFCSP,
LQFP
0 V to 5 V
Serial, SPI
ADA4841-x/
AD8021
LQFP,
LFCSP
1 Subset of the possible ADCs, ADC drivers, and multiplexers suitable for use with the AD5560. Visit http://www.analog.com for more options.
2 Do not allow the MEASOUT output range to exceed the AIN range of the ADC.
3 For the purposes of sharing ADCs among multiple DPS channels, note that the multiplexer is not absolutely necessary because the AD5560 MEASOUT path has a
tristate mode.
Rev. D | Page 34 of 68
Data Sheet
AD5560
VREF
VMID = (VTOP – VBOT)/2
V
MID
VTOP
R
R
2R
8.25R
HV DAC AMP
LOW VOLTAGE
OFFSET DAC
DAC
att
V
= (1 + 2/8.25) × (OFFSET DAC VOLTAGE)
OS
8.25R
2R
2R
8.25R
VBOT
V
5R
MIN
att
REFGND
R
MEASOUT
OSD DAC IN
tri
10R
10R
MI_x10
INTERNAL
MEASI LOW
MEASURE
CURRENT
5R
I
AMP
SENSE
MI_x20
mi
1kΩ
INTERNAL
MEASI HIGH
mi_gain
R
2R
att
att
2R
5R
MEASURE
VOLTAGE
att
1kΩ
mv
5R
5R
5R
5R
DUTGND
SENSE
V
AMP
SENSE
5R
-
NOTES
1. att: ATTENUATION FOR EXTERNAL MEASOUT × 0.20 FOR OUTPUT VOLTAGE RANGE 0V TO 5.125V (WITH OVERRANGE) (VREF = 5V).
tri: TRISTATE MODE
mv: MEASURE VOLTAGE
mi: MEASURE CURRENT
mi_gain: MEASURE I GAIN SELECTION
Figure 56. MI, MV, and MEASOUT Block Showing Gain Settings and Offset DAC Influence
Rev. D | Page 35 of 68
AD5560
Data Sheet
FORCE AMPLIFIER STABILITY
Table 12. External Variables
There are three modes for configuring the force amplifier: safe
mode, autocompensation mode, and manual compensation mode.
Manual compensation mode has highest priority, followed by safe
mode, then autocompensation mode.
Name Description
Min
Max
CR
DUT capacitance with contributing 10 nF
ESR
160 μF
RC
CD
RD
IR
ESR in series with CR
DUT capacitance with negligible ESR
Loading resistance at the DUT
Current range
1 mΩ
100 pF
~2 Ω
5 ꢀA
10 Ω
10 nF
Infinity
1.2 A
Safe Mode
Selected through Compensation Register 1 (see Table 20), this
mode guarantees stability of the force amplifier under all
conditions. Where the load is unknown, this mode is useful but
results in a slow response. This is the power-on default of the
AD5560.
Table 13. Internal Variables
Name Description
Min
Max
RZ
Resistor in series with CC0, which
contributes a zero.
500 Ω
1.6 MΩ
Autocompensation Mode
RP
Resistor to 8 pF to contribute an
additional pole
200 Ω
100 pF
4.7 nF
1 MΩ
Using this mode, the user inputs the CR and ESR values, and
the AD5560 decides the most appropriate compensation
scheme for these load conditions. The compensation chosen
is for an optimum tradeoff between ac response and stability.
CC0:CC3 Capacitors to ensure
unconditional stability
CF0:CF4 Capacitors to optimize ac
performance into different CR, CD
100 nF
10 ꢀF
gmx
Transconductance of force
amplifier input stage
40 ꢀA/V 900 ꢀA/V
Manual Compensation Mode
This mode allows access to all of the internal programmable
parameters to configure poles/zeros, which affect the dynamic
performance of the loop. These variables are outlined in
Table 12 and Table 13.
Figure 57 shows more details of the force amplifier block.
4.7nF
C
C
C
C
C
AD5560
F0
F1
F2
F3
FORCE VOLTAGE LOOP
22nF
100nF
470nF
2.2µF
F4
R
R
2
1
SENSE
SENSE
EXTFORCE2
EXTFORCE1
R
:
P
20Ω
200Ω TO 1MΩ
200Ω
2kΩ
FORCE
8pF
20kΩ
100kΩ
R
C
SENSE
R :
Z
500Ω TO
1.6MΩ
+
–
C
R
D
D
AGND
V
–
C
g
R
m
+
SENSE
+
6kΩ
25kΩ
100kΩ
FORCE
DAC
×1
+
–
–
DUTGND
C
C
C
C
C3
C0
C1
C2
100pF
100pF
330pF
3.3nF
Figure 57. Block Diagram of a Force Amplifier Loop
Rev. D | Page 36 of 68
Data Sheet
AD5560
Placing a capacitor in parallel with this sense resistor provides
an ac feedforward path to the DUT. Therefore, at high frequen-
cies, the DUT is driven through the CFx capacitor rather than
through the sense resistor.
POLES AND ZEROS IN A TYPICAL SYSTEM
Typical closed loop systems have one dominant pole in the
feedback path, providing −20 dB/decade gain roll off and 90°
of phase shift so that the gain decreases to 0 dB where there
is a conservative 90° of phase margin.
Note that each CFx output has an output impedance of about
3 Ω. This is very small compared to the sense resistors of the
low current ranges but not so for the highest current ranges.
Therefore, the CFx capacitors are most effective in the low current
ranges but are of lesser benefit in higher current ranges.
The AD5560 has compensation options to help cope with the
various load conditions that a DPS is presented with.
MINIMIZING THE NUMBER OF EXTERNAL
COMPENSATION COMPONENTS
As shown in the force amplifier diagram (see Figure 57), there
is a pole at 1/( RSENSE × [CFx + CR]) and a zero at 1/[ RSENSE × CFx].
Therefore, the output impedance of each CFx output, at around
1 Ω, limits the improvement available by using the CFx capaci-
tors. For a large load capacitance, there is still a pole at −1/[1 Ω
× CR] above which the phase improvement is lost. If there is
also a cable resistance to the DUT, or if CFx has significant ESR,
this should be added to the 1 Ω to calculate the pole frequency.
Note that, depending on the range of load conditions, not all
external capacitors are required.
CFx Pins
There are five external CFx pins. All five pins are used
in the autocompensation mode to choose a suitable capacitor,
depending on the load being driven. To reduce component
count, it is possible to connect just one capacitor, for instance,
If CFx is chosen to be bigger than the load capacitance, it can
dominate the settling time and slow down the settling of the
whole circuit. Also, it directly affects the time taken to measure
a current (RSENSE × CFx).
C
F2 to the CF2, CF1, and CF0 pins. Therefore, when any of the
smallest three external capacitors are selected, the same physical
capacitor is used because it is connected to all three pins. A
disadvantage here is that the larger CF2 capacitor should be
bigger than optimal and may increase settling time of the
whole circuit (particularly the measure current).
The Effect of RZ
When the load capacitance is known, RZ can be used to optim-
ize the response of the AD5560. Because the CFx buffers have
some output impedance of about 1 Ω, there is likely to be some
additional resistance to the DUT. There can still be an output
pole associated with this resistance and the load capacitance,
CR, 1/[R0 × CR] (where R0 = the series/parallel combination of
the sense resistor, the CFx output impedance, the CFx capacitor
ESR, and the cable to DUT). This is particularly significant for
larger load capacitances in any current range. By programming
a zero into the loop response by setting RZ (in series with CC0),
CCx Pins
To make the AD5560 stable with any unknown capacitor
from 0 pF to 160 μF, all four CCx capacitors are required.
However, if the range of load is from 0 pF to 20 µF, then
C
C3 can be omitted. Similarly, if the load range is from 0 pF to
2.2 µF, then CC2 and CC3 can be omitted. Only CC0 is required
in autocompensation mode.
Note that safe mode, which makes the device stable in any
load from 0 pF to 160 μF, simply switches in all of the four
it is possible to cancel this pole. Above the frequency 1/[CC0
×
C
Cx capacitors. Stability into 160 μF is assured only if all four
RZ], the series resistance and capacitance begin to look resistive
rather than capacitive, and the 90° phase shift and 20 dB/decade
contributed by CC0 no longer apply. Note that, to cancel the
load pole with the RZ zero, the load pole must be known to
exist. Adding a zero to cancel a pole that does not exist causes
an oscillation (perhaps the expected load capacitor is not
present). Also, it is recommended to avoid creating a zero
frequency lower than the pole frequency; instead, allow the zero
frequency to be 2× or 3× higher than the calculated pole
frequency.
capacitors are present; otherwise, the maximum capacitor for
stability is reduced to 20 μF, 2.2 μF, or 220 nF, depending on
how many capacitors are missing.
EXTRA POLES AND ZEROS IN THE AD5560
The Effect of CCx
CC0 is switched on at all times. CC3, CC2, and CC1 can be con-
nected in addition to CC0 to slow down the force amplifier loop.
In the 500 mA range looking into a small load capacitor, with
only CC0 connected, the ac gain vs. phase response results in
~90° of phase margin and a unity gain bandwidth (UGB) of
~400 kHz.
The Effect of RP
RP can be used to ensure circuit stability when a poor load
capacitor with significant ESR is present. Above the frequency,
1/[CR × RC], the DUT begins to look resistive. The ESR of the
DUT capacitor, RC, contributes a zero at this frequency. The
load capacitor, CR, is counted on to stabilize the system when
the user has cancelled the load pole with the RZ zero. Just as the
absence of CR under these circumstances can cause oscillations,
the presence of ESR RC while nonzero RZ is used can cause
The Effect of CFx
The output of the AD5560 passes through a sense resistor to
the DUT. Coupled with the load capacitor, this sense resistor
can act as a low-pass filter that adds phase shift and decreases
phase margin (particularly in the low current ranges where the
sense resistors are large).
Rev. D | Page 37 of 68
AD5560
Data Sheet
stability problems. This is most likely to be the case when there
are both a large CR and large RC.
settings when using the manual compensation register (this
algorithm is what the autocompensation method is based upon):
The RP resistor is intended to solve this problem. Again, it is
prudent not to cancel exact pole/zero cancellation with RZ and
instead allow the zero to be 2× to 3× the frequency of the pole.
It is best to be very conservative when using RZ to cancel the
load pole. Choose a high zero frequency to avoid flat spots in
the gain curve that extend bandwidth, and be conservative when
choosing RP to create a pole. Aim to place the RZ zero at 5× the
exact cancellation frequency and the RP pole at around 2× the
exact cancellation frequency. The best solution here is to avoid
this complexity by using a high quality capacitor with low ESR.
1. Use CR (the load capacitance with a series ESR) and RC (the
ESR of that load capacitance) as inputs.
2. Assume that CR has not been overestimated and that RC has
not been underestimated. (Although, when the ESR RC is
shown to have a frequency dependence, the lowest RC that
occurs near the resonant frequency is probably a better
guide. However, do not underestimate this ESR).
a.
C
C0 is the suggested 100 pF.
b.
C
Fx capacitor values are as suggested, and they extend
up to 2.2 µF (CF4). For faster settling into small
capacitive loads, include smaller CFx values such as CF3
and CF2. If a capacitor is not included, then short the
corresponding CFx pin to one that is.
COMPENSATION STRATEGIES
Ensuring Stability into an Unknown Capacitor Up to a
Maximum Value
c. There is approximately 1 Ω of parasitic resistance, RC,
from the AD5560 to the DUT (for example, the cable);
RC = 1 Ω.
If the AD5560 has to be stable in a range of load capacitance
from no load capacitance to an upper limit, then select manual
compensation mode and, in Compensation Register 2, set the
parameters according to the maximum load capacitance listed
in Table 14.
3. Select gm[1:0] = 2, CC[3:1] = 000. This makes the input stage of
the force amplifier; have gmx = 300 µA/V; deselect the
compensation capacitors, CC1, CC2, CC3, so that only CC0 is
active.
4. Choose a CF[2:0] value from 0 to 4 to select the largest CFx
capacitor that is smaller than CR.
5. If CR < 100 nF, then set RZ[2:0] = 0, RP[2:0] = 0. This ends the
algorithm.
6. Calculate R0, the resistive impedance to the DUT, using the
following steps:
Table 14. Suggested Compensation Settings for Load Capa-
citance Range of Unknown Value to Some Maximum Value
Capacitor
Min Max
gm[1:0]
RP[2:0]
RZ[2:0]
CC[3:1]
000
001
010
011
111
CF[2:0]
0
0
0
0
0
0.22 μF
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0
2
3
4
4
4
2.2 μF
10 μF
20 μF
160 μF
a. Calculate RS, the sense resistor, from the selected
current range using RS = 0.5 V/IRANGE
.
b. Calculate RF, the output impedance, through the CFx
capacitor, by using
Table 14 assumes that the CCx and CFx capacitor values are those
suggested in Table 8.
RF = 1.2 Ω + (ESR of CFx capacitor)
Making a circuit stable over a range of load capacitances for
no load capacitance or greater means that the circuit is over-
compensated for small load capacitances, undercompensated
for high load capacitances, or both. The previous choice settings,
along with the suggested capacitor values, is a compromise
between both. By compromising phase margin into the largest
load capacitors, the system bandwidth can be increased, which
means better performance under load current transient condi-
tions. The disadvantage is that there is more overshoot during a
large DAC step. To reduce this at the expense of settling time, it
may be desirable to temporarily switch a capacitor range 5× or
10× larger before making a large DAC step.
c. Calculate RFM, a modified version of RF, which takes
account of frequency dependent peaking, through the
C
Fx buffers into a large capacitive load, by using
RFM = RF/(1 + [2 × (CFx/2.2 μF)])
That is, RFM is up to 3× smaller than RF, when the
selected CFx capacitor is large compared to 2.2 μF.
Then calculate
R0 = RC + (RS ||RFM
)
where RC takes its value from the assumptions in Step 2.
7. If RC > (R0/5), then the ESR is large enough to make the
DUT look resistive. Choose RZ[2:0] = 0, RP[2:0] = 0. This ends
the algorithm
8. Calculate the unity gain frequency (Fug), the ideal unity
gain frequency of the force amplifier, from Fug =
OPTIMIZING PERFORMANCE FOR A KNOWN
CAPACITOR USING AUTOCOMPENSATION MODE
The autocompensation mode decides what values of gmx, CCx
CFx, RZ, and RP should be chosen for good performance in a
particular capacitor. Both the capacitance and its ESR need to
be known. To avoid creating an oscillator, the capacitance should
not be overestimated and the ESR should not be underesti-
mated. Use the following steps to determine compensation
gmx/2πCC0. Using the previously suggested values (gm[1:0] = 2
gives gmx = 300 µA/V and CC0 = 100 pF), Fug calculates to
480 kHz.
9. Calculate FP, the load pole frequency, using FP =
1/(2πR0CC0).
Rev. D | Page 38 of 68
Data Sheet
AD5560
10. Calculate FZ, the ESR zero frequency, using FZ =
1/(2πRcCr).
11. If FP > Fug, the load pole is above the bandwidth of the
AD5560. Ignore it with RZ[2:0] = 0, RP[2:0] = 0. This ends the
algorithm
12. If RC < (R0/25), then the ESR is negligible. Attempt to
cancel the load pole with RZ zero. Choose an ideal zero
frequency of 2 × FP for some safety margin and then
choose the RZ[2:0] value that gives the closest frequency on a
logarithmic scale. This ends the algorithm
13. Otherwise, this is a troublesome window in which a load
pole and a load zero can’t be ignored. Use the following
steps:
A more complex alternative is to calculate the overall impedance
at the expected unity gain bandwidth and use this to calculate
an equivalent series CR and RC that have the same complex
impedance at that particular frequency.
DAC LEVELS
This device contains all the dedicated DAC levels necessary
for operation: a 16-bit DAC for the force amplifier, two 16-bit
DACs for the clamp high and low levels, two 16-bit DACs for
the comparator high and low levels, a 16-bit DAC to set a
programmable open sense voltage, and a 16-bit offset DAC
to bias or offset a number of DACs on chip (FORCE, CLL,
CLH, CPL, CPH).
•
To cancel the load pole at FP, choose an ideal zero
frequency of 6 × FP (this is more conservative than the
2 × FP suggested earlier, but there is more that can go
wrong with miscalculation). Then choose the RZ[2:0]
value that gives the closest zero to this ideal frequency
of 6 × FP on a logarithmic scale.
To cancel the ESR zero at FZ, choose an ideal pole
frequency of 2 × FZ.
Then choose the RP[2:0] value that gives the closest pole
to this ideal frequency of 2 × FZ on a logarithmic scale.
This ends the algorithm
FORCE AND COMPARATOR DACS
The architecture of the main force amplifier DAC consists of
a 16-bit R-2R DAC, whereas the comparator DACs are resistor-
string DACs followed by an output buffer amplifier. This
resistor-string architecture guarantees DAC monotonicity.
The 16-bit binary digital code loaded to the DAC register
determines at what node on the string the voltage is tapped
off before being fed to the output amplifier.
•
•
The comparator DAC is similarly arranged. The force and
comparator DACs have a 25.62 V span, including overrange
to enable offset and gain errors to be calibrated out.
ADJUSTING THE AUTOCOMPENSATION MODE
The transfer function for these 16-bit DACs is
The autocompensation algorithm assumes that there is 1 Ω of
resistance (RC) from the AD5560 to the DUT. If a particular
application has resistance that differs greatly from this, then
it is likely that the autocompensation algorithm is nonoptimal.
DAC CODE
VOUT = 5.125×VREF ×
− 5.125×VREF ×
216
OFFSET _ DAC _ CODE
+ DUTGND
216
If using the autocompensation algorithm as a starting point,
consider that overstating the CR capacitance and understating
the ESR RC is likely to give a faster response but could cause
oscillations. Understating CR and overstating RC is more likely
to slow things down and reduce phase margin but not create
an oscillator.
where DAC CODE is X2 (see the Offset and Gain Registers
section).
CLAMP DACS
The architecture of the clamp DAC consists of a 16-bit resistor-
string DAC followed by an output buffer amplifier. This resistor-
string architecture guarantees DAC monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
what node on the string the voltage is tapped off before being
fed to the output amplifier.
It is often advisable to err on the side of simplicity. Rather than
insert a pole and zero at similar frequencies, it may be better to
add none at all. Set RP[2:0] = RZ[2:0] = 0 to push them beyond the
AD5560 bandwidth.
The clamp DACs have a 25.62 V span, including overrange, to
enable offset and gain errors to be calibrated out.
DEALING WITH PARALLEL LOAD CAPACITORS
In the event that the load capacitance consists of two parallel
capacitors with different ESRs, it is highly likely that the overall
complex impedance at the unity gain bandwidth is dominated
by the larger capacitor and its ESR. Assuming that the smaller
capacitor does not exist normally is a safer simplifying assump-
tion.
Rev. D | Page 39 of 68
AD5560
Data Sheet
The transfer function for these 16-bit DACs is
Table 15. Offset DAC Relationship with Other DACs, VREF = 5 V
Offset DAC Code DAC Code1 DAC Output Voltage Range
DAC CODE
VCLH,VCLL = 5.125×VREF
×
− 5.125×V
×
REF
216
0
0
0.00
0
0
…
32,768
65,535
…
12.81
25.62
…
OFFSET _ DAC _CODE
+ DUTGND
216
The transfer function for the clamp current value is
32,768
32,768
32,768
…
0
−12.81
0.00
12.81
…
DAC CODE − 32768
32,768
65,535
…
5.125×VREF
×
216
ICLL, ICLH =
RSENSE × MI _ AMP _GAIN
where:
SENSE is the sense resistor.
MI_AMP_GAIN is the gain of the MI amp (either 10 or 20).
57,344
57,344
57,344
…
0
−22.42
−9.61
3.20
…
R
32,768
65,535
…
OSD DAC
65,355
…
Footroom limitations
The OSD DAC is a 16-bit DAC function, again a resistor string
DAC guaranteeing monotonicity. The 16-bit binary digital
code loaded to the DAC register determines at what node on
the string the voltage is tapped off before being fed to the
output amplifier. The OSD function is used to program the
voltage difference needed between the force and sense lines
before the alarm circuit flags an error. The OSD DAC has a
range of 0.62 V to 5 V. The transfer function is as follows:
1 DAC code shown for 16-bit force DAC.
OFFSET AND GAIN REGISTERS
Each DAC level contains independent offset and gain control
registers that allow the user to digitally trim offset and gain.
These registers give the user the ability to calibrate out errors
in the complete signal chain (including the DAC) using the
internal m and c registers, which hold the correction factors.
DAC CODE
(1)
VOUT = VREF ×
216
The digital input transfer function for the DACs can be
represented as
The offset DAC does not affect the OSD DAC output range.
x2 = [x1 × (m + 1)/2n] + (c – 2n – 1
)
DUTGND DAC
where:
Similarly, the DUTGND DAC (DGS) is a 16-bit DAC and uses
a resistor string DAC to guarantee monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
what node on the string the voltage is tapped off before being
fed to the output amplifier. This function is used to program
the voltage difference needed between the DUTGND and
AGND lines before the alarm circuit flags an error.
x2 is the data-word loaded to the resistor string DAC.
x1 is the 16-bit data-word written to the DAC input register.
m is the code in the gain register (default code = 216 – 1).
n is the DAC resolution (n = 16).
c is the code in the offset register (default code = 215).
Offset and Gain Registers for the Force Amplifier DAC
The force amplifier input (FIN) DAC level contains independent
offset and gain control registers that allow the user to digitally
trim offset and gain. There is one set of registers for the force
voltage range: x1, m, and c.
The DUTGND DAC has a range of 0 V to 5 V. The transfer
function for this 16-bit DAC is shown in Equation 1.
The offset DAC does not affect the OSD DAC output range.
OFFSET DAC
Offset and Gain Registers for the Comparator DACs
In addition to the offset and gain trim, there is also a 16-bit
offset DAC that offsets the output of each DAC on chip. There-
fore, depending on headroom available, the input to the force
amplifier can be arranged either symmetrically or asymmetrically
about DUTGND but always within a voltage span of 25 V. Some
extra gain is included to allow for system error correction using
the m (gain) and c (offset) registers.
The comparator DAC levels contain independent offset and
gain control registers that allow the user to digitally trim offset
and gain. There are seven sets of registers consisting of a combi-
nation of x1, m, and c, one set each for the five internal force
current ranges and one set each for the two external high
current ranges.
Offset and Gain Registers for the Clamp DACs
The usable voltage range is −22 V to +25 V. Full scale loaded
to the offset DAC does not give a useful output voltage range
because the output amplifiers are limited by available footroom.
Table 15 shows the effect of the offset DAC on other DACs in
the device (clamp, comparator, and force DACs).
The clamp DAC levels contain independent offset and gain
control registers that allow the user to digitally trim offset
and gain. One set of registers covers the VSENSE range, the five
internal force current ranges, and the two external high current
ranges. Both clamp DAC x1 registers and their associated offset
and gain registers are 16 bit.
Rev. D | Page 40 of 68
Data Sheet
AD5560
When choosing AVDD, remember to take into account the
REFERENCE SELECTION
specified current ranges. The measure current block has either
a gain of 20 or 10 and must have sufficient headroom/
footroom to operate correctly.
The voltage applied to the VREF pin determines the output
voltage range and span applied to the force amplifier, clamp,
and comparator inputs and the current ranges.
As the nominal, VRSENSE is 0.5 V for the full-scale specified
current flowing for all ranges. If this is gained by 20, the
measure current amplifier output (internal node) voltage
range is 10 V with full-scale current and the default offset
DAC setting. The measure current block needs 2.25 V
footroom/headroom for correct operation in addition to
This device can be used with a reference input ranging from
2 V to 5 V. However, for most applications, a reference input
of 5 V is able to meet all voltage range requirements. The DAC
amplifier gain is 5.125, which gives a DAC output span of
25.625 V. The DACs have gain and offset registers that can
be used to calibrate out system errors. In addition, the gain
register can be used to reduce the DAC output range to the
desired force voltage range.
the 0.5 V VRSENSE
.
For simplicity, when VREF = 5 V, minimum |AVDD − AVSS| =
31.125 V (VREF × 5.125 + headroom + footroom); otherwise,
there can be unanticipated effects resulting from headroom/
footroom issues. This does not take into account cable loss or
DUTGND contributions.
Using a 5 V reference and setting the m (gain) register to one-
fourth scale or 0x4000 gives an output voltage span of 6.25 V.
Because the force DAC has 18 bits of resolution even with only
one-fourth of the output voltage span, it is still possible to
achieve 16-bit resolution in this 6.25 V range.
Similarly, when VREF = 2.5 V, minimum |AVDD − AVSS| = 18.3 V
and, when VREF = 2 V, minimum |AVDD − AVSS| = 16 V.
The measure current amplifier has two gain settings, 10 and 20.
The two gain settings allow users to achieve the quoted/speci-
fied current ranges with large or small voltage swings. The 20
gain setting is intended for use with a 5 V reference, and the 10
gain setting is for use with a 2.5 V reference. Both combinations
ensure the specified current ranges. Other VREF/gain setting
combinations should be used only to achieve smaller current
ranges. See Table 27 for suggested references for use with the
AD5560.
The AD5560 is designed to settle fast into large capacitive loads;
therefore, when slewing, the device draws 2× to 3× the current
range from the AVDD/AVSS supplies. When supply rails are
chosen, they should be capable of supplying each DPS channel
with sufficient current to slew.
CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS
Selection of HCAVSSx and HCAVDDx supplies is determined by
the EXTFORCE1 and EXTFORCE2 output ranges. The supply
rails chosen must take into account headroom and footroom,
DUTGND voltage range, cable loss, supply tolerance, and
CHOOSING AVDD/AVSS POWER SUPPLY RAILS
As noted in the Specifications section, the minimum supply
variation across the part is |AVDD − AVSS| ≥ 16 V and ≤ 33 V,
AVDD ≥ 8 V, and AVSS ≤ −5 V. For the AD5560 circuits to
operate correctly, the supply rails must take into account not
only the force voltage range but also the internal DAC
minimum voltage level, as well as headroom/footroom.
V
RSENSE. If diodes are used in series with the HCAVSSx and
HCAVDDx supplies pins (shown in Figure 59), the diode voltage
drop should also be factored into the supply rail calculation.
The AD5560 is designed to settle fast into large capacitive loads
in high current ranges; therefore, when slewing, the device draws
2× to 3× the current range from the HCAVSSx and HCAVDD
supplies. When choosing supply rails, ensure that they are
capable of supplying each DPS channel with sufficient current
to slew.
x
The DAC amplifier gains VREF by 5.125, and the offset DAC
centers that range about some chosen point. Because the DAC
minimum voltage (VMIN) is used in other parts of the circuit
(MEASOUT gain of 0.2), it is important that AVSS be chosen
based on the following:
All output stages of the AD5560 are symmetrical; they can
source and sink the rated current. Supply design/bypassing
should account for this.
AVSS ≤ −5.125 × (VREF × (OFFSET_DAC_CODE/216)) −
AVSS_Headroom − VDUTGND − (RCABLE × ILOAD
)
where:
POWER DISSIPATION
AVSS_Headroom is the 2.75 V headroom (includes the RSENSE
The maximum power dissipation allowed in the EXTFORCE1
stage is 10 W, whereas in the EXTFORCE2 stage, it is 5 W.
Take care to ensure that the device is adequately cooled to
remove the heat. The quiescent current is ~0.8 W with an
internal current range enabled and ~1 W with external current
ranges, EXTFORCE1 or EXTFORCE2, enabled. This device is
specified for performance up to 90°C junction temperature (TJ).
voltage drop).
V
DUTGND is the voltage range anticipated at DUTGND.
CABLE is the cable/path resistance.
LOAD is the maximum load current.
R
I
Rev. D | Page 41 of 68
AD5560
Data Sheet
calibrated and stored. The user must supply a clock to the RCLK
pin to load the new code to the DAC. The output settles in 1.2 µs
for a step of 10 mV with CDUT in the lowest range of <0.2 µF.
PACKAGE COMPOSITION AND MAXIMUM
VERTICAL FORCE
The exposed pad and leads of the TQFP package have a 100%
tin finish. The exposed paddle is connected internally to AVSS.
The simulated maximum allowable force for a single lead is
0.18 lbs; total allowable force for the package is 11.5 lbs. The
quoted maximum force may cause permanent lead bending.
Other package failure (die, mold, board) may occur first at
lower forces.
While the output is settling, the next step is calculated to be
ready for the next ramp clock. The calibration engine is used
here; therefore, there is a calibration delay of 1.2 µs.
The ramp timing is controlled in two ways: by a user-supplied
clock (RCLK) and by a clock divider register. This gives the
user much flexibility over the frequency of the ramp steps. The
ramp typically starts after (2 × clock divider + 2) clocks,
although there can be a 1 clock delay due to the asynchronous
nature of RCLK. The external clock can be a maximum of 833
kHz when using clock divider = 1. Faster RCLK speeds can be
used, but the fastest ramp rate is linked into the DAC
calibration engine.
SLEW RATE CONTROL
There are two methods of achieving different slew rates using
the AD5560. One method is using the programmable slew rate
feature that gives eight programmable rates. The second
method is using the ramp feature and an external clock.
Programmable Slew Rate
For slower ramp rates, an even slower RCLK can be used.
Eight programmable modes of slew rates are available to choose
from through the serial interface, enabling the user to choose
different rates to power up the DUT. The different slew rates
are achieved by variation in the internal compensation of the
force DAC output amplifier. The slew rates available are
1.000 V/µs, 0.875 V/µs, 0.750 V/µs, 0.625 V/µs, 0.5 V/µs,
0.4375 V/µs, 0.35V µs, and 0.313 V/µs.
The step sizes are in multiples of 16 LSBs. If the code previous
to the end code is not a multiple of this step size, the last step is
smaller. If the ramp function must be interrupted at any stage
during the ramp, write the interrupt ramp command. The FIN
DAC x1 stops ramping at the current value and returns to
normal operation.
The fastest ramp rate is 0.775 V/µs (for a 5 V reference and an
833 kHz clock using a 2032 LSB step size and divider = 1).
Ramp Function
Included in the AD5560 is a ramp function that enables the
user to apply a rising or falling voltage ramp to the DUT. The
user supplies a clock, RCLK, to control the timing.
The slowest ramp rate is 24 µV/µs (for a 5 V reference and an
833 kHz clock using a 16 LSB step size and divider = 255).
Even slower ramps can be achieved with slower SCLK. The
ramp continues until any of the following occurs:
This function is controlled via the serial interface and requires
programming of a number of registers to determine the end
value, the ramp size, and the clock divider register to determine
the update rate.
•
•
•
It reaches the end code.
An interrupt ramp is received from the user.
If any enabled alarm triggers, the ramp stops to allow
the user to service the activated alarm.
The contents of the FIN DAC x1 register are the ramp start
value. The user must load the end code register and the step
size register. The sign is now generated from the difference
between the FIN DAC x1 register and the end code; then the
step size value is added to or subtracted from FIN DAC x1,
While the device is in ramp mode, the only command that the
interface accepts is an interrupt ramp. No other commands should
be written to the device while ramping because they are ignored.
Rev. D | Page 42 of 68
Data Sheet
AD5560
NEW RAMP
YES
CHANGE
STEP SIZE?
SELECT RAMP SIZE
NO
CHANGE
CLOCK
YES
YES
PROGRAM
CLOCK DIVIDER
DIVISION?
NO
WRITE NEW
FIN ×1 DAC VALUE
CHANGE RAMP
START?
NO
WRITE RAMP END CODE
RAMP MODE
ENABLE RAMP
CALCULATE
NEXT DAC CODE
LOAD DAC
YES
UPDATE DAC
CODE?
NO
YES
DO NOT LOAD DAC.
RETAIN PREVIOUS
VALUE
INTERRUPT
RAMP?
ALARM?
NO
NO
RAMP
COMPLETE?
YES
RETURN TO
NORMAL MODE
TERMINATE RAMP
Figure 58. Flow Chart for Ramp Function
Rev. D | Page 43 of 68
AD5560
Data Sheet
SERIAL INTERFACE
BUSY FUNCTION
The AD5560 contains an SPI-compatible interface operating at
clock frequencies of up to 50 MHz. To minimize both the
power consumption of the device and on-chip digital noise, the
interface powers up fully only when the device is being written
BUSY
is a digital open-drain output that indicates the status of
BUSY
the AD5560. All writes drive the
output low for some
period of time; however, events that use the calibration engine,
such as all DAC x1 writes, drive it lower for a longer period of
time while the calculations are completed.
SYNC
to, that is, on the falling edge of
.
SPI INTERFACE
For the DACs, the value of the internal data (x2) loaded to the
DAC data register is calculated each time the user writes new
data to the corresponding x1 register. During the calculation
The serial interface is 2.5 V LVTTL-compatible when operating
from a 2.3 V to 3.6 V DVCC supply. It is controlled by the
following four pins:
BUSY
of x2, the
output goes low and x2 writes are pipelined;
SYNC
•
•
•
•
(frame synchronization input)
therefore, x2 writes can still be presented to the device while
SDI (serial data input pin)
SCLK (clocks data in and out of the device)
SDO (serial data output pin for data readback)
BUSY
is still low (see the Register Update Rates section). The
BUSY
DAC outputs update immediately after
goes high.
Writes to other registers must be handled differently and
BUSY BUSY
SPI WRITE MODE
should either watch the
pin or be timed. While
The AD5560 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which
is all registers except the DAC registers.
is low, the user can continue writing new data to any control
register, m register, or c register but should not complete the
SYNC
BUSY
writing process (
has returned high.
returning high) until the
signal
The serial word is 24 bits long. The serial interface works with
both a continuous and a burst (gated) serial clock. Serial data
applied to SDI is clocked into the AD5560 by clock pulses applied
BUSY
also goes low during power-on reset, as well as when a
RESET
low level is detected on the
pin.
SYNC
to SCLK. The first falling edge of
At least 24 falling clock edges must be applied to SCLK to clock
SYNC
starts the write cycle.
BUSY
writes to the system control register, compensation
register, alarm register, and diagnostic register; m or c registers
do not involve the calibration engine, thus speeding up writing
to the device.
in 24 bits of data before
The input register addressed is updated on the rising edge of
SYNC SYNC
is taken high again.
. For another serial transfer to take place,
must be
LOAD FUNCTION
taken low again.
The AD5560 device contains a function with which updates
SDO OUTPUT
LOAD
to multiple devices can be synchronized using the
function. There is not a dedicated pin available for this
HW_INH
The SDO output in the AD5560 is a weak/slow output driver.
If using readback or the daisy-chain function, the frequency of
SCLK must be reduced so that SDO can operate properly. The
SCLK frequency is dependent on the DVCC supply voltage used;
see Table 2 for details and the following example:
function; however, either the CLEN or
pin can
input (selection is made in the system
control register, Address 0x1, Bits[8:7]).
LOAD
LOAD
be used as a
When selected as the
operates in its previous function (power-on default for each
HW_INH
function, the pin no longer
Maximum SCLK = 12 MHz, then DVCC = 2.3 V to 2.7 V
Maximum SCLK = 15 MHz, then DVCC = 2.7 V to 3.3 V
Maximum SCLK = 20 MHz, then DVCC = 4.5 V to 5.5 V
RESET FUNCTION
of these pins is a CLEN or
function).
LOAD
The
function controls the following registers:
•
•
•
•
•
•
0x8 FIN DAC x2 register
0xD CLL DAC x2 register
0x10 CLH DAC x2 register
0x4 Compensation Register 1
0x5 Compensation Register2
0x2 DPS Register1 (only current ranges, Bits[13:11])
RESET
RESET
is a level-sensitive input. Bringing the
resets the contents of all internal registers to their power-on
RESET
line low
reset state. The falling edge of
initiates the reset process;
goes low for the duration, returning high when the
RESET
BUSY
process is complete. This sequence takes 300 µs
BUSY
BUSY
returns high,
maximum. Do not write to the serial interface while
There is, however, an alternate method for updating and using
HW_INH
RESET
is low handling a
command. When
the CLEN and
pins in their normal function.
RESET
normal operation resumes, and the status of the
ignored until it goes low again.
pin is
Rev. D | Page 44 of 68
Data Sheet
AD5560
If Bits[8:7] of the system control register (Address 0x1) are
corresponding x1 register. The calculation is performed by a
HW_INH
three stage process. The first two stages take 600 ns each, and
the third stage takes 300 ns. When the write to one of the x1
registers is complete, the calculation process begins. The user
is free to write to another register provided that the write
operation does not finish until the first stage calculation is
complete, that is, 600 ns after the completion of the first write
operation.
high, then the CLEN and
BUSY
operate as normal, and the
goes high (this way multiple channels
update waits until
BUSY
can still be synchronized by simply tying
pins together).
REGISTER UPDATE RATES
As mentioned previously, the value of the x2 register is
calculated each time the user writes new data to the
Rev. D | Page 45 of 68
AD5560
Data Sheet
CONTROL REGISTERS
A no operation (NOP) command performs no function within
the device. This code may be useful when performing a
readback function where a change of DAC or DPS register is
not required.
DPS AND DAC ADDRESSING
The serial word assignment consists of 24 bits, as shown in
Table 16. All write-to registers can be read back. There are
some read-only registers (Address 0x43 and Address 0x44).
DAC x2 registers are not available for readback.
Table 16. Serial Word Assignment
B23
[B22:B16]
[B15:B0]
R/W
Address bits
Data bits
Table 17. Read or Write Register Addressing
Address Register
Default
0x0000
0x0000
Data Bits, MSB First
0x0
0x1
NOP
NOP command; performs no operation.
System
control
register
Bit Name
Function
15 TMP[1:0]
14
Thermal shutdown bits. TMP1, TMP0 allow the user to program the thermal
shutdown temperature of operation.
TMP
Action
0
1
2
3
Shutdown at a TJ of 130°C (power-on default)
Shutdown at a TJ of 120°C
Shutdown at a TJ of 110°C
Shutdown at a TJ of 100°C
13 Gain[1:0] MEASOUT output range. The MEASOUT range defaults to the voltage force span for
voltage and current measurements (this is 12.81 V), which includes some overrange
to allow for error correction. The MEASOUT range can be reduced by using the gain
bits. This allows for use of asymmetrical supplies or for use of a smaller input range ADC.
12
MEASOUT gain settings do not translate the low voltage temperature sensor signal
(TSENSE).
Gain
MEASOUT Gain
MI Gain
20
0
1
2
3
1
1
10
0.2
0.2
20
10
To allow for system error correction, there is an additional gain of 0.125 for the force
function if this error correction is used as intended; then the output range on
MEASOUT scales accordingly (see Table 9).
11 FINGND
10 CPO
Writing a 1 to FINGND switches the positive input of the force amplifier to GND; when
0, the input of the force amplifier is connected to the output of the force DAC.
Write a 1 to the CPO bit to enable a simple window comparator function. In this
mode, only one comparator output is available (CPOH/CPO). This provides two bits of
information. The compared value is either inside or outside the window and enables
the user to bring only one line back to the controller per DPS device.
9
PD
This bit powers down the force amplifier block. Note that the amplifier must be
powered up but inhibited (SW-INH or HW_INH), to meet leakage specifications. A 0
powers this block down (default).
8
7
LOAD
Updates to registers listed in the following LOAD function column do not occur until
the active LOAD pin is brought low (or in the case of LOAD 3, until BUSY goes high).
Function
LOAD
LOAD
0
1
2
3
Default operation, CLEN and HW_INH function normally.
The CLEN pin is a LOAD input.
The HW_INH pin is a LOAD input.
The device senses the BUSY open-drain pin and doesn't update until that
goes high. No LOAD hardware pin. CLEN and HW_INH function normally.
6:0 Unused
Set to 0.
Rev. D | Page 46 of 68
Data Sheet
AD5560
Table 18. DPS Register 1
Address Default
Data Bits, MSB First
0x2
0x0000
Bit Name
Function
15
This bit enables the force amplifier when high and disables the amplifier when low. This bit is AND’d with the
HW_INH hardware inhibit pin.
SW-INH
14
13
12
11
Reserved Reserved, set to 0.
I[2:0] Current range addressing. These bits allow selection of the required current range.
I
Action
0
1
2
3
4
5
6
7
5 µA current range.
25 µA current range.
250 µA current range.
2.5 mA current range.
25 mA current range.
External Range 2.
External Range 1.
Reserved.
10
9
CMP[1:0] Comparator function. CMP1 acts as a comparator output enable, whereas CMP0 selects between a
comparing DUT current or voltage; by default, the comparators are high-Z on power-on.
CMP
Action
0
1
2
3
Comparator outputs high-Z.
Comparator outputs high-Z.
Compare DUT current.
Compare DUT voltage.
8
7
6
5
ME[3:0]
Bits ME[3:0] allow selection of the required measure mode, allowing the MEASOUT line to be disabled;
connect to the temperature sensor or enable it for measurement. ME3 is MEASOUT enable/disable; when
high, MEASOUT is enabled, and ME[2:0] can be used to preselect the measuring parameter. Where a
number of MEASOUT lines are connected together and passed to a common ADC, this function can allow
for much faster measurement time between channels because the slew time of the measurement buffer is
reduced. For details on diagnostic functions, see Address 0x7, the diagnostic register.
ME[2:0]
Action
0
1
2
3
4
5
6
7
MEASOUT high-Z.
Connect MEASOUT to ISENSE.
Connect MEASOUT to VSENSE.
Connect MEASOUT to KSENSE.
Connect MEASOUT to TSENSE.
Connect MEASOUT to DUTGND SENSE.
Connect MEASOUT to diagnostic functions: DIAG A (see Address 0x7).
Connect MEASOUT to diagnostic functions: DIAG B (see Address 0x7).
4
CLEN
Clamp enable; set high to enable the clamp; set low to disable the clamp. This bit is OR’d with the
hardware CLEN pin.
3:0 Unused
Set to 0.
Rev. D | Page 47 of 68
AD5560
Data Sheet
Table 19. DPS Register 2
Address Default
Data Bits, MSB First
0x3
0x0000
Bit Name
Function
15 SF0
System force and sense line addressing, SF0. Bit SF0 addresses each of the different
combinations of switching the system force and sense lines to the force and sense pins at the
DUT.
Guard High-Z
(Bit 7)
SFO
SYS_SENSE Pin SYS_FORCE Pin GUARD/SYS_DUTGND Pin
0
0
1
1
0
1
0
1
Open
Sense
Open
Sense
Open
Force
Open
Force
Guard
Guard
Open
DUTGND
14 SR[2:0]
Slew rate control, SR2, SR1, SR0. Selects the slew rate for the main DAC output amp.
13
12
SR
0
Action
1 V/μs
1
0.875 V/μs
0.75 V/μs
0.62 V/μs
0.5 V/μs
2
3
4
5
0.43 V/μs
0.35 V/μs
0.3125 V/μs
6
7
11 GPO
General purpose output bit. The GPO bit can be used for any function, such as disconnecting
the decoupling capacitor to help speed up low current testing.
10 SLAVE,
Ganging multiple devices increases the current drive available. Use these bits to enable
selection of the ganging mode and place the device in slave or master mode. In default
operation, each device is a master (gang of one). Figure 54 shows how the device is configured
in this mode.
GANGIMODE
9
SLAVE
Action
0
Master: MASTER_OUT = internally connects to active EXTFORCE1/
EXTFORCE2 output
1
2
Master: MASTER_OUT = master MI
SLAVE FV to EXTFORCE1/EXTFORCE2 connected internally to close the
FVAMP loop
3
SLAVE FI
8
INT10K
Setting this bit high allows the user to connect an internal sense short resistor of 10 kΩ
between the force and the sense lines (closes SW11). This resistor is actually made up of series
4 kΩ resistors followed by a 2 kΩ switch and another 4 kΩ resistor. There is a 10 kΩ resistor that
can be connected between the FORCE and SENSE pins by use of SW11. This 10 kΩ resistor is
intended to maintain a force/sense connection when a DUT is not in place. It is not intended
to be connected when measurements are being made because this defeats the purpose of the
OSD circuit in identifying an open circuit between FORCE and SENSE. In addition, the sense
path has a 2.5 kΩ resistor in series; therefore, if the 10 kΩ switch is closed, errors may become
apparent when in high current ranges.
7
Guard high-Z
Set this bit high to high-Z the guard amplifier. This is required if using the GUARD/
SYS_DUTGND pin in the SYS_DUTGND function.
6:0 Unused
Set to 0.
Rev. D | Page 48 of 68
Data Sheet
AD5560
SAFEMODE
The AD5560 has three compensation modes. The power-on default mode is
enabled. This ensures that the device is stable
into any load. Use Compensation Register 1 to configure the device for autocompensation, where the user inputs the CDUT and ESR
bits, and the AD5560 chooses the most appropriate compensation scheme for these load conditions.
Table 20. Compensation Register 1
Address Default
Data Bits, MSB First
0x4 0x0000
Bit Name
Function
15
14
13
12
CDUT[3:0]
Use these control bits to tell the device how much capacitive load there is so that the device can
optimize the compensation used. Do not overestimate CDUT because this can cause oscillations.
Underestimating CDUT gives suboptimal but stable performance.
CDUT
0
CDUT Min
0 nF
CDUT Max
50 nF
1
50 nF
83 nF
2
83 nF
138 nF
229 nF
380 nF
630 nF
1.1 µF
1.7 µF
2.9 µF
4.8 µF
7.9 µF
13 µF
3
138 nF
229 nF
380 nF
630 nF
1.1 µF
1.7 µF
2.9 µF
4.8 µF
7.9 µF
13 µF
4
5
6
7
8
9
10
11
12
13
14
15
22 µF
22 µF
36 µF
36 µF
60 µF
60 µF
160 µF
11
10
9
ESR[3:0]
Use these control bits to tell the device how much ESR there is in series with CDUT so that the device can
optimize the compensation used. Do not underestimate ESR because this can cause oscillations.
Overestimating ESR gives suboptimal but stable performance.
8
ESR
ESR Min
0 mΩ
ESR Max
1 mΩ
0
1
1 mΩ
1.8 mΩ
3.4 mΩ
6.3 mΩ
12 mΩ
2
1.8 mΩ
3.4 mΩ
6.3 mΩ
12 mΩ
3
4
5
21 mΩ
6
21 mΩ
40 mΩ
7
40 mΩ
74 mΩ
8
74 mΩ
140 mΩ
250 mΩ
460 mΩ
860 mΩ
1500 mΩ
2900 mΩ
5400 mΩ
10,000 mΩ
9
140 mΩ
250 mΩ
460 mΩ
860 mΩ
1500 mΩ
2900 mΩ
6400 mΩ
10
11
12
13
14
15
7
SAFEMODE
SAFEMODE
= 0 overrides values in Compensation Register 1 to make the force amplifier stable under
most load conditions. This mode is useful if it is unknown what the DPS is driving, but it does result in an
extremely slow response. The default operation on power-on or reset is SAFEMODE.
SAFEMODE settings are always gm[1:0] = 2, RP[2:0] = 0, RZ[2:0] = 0, CC[3:1] = 111, CF[2:0] = 5, and CC0 = 1.
Set this bit high to enable autocompensation.
6:0 Reserved
Set to 0.
Rev. D | Page 49 of 68
AD5560
Data Sheet
Table 21. Compensation Register 2
Address Default
Data Bits, MSB First
0x5
0x0110
Bit Name
Function
15
Manual
compensation
The AD5560 can be manually configured to compensate the force amplifier into a wide range of load
conditions. When this bit is high, manual compensation mode is active, and it overrides the settings of
Compensation Register 1. Readback when in manual compensation mode returns the compensation
settings loaded to the force amplifier and loaded to this register. Similarly, when in autocompensation
mode, readback of this register address returns the compensation settings of the force amplifier. However,
SAFEMODE
SAFEMODE
settings.
readback of this register address when in safe mode does not reflect
settings are gm[1:0] = 2, RP[2:0] = 0, RZ[2:0] = 0, CC[3:1] = 111, CF[2:0] = 5, and CC0 = 1.
Set the value of RZ to add a zero at the following frequencies. This calculation assumes that CC0 = 100 pF.
14
13
12
RZ[2:0]
RZ
01
1
RZx(Ω)
500
FZ (Hz)
3.2 M
1 M
1.6 k
5 k
2
320 k
100 k
32 k
3
16 k
4
50 k
5
160 k
500 k
1.6 M
10 k
6
3.2 k
1 k
7
11
10
9
RP[2:0]
Set the value of RP to add an additional pole. There is an internal 8 pF capacitor to provide an RC filter,
creating a pole at one of the following frequencies.
RP[2:0]
RP (Ω)
200
FP (Hz)
100 M
29 M
8.7 M
2.6 M
760 k
220 k
67 k
01
1
2
3
4
5
6
7
675
2280
7700
26 k
88 k
296 k
1 M
20 k
8
7
gm[1:0]
Set the transconductance of the force amplifiers input stage. The gain bandwidth (GBW) of the force
voltage loop is equal to gmx/CC0. The following values assume CC0 = 100 pF.
gmx
0
gmx (µA/V)
40
GBW (Hz)
64 k
1
80
130 k
21
300
480 k (default)
1.3 M
3
900
6
5
4
CF[2:0]
These bits determine which feedforward capacitor CFx is switched in.
CFx
Action
None
CF0
0
1
2
CF1
3
CF2
4
CF3
51
CF4
6
None
None
7
Connect CC3 in series with 100 kΩ1
Connect CC2 in series with 25 kΩ1
Connect CC1 in series with 6 kΩ1
0
3
2
1
0
CC3
CC2
CC1
Reserved
1
SAFEMODE
SAFEMODE
setting (
This item corresponds to a
is the power-on default setting).
Rev. D | Page 50 of 68
Data Sheet
AD5560
Register 0x6 allows the user to enable or disable any of the alarm flags that are not required. If disabled, that particular alarm no longer
flags on the appropriate open-drain pin; however, the alarm status is still available in both of the alarm status registers (Address 0x43 and
Address 0x44).
Table 22. Alarm Setup Register
Address Default Data Bits, MSB First
0x6
0x0000
Bit Name
Function
15 Latched
TMPALM
Set this latched bit high to program the open-drain TMPALM alarm pin as a latched output;
leave low for an unlatched alarm pin (default).
14 Disable
TMPALM
Set this bit high to disable the open-drain TMPALM alarm pin; leave low to leave enabled (default).
13 Latched
OSALM
Set this latched bit high to program the OSALM as a latched alarm on the open-drain KELALM
pin; leave low for an unlatched alarm pin (default).
12 Disable
OSALM
Set this bit high to disable the OSALM alarm function flagging the open-drain KELALM pin;
leave low to remain enabled (default). The disable GRDALM, DUTALM, and OSALM alarm
functions share one open-drain KELALM alarm pin. These bits allow users to choose if they wish
to have all or selected information flagged to the alarm pin.
11 Latched
DUTALM
Set this latched bit high to program the DUTALM as a latched alarm on the open-drain KELALM
pin; leave low for an unlatched alarm pin (default).
10 Disable
DUTALM
Set this bit high to disable the DUTALM alarm function flagging the open-drain KELALM pin.
Leave low to leave enabled (default). The disable GRDALM, DUTALM, and OSALM alarm
functions share one open drain KELALM alarm pin. These bits allow users to choose if they wish
to have all or any information flagged to the alarm pin. The DUTGND pin has a 50 µA pull-up to
allow for detection of an error in the DUTGND path. Setting this bit high also disables the 50 µA
pull-up.
9
8
7
6
Latched
CLALM
Set this latched bit high to program the open-drain CLALM clamp alarm pin as a latched
output; leave low for an unlatched alarm pin (default).
Disable
CLALM
Set this bit high to disable the open drain CLALM alarm pin; leave low to leave enabled (default).
Latched
GRDALM
Set this latched bit high to program the GRDALM as a latched alarm on the open-drain KELALM
pin; leave low for an unlatched alarm pin (default).
Disable
GRDALM
Set this bit high to disable the GRDALM alarm function flagging the open-drain KELALM pin;
leave low to leave enabled (default). The disable GRDALM, DUTALM and OSALM alarm functions
share one open-drain KELALM alarm pin. These bits allow users to choose if they wish to have
all or any information flagged to the KELALM alarm pin.
5:0 Unused
Set to 0.
Rev. D | Page 51 of 68
AD5560
Data Sheet
Table 23. Diagnostic Register
Address
Default
Data Bits, MSB First
0x7
0x0000
Bit
Name
Function
DIAG select selects the set of diagnostic signals that can be made available on MEASOUT. First, use MEASOUT
15
14
13
12
DIAG
select[3:0] addressing (DPS Register 1) to select either the DIAG A or the DIAG B node to be made available on MEASOUT.
Selected
DIAG Select
Measure Block
DIAG A
DIAG B
0:3
4
Disabled
Disabled
Disabled
Force amplifier
Disabled
Disabled
5
6
EXTFORCE1A
FINP
EXTFORCE2A
FINM
7
Output 2.5 mA
VPTAT low
VTSD low (ref V
for −273°C)
Output 25 mA
VPTAT high
VTSD high (ref V for +130°C)
8
9
Measure block
DAC block
10
11
12
13
14
15
MI
MV
VMID Code
VMIN Code
VOS DAC
CLH DAC
CPH DAC
DGS DAC
FORCE DAC
CLL DAC
CPL DAC
OSD DAC
VPTAT low/VPTAT high are temperature sensor devices in the middle of the enabled power stage, which gives a
voltage level that can be mapped back to the VTSD low and VTSD high reference points to get a temperature
value. These sensors are used in the thermal shutdown feature. See the Die Temperature Sensor and
Thermal Shutdown section.
VMID code is the midscale voltage of the DACs; the offset DAC has a direct effect on this voltage level.
VMIN code is the zero-scale voltage of the DACs; again the offset DAC has a direct effect.
11
10
9
8
7
TSENSE
The following codes allow selection of one of three sets of eight thermal diodes. The D+ of the selected thermal
select[3:0] diode is available on the GPO pin; the D− is on the AGND.
These thermal diodes are located across the die, in the cool parts and in the power stages. Diodes [16:23] are located
in the force amplifier NPNs (power output devices for supplying current). Similarly, Diodes [24:31] are located in
the force amplifier PNP devices (output devices for sinking current).
Selected
TSENSE Select
Thermal Block
Connected Sensor
0:7
N/A—normal
No sensor connected
GPO operation
8
Cool block
Cool end of high current drivers, hot side of digital
block
9
25 mA output stage
10
Hottest part of sensitive measurement circuitry
and cool part of force amplifier
11
12
13
14
15
16
17
18
Coolest end of force amplifier block
Coolest end of DACs
Beside TSENSE available on MEASOUT
Hottest part of DACs
Cool side of digital block
1A-1
Force amplifier
PNPs
1A-2
2A (similar location to VPTAT low for EXTFORCE2
range)
19
1B-1 (similar location to VPTAT low for EXTFORCE1
range)
20
21
22
23
1B-2
2B
1C-1
1C-2
Rev. D | Page 52 of 68
Data Sheet
AD5560
Address
Default
Data Bits, MSB First
0x7
0x0000
Bit
Name
Function
24
25
26
Force amplifier
NPNs
1A-1
1A-2
2A (similar location to VPTAT high for EXTFORCE2
range)
27
1B-1 (similar location to VPTAT high for EXTFORCE1
range)
28
29
30
31
1B-2
2B
1C-1
1C-2
6
5
Test Force These register bits allow disabling of stages of the force amplifier. They can be used to ensure connectivity in
AMP[1:0]
each parallel stage. The enabled stage depends also on which current range is selected.
Test Force
Current Range
EXTFORCE1
EXTFORCE1
EXTFORCE1
EXTFORCE1
EXTFORCE2
EXTFORCE2
EXTFORCE2
EXTFORCE2
Set to 0.
Amplifier
Enabled Stage
All stages
EXTFORCE1C
EXTFORCE1B
EXTFORCE1A
All stages
Reserved
EXTFORCE2B
EXTFORCE2A
0
1
2
3
0
1
2
3
4:0
Reserved
Rev. D | Page 53 of 68
AD5560
Data Sheet
Table 24. Other Registers
Address
Register
Default
0x8000
0xFFFF
0x8000
0x8000
0x1FFF
0x0000
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0xFFFF
0xFFFF
Data Bits, MSB First
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
FIN DAC x1
FIN DAC m
FIN DAC c
Offset DAC x
OSD DAC x
CLL DAC x1
CLL DAC m
CLL DAC c
x1 DAC register; D15 to D0, MSB first.
m register; D15 to D0, MSB first.
c register; D15 to D0, MSB first.
D15 to D0.
D15 to D0.
D15 to D0; the low clamp level can only be negative; the MSB is always 0 to ensure this.
D15 to D0.
D15 to D0.
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
CLH DAC x1
CLH DAC m
CLH DAC c
D15 to D0; the high clamp level can only be positive; the MSB is always 1 to ensure this.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
CPL DAC x1 5 μA range
CPL DAC m 5 μA range
CPL DAC c 5 μA range
CPL DAC x1 25 μA range
CPL DAC m 25 μA range
CPL DAC c 25 μA range
CPL DAC x1 250 μA range
CPL DAC m 250 μA range
CPL DAC c 250 μA range
CPL DAC x1 2.5 mA range
CPL DAC m 2.5 mA range
CPL DAC c 2.5 mA range
CPL DAC x1 25 mA range
CPL DAC m 25 mA range
CPL DAC c 25 mA range
CPL DAC x1 EXT Range 2
CPL DAC m EXT Range 2
CPL DAC c EXT Range 2
CPL DAC x1 EXT Range 1
CPL DAC m EXT Range 1
CPL DAC c EXT Range 1
CPH DAC x 1 5 μA range
CPH DAC m 5 μA range
CPH DAC c 5 μA range
CPH DAC x1 25 μA range
CPH DAC m 25 mA range
CPH DAC c 25 μA range
CPH DAC x1 250 μA range
CPH DAC m 250 μA range
CPH DAC c 250 μA range
CPH DAC x1 2.5 mA range
CPH DAC m 2.5 mA range
CPH DAC c 2.5 mA range
CPH DAC x1 25 mA range
CPH DAC m 25 mA range
CPH DAC c 25 mA range
CPH DAC x1 EXT Range 2
CPH DAC m EXT Range 2
CPH DAC c EXT Range 2
CPH DAC x1 EXT Range 1
CPH DAC m EXT Range 1
Rev. D | Page 54 of 68
Data Sheet
AD5560
Address
0x3C
0x3D
Register
Default
0x8000
0x3333
0x0000
Data Bits, MSB First
CPH DAC c EXT Range 1
DGS DAC
Ramp end code
D15 to D0.
D15 to D0 DUTGND SENSE DAC, 0 V to 5 V range.
D15 to D0; this is the ramp end code. The ramp start code is the code that is in the FIN
DAC register.
0x3E
0x3F
Ramp step size
0x0001
0000 0000 D6 to D0.
D6:D0 set the ramp step size in increments of 16 LSB per code, with a 5 V reference,
16 LSB = 6.1 mV.
For example,
000 0000 = 16 LSBs (6.1 mV) step
000 0001 = 16 LSBs (6.1 mV) step
…
111 1111 = 2032 LSBs (775 mV) step.
0x40
RCLK divider
0x0001
0000 0000 D7 to D0.
D7:D0 set the RCLK divider.
0000 0000 = ÷ 1
0000 0001 = ÷ 1
0000 0010 = ÷ 2
0000 0011 = ÷ 3
…
1111 1111 = ÷ 255
0xFFFF to enable.
0x0000 to interrupt.
0x41
0x42
Enable ramp
Interrupt ramp
0x0000
0x0000
Rev. D | Page 55 of 68
AD5560
Data Sheet
Table 25. Alarm Status and Clear Alarm Status Register
Address
Register
Default
Data Bits, MSB first
0x43
Alarm status
0x0000
This register is a read-only register providing information on the status of the alarm functions and
the comparator outputs.
Bit
Name
Function
15
Latched temperature alarm bit; if low, this bit indicates that an alarm event has
occurred.
LTMPALM
14
13
12
11
10
Unlatched alarm bit; if low, these bit indicates that an alarm event is still
present.
Latched open-sense alarm bit; if low, indicates that an alarm event has
occurred.
Unlatched open-sense alarm bit; if low, indicates that an alarm event is still
present.
Latched DUTGND Kelvin sense alarm; if low, indicates that an alarm event has
occurred.
TMPALM
LOSALM
OSALM
LDUTALM
DUTALM
Unlatched DUTGND Kelvin sense alarm; if low, indicates that an alarm event is still
present.
9
Latched clamp alarm; if low, indicates that an alarm event has occurred.
Unlatched clamp alarm; if low, indicates that an alarm event is still present.
Latched guard alarm; if low, indicates that an alarm event has occurred.
Unlatched guard alarm; if low, indicates that an alarm event is still present.
Comparator output low condition as per the comparator output pin.
Comparator output high condition as per the comparator output pin.
Must be zeros.
LCLALM
CLALM
LGRDALM
GRDALM
CPOL
8
7
6
5
4
3:0
CPOH
Unused
0x44
Alarm status
and clear alarm
0x0000
This register is a read-only register providing information on the status of the alarm functions and
the comparator outputs. Reading this register also automatically clears any latched alarm pins or bits.
Bit
Name
Function
15
Latched temperature alarm bit; if low, this bit indicates that an alarm event has
occurred.
LTMPALM
14
13
12
11
10
Unlatched alarm bit; if low, these bit indicates that an alarm event is still
present.
Latched open-sense alarm bit; if low, indicates that an alarm event has
occurred.
Unlatched open-sense alarm bit; if low, indicates that an alarm event is still
present.
Latched DUTGND Kelvin sense alarm; if low, indicates that an alarm event has
occurred.
TMPALM
LOSALM
OSALM
LDUTALM
DUTALM
Unlatched DUTGND Kelvin sense alarm; if low, indicates that an alarm event is still
present.
9
Latched clamp alarm; if low, indicates that an alarm event has occurred.
Unlatched clamp alarm; if low, indicates that an alarm event is still present.
Latched guard alarm; if low, indicates that an alarm event has occurred.
Unlatched guard alarm; if low, indicates that an alarm event is still present.
Comparator output low condition as per the comparator output pin.
Comparator output high condition as per the comparator output pin.
Must be zeros.
LCLALM
CLALM
LGRDALM
GRDALM
CPOL
8
7
6
5
4
3:0
CPOH
Unused
0x45
0x46
0x47
0x48
0x49
0x4A
CPL DAC x1
CPL DAC m
CPL DAC c
CPH DAC x1
CPH DAC m
CPH DAC c
Reserved
0x0000
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
Reserved.
0x4B to
0x7F
Rev. D | Page 56 of 68
Data Sheet
AD5560
READBACK MODE
DAC READBACK
The AD5560 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the DAC register (x2 calibrated register). To
read back contents of a register, it is necessary to write a 1 to
The DAC x1, DAC m, and DAC c registers are available to read
back via the serial interface. Access to the calibrated x2 register
is not available.
POWER-ON DEFAULT
W
the R/ bit, address the appropriate register, and fill the data
During power-on, the power-on state machine resets all internal
bits with all zeros.
BUSY
registers to their default values, and
goes low. A rising
indicates that the power-on event is complete
After the write command has been written, data from the
selected register is loaded to the internal shift register and is
available on the SDO pin during the next SPI operation.
BUSY
edge on
RESET
and that the interface is enabled. The
function in the power-on event.
pin has no
Address 0x43 and Address 0x44 are the only registers that are
read only. The read function gives the user details of the alarm
status and the comparator output result.
During power-on, all DAC x1 registers corresponding to 0 V
are cleared; the calibration register default corresponds to m at
full scale and to c at zero scale.
Alarm flags on latched alarm pins (Pin 1, Pin 2, Pin 3) and bits
are cleared after a read command of Register 0x44 (alarm status
and clear alarm register (see Table 25)).
The default conditions of the DPS and the system control
registers are as shown in the relevant tables (see Table 17
through Table 26).
SCLK frequency for readback does not operate at the full speed
of the SPI interface. See the Timing Characteristics section for
further details.
RESET
During a
default.
function, all registers are reset to the power-on
Rev. D | Page 57 of 68
AD5560
Data Sheet
Table 26. AD5560 Truth Table of Switches1
Reg
Bit Name
Bit
SW1 SW2 SW3 SW4 SW7 SW13 SW14 SW15 SW5 SW6 SW8 SW9 SW11 SW16
System
Control
Register
Gain0,
Gain1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FINGND
0
1
B
A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CPO
PD2, 3
X
On
DPS Register 1
04
X
X
X
c
a
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SW-INH2
15
I2, I1, I0
000
On
On
Off
Off
Off
001
010
011
100
101
110
00
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b
b
c
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
a
X
X
X
X
X
X
X
X
a
On
On
On
On
Off
Off
X
On
On
On
On
Off
Off
X
Off
Off
Off
Off
Off
On
X
Off
Off
Off
Off
On
Off
X
Off
Off
Off
Off
On
On
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
a
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CMP1, CMP0
X
X
X
X
01
X
X
X
X
X
X
X
X
X
10
X
X
X
X
X
X
X
X
X
11
b
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ME3, ME2,
ME1, ME0
000
001
010
011
100
101
110
111
0
X
X
X
X
X
X
X
X
Off
On
On
On
On
On
On
On
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DPS Register 2 SF0
X
X
X
X
X
X
Off
On
X
Off
On
X
1
X
X
X
X
X
X
X
Slave,
GANGIMODE
006
017
108
X
X
X
X
X
Off
Off
On
X
a
X
X
X
X
X
b
Off
X
X
X
c
X
X
X
X
X
X
X
X
119
c
b
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Off
X
On
X
X
X
X
X
X
X
X
X
X
X
INT10K
0
X
X
Off
On
1
X
X
Hardware Pins HW_INH2
CLEN
X
X
c
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1 X = don’t care; the switch is unaffected by the particular bit condition.
2 Active low.
3 Power-down mode; used for low power consumption.
4 Force amplifier outputs tristate, low leakage mode; feedback made around amplifier.
5 FV mode.
6 Master: MASTER_OUT = internally connects to active EXTFORCE1/EXTFORCE2/25 mA output.
7 Master: MASTER_OUT = master MI.
8 Slave FV: EXTFORCE1/EXTFORCE2/25 mA connected internally to close the FVAMP loop.
9 Slave FI.
Rev. D | Page 58 of 68
Data Sheet
AD5560
internal pull-up resistors between the supplies (see Figure 59).
Using diodes here allows a more flexible use of supplies and
can minimize the amount of supply switching required. In the
example, the AVDD and AVSS supplies can support the high
voltage needs, whereas the HCAVDDx and HCAVSSx supplies
support the low voltage, higher current ranges. Diode selection
should take into account the current carrying requirements.
Supply selection for HCAVDDx and HCAVSSx supplies must
allow for this extra voltage drop.
USING THE HCAVDDx AND HCAVSSx SUPPLIES
The first set of power supplies, AVDD and AVSS, provide power
to the DAC levels and associated circuitry. They also supply the
force amplifier stage for the low current ranges (ranges using
internal sense resistors up to 25 mA maximum).
The second set of power supplies, HCAVSS1 and HCAVDD1,
are intended to be used to minimize power consumption in
the AD5560 device for the EXTFORCE1 range (up to 1.2 A).
Similarly, the HCAVSS2 and HCAVDD2 supplies are used for the
EXTFORCE2 range (up to 500 mA). These supplies must be
less than or equal to the AVDD and AVSS supplies. When driving
high currents at low voltages, power can be greatly minimized
by ensuring that the supplies are at the lowest voltages.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5560, it is important
that the AGND and DGND pins be connected to the relevant
ground plane before the positive or negative supplies are applied.
In most applications, this is not an issue because the ground
pins for the power supplies are connected to the ground pins of
the AD5560 via ground planes. The AVDD and AVSS supplies
must be applied to the device either before or at the same time
as the HCAVDDx and HCAVSSx supplies, as indicated in Table 3.
There are no known supply sequences surrounding the DVCC
supply, although it is recommended that it be applied as
indicated by the absolute maximum ratings (see Table 3).
Therefore, HCAVSSx and HCAVDDx can be switched externally
to different power rails as required by the set voltage range.
However, the design of the high current output stage means
that these supplies always have to be at a higher voltage than
the forced voltage, irrespective of the current range being used.
Therefore, depending on the level of supply switching, external
diodes may be required in series with each of the HCAVDDx
and HCAVSSx supplies, as shown in Figure 59. There are
AV = –5V
SS
HCAV 2 = –5V
SS
HCAV 1 = –5V
SS
AV
= +28V
10µF
HCAV 2 = +9V
DD
HCAV 1 = +6V
DD
DD
DV
= 3V/5V
0.1µF
CC
10µF
10µF
10µF
10µF
10µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
100kΩ
33kΩ
100kΩ
33kΩ
3. MIDCURRENT
RANGE
ALLOW ±0.5V
FOR EXT R
500mA
RANGE
SENSE
EXTFORCE2
DUT RANGE
0V TO +6V
2. HIGHEST CURRENT
RANGE
OUTPUT RANGE
–0.2V TO +6.5V
1200mA
RANGE
ALLOW ±0.5V FOR EXT R
SENSE
EXTFORCE1
DUT RANGE
–2V TO +3V
OUTPUT RANGE
–2.5V TO +3.5V
1. LOW CURRENT,
HIGH VOLTAGE
INTERNAL RANGE SELECT
(5µA, 25µA, 250µA, 2.5mA, 25mA)
FORCE
DUT RANGE
0V TO +25V
OUTPUT RANGE
0V TO +25V
INTERNAL R
SENSE
±0.5V AT FULL CURRENT
AD5560
Figure 59. Example of Using the Extra Supply Rails Within the AD5560 to Achieve Multiple Voltage/Current Ranges
Rev. D | Page 59 of 68
AD5560
Data Sheet
five feedforward capacitor input pins, all capacitor inputs may
be used only if the user intends to drive large variations of DUT
load capacitances. If the DUT load capacitance is known and
doesn’t change for all combinations of voltage ranges and test
conditions, then it is possible only one set of CCx and CFx is
required.
REQUIRED EXTERNAL COMPONENTS
The minimum required external components are shown in the
block diagram in Figure 60. Decoupling is very dependent on
the type of supplies used, the board layout, and the noise in the
system. It is possible that less decoupling may be required as a
result. Although there are four compensation input pins and
HCAV
SS2
AV
HCAV
SS
SS1
AV
HCAV
DD
HCAV
DD2
DD1
SHARED
REFERENCE
10µF
10µF
10µF
10µF
10µF
10µF
REF
DV
DV
CC
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
C
C
C
C
AV
AV
VREF
C0 C1
C2 C3
SS
DD
CC
DV
OR
CC
OTHER
DIGITAL
SUPPLY
R
PULLUP
EXTFORCE1
EXTFORCE2
CLALM
KELALM
CF0
CF1
CF2
CF3
CF4
TMPALM
DV
OR
CC
OTHER
DIGITAL
SUPPLY
R
PULLUP
RESET
FORCE
SENSE
EXTMEASHI1
EXTMEASHI2
R
1
SENSE
EXTMEASIL
R
2
SENSE
V
REF
MEASOUT
ADC
DRIVER
ADC
DUT
DUTGND
SHARED
ADC
Figure 60. External Components Required for Use with the DPS
Table 27. References Suggested for Use with the AD55601
Ref Out Tempco
(ppm/°C max)
A/B Grade
10/3
10/3
10/3
Initial
Accuracy %
Ref Output
Current (mA)
Supply Voltage
Range (V)
Part No.
ADR431
ADR435
ADR441
ADR445
Voltage (V)
Package
2.5
5
2.5
5
0.04
0.04
0.04
0.04
30
30
10
10
4.5 to 18
7 to 18
3 to 18
MSOP, SOIC
MSOP, SOIC
MSOP, SOIC
MSOP, SOIC
10/3
5.5 to 18
1 Subset of the possible references suitable for use with the AD5560. See www.analog.com/references for more options.
Rev. D | Page 60 of 68
Data Sheet
AD5560
Digital lines running under the device should be avoided because
these couple noise onto the device. The analog ground plane
should be allowed to run under the AD5560 to avoid noise
coupling. The power supply lines of the AD5560 should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching digital signals should be shielded with digital ground
to avoid radiating noise to other parts of the board and should
never be run near the reference inputs. It is essential to
minimize noise on all VREF lines. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough throughout the board. As is the case for all thin
packages, care must be taken to avoid flexing the package and
to avoid a point load on the surface of this package during the
assembly process.
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consid-
eration of the power supply and ground return layout helps
to ensure the rated performance. The printed circuit board
on which the AD5560 is mounted should be designed so that
the analog and digital sections are separated and confined to
certain areas of the board. If the AD5560 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
The DGND connection in the AD5560 should be treated as
AGND and returned to the AGND plane. For more detail on
decoupling for mixed signal applications, refer to Analog
Devices Tutorial MT 031.
For supplies with multiple pins (AVSS, AVDD, DVCC), it is
recommended to tie these pins together and to decouple
each supply once.
Also note that the exposed paddle of the AD5560 is internally
connected to the negative supply AVSS.
The AD5560 should have ample supply decoupling of 10 µF
in parallel with 0.1 µF on each supply located as close to the
part as possible, ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and effective
series inductance (ESL), such as the common ceramic capaci-
tors that provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
Rev. D | Page 61 of 68
AD5560
Data Sheet
APPLICATIONS INFORMATION
THERMAL CONSIDERATIONS
Table 28. Thermal Resistance for TQFP_EP1
4
θJC (Local)
θJC (Local)
w/TIM6
θJCP
2
3
Cooling
Airflow (LFPM)
θJA
θJC (Uniform)
Ideal TIM6
w/TIM5
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
No Heat Sink
0
39
N/A
200
500
0
200
500
N/A
37.2
35.7
12.2
11.1
9.5
Heat Sink7
N/A
7.5
1.0
1.0
2.8
2.8
4.91
4.91
Cold Plate8
N/A
1 All numbers are simulated and assume a JEDEC 4-layer test board.
2 θJA is the thermal resistance from hottest junction to ambient air.
3 θJC (Uniform) is the thermal resistance from junction to the package top, assuming total power is uniformly distributed.
4 θJC (Local) is the thermal resistance from junction to the center of package top, assuming total power = 8.5 W (1 W uniformly distributed, 7.5 W in power stages—local
heating).
5 θJCP is the thermal resistance from hottest junction to infinite cold plate with consideration of thermal interface material (TIM).
6 Ideal TIM is assuming top of package in perfect contact with an infinite cold plate. w/TIM is assuming TIM is 0.5 mm thick, with thermal conductivity of 2.56 W/m/k.
7 Heat sink with a rated performance of θCA ~5.3°C/W under forced convection, gives ~TJ = 111°C at 500 LFM. Thermal performance of the package depends on the heat
sink and environmental conditions.
8 Attached infinite cold plate should be ≤26°C to maintain TJ < 90°C, given total power = 8.5 W. Thermal performance of the package depends on the heat sink and
environmental conditions.
9 To estimate junction temperature, the following equations can be used:
TJ = Tamb + θJA × Power
TJ = Tcold plate + θJCP × Power
TJ = Ttop + θJC × Power
Table 29. Thermal Resistance for Flip Chip BGA1
4
5
θJC (Local)
θJC (Local)
w/TIM6
θJCP
2
3
Cooling
Airflow (LFPM)
θJA
θJC (Uniform)
Ideal TIM6
w/TIM
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
No Heat Sink
0
40.8
38.1
36
N/A
200
500
0
200
500
N/A
Heat Sink8
18
11.8
9
N/A
6.5
0.05
0.05
1.6
1.6
4.6
4.6
Cold Plate9
N/A
1 All numbers are simulated and assume a JEDEC 4-layer test board.
2 θJA is the thermal resistance from hottest junction to ambient air.
3 θJC (Uniform) is the thermal resistance from junction to the package top, assuming total power is uniformly distributed.
4 θJC (Local) is the thermal resistance from junction to the center of package top, assuming total power = 8.5 W (1 W uniformly distributed, 7.5 W in power stages—local
heating).
5 θJCP is the thermal resistance from hottest junction to infinite cold plate with consideration of thermal interface material (TIM).
6 Ideal TIM is assuming top of package in perfect contact with an infinite cold plate. w/TIM is assuming TIM is 0.4 mm thick, with thermal conductivity of 3.57 W/m/k.
7 Heat sink with a rated performance of θCA ~4.9°C/W under forced convection, gives ~TJ = 112°C at 500 LFM. Thermal performance of the package depends on the heat
sink and environmental conditions.
8 Attached infinite cold plate should be ≤30°C to maintain TJ < 90°C, given total power = 8.5 W. Thermal performance of the package depends on the heat sink and
environmental conditions.
9 To estimate junction temperature, the following equations can be used:
TJ = Tamb + θJA × Power
TJ = Tcold plate + θJCP × Power
TJ = Ttop + θJC × Power
Rev. D | Page 62 of 68
Data Sheet
AD5560
TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE
BGA Package
TQFP_EP Package
Due to localized heating, temperature at the top surface of
Due to localized heating, temperature at the top surface of
the package has steep gradient. Thus, the θJC value is highly
dependent on where the case temperature is measured.
Figure 61 shows the top of the die temperature contour map
for the TQFP_EP.
the package has steep gradient. Thus, the θJC value is highly
dependent on where the case temperature is measured.
Figure 62 shows the top of the die temperature contour map
for the flip chip BGA.
Figure 61. Temperature Contour Map for 64-Lead TQFP_EP
Figure 62. Temperature Contour Map for the Flip Chip BGA
Rev. D | Page 63 of 68
AD5560
Data Sheet
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
1.20
MAX
0.675
5.95 BSC
0.75
0.60
0.45
0.872
64
49
49
64
1
48
1
48
1.00 REF
SEATING
PLANE
10.20
10.00 SQ
9.80
EXPOSED
PAD
7.85
BSC
5.95
BSC
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
1.05
1.00
0.95
16
33
16
33
0.20
0.09
17
32
17
32
7.85
BSC
0.27
0.22
0.17
7°
3.5°
0°
VIEW A
0.15
0.05
0.50
BSC
LEAD PITCH
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
COPLANARITY
SECTION OF THIS DATA SHEET.
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HU
Figure 63. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-64-3)
Dimensions shown in millimeters
8.10
8.00 SQ
7.90
5.720 REF
0.40 REF
A1 BALL
CORNER
A1 BALL
CORNER
(DIE OFFSET)
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
6.40
BSC SQ
6.865 REF
G
H
J
0.80
BSC
0.80
REF
TOP VIEW
DETAIL A
BOTTOM VIEW
0.81
0.76
0.71
*
1.20
1.08
1.00
DETAIL A
0.36
REF
0.39
0.34
0.29
0.50
0.45
0.40
COPLANARITY
0.12
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-225 WITH
EXCEPTION TO PACKAGE HEIGHT.
Figure 64. 72-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-72-2)
Dimensions shown in millimeters
Rev. D | Page 64 of 68
Data Sheet
AD5560
ORDERING GUIDE
Model1
Temperature Range2
TJ = 25°C to +90oC
TJ = 25°C to +90oC
TJ = 25°C to +90oC
TJ = 25°C to +90oC
Package Description
Package Option
SV-64-3
SV-64-3
BC-72-2
BC-72-2
AD5560JSVUZ
AD5560JSVUZ-REEL
AD5560JBCZ
AD5560JBCZ-REEL
EVAL-AD5560EBUZ
64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP)
64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP)
72-Ball Chip Scale Package Ball Grid Array (CSP-BGA)
72-Ball Chip Scale Package Ball Grid Array (CSP-BGA)
Evaluation Kit
1 Z = RoHS Compliant Part.
2 TJ = junction temperature.
Rev. D | Page 65 of 68
AD5560
NOTES
Data Sheet
Rev. D | Page 66 of 68
Data Sheet
NOTES
AD5560
Rev. D | Page 67 of 68
AD5560
NOTES
Data Sheet
©2008-2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07779-0-8/12(D)
Rev. D | Page 68 of 68
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