ADA4922-1ACPZ-R2 [ADI]
High Voltage, Differential 18-Bit ADC Driver; 高压，差分18位ADC驱动器
| 型号： | ADA4922-1ACPZ-R2 |
| 厂家： | 
ADI |
| 描述： | High Voltage, Differential 18-Bit ADC Driver |
| 文件： | 总20页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage, Differential
18-Bit ADC Driver
ADA4922-1
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single-ended-to-differential conversion
Low distortion (VO, dm = 40 V p-p)
−99 dBc HD at 100 kHz
ADA4922-1
8
1
NC
IN
Low differential output referred noise: 12 nV/√Hz
High input impedance: 11 MΩ
Fixed gain of 2
No external gain components required
Low output-referred offset voltage: 1.1 mV max
Low input bias current: 3.5 μA max
Wide supply range
2
3
7
6
5
REF
DIS
V
V
S+
S–
OUT+
4
OUT–
NC = NO CONNECT
5 V to 26 V
Figure 1.
Can produce differential output signals in excess of 40 V p-p
High speed
38 MHz, −3 dB bandwidth @ 0.2 V p-p differential output
Fast settling time
–84
–87
SECOND HARMONIC
THIRD HARMONIC
R
= 2kΩ
L
–90
200 ns to 0.01% for 12 V step on 5 V supplies
Disable feature
–93
–96
V
= ±5V, V
= 12V p-p
O, dm
S
Available in space-saving, thermally enhanced packages
3 mm × 3 mm LFCSP
8-lead SOIC_EP
–99
–102
–105
–108
–111
–114
–117
–120
Low supply current: IS = 10 mA on 12 V supplies
APPLICATIONS
V
= ±12V, V
= 40V p-p
100
S
O, dm
High voltage data acquisition systems
Industrial instrumentation
Spectrum analysis
1
10
FREQUENCY (kHz)
Figure 2. Harmonic Distortion for Various Power Supplies
ATE
Medical instruments
GENERAL DESCRIPTION
The ADA4922-1 is a differential driver for 16-bit to 18-bit
ADCs that have differential input ranges up to 2ꢀ ꢁ.
Configured as an easy-to-use, single-ended-to-differential
amplifier, the ADA4922-1 requires no external components to
drive ADCs. The ADA4922-1 provides essential benefits such as
low distortion and high SNR that are required for driving ADCs
with resolutions up to 18 bits.
The ADA4922-1 is manufactured on ADI’s proprietary second-
generation XFCB process that enables the amplifier to achieve
excellent noise and distortion performance on high supply
voltages.
The ADA4922-1 is available in an 8-lead 3 mm × 3 mm LFCSP
as well as an 8-lead SOIC package. Both packages are equipped
with an exposed paddle for more efficient heat transfer. The
ADA4922-1 is rated to work over the extended industrial
temperature range, −4ꢀ°C to +85°C.
With a wide supply voltage range (5 ꢁ to 26 ꢁ), high input
impedance, and fixed differential gain of 2, the ADA4922-1 is
designed to drive ADCs found to in a variety of applications,
including industrial instrumentation.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADA4922-1
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 14
Applications..................................................................................... 16
ADA4922-1 Differential Output Noise Model .......................... 16
Using the REF Pin ...................................................................... 16
Internal Feedback Network Power Dissipation...................... 17
Disable Feature ........................................................................... 17
Driving a Differential Input ADC............................................ 17
Printed Circuit Board Layout Considerations ....................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 2ꢀ
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
10/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADA4922-1
SPECIFICATIONS
ꢁS = 12 ꢁ, TA = 25°C, RL = 1 kΩ,
= HIGH, CL = 3 pF, unless otherwise noted.
DIS
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +2, VO = 0.2 V p-p, differential
G = +2, VO = 40 V p-p, differential
VS+ + 0.5 V to VS− − 0.5 V; +Recovery/−Recovery
VO, dm = 2 V step
VO, dm = 40 V step
VO, dm = 40 V step
34
6.5
38
7.2
180/330
260
730
MHz
MHz
ns
V/μs
V/μs
ns
Overdrive Recovery Time
Slew Rate
Settling Time to 0.01%
580
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion
fC = 5 kHz, VO = 40 V p-p, RL = 2 kΩ, HD2/HD3
fC = 100 kHz, VO = 40 V p-p, RL = 2 kΩ, HD2/HD3
f = 100 kHz
−116/−109
−99/−100
12
dBc
dBc
nV/√Hz
pA/√Hz
Differential Output Voltage Noise
Input Current Noise
DC PERFORMANCE
f = 100 kHz
1.4
Differential Output Offset Voltage
Differential Output Offset Voltage Drift
Input Bias Current
0.35
14
1.8
1.1
3.5
mV
μV/°C
μA
Gain
Gain Error
Gain Error Drift
2
V/V
%
%/°C
−0.05
0.0002
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
11
1
MΩ
pF
V
Input Voltage Range
±10.7
OUTPUT CHARACTERISTICS
Output Voltage Swing
DC Output Current
Capacitive Load Drive
POWER SUPPLY
Each single-ended output, RL = 1 kΩ
30% overshoot
V
±10.65 ±10.7
40
20
mA
pF
Operating Range
5
26
V
Quiescent Current
Quiescent Current (Disabled)
Power Supply Rejection Ratio (PSRR)
−PSRR
9.4
1.5
10.1
2.0
mA
mA
−89
−91
−80
−83
dB
dB
+PSRR
DISABLE
DIS Input Voltage Threshold
Disabled
Enabled
≤ −11
≥ −9
160
V
V
μs
ns
Turn-Off Time
Turn-On Time
DIS Bias Current
Enabled
78
DIS = −9 V
114
μA
μA
Disabled
DIS = −11 V
−125
Rev. 0 | Page 3 of 20
ADA4922-1
ꢁS = 5 ꢁ, TA = 25°C, RL = 1 kΩ,
= HIGH, CL = 3 pF, unless otherwise noted.
DIS
Table 2.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +2, VO = 0.2 V p-p, differential
G = +2, VO = 12 V p-p, differential
+Recovery/−Recovery
VO, dm = 2 V step
VO, dm = 12 V step
VO, dm = 12 V step
36
6.5
40.5
13.5
200/670
220
350
200
MHz
MHz
ns
V/μs
V/μs
ns
Overdrive Recovery Time
Slew Rate
Settling Time to 0.01%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion
fC = 5 kHz, VO = 12 V p-p, RL = 2 kΩ, HD2/HD3
fC = 100 kHz, VO = 12 V p-p, RL = 2 kΩ, HD2/HD3
f = 100 kHz
−102/−108
−101/−98
12
dBc
dBc
nV/√Hz
Differential Output Voltage Noise
Input Current Noise
f = 100 kHz
1.4
pA/√Hz
DC PERFORMANCE
Differential Output Offset Voltage
0.4
12
2.0
2
−0.05
0.0002
1.2
3.5
mV
μV/°C
μA
V/V
%
%/°C
Differential Output Offset Voltage Drift
Input Bias Current
Gain
Gain Error
Gain Error Drift
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Voltage Range
11
1
MΩ
pF
V
±3.6
OUTPUT CHARACTERISTICS
Output Voltage Swing
DC Output Current
Capacitive Load Drive
POWER SUPPLY
Each single-ended output, RL = 1 kΩ
30% overshoot
V
±3.55 ±3.6
40
20
mA
pF
Operating Range
Quiescent Current
Quiescent Current (Disabled)
Power Supply Rejection Ratio (PSRR)
−PSRR
5
26
7.6
1.6
V
mA
mA
7.0
0.7
−93
−91
−82
−83
dB
dB
+PSRR
DISABLE
DIS Input Voltage
Disabled
Enabled
≤ −4
≥ −2
160
78
V
V
μs
ns
Turn-Off Time
Turn-On Time
DIS Bias Current
Enabled
DIS = −2 V
DIS = −4 V
41
49
μA
μA
Disabled
Rev. 0 | Page 4 of 20
ADA4922-1
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
The power dissipated in the package (PD) is the sum of the
Rating
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (ꢁS) times the
quiescent current (IS). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature Range (Soldering 10 sec)
Junction Temperature
26 V
See Figure 3
–65°C to +125°C
–40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θJA.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.
Figure 3 shows the maximum safe power dissipation in the
packages vs. the ambient temperature for the 8-lead SOIC
(79°C/W) and for the 8-lead LFCSP (81°C/W) on a JEDEC
standard 4-layer board, each with its underside paddle soldered
to a pad that is thermally connected to a PCB plane. θJA values
are approximations.
Table 4. Thermal Resistance
Package Type
8-Lead SOIC with EP on 4-layer board
8-Lead LFCSP with EP on 4-layer board
θJA
79
81
θJC
25
17
Unit
°C/W
°C/W
3.0
Maximum Power Dissipation
2.5
The maximum safe power dissipation in the ADA4922-1
SOIC
2.0
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 15ꢀ°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4922-1. Exceeding a
junction temperature of 15ꢀ°C for an extended period can
result in changes in the silicon devices potentially causing
failure.
LFCSP
1.5
1.0
0.5
0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 20
ADA4922-1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADA4922-1
8
1
NC
IN
2
3
7
6
5
REF
DIS
V
V
S+
S–
OUT+
4
OUT–
NC = NO CONNECT
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
No Internal Connection
Reference Voltage for Single-Ended Input Signal
Positive Power Supply
Noninverting Side of Differential Output
Inverting Side of Differential Output
Negative Power Supply
1
2
3
4
5
6
7
8
NC
REF
VS+
OUT+
OUT−
VS−
DIS
Disable
IN
Single-Ended Signal Input
Rev. 0 | Page 6 of 20
ADA4922-1
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, ꢁS = 12 ꢁ, RL, dm = 1 kΩ, REF = ꢀ ꢁ,
= HIGH, TA = 25°C.
DIS
3
3
0
V
= 0.2V p-p
O, dm
0
–3
V
=
±
5V, V
= 12V p-p
O, dm
–3
S
V
= ±5V
–6
–6
S
–9
–9
–12
–15
–18
–21
–24
–27
–30
–12
–15
–18
–21
–24
–27
V
= ±12V
S
V
=
±
12V, V
= 40V p-p
O, dm
S
–30
1
1
10
100
1000
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response for Various Power Supplies
Figure 8. Large Signal Frequency Response for Various Power Supplies
3
3
0
V
= 0.2V p-p
O, dm
0
–3
–3
–6
–9
–6
–9
V
V
= 12V p-p (V
= 40V p-p (V
=
=
±
±
5V)
12V)
O, dm
O, dm
S
S
–12
–15
–18
–21
–24
–27
–30
–12
–15
–18
–21
–24
–27
–30
(ALL VOLTAGES ARE V
)
O, dm
V
V
V
V
V
V
=
=
=
=
=
=
±
±
±
±
±
±
12V @ +85
5V @ +85
12V @ +25
5V @ +25
12V @ –40
5V @ –40
°C
C
S
S
S
S
S
S
40V p-p +85
°
C
C
C
°
40V p-p +25
°
°C
40V p-p –40
°
°
C
12V p-p +85
°C
°C
12V p-p +25
°C
°
C
12V p-p –40°C
1
10
100
1000
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response for
Various Temperatures and Supplies
Figure 9. Large Signal Frequency Response at
Various Temperatures and Supplies
3
0
3
0
V
, dm = 0.2V p-p
O
–3
–3
–6
–6
–9
–9
V
V
= 12V p-p (V
= 40V p-p (V
=
=
±
±
5V)
12V)
O, dm
O, dm
S
S
–12
–15
–18
–21
–24
–27
–30
–12
–15
–18
–21
–24
–27
–30
V
V
V
V
=
=
=
=
±
±
±
±
12V R
5V R
= 1kΩ
V
=
=
=
=
±
±
±
±
12V, R
5V, R
= 1kΩ
S
S
S
S
L, dm
S
L, dm
= 1kΩ
V
V
V
= 1kΩ
L, dm
S
S
S
L, dm
12V R
5V R
= 500Ω
12V, R
5V, R
= 500
Ω
L, dm
L, dm
= 500Ω
= 500
Ω
L, dm
L, dm
1
10
100
1000
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for
Various Resistive Loads and Supplies
Figure 10. Large Signal Frequency Response for
Various Resistive Loads and Supplies
Rev. 0 | Page 7 of 20
ADA4922-1
3
0
3
0
V
, dm = 0.2V p-p
O
–3
–3
–6
–6
–9
–9
–12
–15
–18
–21
–12
–15
–18
–21
–24
–27
–30
V
V
V
V
=
=
=
=
±
±
±
±
5V, V = 12V p-p, C
L, dm
= 0pF
= 0pF
= 20pF
= 20pF
V
V
V
V
=
±
±
±
±
5V, C
5V, C
12V, C
12V, C
= 10pF
= 20pF
= 0pF
S
S
S
S
IN
S
S
S
S
L, dm
L, dm
–24
–27
–30
12V, V = 40V p-p, C
=
=
=
IN
L, dm
5V, V = 12V p-p, C
L, dm
IN
L, dm
= 20pF
12V, V = 40V p-p, C
IN
L, dm
L, dm
1
10
100
1000
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. Small Signal Frequency Response for Various Capacitive Loads
Figure 14. Large Signal Frequency Response for Various Capacitive Loads
3
0
3
0
–3
–3
–6
0.2V p-p
–6
–9
0.2V p-p
–9
–12
–15
–18
–21
–24
–27
–30
–33
10V p-p
–12
–15
–18
–21
–24
–27
–30
–33
2V p-p
16V p-p
12V p-p
20V p-p
40V p-p
2V p-p
10V p-p
100
1
10
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Frequency Response for Various Output Amplitudes, VS = 12 V
Figure 12. Frequency Response for Various Output Amplitudes, VS = 5 V
3
–50
V
= 0.1V p-p
REF
V
= 0.1V p-p
IN
0
–3
DIS = LOW
–60
–70
V
= ±5V
S
–6
–9
V
= ±12V
S
–80
–12
–15
–18
–21
–24
–27
–30
V
= ±12V
S
–90
V
±5V
S
–100
–110
–120
1
10
100
1000
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 13. Isolation vs. Frequency—Disabled
Figure 16. REF Small Signal Frequency Response for Various Power Supplies
Rev. 0 | Page 8 of 20
ADA4922-1
–84
–87
–84
–87
–90
SECOND HARMONIC
THIRD HARMONIC
SECOND HARMONIC
THIRD HARMONIC
R
= 2kΩ
V
V
=
S
O, dm
±
12V
L
= 40V p-p
–90
–93
–93
–96
–96
V
=
±
5V, V
= 12V p-p
O, dm
S
–99
–99
R
= 600Ω
L
R
= 1kΩ
–102
–105
–102
–105
–108
–111
L
–108
–111
–114
–117
–120
–114
–117
–120
V
=
±
12V, V
= 40V p-p
100
S
O, dm
R
= 2kΩ
L
1
10
FREQUENCY (kHz)
1
10
FREQUENCY (kHz)
100
Figure 20. Harmonic Distortion for Various Loads
Figure 17. Harmonic Distortion for Various Power Supplies
100
10
–60
SECOND HARMONIC
THIRD HARMONIC
R
= 2kΩ
L
–70
–80
VON
S
V
= ±5V
–90
V
= ±5V
S
VON
12V
1
–100
–110
–120
–130
–140
V
= ±
S
VOP
5V
V
= ±
S
0.1
0.01
VOP
12V
V
= ±
S
V
=
±
12V
37
S
0.001
0.01
0.1
1
10
100
2
7
12
17
22
27
32
42
47
FREQUENCY (MHz)
OUTPUT AMPLITUDE (V p-p)
Figure 18. Harmonic Distortion vs. Output Amplitude and
Supply Voltage (f =10 kHz)
Figure 21. Single-Ended Output Impedance vs. Frequency and Supplies
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+PSRR
–PSRR
0.001
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 19. PSRR vs. Frequency
Rev. 0 | Page 9 of 20
ADA4922-1
100
90
80
70
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
0
1
10
100
1k
10k
100k
1M
10M
100M
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. Input Current Noise vs. Frequency
Figure 22. Differential Output Noise vs. Frequency
22
18
14
10
6
0.12
0.10
0.08
0.06
0.04
0.02
0
V
= ±5V
C
OUT
= 20pF
L
20ns/DIV
S
V
= 40V p-p
V
= ±12V
S
2
–2
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–6
–10
–14
–18
–22
100ns/DIV
TIME (μs)
Figure 23. Small Signal Transient Response for Various Power Supplies
Figure 26. Large Signal Transient Response for Various Power Supplies
0.125
22
18
C
C
C
= 0pF
= 10pF
= 20pF
L
L
L
0.100
0.075
0.050
0.025
0
C
= 0pF
L
14
10
C
= 20pF
L
6
2
–2
–0.025
–0.050
–0.075
–0.100
–0.125
–6
–10
–14
–18
–22
5ns/DIV
20ns/DIV
Figure 24. Small Signal Transient Response for Various Capacitive Loads
Figure 27. Large Signal Transient Response for Various Capacitive Loads
Rev. 0 | Page 10 of 20
ADA4922-1
8
6
4.8
3.6
28
21
14
7
16
V
V
OUT, dm
OUT, dm
12
4
2.4
1.2
8
4
V
V
IN
IN
2
0
0
0
0
ERROR
ERROR
–2
–4
–1.2
–2.4
–7
–14
–4
–8
1μs/DIV
1μs/DIV
–6
–8
–3.6
–4.8
–21
–28
–12
V
V
= ±5V
O, dm
V
V
= ±12V
O, dm
S
S
= 12V p-p
= 40V p-p
–16
Figure 28. Settling Time, VS = 5 V
Figure 31. Settling Time, VS = 12 V
12
8
26
22
18
14
10
6
INPUT × 2
INPUT × 2
4
2
0
–2
–6
–10
–4
–8
–12
–14
–18
–22
–26
OUTPUT
OUTPUT
1μs/DIV
1μs/DIV
Figure 29. Input Overdrive Recovery, VS = 5 V
Figure 32. Input Overdrive Recovery, VS = 12 V
1.2
50
45
40
35
30
25
20
15
10
5
V
= ±5V
S
1.0
0.8
0.6
0.4
0.2
0
MEAN = 0.25mV
STD. DEV. = 0.19mV
V
= ±12V
S
MEAN = –0.07mV
STD. DEV. = 0.17mV
V
= ±5V
S
NUMBER OF
UNITS = 590
V
= ±12V
S
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT OFFSET VOLTAGE (mV)
Figure 30. Differential Output Offset Voltage vs. Temperature
Figure 33. Differential Output Offset Voltage Distribution
Rev. 0 | Page 11 of 20
ADA4922-1
12.0
10
9
11.5
11.0
10.5
10.0
9.5
I
= ±12V
= ±5V
SUPPLY
8
7
I
SUPPLY
6
V
= ±12V
S
9.0
5
4
3
2
1
0
8.5
8.0
7.5
V
= ±5V
S
7.0
6.5
6.0
–40
–20
0
20
40
60
80
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TEMPERATURE (°C)
DIS INPUT VOLTAGE WITH RESPECT TO V (V)
S–
Figure 34. Power Supply Current vs. Temperature
Figure 37. Power Supply Current vs. Disable Input Voltage
3.0
2.5
2.0
1.5
1.0
5
4
3
I
= ±12V
2
1
0
B
–1
–2
–3
–4
–5
I
= ±5V
B
INPUT BIAS CURRENT, V = ±5V
S
REFERENCE BIAS CURRENT, V = ±5V
S
INPUT BIAS CURRENT, V = ±12V
S
REFERENCE BIAS CURRENT, V = ±12V
S
–40
–20
0
20
40
60
80
0
2
4
6
8
10 12 14 16 18 20 22 24
TEMPERATURE (°C)
INPUT VOLTAGE WITH RESPECT TO V (V)
S–
Figure 35. Input Bias Current vs. Temperature
Figure 38. Input Bias Current vs. Input Voltage
V
= 2V p-p
V
V
= 2V p-p
O, dm
O, dm
DIS INPUT
= –8.5V
V
= –8.5V
DIS
DIS
V
O, dm
DIS INPUT
V
= –10.5V
V
= –10.5V
DIS
DIS
V
O, dm
40μs/DIV
40μs/DIV
Figure 36. Disable Turn-On Time
Figure 39. Disable Turn-Off Time
Rev. 0 | Page 12 of 20
ADA4922-1
300
250
200
150
100
50
I
= ±5V
DIS
0
I
= ±12V
DIS
–50
–100
–150
0
5
10
15
20
DIS VOLTAGE WITH RESPECT TO V (V)
S–
Figure 40. Disable Current vs. Disable Voltage
Rev. 0 | Page 13 of 20
ADA4922-1
THEORY OF OPERATION
The ADA4922-1 is dual amplifier that has been optimized to
drive a differential ADC from a single-ended input source with
a minimum number of external components (see Figure 41).
If an application uses an input midswing voltage other than
midsupply, the REF pin needs to be offset to the input midswing
level to obtain outputs that do not exhibit a differential offset
(see Figure 43). If the voltage applied to the REF pin is different
from the midswing level of the input signal, a dc offset is
created between outputs ꢁOUT+ and ꢁOUT−. Figure 44 illustrates
this condition when the input signal is referenced to a positive
level, and the REF pin is connected to ꢀ ꢁ.
IN
OUT+
R
R
OUT–
REF
10
V
IN
Figure 41. Functional Diagram
5
0
The differential output voltage is defined as
REF
–5
–10
10
V
O, dm = VOUT+ − VOUT−
(1)
Each amplifier in Figure 41 is identical, and the value of Resistor R
is set at 6ꢀꢀ Ω, yielding an optimal trade-off between output
differential noise, internal power dissipation, and overall
system linearity. For basic operation, the REF input is tied to
the midswing level of the input signal, which is often midsupply.
The input signal (referenced to REF) produces a differential
output signal with an overall gain of +2. Figure 42 shows typical
operation on 12 ꢁ supplies with the source referenced to ꢀ ꢁ
and the REF pin tied to ꢀ ꢁ.
OUT+
5
OUT–
10
0
–2.5
0
5
15
20
25
30
35
40
45
50
TIME (μs)
Figure 43. Typical Input/Output Response—Equal Input/Reference
20
20
15
10
V
IN
10
0
V
IN
REF
5
0
–10
–20
10
5
REF
–5
10
5
OUT+
OUT+
0
0
–5
–10
OUT–
10
–5
–10
OUT–
10
0
5
15
20
25
30
35
40
45
50
0
5
15
20
25
30
35
40
45
50
TIME (μs)
TIME (μs)
Figure 42. Typical Input/Output Response—Centered Reference
Figure 44. Typical Input/Output Response—Unequal Input/Reference
Rev. 0 | Page 14 of 20
ADA4922-1
A more detailed view of the amplifier is shown in Figure 45.
Each amplifier is a 2-stage design that uses an input H-Bridge
followed by a rail-to-rail output stage (see Figure 46).
The architecture used in the ADA4922-1 results in excellent
SNR and distortion performance when compared to other
differential amplifiers.
One of the more subtle points of operation arises when the two
amplifiers are used to generate the differential outputs. Because
the differential outputs are derived from a follower amplifier
and an inverting amplifier, they have different noise gains and,
therefore, different closed-loop bandwidths. For frequencies up
to 1 MHz, the bandwidth difference between outputs causes
little difference in the overall differential output performance.
However, because the bandwidth is the sum of both amplifiers,
the 3 dB point of the inverting amplifier defines the overall
differential 3 dB corner (see Figure 48).
MIRROR
C
I
I
R
IN
OUTPUT
STAGE
INP
INN
OUT
I
I
MIRROR
0
Figure 45. Internal Amplifier Architecture
OUT+
–2
MIRROR
–4
I
I
OUT–
–6
7
R
OUT
INTERNAL
REF
IN
OUT
DIFFERENTIAL OUTPUT
5
I
I
3
1
MIRROR
10k
100k
1M
10M
100M
Figure 46. Output Stage Architecture
FREQUENCY (Hz)
Figure 48. Closed-Loop AC Gain (Differential Outputs)
Figure 47 illustrates the open-loop gain and phase relationships
of each amplifier in the ADA4922-1.
Small delay and gain errors exist between the two outputs
because the inverting output is derived from the noninverting
output through an inverting amplifier. The gain error is due to
imperfect matching of the inverting amplifier gain and feedback
resistors, as well as differences in the transfer functions of the
two amplifiers, as illustrated in Figure 48. The delay error is due
to the delay through the inverting amplifier relative to the
noninverting amplifier output. The delay produces a reduction
in differential gain because the two outputs are not exactly 18ꢀ°
out of phase. Both of these errors combine to produce an overall
gain error because the outputs are completely balanced. This
error is very small at the frequencies involved in most
ADA4922-1 applications.
125
100
GAIN
75
50
25
0
–25
–50
–75
PHASE
–100
–125
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 47. Amplifier Gain/Phase Relationship
Rev. 0 | Page 15 of 20
ADA4922-1
APPLICATIONS
Voltage Noise @ OUT− due to VnRf: VnRF
(8)
(9)
The ADA4922-1 is a fixed-gain, single-ended-to-differential
voltage amplifier, optimized for driving high resolution ADCs
in high voltage applications. There are no gain adjustments
available to the user.
⎛
⎞
⎟
Rf
Rg
⎜
Voltage Noise @ OUT− due toVn2: Vn2 1 +
= 2Vn2
⎜
⎝
⎟
⎠
When looking at OUT− by itself, the contributing noise sources
are uncorrelated, and therefore, the total output noise is
calculated as the root-sum-square (rss) of the individual
contributors. When looking at the differential output noise, the
noise contributors are uncorrelated except for three, ꢁn1, RS(In1),
and ꢁnRs, which are common noise sources for both outputs. It
can be seen from the previous results that the output noise due
to ꢁn1, RS(In1), and ꢁnRs each appear at OUT+ with a gain of +1
and at OUT− with a gain of −1. This produces a gain of 2 for each
of these three sources at the differential output.
ADA4922-1 DIFFERENTIAL OUTPUT NOISE MODEL
The principal noise sources in a typical ADA4922-1 application
circuit are shown in Figure 49.
V
nRf
R
f
V
n1
V
nRg
R
g
R
s
V
OUT–
OUT+
n2
V
I
n1
nRs
REF
Figure 49. ADA4922-1 Differential Output Noise Model
The total differential output noise density is calculated as
Using the traditional approach, a noise source is applied in
series with one of the inputs of each op amp to model input-
referred voltage noise. The input current noise that matters the
most is present at the input pin. The output voltage noise due to
this noise current depends on the source resistance feeding the
input, as well as the downstream gain in the amplifier. Resistor
noise is modeled by placing a noise voltage source in series with
a noiseless resistor. Rf and Rg are both 6ꢀꢀ Ω and therefore have
the same noise voltage density.
Von, dm
=
2
Vn + Rs (1.4pA/ Hz) +VnRs ))2 + 2
(
3.2nꢁ/ Hz
)
+ 4Vn (1ꢀ)
2
2
where ꢁn1 = ꢁn2 ≡ ꢁn = 3.9 nꢁ/√Hz; the input referred voltage
noise of each amplifier is the same.
The output noise due to the amplifier alone is calculated by
setting RS and ꢁnRs equal to zero. In this case:
Von, dm = 12 nꢁ/√Hz
(11)
At room temperature,
Clearly, the output noise is not balanced between the outputs,
but this is not an issue in most applications.
VnRg =VnRf
=
4 kT
(
6ꢀꢀ ꢂ
)
≈ 3.2 nꢁ/ Hz
(2)
USING THE REF PIN
The noise at OUT+ is due to the input-referred current and
voltage noise sources of the noninverting amplifier and the
The REF pin sets the output baseline in the inverting path and
is used as a reference for the input signal. In most applications,
the REF pin is set to the input signal midswing level, which in
many cases is also midsupply. For bipolar signals and power
supplies, REF is generally set to ground. In single-supply
applications, setting REF to the input signal midswing level
provides optimal output dynamic range performance with
minimum differential offset. Note that the REF input only
affects the inverting signal path, or OUT−.
noise of the source resistance, all reflected to the output with a
noise gain of 1, and is equal to:
Voltage Noise @ OUT+: Vn1 + RS(In1) + VnRs
(3)
where RS is the source resistance feeding the input, and VnRs is
the source resistance noise.
The noise at OUT− originates from a number of sources:
⎛
⎜
⎞
⎟
− Rf
Voltage Noise @ OUT− due to Vn1: Vn1
= −Vn1
(4)
(5)
(6)
(7)
Most applications require a differential output signal with the
same dc common-mode level on each output. It is possible for
the signal measured across OUT+ and OUT− to have a common-
mode voltage that is of the desired level but has different dc
levels at both outputs. Typically, this situation is avoided,
because it wastes the amplifier’s output dynamic range.
⎜
⎝
⎟
⎠
Rg
⎛
⎞
⎟
− Rf
⎜
Voltage Noise @ OUT− due to In1: RS
(
In1
)
= − RS
(
In1
)
⎜
⎝
⎟
⎠
Rg
⎛
⎜
⎞
⎟
− Rf
Voltage Noise @ OUT− due to RS: VnRs
Voltage Noise @ OUT− due to VnRg: VnRg
= −VnRs
= −VnRg
⎜
⎝
⎟
⎠
Rg
⎛
⎞
− Rf
⎜
⎟
⎜
⎝
⎟
⎠
Rg
Rev. 0 | Page 16 of 20
ADA4922-1
DISABLE FEATURE
Defining ꢁIN as the voltage applied to the input pin, the
equations that govern the two signal paths are given in
Equation 12 and Equation 13.
The ADA4922-1 includes a disable feature that can be asserted
to minimize power consumption in a device that is not needed
at a particular time. When asserted, the disable feature does not
place the device output in a high impedance or three-state
condition. The disable feature is asserted by applying a control
VOUT+ = +VIN
(12)
(13)
VOUT− = −VIN + 2(REF)
voltage to the
pin and is active low. See the Specifications
DIS
When the REF voltage is set to the midswing level of the input
signal, the two output signals fall directly on top of each other
with minimal offset. Setting the REF voltage elsewhere results
in an offset between the two outputs. This effect is illustrated in
the Theory of Operation section.
section for the high and low level voltage specifications.
DRIVING A DIFFERENTIAL INPUT ADC
The ADA4922-1 provides the single-ended-to-differential
conversion that is required to drive most high resolution ADCs.
Figure 5ꢀ shows how the ADA4922-1 simplifies ADC driving.
The best use of the REF pin can be further illustrated by
considering a single-supply example that uses a 1ꢀ ꢁ dc power
supply and has an input signal that varies between 2 ꢁ and 7 ꢁ.
This is a case where the midswing level of the input signal is not
at midsupply but is at 4.5 ꢁ. By setting the REF input to 4.5 ꢁ
and neglecting offsets, Equation 12 and Equation 13 are used to
calculate the results. When the input signal is at its midpoint of
4.5 ꢁ, ꢁOUT+ is at 4.5 ꢁ, as is ꢁOUT−. This can be considered as a
type of baseline state where the differential output voltage is
zero. When the input increases to 7 ꢁ, ꢁOUT+ tracks the input to
7 ꢁ and ꢁOUT− decreases to 2 ꢁ. This can be viewed as a positive
peak signal where the differential output voltage equals 5 ꢁ.
When the input signal decreases to 2 ꢁ, ꢁOUT+ again tracks to
2 ꢁ, and ꢁOUT− increases to 7 ꢁ. This can be viewed as a negative
peak signal where the differential output voltage equals −5 ꢁ.
The resulting differential output voltage is 1ꢀ ꢁ p-p.
+12V
+12V
0.1μF
7
3
0.1μF
DIS
V
S+
ADA4922-1
8
IN
R
R
OUT+
4
5
V
IN
±10V
C
C
R
HIGH VOLTAGE
HIGH RESOLUTION
ADC
R
OUT–
2
REF
V
S–
0.1μF
6
–12V
0.1μF
–12V
Figure 50. Driving a Differential Input ADC
For example, consider the case where the input signal
bandwidth is 1ꢀꢀ KHz and R = 41.2 Ω and C = 3.9 nF, as is
shown in Figure 5ꢀ, to form a single-pole filter with −3 dB
bandwidth of approximately 1 MHz. The ADA4922-1 output
noise (with zero source resistance) integrated over this
bandwidth appears at the ADC input and is calculated as
The previous discussion exposes how the single-ended-to-
differential gain of 2 is achieved.
INTERNAL FEEDBACK NETWORK POWER
DISSIPATION
π
2
While traditional op amps do not have on-chip feedback
elements, the ADA4922-1 contains two on-chip 6ꢀꢀ Ω resistors
that comprise an internal feedback loop. The power dissipated
in these resistors must be included in the overall power dissipation
calculations for the device. Under certain circumstances, the
power dissipated in these resistors could be considerably more
than the device’s quiescent current. For example, on 12 ꢁ
supplies with the REF pin tied to ground and OUT− at 9 ꢁ dc,
each 6ꢀꢀ Ω resistor carries 15 mA and dissipates 135 mW. This
is a significant amount of power and must therefore be included
in the overall device power dissipation calculations. For ac
signals, rms analysis is required.
⎛
⎜
⎝
⎞
⎟
⎠
V
n, ADC,dm (rms) =
(
12nꢁ/ Hz
)
(
1MHz
)
=15μꢁrms
(14)
The rms value of a 2ꢀ ꢁ p-p signal at the ADC input is 7 ꢁ rms,
yielding a SNR of 113 dB at the ADC input.
Rev. 0 | Page 17 of 20
ADA4922-1
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Although the ADA4922-1 is used in many applications
involving frequencies that are well below 1 MHz, some general
high speed layout practices must be adhered to because it is a
high speed amplifier. Controlled impedance transmission lines
are not required for low frequency signals, provided the signal
rise times are longer than approximately 5 times the electrical
delay of the interconnections. For reference, typical 5ꢀ Ω
transmission lines on FR-4 material exhibit approximately
14ꢀ ps/in delay on outer layers and 18ꢀ ps/in for inner layers.
Most connections between the ADA4922-1 and the
ADC can be kept very short.
Broadband power supply decoupling networks should be placed
as close as possible to the supply pins. Small surface-mount
ceramic capacitors are recommended for these networks, and
tantalum capacitors are recommended for bulk supply
decoupling.
Rev. 0 | Page 18 of 20
ADA4922-1
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
2.29 (0.092)
2.29 (0.092)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
5
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
TOP VIEW
1
4
BOTTOM VIEW
1.27 (0.05)
BSC
(PINS UP)
0.50 (0.020)
0.25 (0.010)
× 45
1.75 (0.069)
1.35 (0.053)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
1.27 (0.050)
0.40 (0.016)
0.51 (0.020)
0.31 (0.012)
0.25 (0.0098)
0.17 (0.0068)
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 51. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
Narrow Body (RD-8-1)
Dimensions shown in millimeters and (inches
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
8
PIN 1
INDICATOR
1
PIN 1
INDICATOR
1.89
1.74
1.59
2.75
BSC SQ
TOP
VIEW
1.50
REF
0.50
BSC
4
5
1.60
1.45
1.30
0.70 MAX
0.65TYP
12° MAX
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 52. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2)
Dimensions shown in millimeters
Rev. 0 | Page 19 of 20
ADA4922-1
ORDERING GUIDE
Model
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
RD-8-1
RD-8-1
Branding
ADA4922-1ARDZ1
ADA4922-1ARDZ-RL1
ADA4922-1ARDZ-R71
ADA4922-1ACPZ-R21
ADA4922-1ACPZ-RL1
ADA4922-1ACPZ-RL71
8-Lead Small Outline Package (SOIC_N_EP)
8-Lead Small Outline Package (SOIC_N_EP)
8-Lead Small Outline Package (SOIC_N_EP)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2
8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2
8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2
RD-8-1
HUB
HUB
HUB
1 Z = Pb-free part.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05681–0–10/05(0)
Rev. 0 | Page 20 of 20
相关型号：
ADA4927-1XCPZ
IC LINE DRIVER, QCC16, 3 X 3 MM, ROHS COMPLIANT, MO-220VEED2, LFCSP-16, Line Driver or Receiver
ADI
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