ADA4927-1 [ADI]
Ultralow Distortion Current Feedback Differential ADC Driver; 超低失真电流反馈差分ADC驱动器
| 型号： | ADA4927-1 |
| 厂家： | 
ADI |
| 描述： | Ultralow Distortion Current Feedback Differential ADC Driver |
| 文件： | 总24页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion
Current Feedback Differential ADC Driver
ADA4927-1/ADA4927-2
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Extremely low harmonic distortion
−105 dBc HD2 @ 10 MHz
−91 dBc HD2 @ 70 MHz
−87 dBc HD2 @ 100 MHz
−103 dBc HD3 @ 10 MHz
−98 dBc HD3 @ 70 MHz
ADA4927-1
12 PD
–FB
+IN
–IN
1
2
3
4
11 –OUT
10 +OUT
+FB
9 V
OCM
−89 dBc HD3 @ 100 MHz
Better distortion at higher gains than VF amplifiers
Low input voltage noise: 1.4 nV/√Hz
High speed
Figure 1.
−3 dB bandwidth of 2.3 GHz
0.1 dB gain flatness: 150 MHz
Slew rate: 5000 V/μs, 25% to 75%
Fast 0.1% settling time: 10 ns
Low input offset voltage: 0.3 mV typical
Externally adjustable gain
Stability and bandwidth controlled by feedback resistor
Differential-to-differential or single-ended-to-differential
operation
–IN1
+FB1
1
18 +OUT1
17 V
2
3
4
5
6
OCM1
16 –V
+V
S2
S2
S1
ADA4927-2
–V
15
14
+V
S1
–FB2
+IN2
PD2
13 –OUT2
Adjustable output common-mode voltage
Wide supply operation: +5 V to 5 V
Figure 2.
APPLICATIONS
–40
–50
–60
–70
–80
ADC drivers
V
,
= 2V p-p
OUT dm
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Differential line drivers
GENERAL DESCRIPTION
–90
–100
–110
–120
–130
The ADA4927 is a low noise, ultralow distortion, high speed,
current feedback differential amplifier that is an ideal choice for
driving high performance ADCs with resolutions up to 16 bits
from dc to 100 MHz. The output common-mode level can easily be
matched to the required ADC input common-mode levels. The
internal common-mode feedback loop provides exceptional output
balance and suppression of even-order distortion products.
G = 1
G = 10
G = 20
1
10
100
1k
FREQUENCY (MHz)
Figure 3. Spurious-Free Dynamic Range vs. Frequency at Various Gains
Differential gain configurations are easily realized using an
external feedback network comprising four resistors. The
current feedback architecture provides loop gain that is nearly
independent of closed-loop gain, achieving wide bandwidth,
low distortion, and low noise at higher gains and lower power
consumption than comparable voltage feedback amplifiers.
The low dc offset and excellent dynamic performance of the
ADA4927 make it well suited for a wide variety of data acquisition
and signal processing applications.
The ADA4927-1 is available in a Pb-free, 3 mm × 3 mm 16-lead
LFCSP, and the ADA4927-2 is available in a Pb-free, 4 mm × 4 mm
24-lead LFCSP. The pinouts are optimized to facilitate printed
circuit board (PCB) layout and to minimize distortion. They are
specified to operate over the −40°C to +105°C temperature range.
The ADA4927 is fabricated using the Analog Devices, Inc., silicon-
germanium complementary bipolar process, enabling very low
levels of distortion with an input voltage noise of only 1.3 nV/√Hz.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADA4927-1/ADA4927-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Definition of Terms.................................................................... 16
Applications Information.............................................................. 17
Analyzing an Application Circuit ............................................ 17
Setting the Closed-Loop Gain .................................................. 17
Estimating the ꢀutput Noise Voltage...................................... 17
Impact of Mismatches in the Feedback Networks................. 18
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V ꢀperation............................................................................. 3
+5 V ꢀperation............................................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 15
Theory of ꢀperation ...................................................................... 16
Calculating the Input Impedance for
an Application Circuit ............................................................... 18
Input Common-Mode Voltage Range..................................... 20
Input and ꢀutput Capacitive AC Coupling............................ 20
Setting the ꢀutput Common-Mode Voltage.......................... 20
Power Down................................................................................ 21
Layout, Grounding, and Bypassing.............................................. 22
High Performance ADC Driving ................................................. 23
ꢀutline Dimensions....................................................................... 24
ꢀrdering Guide .......................................................................... 24
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADA4927-1/ADA4927-2
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = − 5 V, VꢀCM = 0 V, RF = 301 Ω, RG = 301 Ω, RT = 56.2 Ω (when used), RL, dm = 1 kꢁ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 46 for signal definitions.
±±IN to VOUT, dm Performance
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
VOUT, dm = 0.1 V p-p
VOUT, dm = 2.0 V p-p
VOUT, dm = 0.1 V p-p, ADA4927-1
VOUT, dm = 0.1 V p-p, ADA4927-2
VOUT, dm = 2 V step, 25% to 75%
VOUT, dm = 2 V step
VIN = 0 V to 0.9 V step, G = 10
See Figure 45 for distortion test circuit
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p
f = 100 kHz, G = 28
2300
1500
150
120
5000
10
MHz
MHz
MHz
MHz
V/μs
ns
Slew Rate
Settling Time to 0.1%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
10
ns
−105
−91
−87
−103
−98
−89
−94
−85
1.4
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Crosstalk
nV/√Hz
pA/√Hz
dB
f = 100 kHz, G = 28
f = 100 MHz, ADA4927-2
14
−75
INPUT CHARACTERISTICS
Offset Voltage
VIP = VIN = VOCM = 0 V
tMIN to tMAX variation
−1.3
−15
+0.3
1.5
+0.5
0.1
−0.6
14
+1.3
+15
mV
μV/°C
μA
μA/°C
μA
Input Bias Current
tMIN to tMAX variation
Input Offset Current
Input Resistance
−10.5
+10.5
Differential
Ω
Common mode
Differential
120
0.5
kΩ
pF
Input Capacitance
Input Common-Mode Voltage Range
CMRR
−3.5
−70
120
+3.5
+3.8
V
dB
kΩ
∆VOUT, dm/∆VIN, cm, ∆VIN, cm
DC
=
1 V
−93
185
Open-Loop Transresistance
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
Each single-ended output, RF = RG = 10 kΩ
−3.8
V
65
−65
mA p-p
dB
∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, 10 MHz,
see Figure 44 for test circuit
Rev. 0 | Page 3 of 24
ADA4927-1/ADA4927-2
VOCM to VOUT, cm Performance
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
Small Signal −3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
VOCM CMRR
VOUT, cm = 100 mV p-p
VIN = −1.0 V to +1.0 V, 25% to 75%
f = 100 kHz
1300
1000
15
MHz
V/μs
nV/√Hz
3.5
5.0
−2
−97
0.97
V
3.8
7.5
+5.2
kΩ
mV
dB
V/V
VOS, cm = VOUT, cm, VDIN+ = VDIN− = +VS/2
−10
−70
0.90
ΔVOUT, dm/ΔVOCM, ΔVOCM
ΔVOUT, cm/ΔVOCM, ΔVOCM
=
=
1 V
1 V
Gain
1.00
General Performance
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
4.5
11.0
22.1
V
20.0
9.0
mA
μA/°C
mA
dB
tMIN to tMAX variation
Powered down
ΔVOUT, dm/ΔVS, ΔVS = 1 V
2.4
Power Supply Rejection Ratio
POWER-DOWN (PD)
−70
−89
PD Input Voltage
Powered down
Enabled
To 0.1%
<1.8
>3.2
15
V
V
μs
ns
Turn-Off Time
Turn-On Time
To 0.1%
400
PD Pin Bias Current per Amplifier
Enabled
PD = 5 V
PD = 0 V
−2
+2
μA
μA
°C
Disabled
−110
−40
−90
+105
OPERATING TEMPERATURE RANGE
Rev. 0 | Page 4 of 24
ADA4927-1/ADA4927-2
+5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VꢀCM = 2.5 V, RF = 301 Ω, RG = 301 Ω, RT = 56.2 Ω (when used), RL, dm = 1 kꢁ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 46 for signal definitions.
±±IN to VOUT, dm Performance
Table 4.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
VOUT, dm = 0.1 V p-p
VOUT, dm = 2.0 V p-p
VOUT, dm = 0.1 V p-p, ADA4927-1
VOUT, dm = 0.1 V p-p, ADA4927-2
VOUT, dm = 2 V step, 25% to 75%
VOUT, dm = 2 V step
VIN = 0 V to 0.15 V step, G = 10
See Figure 45 for distortion test circuit
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p
f = 100 kHz, G = 28
2000
1300
150
110
4200
10
MHz
MHz
MHz
MHz
V/μs
ns
Slew Rate
Settling Time to 0.1%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
10
ns
−104
−91
−86
−95
−80
−76
−93
−84
1.4
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Crosstalk
nV/√Hz
pA/√Hz
dB
f = 100 kHz, G = 28
f = 100 MHz, ADA4927-2
19
−75
INPUT CHARACTERISTICS
Offset Voltage
VIP = VIN = VOCM = 0 V
tMIN to tMAX variation
−1.3
−30
+0.3
1.5
−12
0.12
−0.8
14
+1.3
+4.0
+10.5
mV
μV/°C
μA
μA/°C
μA
Input Bias Current
tMIN to tMAX variation
Input Offset Current
Input Resistance
−10.5
Differential
Ω
Common mode
Differential
120
0.5
kΩ
pF
Input Capacitance
Input Common-Mode Voltage Range
CMRR
1.3
−70
120
3.7
V
dB
kΩ
∆VOUT, dm/∆VIN, cm, ∆VIN, cm
DC
=
1 V
−96
185
Open-Loop Transresistance
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
Each single-ended output
+1.0
+4.0
V
50
−65
mA p-p
dB
∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, 10 MHz,
see Figure 44 for test circuit
Rev. 0 | Page 5 of 24
ADA4927-1/ADA4927-2
VOCM to VOUT, cm Performance
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
Small signal −3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
VOCM CMRR
VOUT, cm = 100 mV p-p
VIN = 1.5 V to 3.5 V, 25% to 75%
f = 100 kHz
1300
1000
15
MHz
V/μs
nV/√Hz
1.5 to 3.5
5.0
+2.0
−100
0.97
V
3.8
7.5
+10
kΩ
mV
dB
V/V
VOS, cm = VOUT, cm, VDIN+ = VDIN− = +VS/2
−5.0
−70
0.90
ΔVOUT, dm/ΔVOCM, ΔVOCM
ΔVOUT, cm/ΔVOCM, ΔVOCM
=
=
1 V
1 V
Gain
1.00
General Performance
Table 6.
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
4.5
11.0
21.6
V
20
7.0
mA
μA/°C
mA
dB
tMIN to tMAX variation
Powered down
ΔVOUT, dm/ΔVS, ΔVS = 1 V
0.6
Power Supply Rejection Ratio
POWER-DOWN (PD)
−70
−89
PD Input Voltage
Powered down
Enabled
<1.7
>3.0
20
V
V
ꢀs
ns
Turn-Off Time
Turn-On Time
500
PD Pin Bias Current per Amplifier
Enabled
PD = 5 V
PD = 0 V
−2
+2
μA
μA
°C
Disabled
−105
−40
−95
+105
OPERATING TEMPERATURE RANGE
Rev. 0 | Page 6 of 24
ADA4927-1/ADA4927-2
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Table 7.
Parameter
Rating
Supply Voltage
11 V
Power Dissipation
Input Currents +IN, −IN,
See Figure 4
5 mA
PD
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
−65°C to +125°C
−40°C to +105°C
300°C
150°C
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, throughholes, ground, and power
planes reduces θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 4 shows the maximum safe power dissipation in the package
vs. the ambient temperature for the single 16-lead LFCSP (87°C/W)
and the dual 24-lead LFCSP (47°C/W) on a JEDEC standard
4-layer board with the exposed pad soldered to a PCB pad that
is connected to a solid plane.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.
4.5
4.0
3.5
Table 8.
3.0
ADA4927-2
Package Type
θJA
87
47
Unit
°C/W
°C/W
2.5
16-Lead LFCSP (Exposed Pad)
24-Lead LFCSP (Exposed Pad)
2.0
ADA4927-1
1.5
MAXIMUM POWER DISSIPATION
1.0
0.5
0
The maximum safe power dissipation in the ADA4927 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4927. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
ESD CAUTION
Rev. 0 | Page 7 of 24
ADA4927-1/ADA4927-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
PIN 1
INDICATOR
INDICATOR
12 PD
–FB
+IN
–IN
1
2
3
4
–IN1
+FB1
1
2
3
4
5
6
18
17 V
16 –V
15
14
+OUT1
11 –OUT
10 +OUT
ADA4927-1
TOP VIEW
(Not to Scale)
OCM1
+V
ADA4927-2
TOP VIEW
(Not to Scale)
S2
S2
S1
–V
+V
S1
–FB2
+IN2
+FB
9 V
OCM
PD2
13 –OUT2
NOTES
1. CONNECT THE EXPOSED PADDLE TO ANY PLANE
BETWEEN AND INCLUDING +V AND –V
.
S
S
NOTES
1. CONNECT THE EXPOSED PADDLE TO ANY PLANE
BETWEEN AND INCLUDING +V AND –V
Figure 5. ADA4927-1 Pin Configuration
.
S
S
Figure 6. ADA4927-2 Pin Configuration
Table 9. ADA4927-1 Pin Function Descriptions
Table 10. ADA4927-2 Pin Function Descriptions
Pin No.
Mnemonic
Description
Pin No.
Mnemonic
Description
1
−FB
Negative Output for Feedback
Component Connection
Positive Input Summing Node
Negative Input Summing Node
Positive Output for Feedback
Component Connection
Positive Supply Voltage
Output Common-Mode Voltage
Positive Output for Load Connection
Negative Output for Load Connection
Power-Down Pin
1
2
3, 4
5
6
7
8
9, 10
11
12
−IN1
+FB1
+VS1
−FB2
+IN2
−IN2
+FB2
+VS2
VOCM2
+OUT2
−OUT2
PD2
Negative Input Summing Node 1
Positive Output Feedback 1
Positive Supply Voltage 1
Negative Output Feedback 2
Positive Input Summing Node 2
Negative Input Summing Node 2
Positive Output Feedback 2
Positive Supply Voltage 2
Output Common-Mode Voltage 2
Positive Output 2
2
3
4
+IN
−IN
+FB
5 to 8
9
10
11
12
+VS
VOCM
+OUT
−OUT
PD
13
14
Negative Output 2
Power-Down Pin 2
13 to 16
−VS
Negative Supply Voltage
17 (EPAD) Exposed
Pad (EPAD)
Connect the exposed pad to any
plane between and including
+VS and −VS.
15, 16
17
18
19
20
−VS2
Negative Supply Voltage 2
Output Common-Mode Voltage 1
Positive Output 1
Negative Output 1
Power-Down Pin 1
VOCM1
+OUT1
−OUT1
PD1
21, 22
23
24
−VS1
−FB1
+IN1
Negative Supply Voltage 1
Negative Output Feedback 1
Positive Input Summing Node 1
25 (EPAD) Exposed
Pad (EPAD)
Connect the exposed pad to any
plane between and including
+VS and −VS.
Rev. 0 | Page 8 of 24
ADA4927-1/ADA4927-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = −5 V, VꢀCM = 0 V, RG = 301 Ω, RF = 301 Ω, RT = 56.2 ꢁ (when used), RL, dm = 1 kꢁ, unless otherwise noted.
Refer to Figure 43 for basic test setup. Refer to Figure 46 for signal definitions.
3
3
V
,
= 100mV p-p
V
,
= 2V p-p
OUT dm
OUT dm
0
–3
–6
–9
0
–3
–6
–9
G = 1, R = 301Ω
F
G = 1, R = 301Ω
F
G = 10, R = 442Ω
F
G = 10, R = 442Ω
F
G = 20, R = 604Ω
F
G = 20, R = 604Ω
F
–12
–12
1
10
100
FREQUENCY (MHz)
1k
10k
1
10
100
FREQUENCY (MHz)
1k
10k
Figure 7. Small Signal Frequency Response for Various Gains
Figure 10. Large Signal Frequency Response for Various Gains
3
3
V
,
= 100mV p-p
V
,
= 2V p-p
OUT dm
OUT dm
0
0
–3
–3
–6
–9
–6
–9
V
= ±5V
= ±2.5V
V
S
V
S
= ±5V
= ±2.5V
S
V
S
1
10
100
FREQUENCY (MHz)
1k
10k
10
100
1k
10k
FREQUENCY (MHz)
Figure 11. Large Signal Frequency Response for Various Supplies
Figure 8. Small Signal Frequency Response for Various Supplies
3
3
V
,
= 100mV p-p
V
,
= 2V p-p
OUT dm
OUT dm
0
–3
–6
–9
0
–3
–6
–9
T
A
T
A
T
A
+25°C
+105°C
–40°C
T
A
T
A
T
A
+25°C
+105°C
–40°C
–12
–12
1
10
100
FREQUENCY (MHz)
1k
10k
1
10
100
1k
10k
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response for Various Temperatures
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. 0 | Page 9 of 24
ADA4927-1/ADA4927-2
3
3
V
,
= 100mV p-p
V
,
= 2V p-p
OUT dm
OUT dm
0
–3
–6
–9
0
–3
–6
–9
R
R
= 1kΩ
= 200Ω
R
L
R
L
= 200Ω
= 1kΩ
L
L
–12
–12
1
10
100
FREQUENCY (MHz)
1k
10k
1
10
100
1k
10k
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Loads
Figure 16. Large Signal Frequency Response for Various Loads
3
3
V
,
= 100mV p-p
V
,
= 2V p-p
OUT dm
OUT dm
0
–3
–6
–9
0
–3
–6
–9
V
V
V
V
V
= –4V
= –3.5V
= 0V
= +3.5V
= +4V
OCM
OCM
OCM
OCM
OCM
V
V
V
= –3.5V
= 0V
= +3.5V
OCM
OCM
OCM
–12
–12
1
10
100
FREQUENCY (MHz)
1k
10k
1
10
100
FREQUENCY (MHz)
1k
10k
Figure 14. Small Signal Frequency Response at Various VOCM Levels
Figure 17. Large Signal Frequency Response at Various VOCM Levels
3
0.5
V
,
= 100mV p-p
V
,
= 100mV p-p
OUT dm
OUT cm
0.4
0.3
0.2
0.1
0
0
–3
–6
–9
–0.1
V
V
V
V
V
= 0V dc
OCM
OCM
OCM
OCM
OCM
–0.2
–0.3
–0.4
–0.5
= +2.5V dc
= +4.1V dc
= –2.5V dc
= –4.1V dc
V
V
V
V
= ±5V, R = 1kΩ
L
S
S
S
S
= ±2.5V, R = 1kΩ
L
= ±5V, R = 200Ω
L
= ±2.5V, R = 200Ω
L
–12
1
10
100
FREQUENCY (MHz)
1k
5k
1
10
100
1k
FREQUENCY (MHz)
Figure 18. VOCM Small Signal Frequency Response at Various DC Levels
Figure 15. 0.1 dB Flatness Small Signal Frequency Response for Various
Loads and Supplies
Rev. 0 | Page 10 of 24
ADA4927-1/ADA4927-2
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
V
,
= 2V p-p
V
,
= 2V p-p
OUT dm
OUT dm
–90
–100
–110
–120
–130
–90
–100
–110
–120
–130
HD2, G = 1
HD3, G = 1
HD2, G = 10
HD3, G = 10
HD2, G = 20
HD3, G = 20
HD2, R = 1kΩ
L
HD3, R = 1kΩ
L
HD2, R = 200Ω
L
HD3, R = 200Ω
L
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19. Harmonic Distortion vs. Frequency at Various Loads
Figure 22. Harmonic Distortion vs. Frequency at Various Gains
–30
–40
V
,
= 2V p-p
V
,
= 2V p-p
OUT dm
OUT dm
–40
–50
–50
–60
–70
–80
–60
–70
–80
–90
–100
–110
–120
–130
–90
–100
–110
–120
–130
HD2, V = ±5V
S
HD2, V = ±5V
HD3, V = ±5V
S
HD2, V = ±2.5V
S
S
HD3, V = ±5V
S
HD2, V = ±2.5V
S
HD3, V = ±2.5V
S
HD3, V = ±2.5V
S
1
10
100
1k
0
1
2
3
4
5
6
7
8
9
FREQUENCY (MHz)
V
,
(V p-p)
OUT dm
Figure 20. Harmonic Distortion vs. Frequency at Various Supplies
Figure 23. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz
–20
–40
V
,
= 2V p-p
OUT dm
V
,
= 2V p-p
OUT dm
–30
–40
–50
–60
–70
–80
–50
–60
HD2, 10MHz
HD3, 10MHz
–70
–80
–90
–100
–110
–120
–90
–100
–110
–120
HD2, 10MHz
HD3, 10MHz
–4
–3
–2
–1
0
1
2
3
4
–1.2 –1.0 –0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0 1.2
V
(V)
V
(V)
OCM
OCM
Figure 24. Harmonic Distortion vs. VOCM at 10 MHz, 5 V Supplies
Figure 21. Harmonic Distortion vs. VOCM at 10 MHz, 2.5 V Supplies
Rev. 0 | Page 11 of 24
ADA4927-1/ADA4927-2
20
0
–40
V
= ±2.5V
V
,
= 2V p-p
S
OUT dm
–50
–60
–70
–80
–20
–40
–90
–100
–110
–120
–130
–60
–80
HD2, V
HD3, V
HD2, V
HD3, V
,
= 2V p-p
= 2V p-p
= 1V p-p
= 1V p-p
OUT dm
,
–100
OUT dm
,
OUT dm
,
OUT dm
–120
69.6 69.7 69.8 69.9 70.0 70.1 70.2 70.3 70.4 70.5
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. Harmonic Distortion vs. Frequency at Various VOUT, dm
Figure 28. 70 MHz Intermodulation Distortion
–40
–40
V
,
= 2V p-p
OUT dm
INPUT AMP2 TO OUTPUT AMP1
INPUT AMP1 TO OUTPUT AMP2
–50
–60
–50
–60
–70
–80
–70
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
G = 1
G = 10
G = 20
–140
1
10
100
1k
0.1
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 26. Spurious-Free Dynamic Range vs. Frequency at Various Gains
Figure 29. Crosstalk vs. Frequency for ADA4927-2
–20
–40
R ,
= 200Ω
dm
R ,
= 200Ω
dm
L
L
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–30
–40
–50
–60
–70
–80
V
V
= ±5V, –PSRR
= ±5V, +PSRR
S
S
–90
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 30. PSRR vs. Frequency
Figure 27. CMRR vs. Frequency
Rev. 0 | Page 12 of 24
ADA4927-1/ADA4927-2
–30
–40
1k
50
R ,
= 200Ω
dm
L
0
MAGNITUDE
100
–50
–60
–50
10
1
–100
–150
–200
PHASE
–70
–80
0.1
10
1
10
100
1k
100
1k
10k 100k
1M
10M 100M 1G
10G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 31. Output Balance vs. Frequency
Figure 34. Open-Loop Transimpedance Magnitude and Phase vs. Frequency
0
35
R ,
= 200Ω
L
dm
INPUT SINGLE-ENDED, 50Ω LOAD TERMINATION
–10 OUTPUT DIFFERENTIAL, 100Ω SOURCE TERMINATION
V
V
V
V
, V = ±5V
S
OP
ON
OP
ON
30
25
20
15
10
5
, V = ±5V
S
, V = ±2.5V
S
S
S
: COMMON-MODE-TO-COMMON-MODE
: DIFFERENTIAL-TO-DIFFERENTIAL
11
22
, V = ±2.5V
S
–20
–30
–40
–50
–60
S
S
11
22
0
–5
–10
0.1
–70
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 32. Return Loss (S11, S12) vs. Frequency
Figure 35. Closed-Loop Output Impedance Magnitude vs. Frequency at
Various Supplies, G = 1
10
100
V
× 10
IN
V
5
0
,
OUT dm
10
–5
–10
1
10
0
10
20
30
40
50
TIME (ns)
60
70
80
90
100
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 33. Voltage Noise Spectral Density, Referred to Input
Figure 36. Overdrive Recovery, G = 10
Rev. 0 | Page 13 of 24
ADA4927-1/ADA4927-2
60
50
1.0
0.5
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–0.5
–1.0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TIME (ns)
TIME (ns)
Figure 37. Small Signal Pulse Response
Figure 40. Large Signal Pulse Response
60
50
1.5
1.0
40
30
20
0.5
0
10
0
–10
–20
–30
–40
–50
–60
–0.5
–1.0
–1.5
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TIME (ns)
TIME (ns)
Figure 41. VOCM Large Signal Pulse Response
Figure 38. VOCM Small Signal Pulse Response
7
6
5
4
3
2
1
0
2.00
1.75
1.50
1.25
1.2
0.6
1.0
0.8
0.5
0.4
0.6
0.3
0.4
0.2
ERROR
0.2
0.1
1.00
0.75
0.50
0.25
0
0
0
–1
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–2
–3
–4
–5
–6
–7
INPUT
PD
V
,
OUT dm
–0.25
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
–10
0
10
20
30
40
50
60
70
80
90
TIME (µs)
TIME (ns)
PD
Response Time
Figure 39. Settling Time
Figure 42.
Rev. 0 | Page 14 of 24
ADA4927-1/ADA4927-2
TEST CIRCUITS
301Ω
+5V
DC-COUPLED
GENERATOR
50Ω
301Ω
V
IN
56.2Ω
ADA4927
1kΩ
301Ω
0.1µF
–5V
301Ω
Figure 43. Equivalent Basic Test Circuit, G = 1
DIFFERENTIAL
NETWORK
ANALYZER INPUT
NETWORK
ANALYZER
OUTPUT
301Ω
+5V
49.9Ω
50Ω
AC-COUPLED
50Ω
301Ω
V
OCM
56.2Ω
ADA4927
V
IN
301Ω
DIFFERENTIAL
NETWORK
ANALYZER INPUT
0.1µF
–5V
301Ω
49.9Ω
50Ω
Figure 44. Test Circuit for Output Balance, CMRR
301Ω
DC-COUPLED
GENERATOR
+5V
200Ω
50Ω
0.1µF
0.1µF
50Ω
301Ω
442Ω
HP
2:1
DUAL
FILTER
LOW-PASS
FILTER
LP
CT
V
56.2Ω
V
IN
OCM
ADA4927
261Ω
442Ω
301Ω
25.5Ω
0.1µF
–5V
301Ω
Figure 45. Test Circuit for Distortion Measurements
Rev. 0 | Page 15 of 24
ADA4927-1/ADA4927-2
THEORY OF OPERATION
The ADA4927 differs from conventional operational amplifiers
in that it has two outputs whose voltages move in opposite
directions and an additional input, VꢀCM. Moreover, the ADA4927
uses a current feedback architecture. Like a traditional current
feedback op amp, the ADA4927 relies on high open-loop trans-
impedance, T(s), and negative current feedback to force the
outputs to the desired voltages. The ADA4927 behaves much
like a standard current feedback op amp and facilitates single-
ended-to-differential conversions, common-mode level shifting,
and amplifications of differential signals. Also, like a current
feedback op amp, the ADA4927 has low input impedance
summing nodes, which are actually emitter-follower outputs.
The ADA4927 outputs are low impedance, and the closed-loop
output impedances are equal to the open-loop output impedances
divided by a factor of 1 + loop gain. Because it uses current
feedback, the ADA4927 manifests a nominally constant feed-
back resistance, bandwidth product. In other words, the closed-
loop bandwidth and stability of the ADA4927 depend primarily
on the feedback resistor value. The closed-loop gain equations
for typical configurations are the same as those of comparable
voltage feedback differential amplifiers. The chief difference is
that the ADA4927 dynamic performance depends on the feed-
back resistor value rather than on the noise gain. Because of
this, the elements used in the feedback loops must be resistive
with values that ensure stability and sufficient bandwidth.
DEFINITION OF TERMS
–FB
R
F
R
G
+IN
–IN
–OUT
+D
IN
V
R
V
OUT, dm
OCM
L, dm
ADA4927
–D
IN
+OUT
R
G
R
F
+FB
Figure 46. Circuit Definitions
±ifferential Voltage
Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
V
OUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +ꢀUT and
−ꢀUT terminals with respect to a common ground reference.
Similarly, the differential input voltage is defined as
V
IN, dm = (+DIN − (−DIN))
Common-Mode Voltage
Common-mode voltage refers to the average of two node voltages
with respect to the local ground reference. The output
common-mode voltage is defined as
V
OUT, cm = (V+OUT + V−OUT)/2
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback loops
use a current feedback architecture with external resistors and
control only the differential output voltage. The common-mode
feedback loop is internal, uses voltage feedback, and controls only
the common-mode output voltage. This architecture makes it
easy to set the output common-mode level to any arbitrary
value within the specified limits. The output common-mode
voltage is forced, by the internal common-mode loop, to be
equal to the voltage applied to the VꢀCM input.
Balance
ꢀutput balance is a measure of how close the differential signals
are to being equal in amplitude and opposite in phase. ꢀutput
balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the divider midpoint
with the magnitude of the differential signal (see Figure 44). By
this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results
in differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180° apart in phase.
ΔVOUT, cm
Output Balance Error =
ΔVOUT, dm
Rev. 0 | Page 16 of 24
ADA4927-1/ADA4927-2
APPLICATIONS INFORMATION
ANALYZING AN APPLICATION CIRCUIT
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4927 can be estimated
using the noise model in Figure 47. The input-referred noise
voltage density, vnIN, is modeled as a differential input, and the
noise currents, inIN− and inIN+, appear between each input and
ground. The output voltage due to vnIN is obtained by multiplying
The ADA4927 uses high open-loop transimpedance and negative
current feedback to control its differential output voltage in
such a way as to minimize the differential error currents. The
differential error currents are defined as the currents that flow
in and out of the differential inputs labeled +IN and −IN (see
Figure 46). For most purposes, these currents can be assumed
to be zero. The voltage between the +IN and −IN inputs is
internally bootstrapped to 0 V; therefore, the voltages at the
amplifier inputs are equal, and external analysis can be carried
out in a similar fashion to that of voltage feedback amplifiers.
Similarly, the difference between the actual output common-
mode voltage and the voltage applied to VꢀCM can also be assumed
to be zero. Starting from these principles, any application circuit
can be analyzed.
vnIN by the noise gain, GN (defined in the GN equation). The
noise currents are uncorrelated with the same mean-square value,
and each produces an output voltage that is equal to the noise
current multiplied by the associated feedback resistance. The
noise voltage density at the VꢀCM pin is vnCM. When the feedback
networks have the same feedback factor, as in most cases, the
output noise due to vnCM is common mode. Each of the four
resistors contributes (4kTRxx)1/2. The noise from the feedback
resistors appears directly at the output, and the noise from each
gain resistor appears at the output multiplied by RF/RG. Table 11
summarizes the input noise sources, the multiplication factors,
and the output-referred noise density terms.
SETTING THE CLOSED-LOOP GAIN
Using the approach previously described, the differential gain of
the circuit in Figure 46 can be determined by
V
V
nRG1
nRF1
R
R
F1
G1
VOUT, dm
RF
RG
inIN+
=
VIN, dm
+
V
nIN
V
nOD
inIN–
ADA4927
This presumes that the input resistors (RG) and feedback
resistors (RF) on each side are of equal value.
V
OCM
V
nCM
R
R
F2
G2
V
V
nRG2
nRF2
Figure 47. Noise Model
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise
Voltage Density
Output
Multiplication Factor
Differential Output Noise
Voltage Density Term
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor, RG1
Gain Resistor, RG2
Feedback Resistor, RF1
Feedback Resistor, RF2
Input Noise Term
vnIN
inIN
inIN
vnCM
vnRG1
vnRG2
vnRF1
vnRF2
vnIN
inIN × (RF2)
inIN × (RF1)
GN
1
1
0
RF1/RG1
RF2/RG2
1
1
vnO1 = GN(vnIN)
vnO2 = (inIN)(RF2)
vnO3 = (inIN)(RF1)
vnO4 = 0
vnO5 = (RF1/RG1)(4kTRG1
vnO6 = (RF2/RG2)(4kTRG2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
vnCM
(4kTRG1
(4kTRG2
1/2
1/2
1/2
)
)
)
)
1/2
(4kTRF1)1/2
(4kTRF2)1/2
Rev. 0 | Page 17 of 24
ADA4927-1/ADA4927-2
Table 12. Differential Input, DC-Coupled
Nominal Gain (dB)
RF (Ω)
RG (Ω)
RIN, dm (Ω)
602
Differential Output Noise Density (nV/√Hz)
0
301
301
8.0
20
26
442
604
44.2
30.1
88.4
60.2
21.8
37.9
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω
Nominal Gain (dB)
RF (Ω) RG1 (Ω)
RT (Ω) RIN, cm (Ω)
RG2 (Ω)1
328
77.2
74.4
Differential Output Noise Density (nV/√Hz)
0
20
26
309
511
806
301
39.2
28
56.2
158
649
401
73.2
54.2
8.1
18.6
29.1
1 RG2 = RG1 + (RS||RT).
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by the appropriate output factor,
The feedback loops are nominally matched to within 1% in
most applications, and the output noise and offsets due to the
VꢀCM input are negligible. If the loops are intentionally mismatched
by a large amount, it is necessary to include the gain term from
where:
2
VꢀCM to Vꢀ, dm and account for the extra noise. For example, if
GN
=
is the circuit noise gain.
β1 = 0.5 and β2 = 0.25, the gain from VꢀCM to Vꢀ, dm is 0.67. If the
VꢀCM pin is set to 2.5 V, a differential offset voltage is present at the
output of (2.5 V)(0.67) = 1.67 V. The differential output noise
contribution is (15 nV/√Hz)(0.67) = 10 nV/√Hz. Both of these
results are undesirable in most applications; therefore, it is best
to use nominally matched feedback factors.
(
β1 + β2
RG1
)
RG2
β1 =
and β2 =
are the feedback factors.
RF1 + RG1
RF2 + RG2
When the feedback factors are matched, RF1/RG1 = RF2/RG2,
β1 = β2 = β, and the noise gain becomes
Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
1
β
RF
RG
GN
=
=1+
Note that the output noise from VꢀCM goes to zero in this case.
The total differential output noise density, vnꢀD, is the root-sum-
square of the individual output noise terms.
As a practical summarization of the previous issues, resistors of
1% tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 25 mV
due to a 2.5 V VꢀCM input, negligible VꢀCM noise contribution,
and no significant degradation in output balance error.
8
vnOD
=
v2
nOi
∑
i=1
Table 12 and Table 13 list several common gain settings, associated
resistor values, input impedance, and output noise density for
both balanced and unbalanced input configurations.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 48, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = RG + RG = 2 × RG.
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
R
F
+V
S
R
G
G
+IN
+D
–D
IN
V
OCM
V
ADA4927
The gain from the VꢀCM pin to Vꢀ, dm is equal to
2(β1 − β2)/(β1 + β2)
OUT, dm
IN
–IN
R
–V
S
When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the VꢀCM input (including
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from VꢀCM input
to Vꢀ, dm is either +2 or −2, depending on which loop is closed.
R
F
Figure 48. The ADA4927 Configured for Balanced (Differential) Inputs
Rev. 0 | Page 18 of 24
ADA4927-1/ADA4927-2
R
F
For an unbalanced, single-ended input signal (see Figure 49),
the input impedance is
348Ω
+V
R
IN
464Ω
S
⎛
⎜
⎞
⎟
R
R
S
G
RG
RF
RG + RF
50Ω
348Ω
⎜
⎜
⎟
⎟
RIN, SE
=
V
S
V
OCM
ADA4927
R
V
OUT, dm
2V p-p
L
1−
⎜
⎟
2×
(
)
R
G
⎝
⎠
348Ω
R
F
–V
S
+V
R
S
IN, SE
R
F
R
348Ω
G
Figure 50. Calculating Single-Ended Input Impedance RIN
V
OCM
ADA4927
R
V
OUT, dm
L
2. To match the 50 ꢁ source resistance, the termination
resistor, RT, is calculated using RT||464 ꢁ = 50 ꢁ. The
closest standard 1% value for RT is 56.2 ꢁ.
R
G
–V
S
R
F
R
F
348Ω
+V
R
IN
50Ω
Figure 49. The ADA4927 with Unbalanced (Single-Ended) Input
S
R
R
S
G
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG. The common-mode
voltage at the amplifier input terminals can be easily determined
by noting that the voltage at the inverting input is equal to the
noninverting output voltage divided down by the voltage divider
formed by RF and RG in the lower loop. This voltage is present at
both input terminals due to negative voltage feedback and is in
phase with the input signal, thus reducing the effective voltage
across RG in the upper loop and partially bootstrapping RG.
50Ω
348Ω
R
56.2Ω
T
V
S
V
OCM
ADA4927
R
V
OUT, dm
2V p-p
L
R
G
348Ω
–V
S
R
F
348Ω
Figure 51. Adding Termination Resistor RT
3.
It can be seen from Figure 51 that the effective RG in the
upper feedback loop is now greater than the RG in the
lower loop due to the addition of the termination resistors.
To compensate for the imbalance of the gain resistors,
a correction resistor (RTS) is added in series with RG in the
lower loop. RTS is equal to the Thevenin equivalent of the
source resistance RS and the termination resistance RT and
is equal to RS||RT.
Terminating a Single-Ended Input
This section deals with how to properly terminate a single-
ended input to the ADA4927 with a gain of 1, RF = 348 ꢁ, and
RG = 348 ꢁ. An example using an input source with a terminated
output voltage of 1 V p-p and a source resistance of 50 ꢁ illustrates
the four simple steps that must be followed. Note that, because
the terminated output voltage of the source is 1 V p-p, the open
circuit output voltage of the source is 2 V p-p. The source shown
in Figure 50 indicates this open-circuit voltage.
R
R
S
TH
50Ω
R
56.2Ω
26.5Ω
T
V
V
S
TH
1.06V p-p
2V p-p
Figure 52. Calculating the Thevenin Equivalent
1. The input impedance must be calculated using the following
formula:
⎛
⎜
⎞
⎟
⎛
⎜
⎞
⎟
RG
RF
2×(RG + RF )
348
348
2×( 348 + 348)
⎜
⎜
⎟
⎟
⎜
⎜
⎟
⎟
RIN =
=
= 464Ω
1−
1−
⎜
⎟
⎜
⎟
⎝
⎠
⎝
⎠
Rev. 0 | Page 19 of 24
ADA4927-1/ADA4927-2
R
F
RTS = RTH = RS||RT = 26.5 ꢁ. Note that VTH is greater than
1 V p-p, which was obtained with RT = 50 ꢁ. The modified
circuit with the Thevenin equivalent (closest 1% value used for
RTH) of the terminated source and RTS in the lower feedback
loop is shown in Figure 53.
357Ω
+V
1V p-p
S
R
R
S
G
50Ω
348Ω
R
T
V
S
56.2Ω
V
OUT, dm
1.01V p-p
V
OCM
ADA4927
R
2V p-p
L
R
F
R
G
348Ω
+V
348Ω
R
TS
26.7Ω
S
R
R
–V
S
TH
G
R
F
26.7Ω
348Ω
V
TH
1.06V p-p
357Ω
V
OCM
V
OUT, dm
ADA4927
R
L
Figure 54. Terminated Single-Ended-to-Differential System with G = 1
R
G
348Ω
R
TS
26.7Ω
INPUT COMMON-MODE VOLTAGE RANGE
–V
S
The ADA4927 input common-mode range is centered between the
two supply rails, in contrast to other ADC drivers with level-shifted
input ranges, such as the ADA4937. The centered input common-
mode range is best suited to ac-coupled, differential-to-differential,
and dual supply applications.
R
F
348Ω
Figure 53. Thevenin Equivalent and Matched Gain Resistors
Figure 53 presents a tractable circuit with matched
feedback loops that can be easily evaluated.
For operation with 5 V supplies, the input common-mode
range at the summing nodes of the amplifier is specified as
−3.5 V to +3.5 V and is specified as +1.3 V to +3.7 V with a
single +5 V supply. To avoid nonlinearities, the voltage swing
at the +IN and −IN terminals must be confined to these ranges.
It is useful to point out two effects that occur with a
terminated input. The first is that the value of RG is increased
in both loops, lowering the overall closed-loop gain. The
second is that VTH is a little larger than 1 V p-p, as it is
when RT = 50 ꢁ. These two effects have opposite impacts
on the output voltage, and for large resistor values in the
feedback loops (~1 kꢁ), the effects essentially cancel each
other out. For small RF and RG, or high gains, however, the
diminished closed-loop gain is not canceled completely by the
increased VTH. This can be seen by evaluating Figure 53.
INPUT AND OUTPUT CAPACITIVE AC COUPLING
Input ac coupling capacitors can be inserted between the source
and RG. This ac coupling blocks the flow of the dc common-
mode feedback current and causes the ADA4927 dc input
common-mode voltage to equal the dc output common-mode
voltage. These ac coupling capacitors must be placed in both
loops to keep the feedback factors matched.
The desired differential output in this example is 1 V p-p
because the terminated input signal is 1 V p-p and the
closed-loop gain = 1. The actual differential output voltage,
however, is equal to (1.06 V p-p)(348/374.7) = 0.984 V p-p.
To obtain the desired output voltage of 1 V p-p, a final gain
adjustment can be made by increasing RF without modifying
any of the input circuitry. This is discussed in Step 4.
ꢀutput ac coupling capacitors can be placed in series between
each output and its respective load. See Figure 58 for an example
that uses input and output capacitive ac coupling.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VꢀCM pin of the ADA4927 is internally biased with a voltage
divider comprising two 10 kꢁ resistors at a voltage approximately
equal to the midsupply point, [(+VS) + (−VS)]/2. Because of this
internal divider, the VꢀCM pin sources and sinks current, depending
on the externally applied voltage and its associated source resistance.
Relying on the internal bias results in an output common-mode
voltage that is within about 100 mV of the expected value.
In cases where accurate control of the output common-mode level
is required, it is recommended that an external source or resistor
divider be used with source resistance less than 100 ꢁ. The output
common-mode offset listed in the Specifications section presumes
that the VꢀCM input is driven by a low impedance voltage source.
It is also possible to connect the VꢀCM input to a common-mode
level (CML) output of an ADC; however, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VꢀCM pin is approximately 10 kꢁ. If multiple
ADA4927 devices share one ADC reference output, a buffer may
be necessary to drive the parallel inputs.
4. The feedback resistor value is modified as a final gain
adjustment to obtain the desired output voltage.
To make the output voltage VꢀUT = 1 V p-p, RF must be
calculated using the following formula:
RF =
(
Desired VOUT,dm
)
(
RG + RTS
)
(
)(
)
= 35
1V p − p 374.7Ω
=
VTH
1.06V p − p
The closest standard 1% values to 353 ꢁ are 348 ꢁ and
357 ꢁ. Choosing 357 ꢁ for RF gives a differential output
voltage of 1.01 V p-p. The closed-loop bandwidth is
diminished by a factor of approximately 348/357 from
what it would be with RF = 348 ꢁ due to the inversely
proportional relationship between RF and closed-loop
gain that is characteristic of current feedback amplifiers.
The final circuit is shown in Figure 54.
Rev. 0 | Page 20 of 24
ADA4927-1/ADA4927-2
Power-±own in Cold Applications
POWER-DOWN
The power-down feature should not be used in applications in
which the ambient temperature falls below 0°C. Contact sales
for information regarding applications that require the power-
down feature to be used at ambient temperatures below 0°C.
The power-down feature can be used to reduce power
consumption when a particular device is not in use and does
not place the output in a high-Z state when asserted. The
ADA4927 is generally enabled by pulling the power-down pin
to the positive supply. See the Specifications tables for the
specific voltages required to assert and deassert the power-
down feature.
Rev. 0 | Page 21 of 24
ADA4927-1/ADA4927-2
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4927 is sensitive to the PCB
environment in which it operates. Realizing its superior performance
requires attention to the details of high speed PCB design. This
section shows a detailed example of how the ADA4927-1 was
addressed.
Bypassed the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended that two parallel bypass
capacitors (1000 pF and 0.1 μF) be used for each supply. The
1000 pF capacitor should be placed closer to the device. Further
away, provide low frequency bulk bypassing, using 10 μF
tantalum capacitors from each supply to ground.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4927-1 as possible.
However, clear the area near the feedback resistors (RF), gain
resistors (RG), and the input summing nodes (Pin 2 and Pin 3) of
all ground and power planes (see Figure 55). Clearing the ground
and power planes minimizes any stray capacitance at these nodes
and prevents peaking of the response of the amplifier at high
frequencies. Whereas ideal current feedback amplifiers are
insensitive to summing node capacitance, real-world amplifiers
can exhibit peaking due to excessive summing node capacitance.
Make signal routing short and direct to avoid parasitic effects.
Wherever complementary signals exist, provide a symmetrical
layout to maximize balanced performance. When routing
differential signals over a long distance, place PCB traces close
together, and twist any differential wiring such that the loop
area is minimized. Doing this reduces radiated energy and
makes the circuit less susceptible to interference.
1.30
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7.
0.80
1.30 0.80
Figure 56. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
Figure 55. Ground and Power Plane Voiding in Vicinity of RF AND RG
1.30
TOP METAL
GROUND PLANE
0.30
PLATED
VIA HOLE
POWER PLANE
BOTTOM METAL
Figure 57. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
Rev. 0 | Page 22 of 24
ADA4927-1/ADA4927-2
HIGH PERFORMANCE ADC DRIVING
The ADA4927 is ideally suited for high gain, broadband ac-
coupled and differential-to-differential applications on a single
supply, though other applications are possible. Compared with
voltage feedback amplifiers, the current feedback architecture
provides superior distortion and bandwidth performance at
high gains. This is because the ideal current feedback amplifier
loop gain depends only on the feedback value and open-loop
transimpedance, T(s).
In this example, the signal generator has a 1 V p-p symmetric,
ground-referenced bipolar output when terminated in 50 ꢁ.
The VꢀCM pin of the ADA4927 is bypassed for noise reduction
and left floating such that the internal divider sets the output
common-mode voltage nominally at midsupply. Because the
inputs are ac-coupled, no dc common-mode current flows in
the feedback loops, and a nominal dc level of midsupply is
present at the amplifier input terminals. Besides placing the
amplifier inputs at their optimum levels, the ac coupling technique
lightens the load on the amplifier and dissipates less power than
applications with dc-coupled inputs.
The circuit in Figure 58 shows a front-end connection for an
ADA4927 driving an AD9445, 14-bit, 105 MSPS ADC, with ac
coupling on the ADA4927 input and output. (The AD9445
achieves its optimum performance when driven differentially.)
The ADA4927 eliminates the need for a transformer to drive
the ADC and performs a single-ended-to-differential conversion
and buffering of the driving signal.
The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.
The ADA4927 is configured with a single 5 V supply and gain
of 10 for a single-ended input to differential output. The 158 ꢁ
termination resistor, in parallel with the single-ended input
impedance of approximately 73.2 ꢁ, provides a 50 ꢁ termination
for the source. The additional 38.3 ꢁ at the inverting input closely
matches the parallel impedance of the 50 ꢁ source and the
termination resistor driving the noninverting input. Because of the
high gain, a few iterations of the termination technique described
in the Terminating a Single-Ended Input section are required.
Two objectives of the design are to make RF close to 500 ꢁ and
obtain resistor values that are close to standard 1% values.
The AD9445 is configured for a 2 V p-p full-scale input by
connecting the SENSE pin to AGND, as shown in Figure 58.
5V (A) 3.3V (A) 3.3V (D)
511Ω
5V
AVDD2 AVDD1 DRVDD
30nH
0.1µF
0.1µF
0.1µF
39.2Ω
50Ω
VIN–
47pF
VIN+
AD9445
+
BUFFER T/H
24.3Ω
24.3Ω
V
158Ω
OCM
ADA4927
14
ADC
39.2Ω
SIGNAL
GENERATOR
30nH
0.1µF
0.1µF
CLOCK/
TIMING
REF
38.3Ω
511Ω
AGND
SENSE
Figure 58. ADA4927 Driving an AD9445 ADC with AC-Coupled Input and Output
Rev. 0 | Page 23 of 24
ADA4927-1/ADA4927-2
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
13
16
1
0.45
(BOTTOM VIEW)
12
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 59. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad (CP-16-2)
Dimensions shown in millimeters
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
PIN 1
INDICATOR
0.50
BSC
2.25
TOP
VIEW
3.75
BSC SQ
EXPOSED
2.10 SQ
1.95
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
6
13
12
7
0.25 MIN
0.80 MAX
0.65TYP
2.50 REF
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 60. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad (CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Package Option
CP-16-2
CP-16-2
Ordering Quantity
Branding
H1M
H1M
ADA4927-1YCPZ-R21
ADA4927-1YCPZ-RL1
ADA4927-1YCPZ-R71
ADA4927-2YCPZ-R21
ADA4927-2YCPZ-RL1
ADA4927-2YCPZ-R71
250
5,000
1,500
250
5,000
1,500
CP-16-2
H1M
CP-24-1
CP-24-1
CP-24-1
1 Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07574-0-10/08(0)
Rev. 0 | Page 24 of 24
相关型号：
ADA4927-1XCPZ
IC LINE DRIVER, QCC16, 3 X 3 MM, ROHS COMPLIANT, MO-220VEED2, LFCSP-16, Line Driver or Receiver
ADI
©2020 ICPDF网 联系我们和版权申明