ADA4899-1YRDZ-RL [ADI]
Unity Gain Stable, Ultralow Distortion, 1 nV/ Hz Voltage Noise, High Speed Op Amp; 单位增益稳定，超低失真， 1内华达州/ Hz的电压噪声，高速运算放大器
| 型号： | ADA4899-1YRDZ-RL |
| 厂家： | 
ADI |
| 描述： | Unity Gain Stable, Ultralow Distortion, 1 nV/ Hz Voltage Noise, High Speed Op Amp |
| 文件： | 总20页 (文件大小：622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Unity Gain Stable, Ultralow Distortion,
1 nV/√Hz Voltage Noise, High Speed Op Amp
ADA4899-1
FEATURES
CONNECTION DIAGRAMS
Unity gain stable
ADA4899-1
1
2
3
4
8
7
6
5
DISABLE
FEEDBACK
–IN
+V
Ultralow noise: 1 nV/√Hz, 2.6 pA/√Hz
Ultralow distortion −117 dBc at 1 MHz
High speed
−3 dB bandwidth: 600 MHz (G = +1)
Slew rate: 310 V/μs
S
V
OUT
NC
–V
+IN
S
Offset voltage: 230 μV maximum
Low input bias current: 100 nA
Wide supply voltage range: 5 V to 12 V
Supply current: 14.7 mA
High performance pinout
Disable mode
NC = NO CONNECT
Figure 1. 8-Lead LFCSP_VD (CP-8-2)
ADA4899-1
1
2
3
4
8
7
6
5
FEEDBACK
–IN
DISABLE
+V
S
+IN
V
OUT
APPLICATIONS
A-to-D drivers
–V
–V
S
S
Instrumentation
Filters
Figure 2. 8-Lead SOIC_N_EP (RD-8-1)
IF and baseband amplifiers
DAC buffers
Optical electronics
GENERAL DESCRIPTION
The ADA4899-1 is an ultralow noise (1 nV/√Hz) and distortion
(<−117 dBc @1 MHz) unity gain stable voltage feedback op
amp, the combination of which makes it ideal for 16-bit and
18-bit systems. The ADA4899-1 features a linear, low noise
input stage and internal compensation that achieves high slew
rates and low noise even at unity gain. ADI’s proprietary next
generation XFCB process and innovative circuit design enable
such high performance amplifiers.
The ADA4899-1 is available in a 3 mm × 3 mm LFCSP and a
8-lead SOIC package. Both packages feature an exposed metal
paddle that improves heat transfer to the ground plane. This is a
significant improvement over traditional plastic packages. The
ADA4899-1 is rated to work over the extended industrial
temperature range, −40°C to +125°C.
–40
G = +1
V
R
V
= ±5V
= 1kΩ
S
–50
–60
L
= 2V p-p
OUT
The ADA4899-1 drives 100 Ω loads at breakthrough performance
levels with only 15 mA of supply current. With the wide supply
voltage range (4.5 V to 12 V), low offset voltage (230 μV
maximum), wide bandwidth (600 MHz), and slew rate
(310 V/μs), the ADA4899-1 is designed to work in the most
demanding applications. The ADA4899-1 also features an input
bias current cancellation mode, which reduces input bias
current by a factor of 60.
–70
–80
HD3
–90
HD2
–100
–110
–120
–130
0.1
1
10
FREQUENCY (MHz)
100
Figure 3. Harmonic Distortion vs. Frequency
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADA4899-1
TABLE OF CONTENTS
Features .............................................................................................. 1
Packaging Innovation ................................................................ 13
DISABLE
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications with 5 V Supply..................................................... 3
Specifications with +5 V Supply..................................................... 4
Absolute Maximum Ratings............................................................ 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits ..................................................................................... 12
Theory of Operation ...................................................................... 13
Pin .............................................................................. 13
Applications..................................................................................... 14
Unity Gain Operation................................................................ 14
Recommended Values for Various Gains................................ 14
Noise ............................................................................................ 15
ADC Driver................................................................................. 15
DISABLE
Pin Operation ........................................................... 16
ADA4899-1 MUX ...................................................................... 16
Circuit Considerations .............................................................. 16
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
4/06—Rev. 0 to Rev. A
Changes to Figure 2.......................................................................... 1
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADA4899-1
SPECIFICATIONS WITH ± ± V SUPPLY
TA = 25°C, G = +1, RL = 1 kΩ to ground, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
VOUT = 25 mV p-p
VOUT = 2 V p-p
G = +2, VOUT = 2 V p-p
VOUT = 5 V step
600
80
35
310
50
MHz
MHz
MHz
V/μs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
VOUT = 2 V step
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3
fC = 500 kHz, VOUT = 2 V p-p
fC = 10 MHz, VOUT = 2 V p-p
f = 100 kHz
f = 100 kHz, DISABLE pin floating
f = 100 kHz, DISABLE pin = +VS
−123/−123
−80/−86
1.0
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
Input Voltage Noise
Input Current Noise
2.6
5.2
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
35
5
−6
−0.1
3
230
μV
μV/°C
μA
DISABLE pin floating
DISABLE pin = +VS
−12
−1
μA
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
nA/°C
μA
dB
0.05
85
0.7
82
98
INPUT CHARACTERISTICS
Input Resistance
Differential mode
Common mode
4
7.3
4.4
kΩ
MΩ
pF
V
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
DISABLE PIN
−3.7 to +3.7
130
dB
DISABLE Input Threshold Voltage
Turn-Off Time
Output disabled
<2.4
100
V
50% of DISABLE voltage to 10% of VOUT
,
ns
VIN = 0.5 V
Turn-On Time
50% of DISABLE voltage to 90% of VOUT
,
40
ns
VIN = 0.5 V
Input Bias Current
DISABLE = +VS (enabled)
17
21
μA
μA
DISABLE = −VS (disabled)
−44
−35
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time (Rise/Fall)
Output Voltage Swing
VIN = −2.5 V to +2.5 V, G = +2
RL = 1 kΩ
30/50
ns
V
−3.65 to +3.65 −3.7 to +3.7
RL = 100 Ω
−3.13 to +3.15 −3.25 to +3.25
V
Short-Circuit Current
Off Isolation
Sinking/sourcing
f = 1 MHz, DISABLE = −VS
160/200
−48
mA
dB
POWER SUPPLY
Operating Range
4.5
12
V
Quiescent Current
14.7
1.8
16.2
2.1
mA
mA
dB
dB
Quiescent Current (Disabled)
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
DISABLE = −VS
+VS = 4 V to 6 V (input referred)
−VS = −6 V to −4 V (input referred)
84
87
90
93
Rev. A | Page 3 of 20
ADA4899-1
SPECIFICATIONS WITH +± V SUPPLY
VS = 5 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
VOUT = 25 mV p-p
VOUT = 2 V p-p
G = +2, VOUT = 2 V p-p
VOUT = 2 V step
535
60
25
185
50
MHz
MHz
MHz
V/μs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
VOUT = 2 V step
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3
fC = 500 kHz, VOUT = 1 V p-p
fC = 10 MHz, VOUT = 1 V p-p
f = 100 kHz
f = 100 kHz, DISABLE pin floating
f = 100 kHz, DISABLE pin = +VS
−100/−113
−89/−100
1.0
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
Input Voltage Noise
Input Current Noise
2.6
5.2
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
5
5
210
−12
μV
μV/°C
μA
DISABLE pin floating
DISABLE pin = +VS
−6
−0.2
0.05
2.5
80
−1.5 μA
μA
Input Bias Offset Current
Input Bias Offset Current Drift
Open-Loop Gain
nA/°C
dB
76
90
INPUT CHARACTERISTICS
Input Resistance
Differential mode
Common mode
4
7.7
4.4
1.3 to 3.7
114
kΩ
MΩ
pF
V
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
DISABLE PIN
dB
DISABLE Input Threshold Voltage
Turn-Off Time
Output disabled
<2.4
100
V
50% of DISABLE voltage to 10% of VOUT
,
,
ns
VIN = 0.5 V
50% of DISABLE voltage to 90% of VOUT
VIN = 0.5 V
Turn-On Time
60
ns
Input Bias Current
DISABLE = +VS (enabled)
16
18
μA
μA
DISABLE = −VS (disabled)
−42
−33
OUTPUT CHARACTERISTICS
Overdrive Recovery Time (Rise/Fall)
Output Voltage Swing
VIN = 0 V to 2.5 V, G = +2
RL = 1 kΩ
50/70
ns
V
1.25 to 3.75 1.2 to 3.8
RL = 100 Ω
Sinking/sourcing
f = 1 MHz, DISABLE = −VS
1.4 to 3.6
1.35 to 3.65
60/80
−48
V
mA
dB
Short-Circuit Current
Off Isolation
POWER SUPPLY
Operating Range
Quiescent Current
4.5
84
12
16
1.7
V
14.3
1.5
90
mA
mA
dB
dB
Quiescent Current (Disabled)
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio +VS = 5 V, −VS= −0.5 V to +0.5 V (input referred) 86
DISABLE = −VS
+VS = 4.5 V to 5.5 V, −VS = 0 V (input referred)
90
Rev. A | Page 4 of 20
ADA4899-1
ABSOLUTE MAXIMUM RATINGS
Table 3.
The difference between the total drive power and the load
power is the drive power dissipated in the package.
Parameter
Rating
Supply Voltage
12.6 V
PD = Quiescent Power + (Total Drive Power – Load Power)
Power Dissipation
See Figure 4
1.2 V
2
Differential Input Voltage
Differential Input Current
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VS VOUT
VOUT
RL
PD =
(
VS ×IS
)
+
×
–
10 mA
2
RL
–65°C to +150°C
–40°C to +125°C
300°C
RMS output voltages should be considered. If RL is referenced to
VS–, as in single-supply operation, then the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply:
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2
VS /4
RL
)
PD =
(
VS ×IS +
)
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. Soldering the exposed paddle to the ground
plane significantly reduces the overall thermal resistance of the
package.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4899-1
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4899-1.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in silicon devices, potentially
causing failure.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(e-pad) SOIC-8 (70°C/W) and LFCSP (70°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
4.0
3.5
3.0
2.5
2.0
The still-air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as
TJ = TA + (PD × θJA)
1.5
LFCSP AND SOIC
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
1.0
0.5
0.0
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 20
ADA4899-1
TYPICAL PERFORMANCE CHARACTERISTICS
3
3
0
V
= ±5V
G = +1
S
G = +1
R
= 100Ω
R
V
= 1kΩ
L
L
V
= 25mV p-p
= 25mV p-p
OUT
OUT
G = –1
0
–3
G = +2
G = +5
–3
–6
–9
–12
V
= ±5V
S
G = +10
–6
V
= +5V
S
–9
–12
1
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response for Various Supply Voltages
Figure 5. Small Signal Frequency Response for Various Gains
3
6
C
R
= 15pF
L
V
R
V
= ±5V
= 100Ω
G = +1
S
C
= 15pF
L
= 10Ω
R
V
= 1kΩ
SNUB
L
L
G = +1
G = –1
= 25mV p-p
= 25mV p-p
OUT
OUT
3
0
0
–3
C = 5pF
L
C
= 2pF
L
G = +2
G = +5
C
= 0pF
L
–3
–6
–9
–12
G = +10
–6
–9
–12
1
10
100
1000
10
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response for Various Gains
Figure 9. Small Signal Frequency Response for Capacitive Loads
3
5.0
V
V
= ±5V
S
T = +125°C
= 25mV p-p
OUT
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
G = +1
= 100Ω
G = +1
R
0
L
R
= 1kΩ
L
G = +1
V
= ±5V
T = –40°C
S
R
= 1kΩ
–3
–6
L
V
= 25mV p-p
OUT
G = +1
R
R
= 1kΩ
L
= 10Ω
SNUB
G = +2
R
= 1kΩ
L
–9
–12
10
100
1000
0
5
10
15
20
25
30
35
40
45
FREQUENCY (MHz)
CAPACITIVE LOAD (pF)
Figure 7. Small Signal Frequency Response for Various Temperatures
Figure 10. Small Signal Frequency Response Peaking vs.
Capacitive Load for Various Gains
Rev. A | Page 6 of 20
ADA4899-1
0.1
0
3
0
G = +1
V
= ±5V
S
R
= 100Ω
L
V
= 1V p-p
OUT
–0.1
–0.2
–0.3
–0.4
–0.5
V
= 4V p-p
OUT
V
= 100mV p-p
OUT
–3
–6
–9
–12
V
= 7V p-p
OUT
V
= 2V p-p
OUT
G = +2
V
= ±5V
S
R
= 150Ω
L
1
10
FREQUENCY (MHz)
100
1
10
100
1000
FREQUENCY (MHz)
Figure 11. 0.1 dB Flatness for Various Output Voltages
Figure 14. Large Signal Frequency Response for Various Output Voltages
3
0
100
80
60
40
20
0
180
150
120
90
G = +1
V
R
= ±5V
= 100Ω
S
R
= 1kΩ
L
L
V
= 2V p-p
OUT
V
= ±5V
S
–3
–6
–9
–12
V
= +5V
S
60
30
–20
0
10
100
FREQUENCY (MHz)
1000
0.001
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 15. Open-Loop Gain/Phase vs. Frequency
Figure 12. Large Signal Frequency Response for Various Supply Voltages
1k
100
10
10
1
DISABLE = 5V
DISABLE = NC
1
10
0.1
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. Input Current Noise vs. Frequency
Figure 13. Voltage Noise vs. Frequency
Rev. A | Page 7 of 20
ADA4899-1
–40
–40
–50
G = +1
G = +5
V
= ±5V
R
= 1kΩ
S
L
–50
–60
R
= 1kΩ
V
V
= ±5V
L
S
V
= 2V p-p
= 2V p-p
OUT
OUT
–60
–70
–70
–80
–80
HD3
–90
HD2
HD2
–90
–100
–110
–120
–130
–100
–110
–120
HD3
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 20. Harmonic Distortion vs. Frequency
Figure 17. Harmonic Distortion vs. Frequency
–40
–50
–40
–50
G = +5
= ±5V
G = +1
= 1kΩ
f = 5MHz
V
R
S
L
R
= 100Ω
L
V
= 2V p-p
OUT
HD2
SOIC
–60
–60
–V ON PIN 4
S
–70
–70
HD2
LFCSP
HD2
SOIC
–80
–80
–V ON PIN 5
HD2
S
–90
–90
HD3
–100
–110
–120
HD3
–100
–110
–120
SOIC
HD3
LFCSP
–V ON PIN 4 OR PIN 5
S
0.1
10
10
100
1
2
3
4
5
6
7
8
FREQUENCY (MHz)
OUTPUT AMPLITUDE (V p-p)
Figure 18. Harmonic Distortion vs. Output Amplitude
Figure 21. Harmonic Distortion vs. Frequency for
Various Pinouts and Packages
–40
–50
–40
–50
G = +1
G = +1
R
V
= 1kΩ
= 5V
V
= ±5V
L
S
R
= 100Ω
S
L
V
= 2V p-p
OUT
–60
–60
HD3
–70
–70
V
= 2V p-p
OUT
HD2
–80
–80
HD2
SOIC
HD2
LFCSP
–90
–90
HD2
HD3
–100
–110
–120
–100
–110
–120
HD3
V
= 1V p-p
OUT
LFCSP OR SOIC
0.1
1
10
FREQUENCY (MHz)
100
0.1
10
10
100
FREQUENCY (MHz)
Figure 19. Harmonic Distortion vs. Frequency
Figure 22. Harmonic Distortion vs. Frequency for Both Packages
Rev. A | Page 8 of 20
ADA4899-1
0.10
0.08
0.06
0.04
0.02
0
0.10
0.08
0.06
0.04
0.02
0
G = +1
G = +1
C
= 15pF
C = 5pF
L
L
V
= ±5V
V
= ±5V
S
S
C
R
= 15pF
L
R
= 1kΩ
R
= 1kΩ
L
L
= 10Ω
SNUB
C
= 0pF
L
C
= 15pF
L
–0.02
–0.04
–0.06
–0.08
–0.10
–0.02
–0.04
–0.06
–0.08
–0.10
C
= 0pF
L
C
R
= 15pF
L
= 10Ω
SNUB
C
= 5pF
10
L
0
5
10
15
0
5
15
TIME (ns)
TIME (ns)
Figure 23. Small Signal Transient Response for
Various Capacitive Loads (Rising Edge)
Figure 26. Small Signal Transient Response for
Various Capacitive Loads (Falling Edge)
0.08
0.06
0.04
0.02
0
1.5
1.0
R
V
= 1kΩ
= ±5V
L
S
R
V
= 1kΩ
= ±5V
G = +2
L
S
G = +2
G = +10
G = +5
G = +5
0.5
G = +10
0
–0.02
–0.04
–0.06
–0.08
–0.5
–1.0
–1.5
0
10
20
30
40
50
TIME (ns)
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
Figure 24. Small Signal Transient Response for Various Gains
Figure 27. Large Signal Transient Response for Various Gains
1.5
1.5
G = +1
G = +1
R
= 100Ω
R = 1kΩ
L
L
1.0
0.5
1.0
0.5
V
= ±5V
V = ±5V
S
S
V
= +5V
S
V
= +5V
S
0
0
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
0
10
20
30
40
50
TIME (ns)
60
70
80
90
100
0
10
20
30
40
50
TIME (ns)
60
70
80
90
100
Figure 25. Large Signal Transient Response for Various Supply Voltages
Figure 28. Large Signal Transient Response for Various Supply Voltages
Rev. A | Page 9 of 20
ADA4899-1
1.5
1.0
0.5
0.3
0.2
0.1
0
10
1
G = +1
= ±5V
DISABLE = NC
V
S
INPUT
ERROR
0
–0.5
–1.0
–1.5
0.1
OUTPUT
–0.1
–0.2
–0.3
0.01
G = +1
V
= ±5V
S
R
= 1kΩ
L
0.001
0
25
50
75
100
125
150
0.001
0.01
0.1
1
10
100
1000
TIME (ns)
FREQUENCY (MHz)
Figure 29. Settling Time
Figure 32. Output Impedance vs. Frequency
1.5
1.0
0.3
0.2
0.1
0
100k
10k
1k
G = +1
V
= ±5V
S
DISABLE = –5V
INPUT
0.5
0
OUTPUT
ERROR
–0.5
–1.0
–1.5
–0.1
–0.2
–0.3
100
G = +5
V
= ±5V
S
R
= 1kΩ
L
10
0.1
0
25
50
75
100
125
150
1
10
100
1000
TIME (ns)
FREQUENCY (MHz)
Figure 30. Settling Time
Figure 33. Output Impedance vs. Frequency (Disabled)
100k
10k
1k
–20
G = +1
= ±5V
DISABLE = NC
G = +1
R
R
= 1kΩ
= 1kΩ
–30
–40
V
L
F
S
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
V
= +5V
S
100
V
= ±5V
S
10
0.1
1
10
100
1000
10
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 31. Input Impedance vs. Frequency
Figure 34. Common-Mode Rejection vs. Frequency
Rev. A | Page 10 of 20
ADA4899-1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
N: 4651
MEAN: –4.92µV
SD: 29.22µV
500
400
300
200
100
0
V
= 5V
S
–PSR
+PSR
–200
–150
–100
–50
0
50
100
150
200
0.001
0.01
0.1
1
10
100
1000
VOLTAGE OFFSET (µV)
FREQUENCY (MHz)
Figure 38. Input Offset Voltage Distribution (VS = 5 V)
Figure 35. Power Supply Rejection
–22
–28
–34
–40
–46
–52
–58
–64
–70
N: 4655
V
= ±5V
S
500
400
300
200
100
0
MEAN: –34.62µV
SD: 28.94µV
= ±5V
DISABLE = –5V
V
S
–200
–150
–100
–50
0
50
100
150
200
0.1
1
10
100
1000
VOLTAGE OFFSET (µV)
FREQUENCY (MHz)
Figure 39. Input Offset Voltage Distribution(VS = 5 V)
Figure 36. Off Isolation vs. Frequency
N: 4653
MEAN: –0.083µA
SD: 0.13µA
700
V
= ±5V
S
600
500
400
300
200
100
0
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
INPUT BIAS CURRENT (µA)
Figure 37. Input Bias Current Distribution
Rev. A | Page 11 of 20
ADA4899-1
TEST CIRCUITS
+V
S
+V
S
10µF
10µF
R
R
F
G
0.1µF
0.1µF
V
OUT
V
OUT
R
SNUB
V
24.9Ω
IN
C
R
L
L
V
IN
R
L
R
10µF
T
0.1µF
10µF
49.9Ω
0.1µF
–V
S
–V
S
Figure 40. Typical Noninverting Load Configuration
Figure 43. Typical Capacitive Load Configuration
+V
S
+V
S
10µF
AC
49.9Ω
10Ω
10Ω
1kΩ
10Ω
10Ω
1kΩ
0.1µF
V
V
OUT
OUT
R
R
L
L
AC
10µF
0.1µF
49.9Ω
–V
–V
S
S
Figure 41. Positive Power Supply Rejection
Figure 44. Negative Power Supply Rejection
+V
S
10µF
1kΩ
1kΩ
1kΩ
0.1µF
V
V
OUT
IN
53.6Ω
R
L
1kΩ
10µF
0.1µF
–V
S
Figure 42. Common-Mode Rejection
Rev. A | Page 12 of 20
ADA4899-1
THEORY OF OPERATION
The ADA4899-1 is a voltage feedback op amp that combines
unity gain stability with a 1 nV/√Hz input noise. It employs a
highly linear input stage that can maintain greater than −80 dBc
(@ 2 V p-p) distortion out to 10 MHz while in a unity gain
configuration. This rare combination of low gain stability,
input referred noise, and extremely low distortion is the result
of Analog Devices proprietary op amp architecture and high
speed complementary bipolar processing technology.
Both the SOIC and LFCSP have modified pinouts to improve
heavy load second harmonic distortion performance. The intent
of both is to isolate the negative supply pin from the noninverting
input. The LFCSP accomplishes this by rotating the standard
8-lead package pinout counterclockwise by one pin. This puts
the supply pins and output pins on one side of the package and
the input pins on the other. The SOIC is slightly different with
the intent of both isolating the inputs from the supply pins and
giving the user the option of using the ADA4899-1 in a
standard SOIC board layout with little or no modification.
Taking the unused Pin 5 and making it a second negative supply
pin allows for both an input isolated layout and a traditional
layout to be supported.
The simplified ADA4899-1 topology, shown in Figure 45, is a
single gain stage with a unity gain output buffer. It has over
80 dB of open-loop gain and maintains precision specifications
such as CMRR, PSRR, and offset to levels that are normally
associated with topologies having two or more gain stages.
DISABLE PIN
A three-state input pin is provided on the ADA4899-1 for a
high impedance disable and an optional input bias current
cancellation circuit. The high impedance output allows several
ADA4899-1s to drive the same ADC or output line time-
V
gm
BUFFER
OUT
R1
R
L
C
C
Figure 45. ADA4899-1 Topology
DISABLE
interleaved. Pulling the
pin low activates the high
A pair of internally connected diodes limits the differential
voltage between the noninverting input and the inverting input
of the ADA4899-1. Each set of diodes has two series diodes,
which are connected in antiparallel. This limits the differential
voltage between the inputs to approximately 1.2 V. All of the
ADA4899-1 pins are ESD protected with voltage-limiting diodes
connected between both rails. The protection diodes can handle
10 mA. Currents should be limited through these diodes to 10 mA
or less by using a series limiting resistor.
impedance state. See Table 7 for threshold levels. When the
DISABLE
pin is left floating (open), the ADA4899-1 operates
DISABLE
normally. With the
pin pulled within 0.7 V of the
positive supply, an optional input bias current cancellation
circuit is turned on, which lowers the input bias current to less
than 200 nA. In this mode, the user can drive the ADA4899-1
from a high dc source impedance and still maintain minimal
output-referred offset without having to use impedance
matching techniques. In addition, the ADA4899-1 can be
ac-coupled while setting the bias point on the input with a high
dc impedance network. The input bias current cancellation
circuit doubles the input referred current noise, but this effect is
minimal as long as the wideband impedances are kept low (see
Figure 16).
PACKAGING INNOVATION
The ADA4899-1 is available in both a SOIC and a LFCSP, each
of which has a thermal pad that allows the device to run cooler,
thereby increasing reliability. To help avoid routing around this
pad in board layout, both packages have an extra output pin on
the opposite side of the packages for ease in connecting a feedback
network to the inputs. The secondary output pin also isolates
the interaction of any capacitive load on the output and the self-
inductance of the package and bond wire from the feedback
loop. While using the secondary output for feedback, inductance in
the primary output helps to isolate capacitive loads from the
output impedance of the amplifier.
Rev. A | Page 13 of 20
ADA4899-1
APPLICATIONS
3
0
UNITY GAIN OPERATION
G = +1
= 100Ω
R
L
50mV p-p
The ADA4899-1 schematic for unity gain configuration is
nearly a textbook example (see Figure 46). The only exception is
the small 24.9 Ω series resistor at the noninverting input. The
series resistor is only required in unity gain configurations;
higher gains negate the need for the resistor. In Table 4, it can be
seen that the overall noise contribution of the amplifier and the
24.9 Ω resistor is equivalent to the noise of a single 87 Ω resistor.
25mV p-p
200mV p-p
–3
–6
–9
–12
100mV p-p
Figure 47 shows the small signal frequency response for the
unity gain amplifier shown in Figure 46.
+V
S
1
10
100
FREQUENCY (MHz)
1000
10000
0.1µF
Figure 47. Small Signal Frequency Response for Various Output Voltages
V
OUT
24.9Ω
V
IN
RECOMMENDED VALUES FOR VARIOUS GAINS
0.1µF
Table 4 provides a handy reference for determining various
gains and associated performance. For noise gains greater than
one, the series resistor RS is not required. Resistors RF and RG
are kept low to minimize their contribution to the overall noise
performance of the amplifier.
–V
S
Figure 46. Unity Gain Schematic
Table 4. Conditions: VS = 5 Vꢀ TA = 25°Cꢀ RL = 1 kΩ
−3 dB SS BW (MHz)
(25 mV p-p)
Slew Rate (V/μs)
(2 V Step)
ADA4899-1 Voltage
Noise (nV/√Hz)
Total Voltage
Noise (nV/√Hz)
Gain
+1
RF (Ω)
0
RG (Ω)
NA
RS (Ω)
24.9
0
605
294
277
77
274
265
253
227
161
1
2
2
5
1.2
2.7
2.7
6.5
13.3
−1
100
100
200
453
100
+2
100
0
+5
+10
49.9
49.9
0
0
37
10
Rev. A | Page 14 of 20
ADA4899-1
ADC DRIVER
NOISE
The ultralow noise and distortion performance of the
ADA4899-1 makes it an excellent candidate for driving 16-bit
ADCs. The schematic for a single-ended input buffer using the
ADA4899-1 and the AD7677, a 1 MSPS, 16-bit ADC, is shown
in Figure 49. Table 5 shows the performance data of the
ADA4899-1 and the AD7677.
To analyze the noise performance of an amplifier circuit, first
identify the noise sources, then determine if the source has a
significant contribution to the overall noise performance of the
amplifier. To simplify the noise calculations, noise spectral
densities were used, rather than actual voltages to leave
bandwidth out of the expressions (noise spectral density, which
is generally expressed in nV/√Hz, is equivalent to the noise in a
1 Hz bandwidth).
+5V
+5V
15Ω
The noise model shown in Figure 48 has six individual noise
sources: the Johnson noise of the three resistors, the op amp
voltage noise, and the current noise in each input of the
amplifier. Each noise source has its own contribution to the
noise at the output. Noise is generally specified referred to input
(RTI), but it is often simpler to calculate the noise referred to
the output (RTO) and then divide by the noise gain to obtain
the RTI noise.
IN+
25Ω
ANALOG
2.7nF
AD7677
+
INPUT
ADA4899-1
IN–
REF
–5V
+5V
–5V +2.5V
REF
15Ω
25Ω
ANALOG
INPUT
2.7nF
–
ADA4899-1
V
N, R2
R2
–5V
GAIN FROM
"A" TO OUTPUT
=
Figure 49. Single-Ended Input ADC Driver
4kTR2
NOISE GAIN =
V
I
N, R1
N–
R2
R1
B
A
R1
R3
NG = 1 +
Table 5. ADA4899-1ꢀ Single-Ended Driver for AD7677
16-Bitꢀ 1 MSPSꢀ fc = 50 kHz
V
N
4kTR1
V
V
OUT
N, R3
Parameter
Measurement (dB)
I
N+
GAIN FROM
"B" TO OUTPUT
R2
R1
Second Harmonic Distortion
−116.5
= –
4kTR3
Third Harmonic Distortion
−111.9
THD
SFDR
SNR
−108.6
+101.4
+92.6
2
R2
R1 + R2
2
2
V
+ 4kTR3 + 4kTR1
N
2
2
R1 × R2
2
R1
R1 + R2
2
RTI NOISE =
+I
R3 + I
N–
+ 4kTR2
N+
R1 + R2
The ADA4899-1 configured as a single-ended-to-differential
driver for the AD7677 is shown in Figure 50. Table 6 shows the
associated performance.
RTO NOISE = NG × RTI NOISE
Figure 48. Op Amp Noise Analysis Model
All resistors have a Johnson noise that is calculated by
+5V
(4kBTR)
+2.5V REF
590Ω
where:
ANALOG
INPUT
+5V
590Ω
590Ω
15Ω
15Ω
ADA4899-1
590Ω
k is Boltzmann’s Constant (1.38 × 10–23 J/K).
T is the absolute temperature in Kelvin.
B is the bandwidth in Hz.
2.7nF
2.7nF
–5V
IN+
AD7677
+5V
IN–
REF
590Ω
590Ω
–5V +2.5V
+2.5V
REF
R is the resistance in ohms.
ADA4899-1
–5V
A simple relationship that is easy to remember is that a 50 Ω
resistor generates a Johnson noise of 1 nV√Hz at 25°C.
Figure 50. Single-Ended-to-Differential ADC Driver
Table 6. ADA4899-1ꢀ Single Ended-to-Differential Driver for
AD7677 16-Bitꢀ 1 MSPSꢀ fc = 500 kHz
In applications where noise sensitivity is critical, care must be
taken not to introduce other significant noise sources to the
amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors can be
seen in Table 4.
Parameter
Measurement (dB)
THD
SFDR
SNR
−92.7
+91.8
+90.6
Rev. A | Page 15 of 20
ADA4899-1
DISABLE PIN OPERATION
An AD8137 differential amplifier is used as a level translator
that converts the TTL input to a complementary 3 V output to
The ADA4899-1
pin performs three functions:
DISABLE
enable, disable, and reduction of the input bias current. When
the pin is brought to within 0.7 V of the positive
drive the
pins of the ADA4899-1s. The transient
DISABLE
response for the 2:1 mux is shown in Figure 52.
DISABLE
supply, the input bias current circuit is enabled. This reduces
the input bias current by a factor of 100. In this state, the input
current noise doubles from 2.6 pA to 5.2 pA/√Hz. Table 7
1
outlines the
pin operation.
DISABLE
Table 7.
Pin Truth Table
DISABLE
Supply Voltage
Disable
Enable
5 V
+5 V
−5 to +2.4
Open
0 to 2.4
Open
2
Low Input Bias Current
4.3 to 5
4.3 to 5
CH1 = 500mV/DIV
CH2 = 5V/DIV
200ns/DIV
ADA4899-1 MUX
With a true output disable, the ADA4899-1 can be used in
multiplexer applications. The outputs of two ADA4899-1s are
wired together to form a 2:1 mux. Figure 51 shows the 2:1 mux
schematic.
Figure 52. ADA4899-1 2:1 Mux Transient Response
CIRCUIT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the
ADA4899-1 board yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.
+5V
0.1µF
ADA4899-1
PCB Layout
Because the ADA4899-1 can operate up to 600 MHz, it is
essential that RF board layout techniques be employed. All
ground and power planes under the pins of the ADA4899-1
should be cleared of copper to prevent the formation of
parasitic capacitance between the input pins to ground and the
output pins to ground. A single mounting pad on a SOIC
footprint can add as much as 0.2 pF of capacitance to ground if
the ground plane is not cleared from under the mounting pads.
The low distortion pinout of the ADA4899-1 reduces the
distance between the output and the inverting input of the
amplifier. This helps minimize the parasitic inductance and
capacitance of the feedback path, which reduces ringing and
second harmonic distortion.
0.1µF
1V p-p
2kΩ
–5V
15MHz
+5V
2.2µF
+
0.1µF
DISABLE
50Ω
50Ω
1kΩ
50Ω
1MHz
0V TO 5V
V
OUT
R
AD8137
T
50Ω
DISABLE
+5V
2.2µF
0.1µF
+
–5V
0.1µF
2kΩ
1.02kΩ
Power Supply Bypassing
V
= 2.50V
Power supply bypassing for the ADA4899-1 has been optimized
for frequency response and distortion performance. Figure 40
shows the recommended values and location of the bypass
capacitors. Power supply bypassing is critical for stability,
frequency response, distortion, and PSR performance. The
0.1 μF capacitors shown in Figure 40 should be as close to the
supply pins of the ADA4899-1 as possible. The electrolytic
capacitors should be directly adjacent to the 0.1 μF capacitors.
The capacitor between the two supplies helps improve PSR and
distortion performance. In some cases, additional paralleled
capacitors can help improve frequency and transient response.
REF
ADA4899-1
0.1µF
–5V
2V p-p
15MHz
Figure 51. ADA4899-1 2:1 Mux Schematic
Rev. A | Page 16 of 20
ADA4899-1
Grounding
Ground and power planes should be used where possible.
Ground and power planes reduce the resistance and inductance
of the power planes and ground returns. The returns for the
input, output terminations, bypass capacitors, and RG should all
be kept as close to the ADA4899-1 as possible. The output load
ground and the bypass capacitor grounds should be returned to
the same point on the ground plane to minimize parasitic trace
inductance, ringing, and overshoot and to improve distortion
performance.
The ADA4899-1 packages feature an exposed paddle. For
optimum electrical and thermal performance, solder this
paddle to ground. For more information on high-speed circuit
design, see A Practical Guide to High-Speed Printed-Circuit-
Board Layout.
Rev. A | Page 17 of 20
ADA4899-1
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
2.29 (0.092)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
2.29 (0.092)
8
5
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
TOP VIEW
1
4
BOTTOM VIEW
(PINS UP)
1.27 (0.05)
BSC
0.50 (0.020)
0.25 (0.010)
45°
1.65 (0.065)
1.25 (0.049)
1.75 (0.069)
1.35 (0.053)
1.27 (0.050)
0.40 (0.016)
0.10 (0.004)
MAX
SEATING
PLANE
8°
0°
0.25 (0.0098)
0.17 (0.0068)
0.51 (0.020)
0.31 (0.012)
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 53. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
(RD-8-1)
Dimensions shown in millimeters and (inches)
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
8
PIN 1
INDICATOR
1
PIN 1
INDICATOR
1.89
1.74
1.59
2.75
BSC SQ
1.50
REF
TOP
VIEW
0.50
BSC
4
5
1.60
1.45
1.30
0.70 MAX
0.65TYP
12° MAX
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 54. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
Rev. A | Page 18 of 20
ADA4899-1
ORDERING GUIDE
Model
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
Package Option
RD-8-1
RD-8-1
RD-8-1
CP-8-2
Branding
Ordering Quantity
ADA4899-1YRDZ1
ADA4899-1YRDZ-R71
ADA4899-1YRDZ-RL1
ADA4899-1YCPZ-R21
ADA4899-1YCPZ-R71
ADA4899-1YCPZ-RL1
1
1,000
2,500
250
1,500
5,000
CP-8-2
CP-8-2
HBC
HBC
1 Z = Pb-free part.
Rev. A | Page 19 of 20
ADA4899-1
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05720-0-4/06(A)
Rev. A | Page 20 of 20
相关型号：
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IC LINE DRIVER, QCC16, 3 X 3 MM, ROHS COMPLIANT, MO-220VEED2, LFCSP-16, Line Driver or Receiver
ADI
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