AD9042ASTZ [ADI]
12-Bit, 41 MSPS Monolithic A/D Converter;
| 型号： | AD9042ASTZ |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 41 MSPS Monolithic A/D Converter 转换器 |
| 文件： | 总24页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 41 MSPS
Monolithic A/D Converter
a
AD9042
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
41 MSPS Minim um Sam ple Rate
80 dB Spurious-Free Dynam ic Range
595 m W Pow er Dissipation
Single +5 V Supply
AV
CC
DV
CC
TH1
TH2
TH3
A2
A1
AIN
ADC
V
On-Chip T/ H and Reference
Tw os Com plem ent Output Form at
CMOS-Com patible Output Levels
OFFSET
DAC
ADC
7
+2.4V
REFERENCE
AD9042
V
REF
6
ENCODE
DIGITAL ERROR CORRECTION LOGIC
INTERNAL
TIMING
APPLICATIONS
ENCODE
MSB
LSB
Cellular/ PCS Base Stations
GPS Anti-J am m ing Receivers
Com m unications Receivers
Spectrum Analyzers
Electro-Optics
GND
D9
D1
D0
D11D10
D8 D7 D6 D5 D4 D3 D2
cofired ceramic package forms a multilayer substrate to which
internal bypass capacitors and the 9042 die are attached and a
44-pin T QFP low profile surface mount package. T he AD9042
industrial grade is specified from –40°C to +85°C. However,
the AD9042 was designed to perform over the full military
temperature range (–55°C to +125°C); consult factory for
military grade product options.
Medical Im aging
ATE
P RO D UCT D ESCRIP TIO N
T he AD9042 is a high speed, high performance, low power,
monolithic 12-bit analog-to-digital converter. All necessary
functions, including track-and-hold (T /H) and reference are
included on chip to provide a complete conversion solution.
T he AD9042 runs off of a single +5 V supply and provides
CMOS-compatible digital outputs at 41 MSPS.
P RO D UCT H IGH LIGH TS
1. Guaranteed sample rate is 41 MSPS.
2. Dynamic performance specified over entire Nyquist band;
spurious signals typ. 80 dBc for –1 dBFS input signals.
Designed specifically to address the needs of wideband,
multichannel receivers, the AD9042 maintains 80 dB
spurious-free dynamic range (SFDR) over a bandwidth of
20 MH z. Noise performance is also exceptional; typical
signal-to-noise ratio is 68 dB.
3. Low power dissipation: 595 mW off a single +5 V supply.
4. Reference and track-and-hold included on chip.
5. Packaged in 28-pin ceramic DIP and 44-pin T QFP.
AD 9042AST P IN D ESIGNATIO NS
The AD9042 is built on Analog Devices’ high speed complemen-
tary bipolar process (XFCB) and uses an innovative multipass
architecture. Units are packaged in a 28-pin DIP; this custom
44 43 42 41 40 39 38 37 36 35 34
AD 9042AD P IN D ESIGNATIO NS
DV
DV
33 D8
32 D7
1
2
CC
GND
1
2
28
27
D11 (MSB)
D10
PIN 1
CC
DV
CC
ENCODE
ENCODE
31
D6
3
GND
3
26 D9
30 D5
29 D4
28 D3
27 D2
4
ENCODE
D8
25
4
5
GND
GND
AIN
D7
24
5
AD9042
TOP VIEW
(Not to Scale)
ENCODE
GND
AD9042
TOP VIEW
(Not to Scale)
6
6
23
22
21
20
19
18
17
16
15
D6
D5
D4
7
GND
7
V
D1
26
25
24
23
8
8
OFFSET
AIN
V
D0 (LSB)
V
9
9
REF
D3
OFFSET
V
10
11
10
11
12
13
14
D2
C1
GND
NC
REF
GND
D1
AV
CC
AV
CC
D0 (LSB)
13
20
21 22
12
14 15 16 17 18 19
NC = NO CONNECT
GND
NC
NC
AV
CC
NC = NO CONNECT
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
AD9042–SPECIFICATIONS
DC SPECIFICATIONS (AV = DV = +5 V; V tied to VOFFSET through 50 Ω; TMIN = –40؇C, TMAX = +85؇C)1
CC
CC
REF
Test
AD 9042AST
Test
AD 9042AD
P aram eter
Tem p
Level
Min
Typ
Max
Level
Min
Typ
Max
Units
RESOLUT ION
12
12
Bits
DC ACCURACY
No Missing Codes
Offset Error
Offset T empco
Gain Error
Full
Full
Full
Full
Full
VI
VI
V
VI
V
Guaranteed
VI
VI
V
VI
V
Guaranteed
–10
±3
25
0
+10
–10
±3
25
0
+10
mV
ppm/°C
% FS
ppm/°C
–6.5
+6.5
–6.5
+6.5
Gain T empco
–50
–50
2
REFERENCE OUT (VREF
)
+25°C
V
2.4
V
2.4
V
ANALOG INPUT (AIN)
Input Voltage Range
Input Resistance
VREF ±0.500
VREF ±0.500
V
Ω
pF
Full
+25°C
IV
V
200
250
5.5
300
IV
V
200
250
7
300
Input Capacitance
ENCODE INPUT3
Logic Compatibility4
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V)
Logic “0” Current (VINL = 0 V)
Input Capacitance
T T L/CMOS
5.0
T T L/CMOS
5.0
Full
Full
Full
Full
VI
VI
VI
VI
V
2.0
0
VI
VI
VI
VI
V
2.0
0
V
V
µA
µA
pF
0.8
800
0.8
800
450
625
450
625
–400 –300 –200
–400 –300 –200
+25°C
2
2.5
DIGIT AL OUT PUT S
Logic Compatibility
Logic “1” Voltage (IOH = 10 µA)
CMOS
4.2
CMOS
4.2
+25°C
Full
+25°C
Full
I
IV
I
3.5
3.5
I
IV
I
3.5
3.5
V
V
V
V
Logic “0” Voltage (IOL = 10 µA)
0.75 0.80
0.85
0.75 0.80
0.85
IV
IV
Output Coding
T wos Complement
T wos Complement
POWER SUPPLY
AVCC Supply Voltage
I (AVCC) Current
DVCC Supply Voltage
I (DVCC) Current
ICC (T otal) Supply Current
Power Dissipation
Power Supply Rejection
(PSRR)
Full
Full
Full
Full
Full
Full
+25°C
Full
VI
V
VI
V
VI
VI
I
5.0
109
5.0
10
119
595
±1
VI
V
VI
V
VI
VI
I
5.0
109
5.0
10
119
595
±1
V
mA
V
mA
mA
mW
mV/V
mV/V
147
735
+20
147
735
+20
–20
–20
V
±5
V
±5
NOT ES
1C1 (Pin 10 on AD9042AST only) tied to GND through 0.01 µF capacitor.
2VREF is normally tied to VOFFSET through 50 Ω. If VREF is used to provide dc offset to other circuits, it should first be buffered.
3ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor.
4ENCODE may also be driven differentially in conjunction with ENCODE; see “Encoding the AD9042” for details.
Specifications subject to change without notice.
(AV = DV = +5 V; ENCODE & ENCODE = 41 MSPS;
CC
CC
V tied to VOFFSET through 50 Ω; TMIN = –40؇C, TMAX = +85؇C)1
SWITCHING SPECIFICATIONS
REF
Test
AD 9042AST
Test
AD 9042AD
P aram eter (Conditions)
Tem p
Level
Min
Typ
Max
Level
Min
Typ
Max
Units
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
ENCODE Pulse Width High
ENCODE Pulse Width Low
Full
Full
VI
IV
V
41
VI
IV
V
41
MSPS
MSPS
ps
ps rms
ns
ns
ns
5
5
+25°C
+25°C
+25°C
+25°C
Full
–250
0.7
–250
0.7
V
V
IV
IV
IV
10
10
5
IV
IV
IV
10
10
5
Output Delay (tOD
)
9
14
9
14
NOT E
1C1 (Pin 10 on AD9042AST only) tied to GND through 0.01 µF capacitor.
–2–
REV. A
(AV = DV = +5 V; ENCODE & ENCODE = 41 MSPS;
REF
CC
CC
1
V tied to VOFFSET through 50 Ω; TMIN = –40؇C, TMAX = +85؇C)2
AD9042
AC SPECIFICATIONS
Test
AD 9042AST
Test
AD 9042AD
P aram eter (Conditions)
Tem p
Level
Min
Typ
Max
Level
Min
Typ
Max
Units
SNR3
Analog Input 1.2 MHz
@ –1 dBFS
+25°C
Full
+25°C
Full
+25°C
Full
V
V
V
V
I
68
I
V
I
V
I
V
65
68
67.5
dB
dB
dB
dB
dB
dB
67.5
67.5
67
67
66.5
9.6 MHz
64.5 67.5
67
64
19.5 MHz
64
64
73
67
66.5
V
SINAD4
Analog Input 1.2 MHz
@ –1 dBFS
+25°C
Full
+25°C
Full
+25°C
Full
V
V
V
V
I
67.5
67
67.5
67
67
66.5
I
V
I
V
I
V
64
64
64
67.5
67
67.5
67
67
66.5
dB
dB
dB
dB
dB
dB
9.6 MHz
19.5 MHz
V
Worst Spur5
Analog Input 1.2 MHz
@ –1 dBFS
+25°C
Full
+25°C
Full
+25°C
Full
V
V
V
V
I
80
78
80
78
80
78
I
V
I
V
I
V
74
74
73
80
78
80
78
80
78
dBc
dBc
dBc
dBc
dBc
dBc
9.6 MHz
19.5 MHz
V
Small Signal SFDR (w/Dither)6
Analog Input @1.2 MHz
9.6 MHz
Full
Full
Full
V
V
V
90
90
90
V
V
V
90
90
90
dBFS
dBFS
dBFS
19.5 MHz
T wo-T one IMD Rejection7
F1, F2 @ –7 dBFS
Full
V
V
V
80
V
V
V
80
dBc
T wo-T one SFDR (w/Dither)8
T hermal Noise
Full
90
90
dBFS
LSB rms
+25°C
0.33
0.33
Differential Nonlinearity
(ENCODE = 20 MSPS)
+25°C
Full
I
V
–1.0
±0.3 +1.0
±0.4
I
VI
–1.0
–1.0
±0.3 +1.0
LSB
LSB
+1.25
Integral Nonlinearity
(ENCODE = 20 MSPS)
Full
V
V
V
V
±0.75
100
10
V
V
V
V
±0.75
100
10
LSB
MHz
ns
Analog Input Bandwidth
T ransient Response
+25°C
+25°C
+25°C
Overvoltage Recovery T ime
25
25
ns
NOT ES
1All ac specifications tested by driving ENCODE and ENCODE differentially; see “ENCODING the AD9042” for details.
2C1 (Pin 10 on AD9042AST only) tied to GND through 0.01 µF capacitor.
3Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed).
4Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD ) is the ratio of signal level to total noise + harmonics.
5Analog input signal power at –1 dBFS; worst spur is the ratio of the signal level to worst spur, usually limited by harmonics.
6Analog input signal power swept from –20 dBFS to –95 dBFS; dither power = –32.5 dBm; dither circuit used on input signal (see “Overcoming Static Nonlinearities
with Dither”); SFDR is ratio of converter full scale to worst spur.
7Tones at –7 dBFS (F1 = 15.3 MHz, F2 = 19.5 MHz); two tone intermodulation distortion (IMD) rejection is ratio of either tone to worst third order intermod product.
8Both input tones swept from –20 to –95 dBFS; Dither power = –32.5 dBm; dither circuit used on input signal (see “Overcoming Static Nonlinearities with Dither);
two tone spurious-free dynamic range (SFDR) is the ratio of converter full scale to worst spur.
Specifications subject to change without notice.
REV. A
–3–
AD9042
1
(AV = DV = +5 V; ENCODE = 10.3 MSPS unless otherwise noted)
WAFER TEST LIMITS
CC
CC
AD 9042CH IP S
P aram eter
Tem p
Min
Max
Units
POWER SUPPLY
ICC Supply Current
+25°C
90
147
mA
ENCODE Input
Logic “1” Current
Logic “0” Current
+25°C
+25°C
450
–400
800
–200
µA
µA
DC ACCURACY
Offset Error
+25°C
+25°C
+25°C
+25°C
–8
–6
8
6
mV
Gain Error
% FS
No Missing Codes
Differential Nonlinearity @ 5.3 MSPS
Guaranteed
–0.995
LSB
NOT ES
1Electrical test is performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after
packaging is not guaranteed for standard product dice.
2Die substrate is connected to 0 V.
ABSO LUTE MAXIMUM RATINGS1
EXP LANATIO N O F TEST LEVELS
Test Level
P aram eter
Min
Max Units
I
II
–
–
100% production tested.
ELECT RICAL
AVCC Voltage
DVCC Voltage
100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample
basis.
0
0
0.5
7
7
V
V
Analog Input Voltage
Analog Input Current
Digital Input Voltage (ENCODE)
ENCODE, ENCODE Differential
Voltage
4.5
20
AVCC
V
mA
V
III
IV
–
–
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
0
V
VI
–
–
Parameter is a typical value only.
All devices are 100% production tested at +25°C;
sample tested at temperature extremes.
4
40
V
mA
Digital Output Current
–40
ENVIRONMENT AL2
Operating T emperature Range
(Ambient)
–40
+85
°C
Maximum Junction T emperature
AD9042AD
+175 °C
+150 °C
+300 °C
+150 °C
AD9042AST
Lead T emperature (Soldering, 10 sec)
Storage T emperature Range (Ambient) –65
NOT ES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2T ypical thermal impedances for “D” package (custom ceramic 28-pin DIP):
θJC = 14°C/W; θJA = 34°C/W. For “ST ” package (44-pin T QFP) ; θJA = 55°C/W.
O RD ERING GUID E
P ackage D escription
Model
Tem perature Range
P ackage O ption
AD9042AST
AD9042AD
AD9042CHIPS
AD9042ST /PCB
AD9042D/PCB
–40°C to +85°C (Ambient)
–40°C to +85°C (Ambient)
–40°C to +85°C (Ambient)
44-Pin T QFP (T hin Quad Plastic Flatpack)
28-Pin 600 Mil Hermetic Ceramic DIP (DH-28)
Unpackaged Die
Evaluation Board with AD9042AST
Evaluation Board with AD9042AD
ST -44
DH-28
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9042 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–4–
AD9042
AD 9042AST P IN D ESCRIP TIO NS
AD 9042AD P IN D ESCRIP TIO NS
P in No. Nam e
Function
P in No.
Nam e
Function
1, 2
3
DVCC
+5 V Power Supply (Digital).
Powers output stage only.
1
2
GND
DVCC
Ground.
+5 V Power Supply (Digital).
Powers output stage only.
Ground.
Encode input. Data conversion
initiated on rising edge.
Complement of ENCODE. Drive
differentially with ENCODE or
bypass to Ground for single-ended
clock mode.
ENCODE
ENCODE
Encode input. Data conversion
initiated on rising edge.
3
4
GND
ENCODE
4
Complement of ENCODE. Drive
differentially with ENCODE or
bypass to Ground for single-ended
clock mode.
5
ENCODE
5, 6
7
GND
AIN
Ground.
Analog Input.
6, 7
8
9
GND
AIN
VOFFSET
Ground.
Analog Input.
8
VOFFSET
Voltage Offset Input. Sets mid-
point of analog input range.
Normally tied to VREF through
50 Ω resistor.
Voltage Offset Input. Sets mid-
point of analog input range.
Normally tied to VREF through
50 Ω resistor.
Internal Voltage Reference.
Nominally +2.4 V; normally tied
to VOFFSET through 50 Ω resistor.
Bypass to Ground with 0.1 µF cap.
Ground.
+5 V Power Supply (Analog).
Ground.
+5 V Power Supply (Analog).
No Connects.
9
VREF
Internal Voltage Reference.
Nominally +2.4 V; normally tied
to VOFFSET through 50 Ω resistor.
Bypass to Ground with 0.1 µF +
0.01 µF microwave chip cap.
10
VREF
10
C1
Internal Bias Point. Bypass to
ground with 0.01 µF cap.
11
12
13
14
15, 16
17
GND
AVCC
GND
AVCC
NC
11, 12
13, 14
15, 16
17, 18
19, 20
21
AVCC
GND
AVCC
GND
AVCC
GND
GND
NC
+5 V Power Supply (Analog).
Ground.
+5 V Power Supply (Analog).
Ground.
D0 (LSB)
Digital Output Bit.
(Least Significant Bit).
Digital Output Bits.
+5 V Power Supply (Analog).
Ground.
18–27
28
D1–D10
D11 (MSB)1
22
Ground.
Digital Output Bit
(Most Significant Bit).
23
No Connects.
NOT E
24
GND
D0 (LSB)
Ground.
1Output coded as twos complement.
25
Digital Output Bit
(Least Significant Bit)
AD 9042 CUSTO M 28-P IN D IP P ACKAGE
26–33
34, 35
36, 37
D1–D8
GND
Digital Output Bits
Ground.
DVCC
+5 V Power Supply (Digital).
Powers output stage only.
38, 39
40, 41
GND
DVCC
Ground.
+5 V Power Supply (Digital).
Powers Output Stage only.
Digital Output Bits.
42, 43
44
D9–D10
D11 (MSB)1
Digital Output Bit
(Most Significant Bit).
NOT E
1Output coded as twos complement.
REV. A
–5–
AD9042
D IE LAYO UT AND MECH ANICAL INFO RMATIO N
H ar m onic D istor tion
Die Dimensions . . . . . . . . . . . . . . . . 155 × 168 × 21 (±1) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND
T ransistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2,605
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silver Filled
Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
T he ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
Integr al Nonlinear ity
T he deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minim um Conver sion Rate
T he encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
D IE LAYO UT W/P AD LABELS
Maxim um Conver sion Rate
T he encode rate at which parametric testing is performed.
O utput P r opagation D elay
The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within
valid logic levels.
O ver voltage Recover y Tim e
T he amount of time required for the converter to recover to
0.02% accuracy after an analog input signal 150% of full scale is
reduced to midscale.
P ower Supply Rejection Ratio
T he ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-D istor tion (SINAD )
T he ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, including harmonics but excluding dc.
Signal-to-Noise Ratio (without H ar m onics)
T he ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
D EFINITIO N O F SP ECIFICATIO NS
Analog Bandwidth
T he analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Spur ious-Fr ee D ynam ic Range
T he ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. T he peak spurious
component may or may not be a harmonic. May be reported in
dBc (i.e., degrades as signal levels is lowered), or in dBFS
(always related back to converter full scale).
Aper tur e D elay
T he delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Tr ansient Response
T he time required for the converter to achieve 0.02%
accuracy when a one-half full-scale step function is applied to
the analog input.
Aper tur e Uncer tainty (Jitter )
T he sample-to-sample variation in aperture delay.
Two-Tone Inter m odulation D istor tion Rejection
T he ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product;
reported in dBc.
D iffer ential Nonlinear ity
T he deviation of any code from an ideal 1 LSB step.
Encode P ulse Width/D uty Cycle
Two-Tone SFD R
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve
rated performance; pulse width low is the minimum time
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable Encode duty cycle.
T he ratio of the rms value of either input tone to the rms value
of the peak spurious component. T he peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
REV. A
–6–
Equivalent Circuits–AD9042
N
tA = –250 PS TYP
ANALOG
INPUT
(AIN)
N + 1
ENCODE
INPUTS
(ENCODE)
DIGITAL
OUTPUTS
(D11–D0)
N
N – 2
N – 1
tOD = 9ns TYP
Figure 1. Tim ing Diagram
AV
CC
DV
CC
+3.5V
CURRENT
MIRROR
AV
CC
250µA
250Ω
250Ω
AIN
AV
CC
V
DV
CC
OFFSET
250µA
+1.5V
V
REF
200Ω
D0–D11
6pF
Figure 2. Analog Input Stage
CURRENT
MIRROR
AV
CC
AV
CC
AV
CC
Figure 5. Digital Output Stage
R1
17kΩ
R1
17kΩ
ENCODE
ENCODE
AV
CC
TIMING
CIRCUITS
R2
8kΩ
R2
8kΩ
AV
CC
2.4V
V
REF
0.5mA
Figure 3. Encode Inputs
AV
CC
Figure 6. 2.4 V Reference
+5V
+5V
V
2,12,14
REF
AV
CC
AV
CC
0.1µF
10kΩ
28
200kHz
SINEWAVE
8
9
D11
AIN
V
OFFSET
49.9Ω
CURRENT
MIRROR
10
V
REF
4
5
C1
(PIN 10
ENCODE
ENCODE
TTL CLOCK OSC.
NC
*)
*
AD9042AST ONLY
D0
INTERNAL NODE ON AD9042AD
17
1,3,6,7,11,13
Figure 4. Com pensation Pin, C1
NOTE: ALL +5V SUPPLY PINS & V
REF
PIN BYPASSED TO GND
WITH A 0.1µF CAPACITOR. PINS 15,16 ARE NOT CONNECTED.
Figure 7. AD9042AD Burn-In Diagram
REV. A
–7–
AD9042–Typical Performance Characteristics
0
ENCODE = 41 MSPS
AIN = 1.2MHz
ENCODE = 41 MSPS
TEMP = –40°C, +25°C, & +85°C
81
80
79
78
77
–20
–40
–60
T = +25°C
T = –40°C
T = +85°C
2
3
4
5
6
7
8
9
–80
–100
–120
dc
4.1
8.2
12.3
16.4
20.5
20.5
20.5
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY – MHz
ANALOG INPUT FREQUENCY – MHz
Figure 8. Single Tone at 1.2 MHz
Figure 11. Harm onics vs. AIN
0
–20
–40
–60
ENCODE = 41 MSPS
AIN = 9.6MHz
ENCODE = 41 MSPS
TEMP = –40°C, +25°C, & +85°C
70
69
68
67
66
T = –40°C
4
2
8 8
5
3
7
6
T = +25°C
–80
–100
–120
T = +85°C
0
2
4
6
8
10
12
14
16
18
20
dc
4.1
8.2
12.3
16.4
ANALOG INPUT FREQUENCY – MHz
FREQUENCY – MHz
Figure 12. Noise vs. AIN
Figure 9. Single Tone at 9.6 MHz
90
0
–20
–40
–60
ENCODE = 41 MSPS
ENCODE = 41 MSPS
AIN = 19.5MHz
80
70
60
50
40
30
2
4
6
8
9
7
5
3
–80
–100
–120
1
2
4
10
20
40
100
dc
4.1
8.2
12.3
16.4
ANALOG INPUT FREQUENCY – MHz
FREQUENCY – MHz
Figure 10. Single Tone at 19.5 MHz
Figure 13. Harm onics vs. AIN
–8–
REV. A
AD9042
0
–20
–40
–60
85
80
75
70
65
60
AIN = 4.3MHz
ENCODE = 41 MSPS
AIN = 15.3, 19.5MHz
WORST SPUR
SNR
–80
–100
–120
dc
4.1
8.2
12.3
16.4
20.5
dc
5
10
15
20
25
30
35
40
45
50
FREQUENCY – MHz
SAMPLE RATE – MSPS
Figure 14. Two Tones at 15.3 MHz & 19.5 MHz
Figure 17. SNR, Worst Harm onic vs. Encode
100
90
ENCODE = 41 MSPS
AIN = 19.5MHz
85
90
80
70
60
50
40
30
20
10
0
dBFS
80
WORST SPUR
75
70
ENCODE = 41 MSPS
AIN = 19.5MHz
SNR
65
60
55
50
45
40
35
30
SFDR = 80dB
REFERENCE LINE
dBc
–80
–70
–60
–50
–40
–30
–20
–10
0
25
30
35
40
45
50
55
60
65
70
75
ANALOG INPUT POWER LEVEL – dBFS
ENCODE DUTY CYCLE – %
Figure 15. AD9042AD Single Tone SFDR
Figure 18. SNR, Worst Spurious vs. Duty Cycle
0
100
ENCODE = 41 MSPS
AIN = BROADBAND_NOISE
90
80
70
60
50
40
30
20
10
0
–20
–40
ENCODE = 41 MSPS
F1 = 19.3MHz
F2 = 19.51MHz
–60
SFDR = 80dB
REFERENCE LINE
4
–80
–100
–120
–80
–70
–60
–50
–40
–30
–20
–10
0
dc
4.1
8.2
12.3
16.4
20.5
FREQUENCY – MHz
INPUT POWER LEVEL (F1 = F2) – dBFS
Figure 16. AD9042AD Two Tone SFDR
Figure 19. NPR Output Spectrum
REV. A
–9–
AD9042
0
0
–20
–40
–60
ENCODE = 41 MSPS
AIN = 19.5MHz @ –29 dBFS
NO DITHER
ENCODE = 41 MSPS
AIN = 19.5MHz @ –29 dBFS
DITHER = –32.5dBm
–20
–40
–60
2
6
8
8
7
5
3
4
–80
2
4
6
8
8
7
5
3
–80
–100
–120
–100
–120
dc
4.1
8.2
12.3
16.4
20.5
dc
4.1
8.2
12.3
16.4
20.5
FREQUENCY – MHz
FREQUENCY – MHz
Figure 20. 4K FFT without Dither
Figure 23. 4K FFT with Dither
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
ENCODE = 41 MSPS
AIN = 19.5MHz
NO DITHER
ENCODE = 41 MSPS
AIN = 19.5MHz
DITHER = –32.5dBm
SFDR = 80dB
REFERENCE LINE
SFDR = 80dB
REFERENCE LINE
–80
–70
–60
–50
–40
–30
–20
–10
0
–80
–70
–60
–50
–40
–30
–20
–10
0
ANALOG INPUT POWER LEVEL – dBFS
ANALOG INPUT POWER LEVEL – dBFS
Figure 21. SFDR without Dither
Figure 24. SFDR with Dither
0
–20
–40
–60
0
ENCODE = 41 MSPS
AIN = 2.5MHz @ –26 dBFS
NO DITHER
ENCODE = 41 MSPS
AIN = 2.5MHz@–26dBFS
DITHER = –32.5dBm
–20
–40
–60
–80
–100
–120
–80
–100
–120
dc
4.1
8.2
12.3
16.4
20.5
dc
4.1
8.2
12.3
16.4
20.5
FREQUENCY – MHz
FREQUENCY – MHz
Figure 22. 128K FFT without Dither
Figure 25. 128K FFT with Dither
REV. A
–10–
AD9042
TH EO RY O F O P ERATIO N
5R2RX
V1 =
T he AD9042 analog-to-digital converter (ADC) employs a two-
stage subrange architecture. T his design approach ensures
12-bit accuracy, without the need for laser trim, at low power.
to lower logic threshold.
R1R2 + R1RX + R2RX
As shown in the functional block diagram, the 1 V p-p single-
ended analog input, centered at 2.4 V, drives a single-in to
differential-out amplifier, A1. T he output of A1 drives the first
track-and-hold, T H1. T he high state of the ENCODE pulse
places T H1 in hold mode. T he held value of T H1 is applied to
the input of the 6-bit coarse ADC. T he digital output of the
coarse ADC drives a 6-bit DAC; the DAC is 12 bits accurate.
T he output of the 6-bit DAC is subtracted from the delayed
analog signal at the input to T H3 to generate a residue signal.
T H2 is used as an analog pipeline to null out the digital delay of
the coarse ADC.
+5V
ENCODE
SOURCE
ENCODE
R1
V
l
ENCODE
0.01µF
R
R2
X
AD9042
Figure 27. Lower Logic Threshold for Encode
5R2
V1 =
R1RX
R1 + RX
to raise logic threshold.
R2 +
T he residue signal is passed to T H3 on a subsequent clock cycle
where the signal is amplified by the residue amplifier, A2, and
converted to a digital word by the 7-bit residue ADC. One bit
of overlap is used to accommodate any linearity errors in the
coarse ADC.
AV
X
CC
R
+5V
R1
ENCODE
SOURCE
ENCODE
ENCODE
T he 6-bit coarse ADC word and 7-bit residue word are added
together and corrected in the digital error correction logic to
generate the output word. T he result is a 12-bit parallel digital
word which is CMOS-compatible, coded as twos complement.
V
l
R2
0.01µF
AD9042
AP P LYING TH E AD 9042
Encoding the AD 9042
Figure 28. Raise Logic Threshold for Encode
While the single-ended encode will work well for many
applications, driving the encode differentially will provide
increased performance. Depending on circuit layout and system
noise, a 1 dB to 3 dB improvement in SNR can be realized. It is
not recommended that differential T T L logic be used however,
because most T T L families that support complementary
outputs are not delay or slew rate matched. Instead, it is
recommended that the encode signal be ac-coupled into the
ENCODE and ENCODE pins.
T he AD9042 is designed to interface with T T L and CMOS
logic families. T he source used to drive the ENCODE pin(s)
must be clean and free from jitter. Sources with excessive jitter
will limit SNR (ref. Equation 1 under “Noise Floor and SNR”).
AD9042
TTL OR CMOS
ENCODE
SOURCE
ENCODE
0.01µF
T he simplest option is shown below. T he low jitter T T L signal
is coupled with a limiting resistor, typically 100 ohms, to the
primary side of an RF transformer (these transformers are
inexpensive and readily available; part# in Figure 29 is from
Mini-Circuits). T he secondary side is connected to the
ENCODE and ENCODE pins of the converter. Since both
encode inputs are self biased, no additional components are
required.
Figure 26. Single-Ended TTL/CMOS Encode
T he AD9042 encode inputs are connected to a differential input
stage (see Figure 3 under EQUIVALENT CIRCUIT S). With
no input connected to either the ENCODE or input, the voltage
dividers bias the inputs to 1.6 volts. For T T L or CMOS usage,
the encode source should be connected to ENCODE.
ENCODE should be decoupled using a low inductance or
microwave chip capacitor to ground. Devices such as AVX
05085C103MA15, a 0.01 µF capacitor, work well.
100Ω
T1-1T
ENCODE
TTL
AD9042
ENCODE
If a logic threshold other than the nominal 1.6 V is required, the
following equations show how to use an external resistor, RX, to
raise or lower the trip point (see Figure 3; R1 = 17k, R2 = 8k).
Figure 29. TTL Source – Differential Encode
REV. A
–11–
AD9042
If no T T L source is available, a clean sine wave may be
substituted. In the case of the sine source, the matching net-
work is shown below. Since the matching transformer specified
is a 1:1 impedance ratio, R, the load resistor should be selected
to match the source impedance. T he input impedance of the
AD9042 is negligible in most cases.
amplifier offset; this reference is designed to track internal cir-
cuit shifts over temperature.
250Ω
250Ω
AIN
V
OFFSET
50Ω
T1-1T
TIED TO
SINE
SOURCE
ENCODE
AD9042
+2.4V
REFERENCE
V
REF
THROUGH
50 OHMS
R
AD9042
0.1µF
ENCODE
Figure 33. Analog Input Offset by +2.4 V Reference
Figure 30. Sine Source – Differential Encode
Although the AD9042 may be used in many applications, it was
specifically designed for communications systems which must
digitize wide signal bandwidths. As such, the analog input was
designed to be ac-coupled. Since most communications products
do not down-convert to dc, this should not pose a problem. One
example of a typical analog input circuit is shown below. In this
application, the analog input is coupled with a high quality chip
capacitor, the value of which can be chosen to provide a low
frequency cutoff that is consistent with the signal being
If a low jitter ECL clock is available, another option is to ac-
couple a differential ECL signal to the encode input pins as
shown below. T he capacitors shown here should be chip
capacitors but do not need to be of the low inductance variety.
0.1µF
ENCODE
AD9042
0.1µF
ECL
GATE
sampled; in most cases, a 0.1 µF chip capacitor will work well.
ENCODE
510Ω
510Ω
AD9042
0.1µF
ANALOG
SIGNAL
SOURCE
AIN
V
–V
S
R
T
OFFSET
50Ω
Figure 31. Differential ECL for Encode
V
REF
As a final alternative, the ECL gate may be replaced by an ECL
comparator. T he input to the comparator could then be a logic
signal or a sine signal.
0.1µF
Figure 34. AC-Coupled Analog Input Signal
AD96687 (1/2)
0.1µF
Another option for ac-coupling is a transformer. T he imped-
ance ratio and frequency characteristics of the transformer are
determined by examining the characteristics of the input signal
source (transformer primary connection), and the AD9042 in-
put characteristics (transformer secondary connection). “RT ”
should be chosen to satisfy termination requirements of the
source, given the transformer turns ratio. A blocking capacitor
is required to prevent AD9042 dc bias currents from flowing
through the transformer.
ENCODE
AD9042
0.1µF
50Ω
ENCODE
510Ω
510Ω
–V
S
Figure 32. ECL Com parator for Encode
Care should be taken not to overdrive the encode input pin
when ac coupled. Although the input circuitry is electrically
protected from over or under voltage conditions, improper
circuit operations may result from overdriving the encode input
pins.
BPF
0.1µF
AD9042
ANALOG
SIGNAL
SOURCE
XFMR
AIN
V
R
T
OFFSET
50Ω
LO
V
REF
D r iving the Analog Input
0.1µF
Because the AD9042 operates off of a single +5 V supply, the
analog input range is offset from ground by 2.4 volts. T he
analog input, AIN, is an operational amplifier configured in an
inverting mode (ref. Equivalent Circuits: Analog Input Stage).
VOFFSET is the noninverting input which is normally tied
through a 50 ohm resistor to VREF (ref. Equivalent Circuits:
2.4 V Reference). Since the operational amplifier forces its
inputs to the same voltage, the inverting input is also at 2.4 volts.
Therefore, the analog input has a Thevenin equivalent of 250 ohms
in series with a 2.4 volt source. It is strongly recommended
that the AD9042’s internal voltage reference be used for the
Figure 35. Transform er-Coupled Analog Input Signal
When calculating the proper termination resistor, note that the
external load resistor is in parallel with the AD9042 analog
input resistance, 250 ohms. T he external resistor value can be
calculated from the following equation:
1
RT
=
1
Z
1
where Z is desired impedance.
−
250
REV. A
–12–
AD9042
A dc-coupled input configuration (shown below) is limited by
the drive amplifier performance. T he AD9042’s on-chip refer-
ence is buffered using the OP279 dual, rail-to-rail operational
amplifier. T he resulting voltage is combined with the analog
source using an AD9631. Pending improvements in drive
amplifiers, this dc-coupled approach is limited to ~75 dB–80 dB
of dynamic performance depending on which drive amplifier is
used. T he AD9631 and OP279 run off ±5 V.
Layout Infor m ation
T he schematic of the evaluation boards (Figures 37 and 38)
represents a typical implementation of the AD9042. T he pinout
of the AD9042 facilitates ease of use and the implementation of
high frequency/high resolution design practices. All of the
digital outputs are on one side of the packages while the other
sides contain all of the inputs. It is highly recommended that
high quality ceramic chip capacitors be used to decouple each
supply pin to ground directly at the device. Depending on
the configuration used for the encode and analog inputs, one or
more capacitors are required on those input pins. The capacitors
used on the ENCODE and VREF pins must be a low inductance
chip capacitor as referenced previously in the data sheet.
AD9631
21Ω
AD9042
AIN
SIGNAL
SOURCE
50Ω
200Ω
79Ω
0–50pF
114Ω
0.1µF
V
V
OFFSET
Although a multilayer board is recommended, it is not required
to achieve good results. As shown in the DIP evaluation board
layout (Figures 39–42), the top layer forms a near solid ground
plane while the under side is used for routing signal. No vias
or jumpers are required to route signals in and out of the
AD9042AD. Each supply is decoupled to ground directly at the
device.
1kΩ
49.9Ω
571Ω
REF
0.1µF
OP279
(1/2)
OP279
(1/2)
Figure 36. DC-Coupled Analog Input Circuit
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate (broken only by the
insertion of the series resistor). Logic fanout for each bit should
be one CMOS gate.
P ower Supplies
Care should be taken when selecting a power source. Linear
supplies are strongly recommended as switching supplies tend to
have radiated components that may be “received” by the
AD9042. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 µF chip capacitors.
T he AD9042 has separate digital and analog +5 V pins. T he
analog supplies and the denoted AVCC digital supply pins are
denoted DVCC. Although analog and digital supplies may be
tied together, best performance is achieved when the supplies
are separate. T his is because the fast digital output swings can
couple switching noise back into the analog supplies. Note that
AVCC must be held within 5% of 5 volts, however the DVCC
supply may be varied according to output digital logic family
(i.e., DVCC should be connected to the supply for the digital
circuitry).
Evaluation Boar ds
T he evaluation board for the AD9042 is very straight forward
consisting of power, signal inputs and digital outputs. T he
evaluation board includes an onboard clock oscillator for the
encode; all the user must supply is power and an analog signal.
Power to the analog supply pins is connected via banana jacks.
T he analog supply powers the crystal oscillator and the AVCC
pins of the AD9042. T he DVCC power is supplied via J3, the
digital interface. T his digital supply connection also powers the
digital gates on the PCB. By maintaining separate analog and
digital power supplies, degradation in SNR and SFDR is kept
to a minimum. T otal power requirement for either PCB is
approximately 140 mA. T his configuration allows for easy
evaluation of different logic families (i.e., connection to a 3.3
volt logic board).
O utput Loading
Care must be taken when designing the data receivers for the
AD9042. It is recommended that the digital outputs drive a se-
ries resistor of 499 ohms followed by a CMOS gate like the
74AC574. T o minimize capacitive loading, there should only
be one gate on each output pin. An example of this is shown in
the evaluation board schematics shown in Figures 37 and 38.
T he digital outputs of the AD9042 have a unique constant slew
rate output stage. T he output slew rate is about 1 V/ns
independent of output loading. A typical CMOS gate combined
with PCB trace and through hole will have a load of approxi-
mately 10 pF. T herefore as each bit switches, 10 mA
T he analog input is connected via J2 and is capacitively coupled
to the AD9042 (see “Driving the Analog Input”). T he onboard
termination resistor is 60.4 Ω. T his resistor in parallel with
AD9042’s input resistance (250 Ω) provides a 50 Ω load to the
analog source. If a different input impedance is required,
replace R1 by using the following equation
1
R1 =
1V
1ns
1
Z
1
10 pF ×
of dynamic current per bit will flow in or out of
where Z is desired input impedance.
−
250
the device. A full- scale transition can cause up to 120 mA (12
bits × 10 mA/bit) of current to flow through the digital output
stage. T he series resistor will minimize the output currents that
can flow in the output stage. T hese switching currents are
confined between ground and the DVCC pin. Standard T T L
gates should be avoided since they can appreciably add to the
dynamic switching currents of the AD9042.
T he analog input range of PCB is ±0.5 volts (i.e., signal ac-
coupled to AD9042).
T he encode signal is generated using the onboard crystal
oscillator, U1. T he oscillator is socketed and may be replaced
by an external encode source via J1. If an external source is
used, it should be a high quality T T L source. A transformer
converts the single-ended T T L signal to a differential clock (see
“Encoding the AD9042”). Since the encode is coupled with a
REV. A
–13–
AD9042
transformer, a sine wave could have been used; however, note
that U5 requires T T L levels to function properly.
rate while not appreciably distorting the data waveform. Data is
latched in a pipeline configuration; a rising edge generates the
new AD9042 data sample, latches the previous data at the
converter output, and strobes the external data register over J3.
Power and ground must be applied to J3 to power the digital
logic section of the evaluation board.
AD9042 output data is latched using 74ACT 574 (U3, U4)
latches following 499 ohm series resistors. T he resistors limit
the current that would otherwise flow due to the digital output
slew rate. T he resistor value was chosen to represent a time
constant of ~25% of the data rate at 40 MHz. T his reduces slew
U3
74ACT574
U5
74AS00
U5
74AS00
+5VA
9
8
7
6
5
4
3
2
C14
0.1µF
12
13
14
15
16
17
18
19
B06
B07
B08
B09
B10
B11
8D
7D
6D
5D
4D
3D
2D
1D
8Q
7Q
6Q
5Q
4Q
4
1
6
3
BUFLAT
5
2
14
V
CC
R2
499Ω
8
U1
K1115
OUT
R3
499Ω
R4
499Ω
V
EE
R5
499Ω
H40DM
J3
T1
T1–1T
7
3Q
2Q
1Q
U2
AD9042
R15
R6
499Ω
100Ω
R7
499Ω
3
4
GND
GND
BNC
J1
40
1
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
B11
B10
B09
B08
B07
B06
B05
B04
(MSB) D11
2
1
1
2
GND
28
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
DV
CK
6
3
D10 27
D9 26
+5V
CC
GND
OE
1
4
GND
11
3
5
D8
D7
D6
4
ENCODE
ENCODE
25
24
23
6
5
7
GND
GND
6
8
GND
GND
AIN
C2
0.1µF
9
7
D5 22
D4 21
10
11
12
13
14
15
16
17
18
19
20
BNC
J2
8
BUFLAT
R1
60.4Ω
9
V
20
19
18
D3
D2
D1
OFFSET
R14
49.9Ω
B03
B02
10
11
V
REF
GND
GND
B01
C3
0.1µF
U4
74ACT574
AV
CC
+5VA 12
GND 13
(LSB) D0 17
B00
R13
499Ω
16
GND
NC
GND
GND
GND
GND
GND
R12
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
499Ω
+5VA
AV
CC
14
15
NC
R11
499Ω
B00
B01
B02
B03
B04
B05
8D
7D
6D
5D
4D
3D
2D
1D
8Q
7Q
6Q
5Q
4Q
R10
499Ω
NC = NO CONNECT
R9
499Ω
R8
499Ω
+5V
3Q
2Q
1Q
+
C6
10µF
C7
0.1µF
C11
0.1µF
C12
0.1µF
C13
0.1µF
C15
0.1µF
C16
0.1µF
GND
GND
+5VA
CK
OE
1
+
C4
10µF
C8
0.1µF
C9
0.1µF
C17
0.1µF
11
Figure 37. AD9042D/PCB Schem atic
Table I. AD 9042D /P CB Bill of Material
D escription
Item
Quantity
Reference
1
2
+5VA, GND
Banana Jack
2
3
4
5
6
7
8
9
10
11
12
13
14
10
2
1
2
1
12
1
1
1
1
C2–C3, C7–C9, C11–C17
C4, C6
J3
J1, J2
R1
R2–R13
R14
R15
T 1
U1
U2
U3, U4
U5
Ceramic Chip Capacitor 0805, 0.1 µF
T antalum Chip Capacitor 10 µF
40-Pin Double Row Male Header
BNC Coaxial PCB Connector
Surface Mount Resistor 1206, 60.4 ohms
Surface Mount Resistor 1206, 499 ohms
Surface Mount Resistor 1206, 49.9 ohms
Surface Mount Resistor 1206, 100 ohms
Surface Mount T ransformer Mini-Circuits T 1–1T
40.96 MHz Clock Oscillator
AD9042AD 12-Bit–41 MSPS ADC Converter
74ACT 574 Octal Latch
1
2
1
74AS00 Quad T wo Input NAND Gate
REV. A
–14–
AD9042
U3
74ACT574
U5
74AS00
U5
74AS00
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
B06
8D
7D
6D
5D
4D
3D
2D
1D
8Q
7Q
6Q
5Q
4Q
4
1
B07
B08
B09
B10
B11
6
3
BUFLAT
5
2
+5VA
R5
C14
0.1µF
R6
499Ω
14
R7
499Ω
H40DM
J3
3Q
2Q
1Q
V
CC
499Ω
8
U1
R2
499Ω
GND
GND
OUT
K1115
40
1
2
+5V
B11
B10
B09
B08
B07
B06
B05
B04
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
R3
EE
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
499Ω
CK
T1
T1–1T
BNC
J1
7
OE
R4
499Ω
3
42
44 43
41 40 39 38 37 36 35 34
R15
100Ω
1
11
3
4
4
5
DV
CC
D8 33
D7 32
1
2
1
+5V
+5V
6
DV
CC
6
2
3
4
5
6
7
8
9
7
1 : 1
ENCODE
ENCODE
GND
D6
D5
D4
D3
D2
D1
D0
31
30
29
28
27
26
25
24
23
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
GND
U2
AD9042
BNC
J2
BUFLAT
C2
0.1µF
GND
B03
B02
AIN
V
OFFSET
R1
60.4Ω
B01
V
REF
B00
R13
499Ω
R14
49.9Ω
GND
GND
GND
GND
GND
10 C1
AV
11
GND
NC
GND
R12
499Ω
CC
+5VA
U4
74ACT574
R11
499Ω
C1
0.01µF
C18
0.01µF
C3
0.1µF
13
20
21 22
12
14 15 16 17 18 19
12
9
8
7
6
5
4
3
2
R10
499Ω
B00
B01
B02
B03
B04
B05
8D
7D
6D
5D
4D
3D
2D
1D
8Q
7Q
6Q
5Q
4Q
13
14
15
16
17
18
19
R9
499Ω
NC = NO CONNECT
R8
499Ω
GND1
+5VA
GND
+5VA
GND
3Q
2Q
1Q
GND
GND
+5V
CK
OE
+
C6
10µF
C7
0.1µF
C11
0.1µF
C12
0.1µF
C13
0.1µF
C15
C16
1
11
0.1µF
0.1µF
+5VA
+
C4
C8
C9
C17
10µF
0.1µF
0.1µF
0.1µF
Figure 38. AD9042ST/PCB Schem atic
Table II. AD 9042ST/P CB Bill of Material
Item
Quantity
Reference
D escription
1
2
+5VA, GND
Banana Jack
2
3
4
10
2
1
C2–C3, C7–C9, C11–C17
C4, C6
J3
Ceramic Chip Capacitor 0805, 0.1 µF
T antalum Chip Capacitor 10 µF
40-Pin Double Row Male Header
5
6
7
8
2
1
12
1
1
J1, J2
R1
R2–R13
R14
BNC Coaxial PCB Connector
Surface Mount Resistor 1206, 60.4 ohms
Surface Mount Resistor 1206, 499 ohms
Surface Mount Resistor 1206, 49.9 ohms
Surface Mount Resistor 1206, 100 ohms
9
R15
10
11
12
13
14
15
1
1
1
2
1
1
T 1
U1
U2
U3, U4
U5
Surface Mount T ransformer Mini-Circuits T 1–1T
40.96 MHz Clock Oscillator
AD9042AST 12-Bit–41 MSPS ADC Converter
74ACT 574 Octal Latch
74AS00 Quad T wo Input NAND Gate
Ceramic Chip Capacitor 0805, 0.01 µF AVX05085C103MA15
C1, C18
REV. A
–15–
AD9042
C14
M4
M3
C12
J3
U1
U3
U5
J1
AD9042
PIN 1
C13
ENC
U2
C7
GND
U4
GND
+5VA
+5VA
C11
R14
C3
C9
J2
C8
GND1
AIN
MICROPHONE
TO ANTENNA™
AD9042D/PCB
EVALUATION
48391
1995
USA
©
M1
JB8/KU8
6 / 6 / 95
M2
Figure 39. AD9042D/PCB Top Side Silk Screen
Figure 41. AD9042D/PCB Top Side Copper (Negative)
C6
R7
R6
R5
R4
R3
R2
R15
T1
C2
R1
R8
R9
R10
R11
R12
R13
C4
Figure 42. AD9042D/PCB Bottom Side Copper (Negative)
Figure 40. AD9042D/PCB Bottom Side Silk Screen
REV. A
–16–
AD9042
C18
Figure 43. AD9042ST/PCB Top Side Silk Screen
Figure 45. AD9042ST/PCB Top Side Copper (Negative)
Figure 44. AD9042ST/PCB Bottom Side Silk Screen
Figure 46. AD9042ST/PCB Bottom Side Copper (Positive)
REV. A
–17–
AD9042
+5VA
+5V
Figure 47. AD9042ST/PCB Grounded Layer (Negative)
Figure 48. AD9042ST/PCB “Split” Power Layer (Negative)
REV. A
–18–
AD9042
D IGITAL WID EBAND RECEIVERS
Intr oduction
is used for demodulation, different routines may be used to
demodulate different standards such as AM, FM, GMSK or any
other desired standard. In addition, as new standards arise or
new software revisions are generated, they may be field installed
with standard software update channels. A radio that performs
demodulation in software as opposed to hardware is often
referred to as a soft radio because it may be changed or modified
simply through code revision.
Several key technologies are now being introduced that may
forever alter the vision of radio. Figure 49 shows the typical
dual conversion superheterodyne receiver. T he signal picked up
by the antenna is mixed down to an intermediate frequency (IF)
using a mixer with a variable local oscillator (LO); the variable
LO is used to “tune-in” the desired signal. T his first IF is
mixed down to a second IF using another mixer stage and a
fixed LO. Demodulation takes place at the second or third IF
using either analog or digital techniques.
System D escr iption
In the wideband digital radio (Figure 50), the first down
conversion functions in much the same way as a block converter
does. An entire band is shifted in frequency to the desired
intermediate frequency. In the case of cellular base station
receivers, 5 MHz to 20 MHz of bandwidth are down-converted
simultaneously to an IF frequency suitable for digitizing with a
wideband analog-to-digital converter. Once digitized the
broadband digital data stream contains all of the in-band
signals. T he remainder of the radio is constructed digitally using
special purpose and general purpose programmable DSP to
perform filtering, demodulation and signal conditioning not
unlike the analog counter parts.
ADCs
NARROWBAND
FILTER
NARROWBAND
FILTER
LNA
I
Q
IF
IF
2
RF
1
e.g.
900MHz
FIXED
VARIABLE
ONE RECEIVER PER CHANNEL
SHARED
Figure 49. Narrowband Digital Receiver Architecture
In the narrowband receiver (Figure 49), the signal to be received
must be tuned. T his is accomplished by using a variable local
oscillator at the first mix down stage. T he first IF then uses a
narrow band filter to reject out of band signals and condition
the selected carrier for signal demodulation.
If demodulation takes place in the analog domain then
traditional discriminators, envelop detectors, phase locked loops
or other synchronous detectors are generally employed to strip
the modulation from the selected carrier.
In the digital wideband receiver (Figure 50), the variable local
oscillator has been replaced with a fixed oscillator, so tuning
must be accomplished in another manner. T uning is performed
digitally using a digital down conversion and filter chip fre-
quently called a channelizer. T he term channelizer is used
because the purpose of these chips is to select one channel out
of the many within the broadband of spectrum actually present
in the digital data stream of the ADC.
However, as general purpose DSP chips such as the ADSP-2181
become more popular, they will be used in many baseband-
sampled applications like the one shown in Figure 49. As
shown in the figure, prior to ADC conversion, the signal must
be mixed down, filtered, and the I and Q components separated.
T hese functions are realizable through DSP techniques,
however several key technology breakthroughs are required:
high dynamic range ADCs such as the AD9042, new DSPs
(highly programmable with onboard memory, fast), digital tuner
& filter (with programmable frequency and BW) and wide band
mixers (high dynamic range with >12.5 MHz BW).
DECIMATION
FILTER
LOW-PASS
FILTER
I
COS
DIGITAL
TUNER
DATA
WIDEBAND
ADC
WIDEBAND
SIN
WIDEBAND
MIXER
FILTER
DECIMATION
FILTER
LOW-PASS
FILTER
LNA
Q
"n" CHANNELS
TO DSP
RF
e.g.
900MHz
12.5MHz
(416 CHANNELS)
Figure 51. Digital Channelizer
Figure 51 shows the block diagram of a typical channelizer.
Channelizers consist of a complex NCO (Numerically
Controlled Oscillator), dual multiplier (mixer), and matched
digital filters. T hese are the same functions that would be
required in an analog receiver, however implemented in digital
form. T he digital output from the channelizer is the desired
carrier, frequently in I & Q format; all other signals have been
filtered and removed based on the filtering characteristics
desired. Since the channelizer output consists of one selected
RF channel, one tuner chip is required for each frequency
received, although only one wideband RF receiver is needed for
the entire band. Data from the channelizer may then be
processed using a digital signal processor such as the ADSP-
2181 or the SHARC processor, the ADSP-21062. T his data
may then be processed through software to demodulate the
information from the carrier.
FIXED
CHANNEL SELECTION
SHARED
Figure 50. Wideband Digital Receiver Architecture
Figure 50 shows such a wideband system. T his design shows
that the front end variable local oscillator has been replaced with
a fixed oscillator (for single band radios) and the back end has
been replaced with a wide dynamic range ADC, digital tuner
and DSP. T his technique offers many benefits.
First, many passive discrete components have been eliminated
that formed the tuning and filtering functions. T hese passive
components often require “tweaking” and special handling
during assembly and final system alignment. Digital compo-
nents require no such adjustments; tuner and filter characteristics
are always exactly the same. Moreover, the tuning and filtering
characteristics can be changed through software. Since software
REV. A
–19–
AD9042
+5V (A)
+5V (D)
499Ω
CHANNELIZER
(REF. FIG 51)
CMOS
BUFFER
PRESELECT
FILTER
ADSP-2181
5–15MHz
PASSBAND
LNA
D11
AIN
I & Q
DATA
LO
DRIVE
12
NETWORK
CONTROLLER
INTERFACE
AD9042
864MHz
ENCODE
ENCODE
M/N PLL
SYNTHESIZER
REF
IN
CLK
D0
40.96MHz
REFERENCE
CLOCK
Figure 52. Sim plified 5 MHz Wideband “A” Carrier Receiver
System Requir em ents
Another option can be found through bandpass sampling. If the
analog input signal range is from dc to FS/2, then the amplifier
and filter combination must perform to the specification
required. However, if the signal is placed in the third Nyquist
zone (FS to 3 FS/2), the amplifier is no longer required to meet
the harmonic performance required by the system specifications
since all harmonics would fall outside the passband filter. For
example, the passband filter would range from FS to 3 FS/2.
T he second harmonic would span from 2 FS to 3 FS, well
outside the passband filter’s range. T he burden then has been
passed off to the filter design provided that the ADC meets the
basic specifications at the frequency of interest. In many
applications, this is a worthwhile tradeoff since many complex
filters can easily be realized using SAW and LCR techniques
alike at these relatively high IF frequencies. Although harmonic
performance of the drive amplifier is relaxed by this technique,
intermodulation performance cannot be sacrificed since
intermods must be assumed to fall in-band for both amplifiers
and converters.
Figure 52 shows a typical wideband receiver subsystem based
around the AD9042. T his strip consists of a wideband IF filter,
amplifier, ADC, latches, channelizer and interface to a digital
signal processor. T his design shows a typical clocking scheme
used in many receiver designs. All timing within the system is
referenced back to a single clock. While this is not necessary, it
does facilitate PLL design, ease of manufacturing, system test,
and calibration. Keeping in mind that the overall performance
goal is to maintain the best possible dynamic range, many
considerations must be made.
One of the biggest challenges is selecting the amplifier used to
drive the AD9042. Since this is a communications application,
the key specification for this amplifier is spurious-free dynamic
range, or SFDR. An amplifier should be selected that can
provide SFDR performance better than 80 dB into 250 ohms.
One such amplifier is the AD9631. T hese low spurious levels
are necessary as harmonics due to the drive amplifier and ADC
could distort the desired signals of interest.
T wo other key considerations for the digital wideband receiver
are converter sample rate and IF frequency range. Since
performance of the AD9042 converter is nearly independent of
both sample rate and analog input frequency (Figures 11, 12,
and 17), the designer has greater flexibility in the selection of
these parameters. Also, since the AD9042 is a bipolar device,
power dissipation is not a function of sample rate. T hus there is
no penalty paid in power by operating at faster sample rates. All
of this is good, because by carefully selecting input frequency
range and sample rate, the drive amplifier and ADC harmonics
can actually be placed out-of-band. T hus other components
such as filters and IF amplifiers may actually end up being the
limiting factor on dynamic range.
Noise Floor and SNR
Oversampling is the act of sampling at a rate that is greater than
twice the bandwidth of the signal desired. Oversampling does
not have anything to do with the actual frequency of the
sampled signal, it is the bandwidth of the signal that is key.
Bandpass or “IF” sampling refers to sampling a frequency that
is higher than Nyquist and often provides additional benefits
such as down conversion using the ADC and track-and-hold as
a mixer. Oversampling leads to processing gains because the
faster the signal is digitized, the wider the distribution of noise.
Since the integrated noise must remain constant, the actual
noise floor is lowered by 3 dB each time the sample rate is
doubled. T he effective noise density for an ADC may be
calculated by the equation:
For example, if the system has second and third harmonics that
are unacceptably high, by carefully selecting the encode rate and
signal bandwidth, these second and third harmonics can be
placed out-of-band. For the case of an encode rate equal to
40.96 MSPS and a signal bandwidth of 5.12 MHz, placing the
fundamental at 5.12 MHz places the second and third harmon-
ics out of band as shown in the table below.
10−SNR /20
VNOISE rms
/ Hz =
4 FS
For a typical SNR of 68 dB and a sample rate of 40.96 MSPS,
this is equivalent to . T his equation shows the
31 nV / Hz
relationship between SNR of the converter and the sample rate
FS. T his equation may be used for computational purposes to
determine overall receiver noise.
Table III.
Encode Rate
Fundamental
Second Harmonic 10.24 MHz–20.48 MHz
T hird Harmonic 15.36 MHz–10.24 MHz
40.96 MSPS
5.12 MHz–10.24 MHz
T he signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, the following equation
accurately predicts the SNR based on three terms. T hese are
jitter, average DNL error and thermal noise. Each of these
terms contributes to the noise within the converter.
REV. A
–20–
AD9042
Equation 1:
linearity to appear as if it were random. T hen, the average
linearity over the range of dither will dominate SFDR
performance. In the AD9042, the repetitive cycle is every
15.625 mV p-p.
1/2
2
2
VNOISE rms
2
)
1+ε
212
SNR = –20 log 2 πF
tJ rms
+
+
(
ANALOG
212
T o insure adequate randomization, 5.3 mV rms is required;
this equates to a total dither power of –32.5 dBm. T his will
randomize the DNL errors over the complete range of the
residue converter. Although lower levels of dither such as that
from previous analog stages will reduce some of the linearity
errors, the full effect will only be gained with this larger dither.
Increasing dither even more may be used to reduce some of the
global INL errors. However, signals much larger than the mVs
proposed here begin to reduce the usable dynamic range of the
converter.
FANALOG = analog input frequency
t
= rms jitter of the encode (rms sum of encode source
and internal encode circuitry)
J
rms
ε
= average DNL of the ADC
VNOISE rms = V rms thermal noise referred to the analog input of
the ADC
P r ocessing Gain
Processing gain is the improvement in signal-to-noise ratio
(SNR) gained through DSP processes. Most of this processing
gain is accomplished using the channelizer chips. T hese special
purpose DSP chips not only provide channel selection and
filtering but also provide a data rate reduction. Few, if any,
general purpose DSPs can accept and process data at
40.96 MSPS. T he required rate reduction is accomplished
through a process called decimation. T he term decimation rate
is used to indicate the ratio of input data rate to output data
rate. For example, if the input data rate is 40.96 MSPS and the
output data rate is 30 kSPS, then the decimation rate is 1365.
Even with the 5.3 mV rms of noise suggested, SNR would be
limited to 36 dB if injected as broadband noise. T o avoid this
problem, noise may be injected as an out-of-band signal. Typically,
this may be around dc but may just as well be at FS/2 or at
some other frequency not used by the receiver. T he bandwidth
of the noise is several hundred kilohertz. By band-limiting and
controlling its location in frequency, large levels of dither may
be introduced into the receiver without seriously disrupting
receiver performance. T he result can be a marked improvement
in the SFDR of the data converter.
Figure 23 shows the same converter shown earlier but with this
injection of dither (ref. Figure 20). Spurious-free dynamic
range is now 94 dBFS. Figure 21 and 24 show an SFDR sweep
before and after adding dither.
Large processing gains may be achieved in the decimation and
filtering process. T he purpose of the channelizer, beyond
tuning, is to provide the narrowband filtering and selectivity that
traditionally has been provided by the ceramic or crystal filters
of a narrowband receiver. T his narrowband filtering is the
source of the processing gain associated with a wideband
receiver and is simply the ratio of the passband to whole band
expressed in dB. For example, if a 30 kHz AMPS signal is
being digitized with an AD9042 sampling at 40.96 MSPS, the
ratio would be 0.030 MHz/20.48 MHz. Expressed in log form,
the processing gain is –10 × log (0.030 MHz / 20.48 MHz) or
28.3 dB!
T o more fully appreciate the improvement that dither can have
on performance, Figures 22 and 25 show a before-and-after
dither using additional data samples in the Fourier transform.
Increasing to 128k sample points lowers the noise floor of the
FFT ; this simply makes it easier to “see” the dramatic reduction
in spurious levels resulting from dither.
+15V
LOW CONTROL
(0–1 VOLT)
Additional filtering and noise reduction techniques can be
achieved through DSP techniques; many applications do use
additional process gains through proprietary noise reduction
algorithms.
16kΩ
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1µF
A
NC202
NOISE
DIODE
2.2kΩ
+5V
(NoiseCom)
2kΩ
REF
A
O ver com ing Static Nonlinear ities with D ither
–5V
1kΩ
T ypically, high resolution data converters use multistage
techniques to achieve high bit resolution without large
comparator arrays that would be required if traditional “flash”
ADC techniques were employed. T he multistage converter
typically provides better wafer yields meaning lower cost and
much lower power. However, since it is a multistage device,
certain portions of the circuit are used repetitively as the analog
input sweeps from one end of the converter range to the other.
Although the worst DNL error may be less than an LSB, the
repetitive nature of the transfer function can play havoc with low
level dynamic signals. Spurious signals for a full-scale input
may be –88 dBc, however 29 dB below full scale, these repeti-
tive DNL errors may cause spurious-free dynamic range (SFDR)
to fall to 80 dBc as shown in Figure 20.
OP27
0.1µF
AD600
OPTIONAL HIGH
POWER DRIVE
CIRCUIT
39Ω
390Ω
Figure 53. Noise Source (Dither Generator)
T he simplest method for generating dither is through the use of
a noise diode (Figure 53). In this circuit, the noise diode
NC202 generates the reference noise that is gained up and
driven by the AD600 and OP27 amplifier chain. T he level of
noise may be controlled by either presetting the control voltage
when the system is set up, or by using a digital-to-analog
converter (DAC) to adjust the noise level based on input signal
conditions. Once generated, the signal must be introduced to
the receiver strip. T he easiest method is to inject the signal into
the drive chain after the last down conversion as shown in
Figure 54.
A common technique for randomizing and reducing the effects
of repetitive static linearity is through the use of dither. T he
purpose of dither is to force the repetitive nature of static
REV. A
–21–
AD9042
present in the ADC bandwidth, then each must be placed 18 dB
below full scale to prevent ADC overdrive. In addition, 3 dB to
15 dB should be used for ADC headroom should another signal
come in-band unexpectedly. For this example, 12 dB of
headroom will be allocated. T herefore we give away 30 dB of
range and reduce the carrier-to-noise ratio (C/N)* to 54.8 dB.
FROM
RF/IF
AIN
AD9042
V
OFFSET
LPF
NOISE SOURCE
(REF. FIGURE 53)
V
Assuming that the C/N ratio must be 6 dB or better for accurate
demodulation, one of the eight signals may be reduced by 48.8 dB
before demodulation becomes unreliable. At this point, the
input signal power would be 40.6 µV rms on the ADC input or
–74.8 dBm. Referenced to the antenna, this is –104.8 dBm.
REF
Figure 54. Using the AD9042 with Dither
Receiver Exam ple
T o improve sensitivity, several things can be done. First, the
noise figure of the receiver can be reduced. Since front end
noise dominates the 0.529 mV rms, each dB reduction in noise
figure translates to an additional dB of sensitivity. Second, pro-
viding broadband AGC can improve sensitivity by the range of
the AGC. However, the AGC would only provide useful im-
provements if all in-band signals are kept to an absolute minimal
power level so that AGC can be kept near the maximum gain.
T o determine how the ADC performance relates to overall
receiver sensitivity, the simple receiver in Figure 55 will be
examined. T his example assumes that the overall down
conversion process can be grouped into one set of specifications,
instead of individually examining all components within the
system and summing them together. Although a more detailed
analysis should be employed in a real design, this model will
provide a good approximation.
T his noise limited example does not adequately demonstrate the
true limitations in a wideband receiver. Other limitations such
as SFDR are more restrictive than SNR and noise. Assume that
the analog-to-digital converter has an SFDR specification of
–80 dBFS or –76 dBm (Full scale = +4 dBm). Also assume
that a tolerable carrier-to-interferer (C/I)** (different from C/N)
ratio is 18 dB. T his means that the minimum signal level is
–62 dBFS (–80 plus 18) or –58 dBm. At the antenna, this is
–88 dBm. T herefore, as can be seen, SFDR (single or multi-
tone) would limit receiver performance in this example.
However, as shown previously, SFDR can be greatly improved
through the use of dither (Figures 22, 25). In many cases, the
addition of the out-of-band dither can improve receiver
sensitivity nearly to that limited by thermal noise.
In examining a wideband digital receiver, several considerations
must be applied. Although other specifications are important,
receiver sensitivity determines the absolute limits of a radio
excluding the effects of other outside influences. Assuming that
receiver sensitivity is limited by noise and not adjacent signal
strength, several sources of noise can be identified and their
overall contribution to receiver sensitivity calculated.
GAIN = 30dB
NF = 20dB
BW =12.5MHz
SINGLE CHANNEL
BW = 30kHz
CHANNELIZER
RF/IF
AD9042
ENC
DSP
REF IN
40.96MHz
Multitone P er for m ance
Figure 55. Receiver Analysis
T he plot below shows the AD9042 in a worst case scenario of
four strong tones spaced fairly close together. In this plot no
dither was used, and the converter still maintained 85 dBFS of
spurious-free range. As illustrated previously, a modest amount
of dither introduced out-of-band could be used to lower the
nonlinear components.
T he first noise calculation to make is based on the signal band-
width at the antenna. In a typical broadband cellular receiver,
the IF bandwidth is 12.5 MHz. Given that the power of noise
in a given bandwidth is defined by Pn = kTB, where B is
bandwidth, k = 1.38 × 10–23 is Boltzman’s constant and
T = 300k is absolute temperature, this gives an input noise
power of 5.18 × 10–14 watts or –102.86 dBm. If our receiver
front end has a gain of 30 dB and a noise figure of 20 dB, then
the total noise presented to the ADC input becomes –52.86 dBm
(–102.86 + 30 + 20) or 0.51 mV rms. Comparing receiver
noise to dither required for good SFDR, we see that in this
example, our receiver supplies about 10% of the dither required
for good SFDR.
0
–20
ENCODE = 41 MSPS
–40
–60
3
6
9
7
4
2
5
8
Based on a typical ADC SNR specification of 68 dB, the
equivalent internal converter noise is 0.140 mV rms. T herefore
total broadband noise is 0.529 mV rms. Before processing gain,
this is an equivalent SNR (with respect to full scale) of 56.5 dB.
Assuming a 30 kH z AMPS signal and a sample rate of
40.96 MSPS, the SNR through processing gain is increased by
28.3 dB to 84.8 dB. However, if 8 strong and equal signals are
–80
–100
–120
dc
4.1
8.2
12.3
16.4
20.5
FREQUENCY – MHz
Figure 56. Multitone Perform ance
**C/N is the ratio of signal to inband noise.
**C/I is the ratio of signal to inband interferer.
REV. A
–22–
AD9042
IF Sam pling, Using the AD 9042 as a Mix-D own Stage
Since performance of the AD9042 extends beyond the baseband
region into the second and third Nyquist zone, the converter
may find many uses as a mix down converter in both narrowband
and wideband applications. Many common IF frequencies exist
in this range of frequencies. If the ADC is used to sample these
signals, they will be aliased down to baseband during the sampling
process in much the same manner that a mixer will down-convert a
signal. For signals in various Nyquist zones, the following
equation may be used to determine the final frequency after
aliasing.
RECEIVE CH AIN FO R D IGITAL BEAM-FO RMING
MED ICAL ULTRASO UND USING TH E AD 9042
T he AD9042 is an excellent digitizer for digital and analog
beam-forming medical ultrasound systems. T he price/
performance ratio of the AD9042 allows ultrasound designers
the luxury of using state-of-the-art ADCs without jeopardizing
their cost budgets. ADC performance is critical for image
quality. T he high dynamic range and excellent noise
performance of the AD9042 enable higher image quality
medical ultrasound systems.
Figure 58 shows the AD9042 used in one channel of the receive
chain of a medical ultrasound system. T he AD604 receives its
input directly from the transducer, or from an external preamp
connected to the transducer. T he AD604 contains two separate
stages. T he first stage is a preamp with a fixed gain (14 dB to
20 dB) selected by a fixed resistor. T he second stage is a
variable gain amplifier with the gain set by the AD7226 DAC.
T he gain is increased over time to compensate for the attenu-
ation of signal level in the body.
f1NYQUISTS = fSAMPLE − fSIGNAL
f2NYQUISTS = abs ( fSAMPLE − fSIGNAL
f3NYQUISTS = 2 × fSAMPLE − fSIGNAL
f4NYQUISTS = abs (2 × fSAMPLE − fSIGNAL
)
)
Using the converter to alias down these narrowband or wideband
signals has many potential benefits. First and foremost is the
elimination of a complete mixer stage, along with amplifiers,
filters and other devices, reducing cost and power dissipation.
PRE-AMP
VGA
14 TO 20dB
–14 TO 34dB
One common example is the digitization of a 21.4 MHz IF
using a 10 MSPS sample clock. Using the equation above for
the fifth Nyquist zone, the resultant frequency after sampling is
1.4 MHz. Figure 57 shows performance under these conditions.
Even under these conditions, the AD9042 typically maintains
better than 80 dB SFDR.
TRANSDUCER/
PRE-AMP
INPUT
AD9042
AD8041
AD604
LPF
AD7226
0
ENCODE = 10.0 MSPS
AIN = 21.4MHz
Figure 58. Using the AD9042 in Ultrasound Applications
–20
Following the AD604, a low-pass filter is used to minimize the
amount of noise presented to the ADC. T he AD8041 is used to
buffer the filter from the AD9042 input. T his function may not
be required depending on the filter configuration and PC board
partitioning. T he digital outputs of the AD9042 are then
presented to the digital system for processing.
–40
–60
8
7
8
6
2
5
3
4
–80
–100
–120
dc
1.0
2.0
3.0
4.0
5.0
FREQUENCY – MHz
Figure 57. IF-Sam pling a 21.4 MHz Input
REV. A
–23–
AD9042
AD 9042AST O UTLINE D IMENSIO NS
D imensions shown in inches and (mm)
44-P in Thin Q uad Flatpack
(ST-44)
0.063 (1.60)
MAX
0.472 (12.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
44
34
1
33
SEATING
PLANE
0.393
(10.0)
BSC
SQ
TOP VIEW
(PINS DOWN)
11
23
0.006 (0.15)
0.002 (0.05)
0.039
(1.00)
REF
12
22
0.018 (0.45)
0.012 (0.30)
0.031 (0.80)
BSC
0.008 (0.20)
0.003 (0.09)
AD 9042AD O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-P in H er m etic Cer am ic D IP
(D H -28)
28
15
0.595 ± 0.010
(15.11 ± 0.25)
1
14
PIN 1 IDENTIFIERS
0.050 ± 0.010
(1.27 ± 0.25)
1.400 ± 0.014
(35.56 ± 0.35)
0.225
(5.72)
MAX
0.150
(3.81)
MIN
0.010 ± 0.002
(0.25 ± 0.05)
0.600 (15.24)
REF
0.100 (2.54)
TYP
0.018 ± 0.002
(0.46 ± 0.05)
0.05 (1.27)
TYP
SEATING
PLANE
REV. A
–24–
相关型号：
©2020 ICPDF网 联系我们和版权申明