AD8347ARU [ADI]
0.8 GHz-2.7 GHz Direct Conversion Quadrature Demodulator; 0.8千兆赫， 2.7 GHz直接转换正交解调器
| 型号： | AD8347ARU |
| 厂家： | 
ADI |
| 描述： | 0.8 GHz-2.7 GHz Direct Conversion Quadrature Demodulator |
| 文件： | 总20页 (文件大小：746K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.8 GHz–2.7 GHz
a
Direct Conversion Quadrature Demodulator
AD8347*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Integrated RF and Baseband AGC Amplifiers
Quadrature Phase Accuracy 1؇ Typ
I/Q Amplitude Balance 0.3 dB Typ
Third Order Intercept (IIP3) +11.5 dBm @ Min Gain
Noise Figure 11 dB @ Max Gain
AGC Range 69.5 dB
Baseband Level Control Circuit
Low LO Drive –8 dBm
ADC Compatible I/Q Outputs
Single Supply 2.7 V–5.5 V
AD8347
1
2
LOIN
VPS1
IOPN
IOPP
VCMO
IAIN
28 LOIP
PHASE
SPLITTER
27 COM1
26 QOPN
25 QOPP
3
4
PHASE
SPLITTER
5
24
23
22
21
20
19
18
17
16
15
QAIN
COM3
QMXO
VPS3
VDT1
VAGC
VDT2
VGIN
6
7
COM3
IMXO
COM2
RFIN
RFIP
8
9
Power-Down Mode
Package 28-Lead TSSOP
10
11
12
13
14
DET
VPS2
IOFS
VREF
APPLICATIONS
Cellular Basestations
Radio Links
QOFS
ENBL
GAIN
CONTROL
BIAS
Wireless Local Loop
IF Broadband Demodulator
RF Instrumentation
Satellite Modems
GENERAL DESCRIPTION
amplifiers together provide 69.5 dB of gain control. A precision
control circuit sets the Linear-in-dB RF gain response to the gain
control voltage.
The AD8347 is a broadband Direct Quadrature Demodulator
with RF and baseband Automatic Gain Control (AGC) amplifiers.
It is suitable for use in many communications receivers,
performing Quadrature demodulation directly to baseband
frequencies. The input frequency range is 800 MHz to 2.7 GHz.
The outputs can be connected directly to popular A-to-D converters
such as the AD9201 and AD9283.
Baseband level detectors are included for use in an AGC loop to
maintain the output level. The demodulator dc offsets are
minimized by an internal loop, whose time constant is controlled
by external capacitor values. The offset control can also be
overridden by forcing an external voltage at the offset nulling pins.
The RF input signal goes through two stages of variable gain
amplifiers prior to two Gilbert-cell Mixers. The LO quadrature
phase splitter employs polyphase filters to achieve high quadra-
ture accuracy and amplitude balance over the entire operating
frequency range. Separate I & Q channel variable-gain amplifiers
follow the baseband outputs of the mixers. The RF and baseband
The baseband variable gain amplifier outputs are brought off-chip
for filtering before final amplification. By inserting a channel
selection filter before each output amplifier high-level out-of-
channel interferers can be eliminated. Additional internal circuitry
also allows the user to set the dc common-mode level at the
baseband outputs.
*U.S. Patents Issued and Pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
(VS = 5 V; TA = 25؇C; FLO = 1.9 GHz; VVCMO = 1 V; FRF = 1.905 GHz; PLO = –8 dBm,
RLOAD = 10 k⍀, dBm with respect to 50 ⍀, unless otherwise noted.)
AD8347–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
OPERATING CONDITIONS
LO/RF Frequency Range
LO Input Level
VGIN Input Level
VSUPPLY (VS)
0.8
–10
0.2
2.7
–40
2.7
0
1.2
5.5
+85
GHz
dBm
V
V
°C
Temperature Range
RF AMPLIFIER/DEMODULATOR
From RFIP/RFIN to IMXO and QMXO
(IMXO/QMXO Load >1 kΩ)
AGC Gain Range
Conversion Gain (Max)
Conversion Gain (Min)
Gain Linearity
Gain Flatness
Input P1 dB
69.5
39.5
–30
±2
0.7
–30
–2
dB
dB
dB
dB
dB p-p
dBm
dBm
dBm
VVGIN = 0.2 V (Max Gain)
VVGIN = 1.2 V (Min Gain)
VVGIN = 0.3 V to 1 V
FLO = 0.8 GHz – 2.7 GHz, FBB = 1 MHz
VVGIN = 0.2 V
V
VGIN = 1.2 V
FRF1 = 1.905 GHz,
RF2 = 1.906 GHz, –10 dBm Each Tone,
(Min Gain)
Second Order Input Intercept (IIP2) FRF1 = 1.905 GHz,
Third Order Input Intercept (IIP3)
+11.5
F
+25.5
dBm
F
RF2 = 1.906 GHz, –10 dBm Each Tone,
(Min Gain)
At RFIP
At IMXO/QMXO
–3 dB
FRF = 1.9 GHz
LO Leakage (RF)
–60
–42
90
±1
0.3
11
24
2
dBm
dBm
MHz
Degree
dB
dB
mV p-p
mV
LO Leakage (MXO)
Demodulation Bandwidth
Quadrature Phase Error
I/Q Amplitude Imbalance
Noise Figure
Mixer AGC Output Level
Baseband DC Offset
–3
+3
F
RF = 1.9 GHz
Max Gain
See TPC 30
At IMXO/QMXO, Max Gain
(Corrected, Ref to VREF)
Level at which IMD3 = 45 dBc
RLOAD = 200 Ω
Mixer Output Swing
65
65
3
mV p-p
mV p-p
Ω
RLOAD = 1 kΩ
Mixer Output Impedance
BASEBAND OUTPUT AMPLIFIER
From IAIN to IOPP/IOPN and
QAIN to QOPP/QOPN
RLOAD = 10 kΩ
Gain
30
dB
Bandwidth
–3 dB (See TPC 18)
(VIOPP – VIOPN
(VIOPP + VIOPN)/2 – VVCMO
0 MHz–50 MHz
FIN1 = 5 MHz, FIN2 = 6 MHz,
VIN1 = VIN2 = 8 mV p-p
FIN1 = 5 MHz, FIN2 = 6 MHz,
VIN1 = VIN2 = 8 mV p-p
65
±50
±5
1.8
–49
MHz
mV
mV
ns p-p
dBc
Output DC Offset (Differential)
Common-Mode Offset
Group Delay Flatness
Second Order Intermod. Distortion
)
–200
–40
+200
+40
Third Order Intermod. Distortion
–67
dBc
Input Bias Current
2
µA
Input Impedance
Output Swing Limit (Upper)
Output Swing Limit (Lower)
1ʈ3
MΩʈpF
V
V
VS – 1.3
0.4
–2–
REV. 0
AD8347
Parameter
Conditions
Min
Typ
Max
Unit
CONTROL INPUT/OUTPUTS
VCMO Input
@ VS = 2.7 V
@ VS = 5 V
VGIN
IOFS, QOFS
RLOAD = 10 kΩ
1
1
<1
10
1.00
V
V
µA
µA
V
0.5
2.5
Gain Control Input Bias Current
Offset Input Overriding Current
VREF Output
0.95
1.05
RESPONSE FROM RF INPUT TO
FINAL BB AMP
IMXO/QMXO Connected Directly to
IAIN/QAIN Respectively
Gain @ VVGIN = 0.2 V
Gain @ VVGIN = 1.2 V
Gain Slope
65.5
–3
–96.5
88
69.5
+0.5
–89
94
72.5
+4
–82.5
101
dB
dB
dB/V
dB
Gain Intercept
Linear extrapolation back to
theoretical value at VGIN = 0
LO/RF INPUT
LOIP Input Return Loss
(See TPC 26 Through 29 for More Detail)
Measuring LOIP LOIN, ac-coupled to
Ground with 100 pF.
–4
dB
Measuring Through Evaluation Board
Balun with Termination
RFIP Input Pin
–9.5
–10
dB
dB
RFIP Input Return Loss
ENABLE
Power-Up Control
Power-Up Control
Power-Up Time
Low = Standby
High = Enabled
Time for Final BB Amps to be Within
90% of Final Amplitude
@ VS = 5 V
0
0.5
+VS
V
V
+VS – 1
20
10
µs
µs
@ VS = 2.7 V
Power-Down Time
Time for Supply Current to be <4 mA
@ VS = 5 V
30
1.5
µs
ms
@ VS = 2.7 V
POWER SUPPLIES
Voltage
Current (Enabled)
Current (Standby)
Current (Standby)
VPS1, VPS2, VPS3
2.7
48
5.5
80
V
@ 5 V
@ 5 V
@ 3.3 V
64
400
80
mA
µA
µA
Specifications subject to change without notice.
–3–
REV. 0
AD8347
ABSOLUTE MAXIMUM RATINGS
*
PIN CONFIGURATION
Supply Voltage VPS1, VPS2, VPS3 . . . . . . . . . . . . . . . . . . . 5.5 V
LO and RF Input Power . . . . . . . . . . . . . . . . . . . . . . 10 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 500 mW
1
2
LOIN
VPS1
IOPN
IOPP
VCMO
IAIN
28 LOIP
27 COM1
26 QOPN
25 QOPP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
JA
3
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
4
5
24
23
22
21
20
19
18
17
16
15
QAIN
COM3
QMXO
VPS3
VDT1
VAGC
VDT2
VGIN
6
AD8347
TOPVIEW
(Not to Scale)
7
COM3
IMXO
COM2
RFIN
RFIP
8
9
10
11
12
13
14
VPS2
IOFS
VREF
QOFS
ENBL
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8347ARU
–40°C to +85°C
Tube (28-Lead TSSOP) Thin
Shrink Small Outline Package
13" Tape and Reel
7" Tape and Reel
Evaluation Board
RU-28
AD8347ARU-REEL
AD8347ARU-REEL7
AD8347-EVAL
VPS1
VPS2
VPS3
VREF
IMXO IOFS
IAIN
IOPP IOPN
AD8347
VREF
BIAS
CELL
ENBL
VREF
VCMO
VCMO
RFIN
RFIP
LOIN
LOIP
PHASE
SPLITTER
1
PHASE
SPLITTER
2
COM3
COM2
COM3
COM1
VCMO
GAIN
CONTROL
INTERFACE
VGIN
DET 1
DET 2
VREF
VDT1 VAGC VDT2
QMXO QOFS
QAIN
QOPP QOPN
Figure 1. Block Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8347 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD8347
PIN FUNCTION DESCRIPTIONS
Pin
No.
Equiv.
Cir.
Mnemonic
Description
1, 28
LOIN, LOIP
A
LO Input. For optimum performance, these inputs should be driven differentially. Typical input
drive level is equal to –8 dBm. To improve the match to a 50 Ω source, connect a 200 Ω shunt
resistor between LOIP and LOIN. A single-ended drive is also possible but this will slightly
increase LO leakage.
2
3, 4
VPS1
IOPN, IOPP
Positive Supply for LO Section. This pin should be decoupled with 0.1 µF and 100 pF capacitors.
I Channel Differential Baseband Output. Typical output swing is equal to 760 mV p-p differential
in AGC mode. The common mode level on these pins is programmed by the voltage on VCMO.
Baseband Amplifier Common-Mode Voltage. The voltage applied to this pin sets the output
common-mode level of the baseband amplifiers. This pin can either be connected to VREF
(Pin 14) or to a reference voltage from another device (typically an ADC).
I Channel Baseband Amplifier Input. This pin, which has a high input impedance, should be
biased to VREF (approximately 1 V). If IAIN is connected directly to IMXO, biasing will be
provided by IMXO. If an ac-coupled filter is placed between IMXO and IAIN, this pin can be
biased from VREF through a 1 kΩ resistor. The gain from IAIN to the differential outputs
IOPN/IOPP is 30 dB.
B
5
6
VCMO
IAIN
C
D
B
7, 23
8, 22
COM3
IMXO, QMXO
Ground for Biasing and Baseband Sections
I & Q Channel Baseband Mixer/VGA Outputs. These are low impedance outputs whose bias
levels are equal to VREF. IMXO and QMXO are typically connected to IAIN and QAIN
respectively, either directly or through filters. These outputs have a maximum current limit of
about 1.5 mA. This allows for a 600 mV p-p swing into a 200 Ω load. This corresponds to an
input level of –40 dBm @ max gain of 39.5 dB. At lower output levels, IMXO and QMXO, can
drive a lower load resistance, subject to the same current limit.
9
COM2
RF Section Ground
10, 11 RFIN, RFIP
E
RF Input. RFIN must be ac-coupled to ground. The RF input signal should be ac-coupled into
RFIP. For a broadband 50 Ω input impedance, connect a 200 Ω resistor from the signal side of
RFIP’s coupling capacitor to ground. Please note that RFIN and RFIP are not interchangeable
differential inputs. RFIN is the ground reference for the input system.
12
VPS2
Positive Supply for RF Section. This pin should be decoupled with 0.1 µF and 100 pF capacitors.
I Channel and Q Channel Offset Nulling Inputs. To null the dc-offset on the I Channel and
Q Channel Mixer Outputs (IMXO, QMXO), connect a 0.1 µF capacitor from these pins to
ground. Alternately, a forced voltage of approximately 1 V on these pins will disable the offset
compensation circuit.
13, 16 IOFS, QOFS
F
14
VREF
G
Reference Voltage Output. This output voltage (1 V) is the main bias level for the device and
can be used to externally bias the inputs and outputs of the baseband amplifiers.
Chip Enable Input. Active high.
15
17
ENBL
VGIN
H
C
Gain Control Input. The voltage on this pin controls the gain on the RF and baseband VGAs.
The gain control is applied in parallel to all VGAs. The gain control voltage range is from 0.2 V
to 1.2 V and corresponds to a gain range from +39.5 dB to –30 dB. This is the gain to the output
of the baseband VGAs (i.e., QMXO and IMXO). There is an additional 30 dB of gain in the
baseband amplifiers. Note that the gain control function has a negative sense (i.e., increasing
control voltage decreases gain). In AGC mode, this pin is connected directly to VAGC.
Detector Inputs. These pin are the inputs to the on-board detector. VDT2 and VDT1, which
have high input impedances, are normally connected to IMXO and QMXO respectively.
AGC Output. This pin provides the output voltage from the on-board detector. In AGC mode,
this pin is connected directly to VGIN.
Positive Supply for Biasing and Baseband Sections. This pin should be decoupled with 0.1 µF
and 100 pF capacitors.
Q Channel Baseband Amplifier Input. This pin, which has a high input impedance, should be
biased to VREF (approximately 1 V). If QAIN is connected directly to QMXO, biasing will be
provided by QMXO. If an ac-coupled filter is placed between QMXO and QAIN, this pin can
be biased from VREF through a 1 kΩ resistor. The gain from QAIN to the differential outputs
QOPN/QOPP is 30 dB.
18, 20 VDT2, VDT1
D
I
19
21
24
VAGC
VPS3
QAIN
D
B
25, 26 QOPP, QOPN
Q Channel Differential Baseband Output. Typical output swing is equal to 1 V p-p differential.
The common-mode level on these pins is programmed by the voltage on VCMO.
LO Section Ground
27
COM1
–5–
REV. 0
AD8347
EQUIVALENT CIRCUITS
VPS1
VPS3
VPS3
LOIN
IOPP, IOPN,
QOPP, QOPN,
IMXO, QMXO
VCMO
PHASE
SPLITTER
CONTINUES
CURRENT MIRROR
LOIP
COM3
COM3
COM1
Circuit A
Circuit B
Circuit C
VPS3
VPS3
VPS2
IOFS
QOFS
IAIN
QAIN
RFIP
CURRENT MIRROR
RFIN
COM3
COM3
COM2
Circuit D
Circuit E
Circuit F
VPS3
VPS3
VAGC
VPS3
VREF
ENBL
COM3
COM3
COM3
Circuit G
Circuit H
Circuit I
Figure 2. Equivalent Circuits
–6–
REV. 0
Typical Performance Characteristics–
AD8347
RF AMP AND DEMODULATOR
3.0
2.5
2.0
1.5
1.0
0.5
0
45
14
12
10
8
T
= –40؇C
40
35
30
25
20
A
T
= +85؇C
A
T
= +25؇C
V
= 2.7V,T = +25؇C
A
S
A
6
4
15
10
V
T
= 5V,
V
= 2.7V,T = –40؇C
S
S
A
2
0
= +25؇C
A
5
0
–2
–5
T
= –40؇C
T
= +25؇C
A
A
V
= 5V, T = –40؇C
S
A
–10
–15
–20
–4
V
= 5V, T = +85؇C
A
S
–6
T
A
= +85؇C
–8
–0.5
–1.0
–25
–30
–35
V
= 2.7V, T = +85؇C
A
–10
–12
S
0.2
0.3
0.4
0.5
0.6
0.7
–V
0.8
0.9
1.0
1.1
1.2
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
V
RF FREQUENCY – MHz
GIN
TPC 1. Gain and Linearity Error vs. VGIN, VS = 5 V,
FLO = 1900 MHz, FBB = 1 MHz
TPC 4. Gain vs. FLO, VGIN = 0.7 V, FBB = 1 MHz
45
40
35
30
25
20
–27
14
12
10
8
T
= –40؇C
V
T
= 5V,
A
S
–28
= +25؇C
A
V = 2.7V, T = –40؇C
S A
V
= 2.7V, T = +25؇C
S
A
–29
–30
T
= +25؇C
A
T
= +85؇C
= –40؇C
A
6
4
15
10
–31
–32
–33
T
A
5
0
2
0
V
S
= 5V, T = –40؇C
A
–5
V
= 5V, T = +85؇C
–2
–4
–6
–8
–10
S
A
–10
–15
–20
V
= 2.7V, T = +85؇C
A
–34
–35
–36
T
= +25؇C
S
A
–25
–30
–35
T
= +85؇C
A
–37
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
V
–V
GIN
RF FREQUENCY – MHz
TPC 2. Gain and Linearity Error vs. VGIN, VS = 2.7 V,
TPC 5. Gain vs. FLO, VGIN = 1.2 V, FBB = 1 MHz
F
LO = 1900 MHz, FBB = 1 MHz
40
39
42
V
= 2.7V, T = +25؇C
A
S
41
40
V
= 2.7V, T = –40؇C
S
A
V
T
= 5V,
S
38
37
36
V
S
= 2.7V, T = +25؇C
A
= +25؇C
39
38
37
A
V
= 2.7V, T = –40؇C
A
S
V
T
= 5V,
V
= 5V, T = –40؇C
A
S
S
= +25؇C
A
V
= 2.7V, T = +85؇C
A
S
35
34
33
32
31
30
36
35
34
V
= 2.7V, T = +85؇C
A
S
V
= 5V, T = –40؇C
A
S
V
= 5V, T = +85؇C
A
S
V
= 5V, T = +85؇C
A
S
33
32
31
30
1
10
BASEBAND FREQUENCY – MHz
100
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY – MHz
TPC 3. Gain vs. FLO, VGIN = 0.2 V , FBB = 1 MHz
TPC 6. Gain vs. FBB, VGIN = 0.2 V, FLO = 1900 MHz
–7–
REV. 0
AD8347
15
14
13
12
11
10
V
T
= 2.7V,
S
V = 5V, T = +85؇C
S A
9
= +85؇C
A
V
= 5V, T = +25؇C
A
8
S
7
V
= 2.7V, T = +85؇C
S
A
6
5
V = 5V, T = +85؇C
S A
V
= 2.7V,T = –40؇C
A
4
S
V
= 2.7V, T = +25؇C
A
S
3
2
V
= 5V, T = –40؇C
A
10
9
S
V
= 2.7V, T = +25؇C
A
S
1
V
= 5V,
S
A
0
T
= +25؇C
8
–1
–2
–3
–4
–5
V
= 2.7V, T = –40؇C
A
S
7
V
= 5V, T = –40؇C
A
S
6
5
1
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
10
BASEBAND FREQUENCY – MHz
100
RF FREQUENCY – MHz
TPC 7. Gain vs. FBB, VGIN = 0.7 V, FLO = 1900 MHz
TPC 10. IIP3 vs. FLO, VGIN = 1.2 V, FBB = 1 MHz
–25
–26
–10
V
T
= 2.7V,
S
–12
–14
–16
–18
–20
V
= 5V, T = +25؇C
S
A
V
T
= 2.7V,
V
= 2.7V, T = –40؇C
= +85؇C
S
S
A
A
–27
–28
–29
–30
–31
–32
–33
–34
–35
= +25؇C
A
V
T
= 2.7V,
S
= +25؇C
V
T
= 5V,
A
S
= +25؇C
A
V
= 5V,
S
A
–22
–24
T
= –40؇C
V
= 2.7V, T = –40؇C
A
S
V
= 5V, T = –40؇C
V
T
= 2.7V,
S
A
S
V
= 5V, T = +85؇C
A
S
–26
–28
–30
= +85؇C
A
V
= 5V, T = +85؇C
A
S
1
10
100
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
BASEBAND FREQUENCY – MHz
RF FREQUENCY – MHz
TPC 8. Gain vs. FBB, VGIN = 1.2 V, FLO = 1900 MHz
TPC 11. IIP3 vs. FLO, VGIN = 0.2 V, FBB = 1 MHz,
0
15
V
= 2.7V, T = +85؇C
A
S
–5
–10
–15
V
= 2.7V, T = –40؇C
A
S
14
V
T
= 5V,
S
= +85؇C
A
V
= 5V, T = +85؇C
A
S
V
= 2.7V, T = +85؇C
A
S
V
T
= 5V,
S
13
12
11
= –40؇C
A
–20
–25
–30
V
T
= 5V,
S
= +25؇C
A
V
= 5V, T = +25؇C
A
S
V
S
= 2.7V,
T
= +25؇C
A
V
T
= 2.7V,
S
V
= 2.7V,T = –40؇C
A
= +25؇C
S
A
V
= 5V, T = –40؇C
A
S
–35
10
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95100
0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20
–V
V
BASEBAND FREQUENCY – MHz
GIN
TPC 9. Input 1 dB Compression Point (OP1 dB) vs. VGIN
FLO = 1900 MHz, FBB = 1 MHz
,
TPC 12. IIP3 vs. FBB, VGIN = 1.2 V, FLO = 1900 MHz
–8–
REV. 0
AD8347
15
70
60
50
40
30
20
10
0
–10
–12
–14
10
V
= 5V, T = +85؇C
A
S
5
–16
–18
–20
–22
V
= 2.7V, T = +85؇C
0
S
A
–5
–10
V
= 5V, T = +25؇C
S
A
V
= 5V
–24
–26
–28
–30
–32
–34
S
V
= 5V, T = –40؇C
A
S
–15
–20
–25
–30
V
= 2.7V
= 5V
S
V
= 2.7V,
S
A
T
= +25؇C
V
T
= 2.7V,
S
= –40؇C
A
V
=2.7V
S
V
S
0.2
0.3
0.4
0.5
0.6
–V
0.7
0.8
0.9
1.0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95100
V
GIN
BASEBAND FREQUENCY – MHz
TPC 13. IIP3 vs. FBB, VGIN = 0.2 V, FLO = 1900 MHz
TPC 16. Noise Figure and IIP3 vs. VGIN,
Temperature = 25؇C, FLO = 1900 MHz, FBB = 1 MHz
50
45
40
35
30
25
2.5
2.0
1.5
1.0
0.5
LO FREQUENCY = 2700MHz
0
–0.5
–1.0
LO FREQUENCY = 800MHz
–1.5
LO FREQUENCY = 1900MHz
–2.0
20
–2.5
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
–20 –18 –16 –14 –12 –10
–8
–6
–4
–2
0
RF FREQUENCY – MHz
LO INPUT LEVEL – dBm
TPC 14. IIP2 vs. FLO, VGIN = 1.2 V, Baseband
Tone1 = 5 MHz, –10 dBm, Baseband Tone2 = 6 MHz,
–10 dBm, Temperature = 25؇C, VS = 5 V
TPC 17a. Quadrature Error vs. LO Power Level,
Temperature = 25؇C, VGIN = 0.2 V, VS = 5 V
13.0
12.5
12.0
11.5
11.0
14.0
13.5
13.0
12.5
12.0
2700MHz
11.5
11.0
10.5
10.0
9.5
1900MHz
800MHz
V
= 5V
S
V
= 2.7V
S
10.5
10.0
9.0
–20 –18 –16 –14 –12 –10
–8
–6
–4
–2
0
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
LO INPUT LEVEL – dBm
LO FREQUENCY – MHz
TPC 15. Noise Figure vs. LO Frequency (FLO),
TPC 17b. Noise Figure vs. LO Input Level,
Temperature = 25؇C, VGIN = 0.2 V, FBB = 1 MHz
Temperature = 25؇C, VGIN = 0.2 V, VS = 5 V
–9–
REV. 0
AD8347
BASEBAND OUTPUT AMPLIFIERS
20
34
V
= 5V, T = –40؇C
A
T
= –40؇C, V = 5V
S
S
A
T
= –40؇C, V = 2.7V
S
A
15
10
5
32
30
28
V
= 5V, T = 25؇C
A
S
T
= +25؇C, V = 5V
V = 2.7V, T = +25؇C
S A
A
S
V
T
= 5V,
S
= +85؇C
T
= +85؇C,V = 2.7V
S
V
T
= 2.7V,
0
A
A
S
V
= 2.7V, T = –40؇C
S
A
26
24
22
20
= +85؇C
A
–5
–10
–15
–20
–25
–30
T
= +25؇C, V = 2.7V
S
A
T
= +85؇C, V = 5V
S
A
18
16
1
10
100
1
10
BASEBAND FREQUENCY – MHz
100
BASEBAND FREQUENCY – MHz
TPC 20. OIP3 vs. FBB, VVCMO = 1 V
TPC 18. Gain vs. FBB, VVCMO = 1 V
8
6
5
0
T
= –40؇C, V = 5V
S
T
= +85؇C, V = 5V
S
A
A
V
= 2.7V, MEAN +
S
V
= 2.7V, MEAN
S
T
= +25؇C,
A
V
= 5V
S
4
V
= 5V, MEAN
–5
S
T
= –40؇C, V = 2.7V
S
A
V
= 5V,
S
2
MEAN +
T
= +25؇C, V = 2.7V
S
A
–10
0
T
= +85؇C,V = 2.7V
S
A
–15
–20
–2
V
= 2.7V, MEAN –
S
–4
–6
V
= 5V, MEAN –
S
–25
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1
10
BASEBAND FREQUENCY – MHz
100
V
–V
VCMO
TPC 21. Common-Mode Output Offset Voltage vs. VVCMO
,
TPC 19. OP1 vs. FBB, VVCMO = 1 V
Temperature = 25؇C ( = 1 Standard Deviation)
–10–
REV. 0
AD8347
RF AMP/DEMOD AND BASEBAND OUTPUT AMPLIFIERS
75
1.0
V
V
V
V
= 2.7V, T = –40؇C
S
S
S
S
A
0.8
0.6
0.4
0.2
= 5V, T = –40؇C
65
A
= 2.7V, T = +25؇C
A
= 5V, T = +25؇C
A
55
45
35
25
15
V
T
= 2.7V,
S
= +85؇C
A
T
= +85؇C
A
0
–0.2
–0.4
–0.6
T
= +25؇C
V
= 5V, T = +85؇C
A
A
S
T
= –40؇C
A
5
–0.8
–1.0
–5
0.2
0.3
0.4
0.5
0.6
0.7
–V
0.8
0.9
1.0
1.1
1.2
0
5
10
15
20
25
30
35
40
V
GIN
BASEBAND FREQUENCY – MHz
TPC 22. Voltage Gain vs. VVGIN, FLO = 1900 MHz,
FBB = 1 MHz
TPC 25. I/Q Amplitude Imbalance vs. FBB,
Temperature = 25؇C, VS = 5 V
2.5
2.0
1.5
1.0
0.5
0
–2
–4
V
= 5V, T = +25؇C
A
S
0
–0.5
–1.0
–1.5
–2.0
–2.5
–6
RF WITH TERMINATION
–8
V
= 5V, T = +85؇C
A
S
V
= 5V, T = –40؇C
A
–10
S
RF WITHOUT TERMINATION
–12
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY – MHz
RF FREQUENCY – MHz
TPC 23. Quadrature Phase Error vs. FLO, VVGIN = 0.7 V,
VS = 5 V
TPC 26. Return Loss of RFIP vs. FRF, VVGIN = 0.7 V, VS = 5 V
2.5
2.0
1.5
1.0
0.5
WITH TERMINATION
2.7GHz
0
T
= +85؇C
A
800MHz
–0.5
–1.0
–1.5
T
= +25؇C
A
T
= –40؇C
A
2.7GHz
800MHz
WITHOUT TERMINATION
–2.0
–2.5
0
5
10
15
20
25
30
35
40
BASEBAND FREQUENCY – MHz
TPC 24. Quadrature Phase Error vs. FBB, VVGIN = 0.7 V,
VS = 5 V
TPC 27. S11 of RFIN vs. FRF, VVGIN = 0.7 V, VS = 5 V
–11–
REV. 0
AD8347
30
25
20
1.20
1.00
0.80
0
–2
–4
T
= –40؇C
A
T
= +85؇C
= +25؇C
A
LO PORT WITHOUT TERMINATION
T
= +25؇C
A
T
= +85؇C
A
–6
–8
T
A
15
10
5
0.60
0.40
0.20
T
= –40؇C
A
–10
–12
–14
LO PORT WITH TERMINATION
0
–70
0
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
–60
–50
–40
–30
–20
–10
0
10
RF FREQUENCY – MHz
RF INPUT POWER – dBm
TPC 28. Return Loss of LOIP vs. FLO, VVGIN = 0.7 V, VP = 5 V
TPC 30. AGC Voltage and Mixer Output Level vs. RF Input
Power, FLO = 1900 MHz, FBB = 1 MHz, VS = 5 V
85
80
75
WITH TERMINATION
800MHz
V
= 5V
P
70
65
60
55
V
= 5.5V
P
2.7GHz
2.7GHz
V
= 3V
P
800MHz
V
= 2.7V
P
50
45
WITHOUT TERMINATION
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE – ؇C
TPC 29. S11 of LOIN vs. FLO, VVGIN = 0.7 V, VS = 5 V
TPC 31. Supply Current vs. Temperature, VVGIN = 0.7 V,
VVCMO = 1 V
–12–
REV. 0
AD8347
VPS1
VPS2
VPS3
VREF
IMXO IOFS
IAIN
IOPP IOPN
AD8347
VREF
BIAS
CELL
ENBL
VCMO
VREF
VCMO
RFIN
RFIP
LOIN
LOIP
PHASE
SPLITTER
1
PHASE
SPLITTER
2
COM3
COM2
COM3
COM1
VCMO
GAIN
CONTROL
INTERFACE
VGIN
DET 1
DET 2
VREF
VDT1 VAGC VDT2
QMXO QOFS
QAIN
QOPP QOPN
Figure 3. Block Diagram
terminated in resistive loads and feed the differential baseband
variable gain amplifiers for each channel. The bases of the mixer
transistors are driven by the quadrature LO signals.
CIRCUIT DESCRIPTION
OVERVIEW
The AD8347 is a direct I/Q demodulator usable in digital
wireless communication systems including Cellular, PCS, and
Digital Video receivers. An RF signal in the frequency range of
800 MHz–2700 MHz is directly downconverted to the I & Q
components at baseband using a Local Oscillator (LO) signal at
the same frequency as the RF signal.
Baseband Variable Gain Amplifiers
The baseband VGA’s also use the X-AMP approach with NPN-
differential pairs separated by sections of resistive attenuators.
The same interpolator controlling the RF amplifiers controls the
tail currents of the differential pairs. The outputs of these ampli-
fiers are provided off chip for external filtering. Automatic offset
nulling minimizes the dc offsets at both I & Q channels. The
common-mode output voltage is set to be the same as the reference
voltage (1.0 V) generated in the Bias section, also made available
at the VREF pin.
The RF input signal goes through two stages of variable gain
amplifiers before splitting up to reach two Gilbert-cell Mixers.
The mixers are driven by a pair of Local Oscillator (LO)
signals which are in quadrature (90 degrees of phase difference).
The outputs of the mixers are applied to baseband I & Q channel
variable-gain amplifiers. The outputs from these baseband
variable gain amplifiers are brought out to pins for external
filtering. The filter outputs are then applied to a pair of on-chip,
fixed-gain baseband amplifiers. These amplifiers gain up the
outputs from the external filters to a level compatible with most
A-to-D Converters. A sum-of-squares detector is available for
use in an Automatic Gain Control (AGC) loop to set the output
level. The RF and baseband amplifiers provide approximately
69.5 dB of gain control range. Additional on-chip circuits allow
the setting of the dc level at the I & Q channel baseband out-
puts, as well as nulling the dc offset at each channel.
Output Amplifiers
The output amplifiers gain up the signal coming back from each
of the external filters to a level compatible with most high speed
A-to-D converters. These amplifiers are based on an active-feedback
design to achieve the high gain bandwidth and low distortion.
LO and Phase-Splitters
The incoming LO signal is applied to a polyphase phase-splitter
to generate the LO signals for the I channel and Q channel
mixers. The polyphase phase-splitters are RC networks con-
nected in a cyclical manner to achieve gain balance and phase
quadrature. The wide operating frequency range of these phase-
splitters is achieved by cascading multiple sections of these
networks with staggered RC constants. Each branch goes through
a buffer to make up for the loss and high frequency roll-off. The
output from the buffers then go into another polyphase phase-
splitter to enhance the accuracy of phase quadrature. Each LO
signal gets buffered again to drive the mixers.
RF Variable Gain Amplifiers (VGA)
These amplifiers use the patented X-AMP approach with NPN-
differential pairs separated by sections of resistive attenuators.
The gain control is achieved through a gaussian interpolator
where the control voltage sets the tail currents to be supplied to
the different differential pairs according to the gain desired. In
the first amplifier, the combined output currents from the trans-
conductance cells go through a cascode stage to resistive loads
with inductive peaking. In the second amplifier the differential
currents are split and fed to the two Gilbert-cell mixers through
separate cascode stages.
Output Level Detector
Two signals proportional to the square of each output channel
are summed together and compared to a built-in threshold to
create an AGC voltage (VAGC). The inputs to this rms detector
are referenced to VREF.
Mixers
Bias
Two double balanced Gilbert-cell mixers, one for each channel,
perform the In-phase (I) and Quadrature (Q) down conversion.
Each mixer has four cross-connected transistor pairs which are
An accurate reference circuit generates the reference currents
used by the different sections. The reference circuit is controlled
by an external power-up (ENBL) logic signal which, when set
low, puts the whole chip into a sleep mode typically requiring
X-AMP is a registered trademark of Analog Devices, Inc.
REV. 0
–13–
AD8347
less than 400 µA of supply current. The reference voltage (VREF)
of 1.0 V, which serves as the common-mode reference for the
baseband circuits, is made available for external use.
RF Input and Matching
The RF input signal should be ac-coupled into the RFIP pin and
RFIN should be ac-coupled to ground. To improve broadband
matching to a 50 Ω source, a 200 Ω resistor may be connected
from the signal side of RFIP’s coupling capacitor to ground.
OPERATING THE AD8347
Basic Connections
LO Drive Interface
Figure 4 shows the basic connections for operating the AD8347.
The device is powered through three power supply pins: VPS1,
VPS2, and VPS3. These pins supply current to different parts of
the overall circuit. VPS1 and VPS2 power the Local Oscillator (LO)
and RF sections, respectively, while VPS3 powers the baseband
amplifiers. While all of these pins should be connected to the same
supply voltage, each pin should be separately decoupled using two
capacitors. 100 pF and 0.1 µF are recommended (values close
to these may also be used).
For optimum performance the LO inputs, LOIN and LOIP,
should be driven differentially. M/A-COM balun, ETC1-1-13
is recommended. Unless an (ac-coupled) transformer is being
used to generate the differential LO, the inputs must be ac-coupled
as shown. To improve broadband matching to a 50 Ω source, a
200 Ω shunt resistor may be connected between LOIP and LOIN.
An LO drive level of –8 dBm is recommended. TPC 17a shows
the relationship between LO drive level, LO frequency, and
quadrature error for a typical device.
A supply voltage in the range 2.7 V to 5.5 V should be used. The
quiescent current is 64 mA when operating from a 5 V supply.
By pulling the ENBL pin low, the device goes into its power- down
mode. The power-down current is 400 µA when operating on a
5 V supply and 80 µA on a 2.7 V supply.
A single-ended drive is also possible as shown in Figure 5, but
this will slightly increase LO leakage. The LO signal should be
applied through a coupling capacitor to LOIP, and LOIN should
be ac-coupled to ground. Because the inputs are fully differen-
tial, the drive orientation can be reversed. As in the case of the
differential drive, a 200 Ω resistor connected across LOIP and
LOIN improves the match to a 50 Ω source.
Like the supply pins, the individual sections of the circuit are
separately grounded. COM1, COM2, and COM3 provide ground
for the LO, RF, and baseband sections respectively. All of these
pins should be connected to the same low impedance ground.
+V
S
(2.7V–5.5V)
IOPP
24mV p-p
(AGC MODE)
1V BIAS (VREF)
C9
C10
C6
C5
C7
C8
0.1F 100pF
0.1F 100pF 0.1F 100pF
760mV p-p
DIFFERENTIAL
(AGC MODE)
C13
0.1F
V
= 1V
CM
VPS3
IOFS IAIN
VREF
IOPP
VREF
IMXO
IOPN
VPS1
VPS2
AD8347
IOPN
VREF
BIAS
CELL
ENBL
VCMO
LO INPUT
C1
100pF
–8dBm
0.8GHz–2.7GHz
C4
100pF
VCMO
RFIN
RFIP
LOIN
LOIP
R1
200⍀
3
1
4
PHASE
SPLITTER
1
R17
200⍀
PHASE
SPLITTER
2
5
C2
100pF
T1
RF INPUT
0.8GHz–2.7GHz
0dBm MAX
C3
100pF
ETC 1-1-13
(M/A-COM)
COM3
COM2
COM3
COM1
VCMO
(AGC MODE)
VGIN
GAIN
CONTROL
INTERFACE
DET 1
DET 2
VREF
QOPN
VDT1 VAGC VDT2
C15
QMXO
QOFS
QAIN
QOPP QOPN
C14
0.1F
760mV p-p
DIFFERENTIAL
(AGC MODE)
24mV p-p
(AGC MODE)
1V BIAS (VREF)
0.1F
V
= 1V
CM
QOPP
Figure 4. Basic Connections
–14–
REV. 0
AD8347
100pF
Mixer Output Level and Drive Capability
LOIN
LO
I & Q channel baseband outputs, IMXO and QMXO are low
impedance outputs (ROUT @ 3 Ω) whose bias level is equal to
VVREF, the voltage on Pin 14. The achievable output level on
IMXO/QMXO is limited by their current drive capability of
1.5 mA max. This would allow for a 600 mV p-p swing into a
200 Ω load. At lower output levels, IMXO and QMXO can
drive smaller load resistances, subject to the same current limit.
These output stages are not, however, designed to drive 50 Ω
loads directly.
200⍀
AD8347
LOIP
100pF
Figure 5. Single-Ended LO Drive
Operating the VGA
A three-stage VGA sets the gain in the RF section. Two of the
three stages come before the mixer while the third amplifies the
mixer output. All three stages are driven in parallel. The gain
range of the first RF VGA and that of the second RF VGA
combined with the mixer are both –13 dB to +10 dB. The
gain range of the baseband VGA is –4 dB to +19.5 dB. So the
overall gain range from the RF input to the IMXO/QMXO pins
is –30 dB to approximately +39.5 dB.
Operating the VGA in AGC Mode
While the VGA can be driven by an external source such as a
DAC, the AD8347 has an on-board sum of squares detector
which allows the AD8347 to operate in an automatic leveling
mode. The connections for operating in this mode are shown in
Figure 4. The two mixer outputs are connected to the detector
inputs VDT1 and VDT2. The summed detector output drives
an internal integrator which in turn delivers a gain correction
voltage to the VAGC pin. A 0.1 µF capacitor from VAGC to
ground sets the dominant pole of the integrator circuit. VAGC,
which should be connected to VGIN, adjusts gain until an
internal threshold is reached. This threshold corresponds to a level
at the IMXO/QMXO pins of approximately 8.5 mV rms. This
level will change slightly as a function of RF input power (see
TPC 30). For a CW (sine wave) input this corresponds to
The gain of the VGA is set by the voltage on the VGIN pin,
which is a high impedance input. The gain control function
(which is linear-in-dB) and linearity are shown in TPC 1 and
TPC 2 at 1.9 GHz. Note that the sense of the gain control
voltage is negative so as the gain control voltage ranges from 0.2 V
to 1.2 V, the gain decreases from +39.5 dB to –30 dB.
R19
1k⍀
+V +5V
S
R20
4k⍀
2.5V
IOPP
C9
C10
C6
C5
C7
C8
120mV p-p
1V BIAS
0.1F 100pF
0.1F 100pF 0.1F 100pF
3.8V p-p
DIFFERENTIAL
C13
0.1F
V
= 2.5V
CM
VPS3
VREF
IMXO
IOFS IAIN
VREF
IOPP
IOPN
VPS1
VPS2
AD8347
IOPN
VREF
BIAS
CELL
ENBL
VCMO
LO INPUT
C1
100pF
–8dBm
0.8GHz–2.7GHz
C4
100pF
VCMO
RFIN
RFIP
LOIN
LOIP
R1
200⍀
3
1
4
PHASE
SPLITTER
1
R17
200⍀
PHASE
SPLITTER
2
5
C2
100pF
T1
RF
INPUT
C3
100pF
ETC 1-1-13
(M/A-COM)
COM3
VCMO
COM2
COM3
COM1
VGIN
GAIN
CONTROL
INTERFACE
DET 1
DET 2
VREF
QOPN
VDT1 VAGC VDT2
QMXO
QOFS
QAIN
QOPP QOPN
C14
0.1F
3.8V p-p
DIFFERENTIAL
120mV p-p
1V BIAS
V
= 2.5V
R21
4k⍀
CM
R22
1k⍀
QOPP
Figure 6. Adjusting AGC Level to Increase Baseband Amplifier Output Swing
REV. 0
–15–
AD8347
approximately 24 mV p-p. If this signal is applied directly to the
subsequent baseband amplifier stage, the final baseband output
is 760 mV p-p differential. (See Baseband Amplifier section.)
The differential output offset voltages of the baseband amplifiers
are typically ±50 mV. This offset voltage results from both input
and output effects.
If the VGA gain is being set from an external source, the on-board
detector inputs (VDT1 and VDT2) are not used and should be
tied to VREF.
The overall signal-to-noise ratio can be improved by increasing
the VGA gain by driving it with an external voltage or by changing
the setpoint of the AGC circuit. (See Changing the AGC Setpoint.)
Note that in subsequent sections, peak-to-peak calculations
assume a sine wave input. If the input signal has a higher peak-
to-average ratio, the mixer output peak-to-peak voltage at which
the AGC loop settles will be higher.
Driving Capacitive Loads
In applications where the baseband amplifiers are driving unbal-
anced capacitive loads, some series resistance should be placed
between the amplifier and the capacitive load. For example, for
a 10 pF load, four 220 Ω series resistors (one in each baseband
output) should be used.
Changing the AGC Setpoint
The AGC circuit can be easily set up to level at voltages higher
than the nominal 24 mV p-p as shown in Figure 6. The voltages
on Pins IMXO and QMXO are attenuated before being applied
to the detector inputs. In the example shown, an attenuation
factor of 0.2 (–14 dB) between IMXO/QMXO and the detector
inputs, will cause the VGA to level at approximately 120 mV p-p
(note that resistor divider network must be referenced to VVREF).
This results in a peak-to-peak output swing at the baseband
amplifier outputs of 3.8 V differential, that is, 1.6 V to 3.4 V on
each side. Note that VVCMO has been increased to 2.5 V to avoid
signal clipping at the baseband outputs. Due to the attenuation
between the mixer output and the detector input, the variation
in the settled mixer output level, versus RF input power, will be
greater than the variation shown in TPC 30. The variation will
be greater by a factor equal to the inverse of the attenuation factor.
External Baseband Amplification
The baseband output offset voltage and noise can be reduced by
bypassing the internal baseband amplifiers and amplifying the
mixer output signal using a high quality differential amplifier. In
the example shown in Figure 7, two AD8132 differential ampli-
fiers are used to gain the mixer output signals up by 20 dB. In this
example, the setpoint of the AGC circuit has been increased so that
the input to the external amplifiers is approximately 72 mV p-p.
This results in final baseband output signals of 720 mV p-p.
The closed-loop bandwidth of the amplifiers in Figure 7 is equal
to roughly 20 MHz. Higher bandwidths are achievable, but at
the cost of lower closed-loop gain. In Figure 7, the output common
mode levels (VOCM, Pin 2) of the differential amplifiers are set
by the AD8347’s VREF (approximately 1 V). The output common
mode levels can also be set externally (e.g., by the reference voltage
from an ADC).
Baseband Amplifiers
The final baseband amplifier stage takes the signals from IMXO/
QMXO and amplifies them by 30 dB, or a factor of 31.6. This
results in a maximum system gain of 69.5 dB. When the VGA is
in AGC mode, the baseband I & Q outputs (IOPN, IOPP,
QOPN, and QOPP) deliver a differential voltage of approxi-
mately 760 mV p-p (380 mV p-p on each side).
+5V
R19A
10F
0.1F
4.99k⍀
AD8347
R17A
499⍀
72mV p-p
R22
IMXO
The single-ended input signal to the baseband amplifiers is
applied at the high impedance inputs IAIN and QAIN. As can
be seen in Figure 4, the baseband amplifier operates internally
as a differential amplifier, with the second input being driven by
VVREF. As a result, the input signal to the baseband amplifier
720mV p-p
DIFFERENTIAL
20k⍀
AD8132
VDT1
VREF
R23
10k⍀
V
= 1V
CM
R18A
499⍀
4.99k⍀
0.1F
10F
10F
R20A
should be biased at VVREF
.
–5V
+5V
The output common-mode level of the baseband amplifiers is
set by the voltage on Pin 5, VCMO. This pin can either be
connected to VREF (Pin 14) or to an external reference voltage
from a device such as an analog-to-digital converter (ADC).
R24
4.99k⍀
0.1F
10k⍀
R19B
VDT2
R17B
499⍀
R25
20k⍀
QMXO
V
VCMO has a nominal range from 0.5 V to 2.5 V. However, since
72mV p-p
720mV p-p
DIFFERENTIAL
the baseband amplifiers can only swing down to 0.4 V, higher
values of VVCMO will generally be required to avoid low-end
signal clipping. On the other hand, the positive swing at each
output is limited to 1.3 V below the supply voltage. So the max
p-p swing is given by 2 ϫ (VPS – 1.3 – 0.4) V differentially.
R18B
499⍀
AD8132
V
= 1V
CM
4.99k⍀
0.1F
10F
R20B
For example, in order for the baseband output amplifier to be able
to deliver an output swing of 2 V p-p (1 V p-p on each side),
–5V
V
VCMO must be in the range from 0.9 V to 2.5 V.
Figure 7. External Baseband Amplification Example
–16–
REV. 0
AD8347
Filter Design Considerations
50
45
Baseband low-pass or band-pass filtering can be conveniently
performed between the mixer outputs (IMXO/QMXO) and the
input to the baseband amplifiers. Because the output impedance
of the mixer is low (roughly 3 Ω) and the input impedance of
the baseband amplifier is high, it is not practical to design a
filter which is reactively matched to these impedances. An LC
filter can be matched by placing a series resistor at the mixer
output and a shunt resistor (terminated to VVREF) at the input to
the baseband amplifier.
40
35
30
25
20
15
10
5
Because the mixer output drive level is limited to a maximum cur-
rent of 1.5 mA, the characteristic impedance of the filter should be
greater than 50 Ω, especially if larger signal swings are to be achieved.
0
1
10
100
Figure 8 shows the schematic for a 100 Ω, fourth order elliptic
low-pass filter with a 3 dB cutoff frequency of 20 MHz. Source
and load impedances of approximately 100 Ω ensure that the
filter sees a matched source and load. This also ensures that the
mixer output is driving an overall load of 200 Ω. Note that the
shunt termination resistor is tied to VREF and not to ground.
The frequency response and group delay of this filter are shown
in Figures 9 and 10.
FREQUENCY – MHz
Figure 10. Group Delay of 20 MHz Baseband Low-Pass
Filter
If the VGA is operating in AGC mode, the detector input (VDT1/
VDT2) can be tied either to the input or output of the filter.
Connecting the detector input to the input of the filter (i.e.,
IMXO and QMXO) will cause the VGA leveling point to be
determined by the composite of the wanted signal and any unfiltered
components such as blockers or signal harmonics. Connecting
VDT1/VDT2 to the outputs of the filters ensures that the leveling
point of the AGC circuit is based upon the amplitude of the
filtered output only. The latter option is more desirable as it
results in a more constant baseband output. However, when
using this method, the leveling point of the AGC should be set
so that out-of-band blockers do not overdrive the mixer output.
C1
4.7pF
C3
8.2pF
L
L
3
RS
R3
R4
2⍀
1
95.3⍀
2⍀
0.68H
1.2H
C2
150pF
C4
RL
82pF 100⍀
DC Offset Compensation
IMXO
VREF
IAIN VDT1
(SEE
TEXT)
Feedthrough of the LO signal to the RF input port results in
self-mixing of the LO signal. This produces a dc component
at the mixer output that is frequency-dependent.
AD8347
Figure 8. Typical Baseband Low-Pass Filter
The AD8347 includes an internal circuit which actively nulls
out any dc offsets that appear at the mixer output. The dc-bias
0
level of the mixer output (which should ideally be equal to VVREF
the bias level for the baseband sections of the chip) is continually
being compared to VVREF. Any differences between the mixer
output level and VVREF, will force a compensating voltage on to
the mixer output.
,
–10
–20
–30
–40
The time constant of this correction loop is set by the capacitors
which are connected to pins IOFS and QOFS (each output can
be compensated separately). For normal operation 0.1 µF capacitors
are recommended. The corner frequency of the compensation
loop is given approximately by the equation
–50
–60
–70
–80
40
COFS
f3 dB
=
C
in µF
(
)
OFS
1
10
100
FREQUENCY – MHz
The corner frequency must be set to a frequency that is much
lower than the symbol rate of the demodulated data. This prevents
the compensation loop from falsely interpreting the data stream
as a changing offset voltage.
Figure 9. Frequency Response of 20 MHz Baseband
Low-Pass Filter
To disable the offset compensation circuits, IOFS and QOFS
should be tied to VREF.
REV. 0
–17–
AD8347
Evaluation Board
Figure 11 shows the schematic of the AD8347 evaluation board.
Note that uninstalled components are indicated with the “open”
designation. The board is powered by a single supply in the
range of 2.7 V to 5.5 V. Table I details the various configuration
options of the evaluation board.
TP1
J3
LO
+V
S
4
3
5
1
R35
0⍀
T1
ETC 1-1-13
R37
0⍀
J6
IOPN
J1
QOPN
C2
100pF
C3
100pF
R17
200⍀
R36
0⍀
J5
IOPP
R38
0⍀
C6
C5
C1
0.1F
AD8347
0.1F 100pF
J2
QOPP
1
2
LOIN 28
LOIP
VPS1
IOPN
IOPP
VCMO
IAIN
J11
VCMO
COM1 27
QOPN 26
QOPP 25
3
L6
(OPEN)
L5
(OPEN)
L4
(OPEN)
R33
0⍀
4
R34
(OPEN)
TP5
5
24
23
22
21
20
19
18
17
16
15
R6
QAIN
COM3
QMXO
VPS3
VDT1
VAGC
VDT2
VGIN
J8
QMXO
0⍀
L3
(OPEN)
L2
(OPEN)
L1
(OPEN)
6
LK4
R40
C30
(OPEN)
C26
(OPEN)
C31
(OPEN)
R8
(OPEN)
LK5
7
COM3
IMXO
COM2
RFIN
RFIP
+V
S
J7
IMXO
C28
(OPEN)
C25
(OPEN)
C29
(OPEN)
C27
(OPEN)
8
C9
0.1F
C10
100pF
R39
LK6
C18
(OPEN)
C4
(OPEN)
C19
(OPEN)
(OPEN)
9
J9
VAGC
10
11
12
13
14
C11
100pF
C21
(OPEN)
C15
0.1F
C22
(OPEN)
C20
(OPEN)
C17
(OPEN)
LK3
(OPEN)
R18
200⍀
J4
C12
VPS2
IOFS
VREF
LK1
RFIP
100pF
J10
TP6
QOFS
ENBL
+V
S
VGIN
V
POS
C8
100pF
C7
0.1F
A
TP2
TP3
C14
0.1F
SW1
LK2
C13
0.1F
B
C16
0.1F
Figure 11. Evaluation Board Schematic
–18–
REV. 0
AD8347
Figure 12. Silkscreen of Component Side
Figure 13. Layout of Component Side
Figure 14. Layout of Circuit Side
REV. 0
–19–
AD8347
Table I. Evaluation Board Configuration Options
Component
Function
Default Condition
TP1, TP4, TP5
TP2, TP6
TP3
Power Supply and Ground Vector Pins
IOFS and QOFS Probe Points
VREF Probe Point
Baseband Amplifier Output Bias: Installing this link connects VREF
to VCMO. This sets the bias level on the baseband amplifiers to VREF,
which is equal to approximately 1 V. Alternatively, the bias level of the
baseband amplifiers can be set by applying an external voltage to SMA
connector J11.
Not Applicable
Not Applicable
Not Applicable
LK1 Installed
LK1, J11
LK2, LK6, LK3, J9, J10
AGC Mode: Installing LK2 and LK6 connects the mixer outputs IMXO LK2, LK6, LK3 Installed
and QMXO to the detector inputs VDT2 and VDT1. By installing LK3,
which connects VGIN to VAGC, the AGC mode is activated. The AGC
voltage can be observed on SMA connector J9. With LK3 removed, the
gain control signal for the internal variable gain amplifiers should be
applied to SMA connector J10.
LK4, LK5
R6, R33,
L1–L5
Baseband Filtering: Installing LK4 and LK5, connects the mixer
outputs IMXO and QMXO directly to the baseband amplifier inputs
IAIN and QAIN. With R6 and R33 installed (0 Ω), IAIN and QAIN
LK4, LK5 Installed
R6 = R33 = 0 Ω (Size 0603)
L1–L5 = Open (Size 0805)
C4, C17–C22, C25–C31
R8, R34, R39, R40
can be observed on SMA connectors J7 and J8. By removing LK4 and LK5 C4, C17–C22, C25–C31 =
and installing R8 and R34, LC filters can be inserted between the
mixer outputs and the baseband amplifier inputs. R8 and R34 can be
used to increase the effective output impedance of IMXO and QMXO.
(These outputs have low output impedances.) R39 and R40 can be used
to provide terminations for the filter at IAIN and QAIN. (IAIN and QAIN
are high impedance inputs.) R39 and R40 are terminated to VREF.
Baseband Amplifier Output Series Resistors
Open (Size 0805)
R8 = R34 = Open (0603)
R39 = R40 = Open (0603)
R35, R36, R37, R38
SW1
R35 = R36 = R37 = R38 =
0 Ω (Size 0603)
Device Enable: When in position A, the ENBL pin is connected to +VS
and the AD8347 is in operating mode. In position B, the ENBL pin is
grounded, putting the device in power-down mode.
SW1 = A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead TSSOP
(RU-28)
0.386 (9.80)
0.378 (9.60)
28
15
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
14
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0256 (0.65) 0.0118 (0.30)
BSC
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
0.0075 (0.19)
–20–
REV. 0
相关型号：
AD8347ARU-REEL7
800 MHz - 2700 MHz RF/MICROWAVE QUADRAPHASE DEMODULATOR, MO-153AE, RU-28, TSSOP-28
ROCHESTER
AD8347ARUZ
800MHz - 2700MHz RF/MICROWAVE QUADRAPHASE DEMODULATOR, MO-153AE, RU-28, TSSOP-28
ROCHESTER
AD8347ARUZ-REEL7
800MHz - 2700MHz RF/MICROWAVE QUADRAPHASE DEMODULATOR, MO-153AE, RU-28, TSSOP-28
ROCHESTER
©2020 ICPDF网 联系我们和版权申明