AD7274BRMZ-REEL2 [ADI]
3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT; 3 MSPS ， 10位/ 12位ADC，采用8引脚TSOT
| 型号： | AD7274BRMZ-REEL2 |
| 厂家： | 
ADI |
| 描述： | 3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| 文件： | 总29页 (文件大小：549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 MSPS,10-/12-Bit
ADCs in 8-Lead TSOT
AD7273/AD7274
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Throughput rate: 3 MSPS
V
DD
AGND
Specified for VDD of 2.35 V to 3.6 V
Power consumption
11.4 mW at 3 MSPS with 3 V supplies
Wide input bandwidth
70 dB SNR at 1 MHz input frequency
Flexible power/serial clock speed management
No pipeline delays
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
T/H
IN
V
REF
High speed serial interface
SCLK
SDATA
CS
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Temperature range: −40°C to +125°C
Power-down mode: 0.1 μA typ
8-lead TSOT package
CONTROL
LOGIC
AD7273/AD7274
8-lead MSOP package
DGND
Figure 1.
GENERAL DESCRIPTION
Table 1.
Part Number
AD72731
AD72741
AD7276
The AD7273/AD7274 are 10-/12-bit, high speed, low power,
successive approximation ADCs, respectively. The parts operate
from a single 2.35 V to 3.6 V power supply and feature
throughput rates of up to 3 MSPS. Each part contains a low
noise, wide bandwidth track-and-hold amplifier that can handle
input frequencies in excess of 55 MHz.
Resolution
Package
10
12
12
10
8
8-lead MSOP
8-lead MSOP
8-lead MSOP
8-lead MSOP
8-lead MSOP
8-Lead TSOT
8-Lead TSOT
6-Lead TSOT
6-Lead TSOT
6-Lead TSOT
AD7277
AD7278
The conversion process and data acquisition are controlled
1 Parts contain external reference pin.
using
and the serial clock, allowing the devices to interface
CS
with microprocessors or DSPs. The input signal is sampled on
the falling edge of , and the conversion is also initiated at this
CS
point. The conversion rate is determined by the SCLK. There
are no pipeline delays associated with these parts.
PRODUCT HIGHLIGHTS
1. 3 MSPS ADCs in an 8-lead TSOT package.
2. High throughput with low power consumption.
3. Flexible power/serial clock speed management.
The AD7273/AD7274 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
Allows maximum power efficiency at low throughput rates.
4. Reference can be driven up to the power supply.
5. No pipeline delay.
The reference for the parts is applied externally and can be in
the range of 1.4 V to VDD. This allows the widest dynamic input
range to the ADC.
6. The parts feature a standard successive approximation ADC
with accurate control of the sampling instant via a
input
CS
and once-off conversion control.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
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Last content update 11/12/2013 05:15 pm
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AD7273/AD7274
TABLE OF CONTENTS
Features .............................................................................................. 1
ADC Transfer Function............................................................. 15
Typical Connection Diagram ....................................................... 16
Analog Input ............................................................................... 16
Digital Inputs .............................................................................. 16
Modes of Operation ....................................................................... 17
Normal Mode.............................................................................. 17
Partial Power-Down Mode ....................................................... 17
Full Power-Down Mode ............................................................ 17
Power-Up Times......................................................................... 18
Power vs. Throughput Rate....................................................... 20
Serial Interface ................................................................................ 21
Microprocessor Interfacing....................................................... 23
Application Hints ........................................................................... 24
Grounding and Layout .............................................................. 24
Evaluating the AD7273/AD7274 Performance......................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7274 Specifications................................................................. 3
AD7273 Specifications................................................................. 5
Timing Specifications .................................................................. 7
Timing Examples.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 14
Circuit Information........................................................................ 15
Converter Operation.................................................................. 15
REVISION HISTORY
9/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7273/AD7274
SPECIFICATIONS
AD7274 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, VREF = 2.35 V to VDD, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
B Grade1
Unit2
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)3
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)3
fIN = 1 MHz sine wave
68
dB min
dB min
dB max
dB typ
dB typ
69.5
−73
−78
−80
Peak Harmonic or Spurious Noise (SFDR)3
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
−82
−82
5
dB typ
dB typ
ns typ
fa = 1 MHz, fb = 0.97 MHz
fa = 1 MHz, fb = 0.97 MHz
Aperture Jitter
Full Power Bandwidth
18
55
8
ps typ
MHz typ
MHz typ
dB typ
@ 3 dB
@ 0.1 dB
Power Supply Rejection Ratio (PSRR)
DC ACCURACY
82
Resolution
12
1
1
3
3.5
3.5
Bits
Integral Nonlinearity3
Differential Nonlinearity3
Offset Error3
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 12 bits
Gain Error3
Total Unadjusted Error (TUE)3
ANALOG INPUT
Input Voltage Range
DC Leakage Current
0 to VREF
V
1
5.5
42
10
μA max
μA max
pF typ
pF typ
−40°C to +85°C
85°C to 125°C
When in track
When in hold
Input Capacitance
REFERENCE INPUT
VREF Input Voltage Range
DC leakage Current
Input Capacitance
Input Impedance
1.4 to VDD
V min/V max
μA max
pF typ
1
20
32
Ω typ
LOGIC INPUTS
Input High Voltage, VINH
1.7
2
V min
V min
2.35 V ≤ VDD ≤ 2.7 V
2.7 V < VDD ≤ 3.6 V
Input Low Voltage, VINL
Input Current, IIN
0.7
0.8
1
V max
V max
μA max
pF max
2.35 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 3.6 V
Typically 10 nA, VIN = 0 V or VDD
4
Input Capacitance, CIN
2
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
VDD − 0.2
0.2
2.5
V min
ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V
ISINK = 200 μA
V max
μA max
pF max
4.5
Straight (natural) binary
Rev. 0 | Page 3 of 28
AD7273/AD7274
Parameter
B Grade1
Unit2
Test Conditions/Comments
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time3
Throughput Rate
POWER RQUIREMENTS
VDD
291
60
3
ns max
ns max
MSPS max
14 SCLK cycles with SCLK at 48 MHz
See the Serial Interface section
2.35/3.6
V min/V max
IDD
Digital I/Ps = 0 V or VDD
VDD = 3 V, SCLK on or off
VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS
VDD = 3 V
Normal Mode (Static)
Normal Mode (Operational)
1
5
3.8
34
2
mA typ
mA max
mA typ
μA typ
μA max
μA max
Partial Power-Down Mode (Static)
Full Power-Down Mode (Static)
−40°C to +85°C, typically 0.1 μA
85°C to 125°C
10
Power Dissipation5
Normal Mode (Operational)
18
mW max
mW typ
μW max
μW max
VDD = 3.6 V , fSAMPLE = 3 MSPS
VDD = 3 V
VDD = 3 V
11.4
102
7.2
Partial Power-Down
Full Power-Down
VDD = 3.6 V, −40°C to +85°C
1 Temperature range from −40°C to +125°C.
2 Typical specifications are tested with VDD = 3 V and VREF = 3 V at 25°C.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
Rev. 0 | Page 4 of 28
AD7273/AD7274
AD7273 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, VREF = 2.35 V to VDD, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
B Grade1
Unit2
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)3
Total Harmonic Distortion (THD)3
fIN = 1 MHz sine wave
61
dB min
dB max
dB typ
dB typ
−72
−77
−80
Peak Harmonic or Spurious Noise (SFDR)3
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
−81
−81
5
dB typ
dB typ
ns typ
fa = 1 MHz, fb = 0.97 MHz
fa = 1 MHz, fb = 0.97 MHz
Aperture Jitter
Full Power Bandwidth
18
74
10
82
ps typ
MHz typ
MHz typ
dB typ
@ 3 dB
@ 0.1 dB
Power Supply Rejection Ratio (PSRR)
DC ACCURACY
Resolution
10
0.5
0.5
1
1.5
2.5
Bits
Integral Nonlinearity3
Differential Nonlinearity3
Offset Error3
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 10 bits
Gain Error3
Total Unadjusted Error (TUE)3
ANALOG INPUT
Input Voltage Range
DC Leakage Current
0 to VREF
V
1
5.5
42
10
μA max
μA max
pF typ
pF typ
−40°C to +85°C
85°C to 125°C
When in track
When in hold
Input Capacitance
REFERENCE INPUT
VREF Input Voltage Range
DC leakage Current
Input Capacitance
Input Impedance
1.4 to VDD
V min/V max
μA max
pF typ
1
20
32
Ω typ
LOGIC INPUTS
Input High Voltage, VINH
1.7
2
V min
V min
2.35 V ≤ VDD ≤ 2.7 V
2.7 V < VDD ≤ 3.6 V
Input Low Voltage, VIN
0.7
0.8
1
V max
V max
μA max
pF max
2.35 V ≤ VDD< 2.7 V
2.7 V ≤ VDD ≤ 3.6 V
Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN
Input Capacitance, CIN
4
2
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
VDD − 0.2
0.2
2.5
V min
ISOURCE = 200 μA; VDD = 2.35 V to 3.6 V
ISINK = 200 μA
V max
μA max
pF max
4.5
Straight (natural) binary
CONVERSION RATE
Conversion Time
250
60
3.45
ns max
ns max
MSPS max
12 SCLK cycles with SCLK at 48 MHz
See the Serial Interface section
Track-and-Hold Acquisition Time3
Throughput Rate
Rev. 0 | Page 5 of 28
AD7273/AD7274
Parameter
B Grade1
Unit2
Test Conditions/Comments
POWER RQUIREMENTS
VDD
2.35/3.6
V min/V max
IDD
Digital I/Ps = 0 V or VDD
VDD = 3 V, SCLK on or off
VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS
VDD = 3 V
Normal Mode (Static)
Normal Mode (Operational)
0.6
5
3.2
34
2
mA typ
mA max
mA typ
μA typ
μA max
μA max
Partial Power-Down Mode (Static)
Full Power-Down Mode (Static)
−40°C to +85°C, typically 0.1 μA
85°C to 125°C
10
Power Dissipation5
Normal Mode (Operational)
18
mW max
mW typ
μW max
μW max
VDD = 3.6 V , fSAMPLE = 3 MSPS
VDD = 3 V
VDD = 3 V
9.6
102
7.2
Partial Power-Down
Full Power-Down
VDD = 3.6 V, −40°C to +85°C
1 Temperature range from −40°C to +125°C.
2 Typical specifications are tested with VDD = 3 V and VREF = 3 V at 25°C.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
Rev. 0 | Page 6 of 28
AD7273/AD7274
TIMING SPECIFICATIONS
VDD = 2.35 V to 3.6 V; VREF = 2.35 to VDD; TA = TMIN to TMAX, unless otherwise noted.1 Guaranteed by characterization. All input signals
are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 4.
Limit at TMIN, TMAX
AD7273/AD7274
Parameter
Unit
kHz min3
Description
2
fSCLK
500
48
MHz max
tCONVERT
tQUIET
14 × tSCLK
12 × tSCLK
4
AD7274
AD7273
ns min
Minimum quiet time required between bus relinquish and start of
next conversion
t1
t2
3
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
μs max
Minimum CS pulse width
6
CS to SCLK setup time
4
t3
4
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA three-state
SCLK falling edge to SDATA three-state
CS rising edge to SDATA three-state
Power-up time from full power-down
4
t4
15
0.4 tSCLK
0.4 tSCLK
5
14
5
4.2
1
t5
t6
t7
4
t8
t9
5
tPOWER-UP
1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Minimum fSCLK at which specifications are guaranteed.
4 The time required for the output to cross the VIH or VIL voltage.
5 See the Power-Up Times section
t4
t8
SCLK
SCLK
V
V
IH
1.4V
SDATA
SDATA
IL
Figure 2. Access Time After SCLK Falling Edge
Figure 4. SCLK Falling Edge SDATA Three-State
t7
SCLK
V
IH
SDATA
V
IL
Figure 3. Hold Time After SCLK Falling Edge
Rev. 0 | Page 7 of 28
AD7273/AD7274
Timing Example 2
TIMING EXAMPLES
The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time
of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and
For the AD7274, if
rising edge after the two leading zeros and 12 bits of the
conversion are provided, the part can achieve the fastest
is brought high during the 14th SCLK
CS
t
ACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) +
throughput rate, 3 MSPS. If
is brought high during the 16th
CS
t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum
requirement of 4 ns for tQUIET.
SCLK rising edge after the two leading zeros, 12 bits of the
conversion, and two trailing zeros are provided, a throughput
rate of 2.97 MSPS is achievable. This is illustrated in the
following two timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz, and
the throughput is 3 MSPS. This produces a cycle time of
t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns min and
t
ACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ
.
Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t9 + tQUIET
,
where t9 = 4.2 ns max. This allows a value of 52.8 ns for tQUIET
,
satisfying the minimum requirement of 4 ns.
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
5
13
14
t5
15
16
t8
t7
t3
tQUIET
t4
Z
ZERO
DB11
DB10
DB9
DB1
DB0
ZERO
ZERO
SDATA
THREE-
STATE
THREE-STATE
TWO LEADING
ZEROS
TWO TRAILING
ZEROS
1/THROUGHPUT
Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
5
13
t5
14
t9
t7
t3
ZERO
tQUIET
t4
Z
DB11
DB10
DB9
DB1
DB0
SDATA
THREE-
STATE
THREE-STATE
TWO LEADING
ZEROS
1/THROUGHPUT
Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle
t1
CS
tCONVERT
t2
B
SCLK
1
2
3
4
5
12
13
14
15
t8
16
tQUIET
12.5(1/f
SCLK
)
tACQUISITION
1/THROUGHPUT
Figure 7. Serial Interface Timing 16 SCLK Cycle
Rev. 0 | Page 8 of 28
AD7273/AD7274
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameters
Ratings
VDD to AGND/DGND
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
10 mA
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial (B Grade)
Storage Temperature Range
Junction Temperature
6-Lead TSOT Package
−40°C to +125°C
−65°C to +150°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
8-Lead MSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature Soldering
Reflow (10 to 30 sec)
230°C/W
92°C/W
205.9°C/W
43.74°C/W
255°C
Lead Temperature Soldering
Reflow (10 to 30 sec)
ESD
260°C
1.5 kV
1 Transient currents of up to 100 mA cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 9 of 28
AD7273/AD7274
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
6
5
AGND
CS
DD
V
1
2
3
4
8
7
6
5
V
IN
DD
AD7273/
AD7274
TOP VIEW
SDATA
DGND
AD7273/
AD7274
TOP VIEW
SDATA
CS
DGND
SCLK
SCLK
(Not to Scale)
V
V
REF
IN
AGND
V
(Not to Scale)
REF
Figure 8. 8-Lead MSOP Pin Configuration
Figure 9. 8-Lead TSOT Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
MSOP TSOT
Mnemonic
VDD
Description
1
2
1
2
Power Supply Input. The VDD range for the AD7273/AD7274 is from 2.35 V to 3.6 V.
SDATA
Data Out. Logic output. The conversion result from the AD7273/AD7274 is provided on this output as a
serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from
the AD7274 consists of two leading zeros followed by the 12 bits of conversion data and two trailing
zeros, provided MSB first. The data stream from the AD7273 consists of two leading zeros followed
by the 10 bits of conversion data and four trailing zeros, provided MSB first.
3
4
5
7
8
5
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversion on
the AD7273/AD7274 and framing the serial data transfer.
Analog Ground. Ground reference point for all circuitry on the AD7273/AD7274. All analog signals
and any external reference signal should be referred to this AGND voltage.
Voltage Reference Input. This pin becomes the reference voltage input. An external reference should
be applied at this pin. The external reference input range is 1.4 V to VDD. A 10 μF capacitor should be
tied between this pin and AGND.
AGND
VREF
6
7
6
3
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the conversion process of AD7273/AD7274.
Digital Ground. Ground reference point for all digital circuitry on the AD7273/AD7274. The DGND and
AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even
on a transient basis.
DGND
8
4
VIN
Analog Input. Single-ended analog input channel. The input range is 0 to VREF.
Rev. 0 | Page 10 of 28
AD7273/AD7274
TYPICAL PERFORMANCE CHARACTERISTICS
72.2
72.0
71.8
71.6
71.4
71.2
71.0
70.8
V
= 3V
DD
F
= 3MSPS
16384 POINT FFT
SAMPLE
–20
F
F
= 3MSPS
SAMPLE
= 1MHz
IN
V
= 2.5V
DD
SINAD = 71.05
V
= 3.6V
THD = –80.9
SFDR = –82.2
–40
–60
DD
–80
–100
–120
70.6
70.4
70.2
100
1000
1500
INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 13. AD7274 SNR vs. Analog Input Frequency at 3 MSPS
for Various Supply Voltages, SCLK Frequency = 48 MHz
Figure 10. AD7274 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz
–72
–74
–76
16384 POINT FFT
–20
F
F
= 3MSPS
SAMPLE
= 1MHz
IN
SINAD = 66.56
THD = –77.4
SFDR = –78.2
–40
–60
V
= 3V
DD
–78
–80
–82
–84
V
= 2.5V
DD
–80
V
= 3.6V
DD
–86
–88
–90
–100
–120
100
1000
1500
INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 14. THD vs. Analog Input Frequency at 3 MSPS
for Various Supply Voltages, SCLK Frequency = 48 MHz
Figure 11. AD7273 Dynamic Performance at 3 MSP, Input Tone = 1 MHz
72.2
–40
F
= 3MSPS
72.0
71.8
SAMPLE
71.6
71.4
71.2
71.0
70.8
70.6
70.4
70.2
70.0
69.8
69.6
–50
–60
–70
V
= 3.6V
DD
R
= 100Ω
IN
R
= 10Ω
IN
V
= 2.5V
DD
–80
–90
V
= 3V
69.4
69.2
69.0
DD
R
= 0Ω
IN
100
1000
1500
100
1000
1500
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 12. AD7274 SINAD vs. Analog Input Frequency at 3 MSPS
for Various Supply Voltages, SCLK Frequency = 48 MHz
Figure 15. THD vs. Analog Input Frequency at 3 MSPS for Various Source
Impedance, SCLK Frequency = 48 MHz, Supply Voltage = 3 V
Rev. 0 | Page 11 of 28
AD7273/AD7274
–70
1.0
0.8
0.6
–80
–90
0.4
POSITIVE INL
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
NEGATIVE INL
–100
100mV p-p SINE WAVE ON AV
NO DECOUPLING
DD
–110
0
500 1000
1500
2000
2500
3000
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY RIPPLE FREQUENCY (MHz)
REFERENCE VOLTAGE (V)
Figure 16. Power Supply Rejection Ratio (PSRR) vs. Supply Ripple
Frequency Without Decoupling
Figure 19. Change in INL vs. Reference Voltage, 3 V Supply
1.0
1.0
V
= 3V
DD
0.8
0.6
0.8
0.6
POSITIVE DNL
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
NEGATIVE DNL
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
0
500
1000 1500 2000 2500 3000 3500
CODES
4000
REFERENCE VOLTAGE (V)
Figure 17. AD7274 INL Performance
Figure 20. Change in DNL vs. Reference Voltage, 3 V Supply
1.0
0.8
3.60
V
= 3V
DD
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
0.6
V
= 3V
DD
0.4
V
= 3.6V
DD
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 2.5V
DD
1.20
1.00
0.80
0.60
0
10
20
30
40
50
0
500
1000 1500 2000 2500 3000 3500
CODES
4000
SCLK FREQUENCY (MHz)
Figure 21. Maximum Current vs. Supply Voltage
for Different SCLK Frequencies
Figure 18. AD7274 DNL Performance
Rev. 0 | Page 12 of 28
AD7273/AD7274
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
12.0
30,000 CODES
11.5
11.0
10.5
10.0
2045
2046
2047
2048
2049
2050
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
CODE
V
(V)
REF
Figure 22. Histogram of Codes for 30,000 Samples
Figure 23. ENOB/SINAD vs. Reference Voltage
Rev. 0 | Page 13 of 28
AD7273/AD7274
TERMINOLOGY
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7273/
AD7274, the endpoints of the transfer function are zero scale at
0.5 LSB below the first code transition and full scale at 0.5 LSB
above the last code transition.
Peak Harmonic or Spurious Noise (SFDR)
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2, excluding dc) to the rms value
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum; however,
for ADCs with harmonics buried in the noise floor, it is deter-
mined by a noise peak.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
Intermodulation Distortion (IMD)
The deviation of the first code transition (00 . . . 000) to (00 . . .
001) from the ideal, that is, AGND + 0.5 LSB.
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa nfb, where m and
n = 0, 1, 2, 3, …. Intermodulation distortion terms are those for
which neither m nor n are equal to zero. For example, the second-
order terms include (fa + fb) and (fa − fb), and the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Gain Error
The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal, that is, VREF – 1.5 LSB, after
adjusting for the offset error.
Total Unadjusted Error (TUE)
The AD7273/AD7274 are tested using the CCIF standard in
which two input frequencies are used (see fa and fb in the
Specifications section). In this case, the second-order terms are
usually distanced in frequency from the original sine waves, and
the third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in decibels.
A comprehensive specification that includes gain, linearity, and
offset errors.
Track-and-Hold Acquisition Time
The time required for the output of the track-and-hold amplifier
to reach its final value, within 0.5 LSB, after the end of the
conversion. See the Serial Interface section for more details.
Signal-to-Noise + Distortion Ratio (SINAD)
The measured ratio of signal to noise plus distortion at the
output of the ADC. The signal is the rms amplitude of the
fundamental, and noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), including
harmonics but excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process: the
more levels, the smaller the quantization noise. For an ideal N-bit
converter, the SINAD is
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 100 mV p-p sine wave applied to
the ADC VDD supply of frequency fS.
PSRR
(
dB
)
=10 log
Pf PfS
where Pf is the power at frequency f in the ADC output; PfS is
the power at frequency fS coupled onto the ADC VDD supply.
SINAD = 6.02 N + 1.76 dB
According to this equation, the SINAD is 74 dB for a 12-bit
converter and 62 dB for a 10-bit converter. However, various
error sources in the ADC, including integral and differential
nonlinearities and internal ac noise sources, cause the measured
SINAD to be less than its theoretical value.
Aperture Delay
The measured interval between the leading edge of the sampling
clock and the point at which the ADC actually takes the sample.
Aperture Jitter
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. It is
defined as:
The sample-to-sample variation in the effective point in time at
which the sample is taken.
2
2
2
2
2
V2 + V3 + V4 + V5 + V6
THD dB = 20 log
( )
V1
Rev. 0 | Page 14 of 28
AD7273/AD7274
CIRCUIT INFORMATION
The AD7273/AD7274 are high speed, low power, 10-/12-bit,
single supply ADCs, respectively. The parts can be operated
from a 2.35 V to 3.6 V supply. When operated from any supply
voltage within this range, the AD7273/AD7274 are capable of
throughput rates of 3 MSPS when provided with a 48 MHz clock.
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced
(see Figure 25). The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 26 shows the ADC transfer function.
The AD7273/AD7274 provide the user with an on-chip track-
and-hold ADC and a serial interface housed in an 8-lead TSOT
or an 8-lead MSOP package, which offers the user considerable
space-saving advantages over alternative solutions. The serial
clock input accesses data from the part and provides the clock
source for the successive approximation ADC. The analog input
range is 0 to VREF. An external reference in the range of 1.4 V to
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
A
V
IN
VDD is required by the ADC.
CONTROL
LOGIC
SW1
SW2
ACQUISITION
PHASE
B
The AD7273/AD7274 also feature a power-down option to save
power between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
COMPARATOR
V
/2
DD
AGND
Figure 25. ADC Conversion Phase
ADC TRANSFER FUNCTION
CONVERTER OPERATION
The output coding of the AD7273/AD7274 is straight binary.
The designed code transitions occur midway between
successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The
LSB size is VREF/4,096 for the AD7274 and VREF/1,024 for the
AD7273. The ideal transfer characteristic for the
The AD7273/AD7274 are successive approximation ADCs
based on a charge redistribution DAC. Figure 24 and Figure 25
show simplified schematics of the ADC. Figure 24 shows the
ADC during its acquisition phase, where SW2 is closed, SW1 is
in Position A, the comparator is held in a balanced condition,
and the sampling capacitor acquires the signal on VIN.
AD7273/AD7274 is shown in Figure 26.
CHARGE
REDISTRIBUTION
DAC
111...111
111...110
SAMPLING
111...000
011...111
CAPACITOR
A
V
IN
CONTROL
LOGIC
SW1
SW2
ACQUISITION
PHASE
1LSB = V
1LSB = V
/4096 (AD7274)
/1024 (AD7273)
REF
REF
B
000...010
000...001
000...000
COMPARATOR
V
/2
DD
AGND
0.5LSB
+V – 1.5LSB
REF
0V
Figure 24. ADC Acquisition Phase
ANALOG INPUT
Figure 26. AD7273/AD7274 Transfer Characteristic
Rev. 0 | Page 15 of 28
AD7273/AD7274
TYPICAL CONNECTION DIAGRAM
on resistance of a switch. This resistor is typically about 75 Ω.
Capacitor C2 is the ADC sampling capacitor and has a capacitance
of 32 pF typically. For ac applications, removing high frequency
components from the analog input signal is recommended by
using a band-pass filter on the relevant analog input pin. In
applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances significantly affect
the ac performance of the ADCs. This may necessitate the use
of an input buffer amplifier. The AD8021 op amp is compatible
with this device; however, the choice of the op amp is a function
of the particular application.
Figure 27 shows a typical connection diagram for the AD7273/
AD7274. An external reference must be applied to the ADC.
This reference can be in the range of 1.4 V to VDD. A precision
reference, such as the REF19x family or the ADR421, can be
used to supply the reference voltage to the AD7273/AD7274.
The conversion result is output in a 16-bit word with two leading
zeros followed by the 12-bit or 10-bit result. The 12-bit result from
the AD7274 is followed by two trailing zeros, and the 10-bit result
from the AD7273 is followed by four trailing zeros.
Table 7 provides some typical performance data with various
references under the same setup conditions for the AD7274.
V
DD
Table 7. AD7274 Performance (Various Voltage Reference IC)
D1
AD7274 SNR Performance
1 MHz Input
C2
R1
Voltage Reference
AD780 @ 2.5 V
AD780 @ 3 V
REF195
V
IN
C1
4pF
71.3 dB
70.1 dB
D2
CONVERSION PHASE–SWITCH OPEN
TRACK PHASE–SWITCH CLOSED
70.9 dB
Figure 28. Equivalent Analog Input Circuit
3.6V
SUPPLY
4.6 mA
When no amplifier is used to drive the analog input, the source
impedance should be limited to a low value. The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD increases as the source impedance increases and perfor-
mance degrades. Figure 14 shows a graph of the THD vs. the
analog input frequency for different source impedances when
using a supply voltage of 3 V and sampling at a rate of 3 MSPS.
0.1μF
10μF
0V TO V
INPUT
V
DD
V
V
REF
IN
SCLK
SDATA
CS
AD7273/
AD7274
2.5V
REF195
REF
DSP/
μC/μP
10pF
0.1μF
AGND/DGND
SERIAL
INTERFACE
DIGITAL INPUTS
Figure 27. AD7273/AD7274 Typical Connection Diagram
The digital inputs applied to the AD7273/AD7274 are not
limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs can be applied at up to 6 V and are
not restricted by the VDD + 0.3 V limit of the analog inputs. For
example, if the AD7273/AD7274 were operated with a VDD of
3 V, then 5 V logic levels could be used on the digital inputs.
However, it is important to note that the data output on SDATA
still has 3 V logic levels when VDD = 3 V. Another advantage of
ANALOG INPUT
Figure 28 shows an equivalent circuit of the analog input
structure of the AD7273/AD7274. The two diodes, D1 and D2,
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 300 mV. Signals exceeding this value
cause these diodes to become forward biased and to start
conducting current into the substrate. These diodes can
conduct a maximum current of 10 mA without causing
irreversible damage to the part. Capacitor C1 in Figure 28 is
typically about 4 pF and can primarily be attributed to pin
capacitance. Resistor R1 is a lumped component made up of the
SCLK and
not being restricted by the VDD + 0.3 V limit is
CS
that power supply sequencing issues are avoided. For example,
unlike with the analog inputs, with the digital inputs, if or
CS
SCLK are applied before VDD, there is no risk of latch-up.
Rev. 0 | Page 16 of 28
AD7273/AD7274
MODES OF OPERATION
The mode of operation of the AD7273/AD7274 is selected by
To enter partial power-down mode, interrupt the conversion
th
controlling the logic state of the
signal during a conversion.
CS
CS
process by bringing
high between the second and 10 falling
CS
There are three possible modes of operation: normal mode,
partial power-down mode, and full power-down mode. The
edges of SCLK, as shown in Figure 30. Once
is brought high
in this window of SCLKs, the part enters partial power-down
mode, the conversion that was initiated by the falling edge of
CS
point at which
determines which power-down mode, if any, the device enters.
CS
is pulled high after the conversion is initiated
CS
CS
is terminated, and SDATA goes back into three-state. If
Similarly, if the device is already in power-down mode,
control whether the device returns to normal operation or
can
is brought high before the second SCLK falling edge, the part
remains in normal mode and does not power down. This prevents
CS
remains in power-down mode. These modes of operation are
designed to provide flexible power management options, which
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements.
accidental power-down due to glitches on the
line.
To exit this mode of operation and power up the AD7274/
AD7273, perform a dummy conversion. On the falling edge of
CS
long as
, the device begins to power up and continues to power up as
th
NORMAL MODE
CS
is held low until after the falling edge of the 10 SCLK.
The device is fully powered up once 16 SCLKs elapse; valid data
CS
This mode is intended for fastest throughput rate performance
because the AD7273/AD7274 remain fully powered at all times,
eliminating worry about power-up times. Figure 29 shows the
general diagram of the operation of the AD7273/AD7274 in
this mode.
results from the next conversion, as shown in Figure 31. If
brought high before the 10th falling edge of SCLK, the AD7274/
AD7273 goes into full power-down mode. Therefore, although
CS
is
the device may begin to power up on the falling edge of , it
CS
powers down on the rising edge of
as long as this occurs
The conversion is initiated on the falling edge of
as described
CS
in the Serial Interface section. To ensure that the part remains
fully powered up at all times, must remain low until at least
before the 10th SCLK falling edge.
CS
10 SCLK falling edges elapse after the falling edge of . If
brought high any time after the 10th SCLK falling, but before the
16th SCLK falling edge, the part remains powered up, but the
conversion is terminated, and SDATA goes back into three-state.
If the AD7273/AD7274 is already in partial power-down mode
th
CS
is
and
is brought high before the 10 falling edges of SCLK, the
CS CS
device enters full power-down mode. For more information on
the power-up times associated with partial power-down mode
in various configurations, see the Power-Up Times section.
FULL POWER-DOWN MODE
For the AD7274, a minimum of 14 serial clock cycles are
required to complete the conversion and access the complete
conversion result. For the AD7273, a minimum of 12 serial
clock cycles are required to complete the conversion and access
the complete conversion result.
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, because power-up from a full power-down takes
substantially longer than that from a partial power-down. This
mode is suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by
a long period of inactivity and thus power-down.
can idle high until the next conversion or low until
CS
CS
returns high before the next conversion (effectively idling
CS
low). Once a data transfer is complete (SDATA has returned to
three-state), another conversion can be initiated after the quiet
When the AD7273/AD7274 are in full power-down mode, all
analog circuitry is powered down. To enter full power-down
mode put the device into partial power-down mode by bringing
time, tQUIET, has elapsed by bringing
low again.
CS
high between the second and 10th falling edges of SCLK. In
PARTIAL POWER-DOWN MODE
CS
the next conversion cycle, interrupt the conversion process in
the way shown in Figure 32 by bringing
high before the 10th
This mode is intended for use in applications where slower
throughput rates are required. An example of this is when either
the ADC is powered down between each conversion or a series
of conversions is performed at a high throughput rate and then
the ADC is powered down for a relatively long duration between
these bursts of several conversions.
CS
is brought high in this window of
SCLK falling edge. Once
CS
SCLKs, the part powers down completely. Note that it is not
necessary to complete 16 SCLKs once is brought high to enter
CS
either of the power-down modes. Glitch protection is not
available when entering full power-down mode.
When the AD7273/AD7274 are in partial power-down mode,
all analog circuitry is powered down except the bias generation
circuit.
To exit full power-down mode and power up the AD7273/
AD7274 again, perform a dummy conversion, similar to when
powering up from partial power-down mode. On the falling
Rev. 0 | Page 17 of 28
AD7273/AD7274
CS
mode, the track-and-hold, which is in hold mode while the part
is powered down, returns to track mode after the first SCLK
edge of , the device begins to power up and continues to
power up until after the falling edge of the 10th SCLK as long as
CS
edge is received after the falling edge of . This is shown as
CS
is held low. The power-up time required must elapse before
Point A in Figure 31.
a conversion can be initiated, as shown in Figure 33. See the
Power-Up Times section for the power-up times associated with
the AD7273/AD7274.
When power supplies are first applied to the AD7273/AD7274,
the ADC can power up in either of the power-down modes or
in normal mode. Because of this, it is best to allow a dummy
cycle to elapse to ensure that the part is fully powered up before
attempting a valid conversion. Likewise, if the part is to be kept
in partial power-down mode immediately after the supplies are
POWER-UP TIMES
The AD7273/AD7274 has two power-down modes, partial
power-down and full power-down, which are described in
detail in the Modes of Operation section. This section deals
with the power-up time required when coming out of either of
these modes.
applied, two dummy cycles must be initiated. The first dummy
th
CS
cycle must hold
low until after the 10 SCLK falling edge
CS
(see Figure 29). In the second cycle,
must be brought high
between the second and 10th SCLK falling edges (see Figure 30).
To power up from partial power-down mode, one cycle is
required. Therefore, with a SCLK frequency of up to 48 MHz,
one dummy cycle is sufficient to allow the device to power up
from partial power-down mode. Once the dummy cycle is
complete, the ADC is fully powered up and the input signal is
acquired properly. The quiet time, tQUIET, must be allowed from
the point where the bus goes back into three-state after the
Alternatively, if the part is to be placed into full power-down
mode after the supplies are applied, three dummy cycles must
CS
be initiated. The first dummy cycle must hold
low until after
the 10th SCLK falling edge (see Figure 29); the second and third
dummy cycles place the part into full power-down mode (see
Figure 32). See also the Modes of Operation section.
CS
dummy conversion to the next falling edge of
.
To power up from full power-down, approximately 1 μs should
CS
be allowed from the falling edge of , shown in Figure 33 as
tPOWER-UP. Note that during power-up from partial power-down
AD7273/AD7674
CS
1
10
12
14
16
SCLK
SDATA
VALID DATA
Figure 29. Normal Mode Operation
Rev. 0 | Page 18 of 28
AD7273/AD7274
CS
SCLK
1
2
10
16
THREE-STATE
SDATA
Figure 30. Entering Partial Power-Down Mode
THE PART IS FULLY
POWERED UP, SEE POWER-
UP TIMES SECTION
THE PART BEGINS
TO POWER UP
CS
1
10
16
1
16
SCLK
A
SDATA
INVALID DATA
VALID DATA
Figure 31. Exiting Partial Power-Down Mode
THE PART ENTERS
PARTIAL POWER DOWN
THE PART BEGINS
TO POWER UP
THE PART ENTERS
FULL POWER DOWN
CS
1
2
10
16
1
10
16
SCLK
THREE-STATE
THREE-STATE
INVALID DATA
VALID DATA
SDATA
Figure 32. Entering Full Power-Down Mode
THE PART BEGINS
TO POWER UP
THE PART IS
FULLY POWERED UP
tPOWER-UP
CS
1
10
16
1
16
SCLK
SDATA
INVALID DATA
VALID DATA
Figure 33. Exiting Full Power-Down Mode
Rev. 0 | Page 19 of 28
AD7273/AD7274
7.00
6.60
6.20
5.80
5.40
5.00
4.60
4.20
3.80
3.40
V
= 3V
DD
POWER VS. THROUGHPUT RATE
Figure 34 shows the power consumption of the device in
normal mode, in which the part is never powered down. By
using the power-down mode of the AD7273/AD7274 when not
performing a conversion, the average power consumption of the
ADC decreases as the throughput rate decreases.
48MHz SCLK
Figure 35 shows that as the throughput rate is reduced, the
device remains in its power-down state longer and the average
power consumption over time drops accordingly. For example,
if the AD7273/AD7274 are operated in continuous sampling
mode with a throughput rate of 200 kSPS and a SCLK of 48 MHz
(VDD = 3 V) and the devices are placed into power-down mode
between conversions, the power consumption is calculated as
follows. The power dissipation during normal operation is
11.6 mW (VDD = 3 V). If the power-up time is one dummy
cycle, that is, 333 ns, and the remaining conversion time is
290 ns, the AD7273/AD7274 can be said to dissipate 11.6 mW
for 623 ns during each conversion cycle. If the throughput rate
is 200 kSPS, the cycle time is 5 ꢀs and the average power dissipated
during each cycle is 623/5,000 × 9.6 mW = 1.42 mW. Figure 35
shows the power vs. throughput rate when using the partial
power-down mode between conversions at 3 V. The power-
down mode is intended for use with throughput rates of less
than 600 kSPS, because at higher sampling rates there is no
power saving achieved by using the power-down mode.
VARIABLE SCLK
200
400
600
800 1000 1200 1400 1600 1800 2000
THROUGHPUT (kSPS)
Figure 34. Power vs. Throughput, Normal Mode
7.2
6.8
6.4
6.0
5.6
5.2
4.8
4.4
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
V
= 3V
DD
0
200
400
600
800
1000
THROUGHPUT (kSPS)
Figure 35. Power vs. Throughput, Partial Power-Down Mode
Rev. 0 | Page 20 of 28
AD7273/AD7274
SERIAL INTERFACE
Figure 36 through Figure 38 show the detailed timing diagrams
for serial interfacing to the AD7274 and AD7273, respectively.
The serial clock provides the conversion clock and controls the
transfer of information from the AD7273/AD7274 during
conversion.
If the user considers a 14-SCLK cycle serial interface for the
AD7273/AD7274,
must be brought high after the 14th SCLK
CS
falling edge. Then the last two trailing zeros are ignored, and
SDATA goes back into three-state. In this case, the 3 MSPS
throughput can be achieved by using a 48 MHz clock frequency.
The
signal initiates the data transfer and conversion process.
CS
going low clocks out the first leading zero to be read by the
CS
The falling edge of
and takes the bus out of three-state. The analog input is sampled
and the conversion is initiated at this point.
puts the track-and-hold into hold mode
CS
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Therefore, the first falling clock edge on the serial
clock provides the first leading zero and clocks out the second
leading zero. The final bit in the data transfer is valid on the 16th
falling edge, because it is clocked out on the previous (15th)
falling edge.
For the AD7274, the conversion requires completing 14 SCLK
cycles. Once 13 SCLK falling edges have elapsed, the track-and-
hold goes back into track mode on the next SCLK rising edge,
as shown in Figure 36 at Point B. If the rising edge of
occurs
CS
In applications with a slower SCLK, it is possible to read data on
each SCLK rising edge. In such cases, the first falling edge of
SCLK clocks out the second leading zero and can be read on the
first rising edge. However, the first leading zero clocked out
before 14 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the last two bits are zeros and SDATA
returns to three-state on the 16th SCLK falling edge, as shown in
Figure 37.
when
goes low is missed if read within the first falling edge.
CS
The 15th falling edge of SCLK clocks out the last bit and can be
read on the 15th rising SCLK edge.
For the AD7273, the conversion requires completing 12 SCLK
cycles. Once 11 SCLK falling edges elapse, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
If
goes low just after one SCLK falling edge elapses,
CS
CS
shown in Figure 38 at Point B. If the rising edge of
occurs
CS
clocks out the first leading zero and can be read on the SCLK
rising edge. The next SCLK falling edge clocks out the second
leading zero and can be read on the following rising edge.
before 12 SCLKs elapse, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the AD7273 clocks out four trailing
zeros for the last four bits and SDATA returns to three-state on
the 16th SCLK falling edge, as shown in Figure 38.
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
5
13
t5
14
SCLK
t7
t9
t3
t4
DB9
tQUIET
SDATA
Z
ZERO
DB11
DB10
DB1
DB0
THREE-
STATE
THREE-STATE
TWO LEADING
ZEROS
1/THROUGHPUT
Figure 36. AD7274 Serial Interface Timing Diagram 14 SCLK Cycle
Rev. 0 | Page 21 of 28
AD7273/AD7274
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
5
13
14
t5
15
16
SCLK
t8
t7
t3
ZERO
t4
tQUIET
SDATA
Z
DB11
DB10
DB9
DB1
DB0
ZERO
ZERO
THREE-
STATE
THREE-STATE
TWO LEADING
ZEROS
TWO TRAILING
ZEROS
1/THROUGHPUT
Figure 37. AD7274 Serial Interface Timing Diagram 16 SCLK Cycle
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
10
11
12
13
14
15
16
SCLK
t5
t8
t7
t3
ZERO
t4
tQUIET
SDATA
Z
DB9
DB8
DB1
DB0
ZERO
ZERO
ZERO
ZERO
THREE-
STATE
THREE-STATE
TWO LEADING
ZEROS
FOUR TRAILING
ZEROS
1/THROUGHPUT
Figure 38. AD7273 Serial Interface Timing Diagram
Rev. 0 | Page 22 of 28
AD7273/AD7274
Table 8. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
MICROPROCESSOR INTERFACING
AD7273/AD7274 to ADSP-BF53x
Setting
Description
The ADSP-BF53x family of DSPs interfaces directly to the
AD7273/AD7274 without requiring glue logic. The SPORT0
Receive Configuration 1 register should be set up as outlined in
Table 8.
RCKFE = 1
LRFS = 1
RFSR = 1
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
IRFS = 1
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
Receive MSB first
Zero fill
Internal receive clock
Receive enabled
16-bit data-word (or can be set to 1101 for a
14-bit data-word)
AD7273/
AD72741
ADSP-BF53x1
SPORT0
RCLK0
SCLK
DOUT
CS
DR0PRI
RFS0
DT0
TFSR = RFSR = 1
DIN
1
ADDITIONAL PINS OMITTED FOR CLARITY
To implement the power-down modes, set SLEN to 1001 to
issue an 8-bit SCLK burst.
Figure 39. Interfacing to the ADSP-BF53x
Rev. 0 | Page 23 of 28
AD7273/AD7274
APPLICATION HINTS
Good decoupling is also important. All analog supplies should
be decoupled with 10 ꢀF ceramic capacitors in parallel with
0.1 ꢀF capacitors to AGND/DGND. To achieve the best results
from these decoupling components, they must be placed as close
as possible to the device, ideally right up against the device. The
0.1 ꢀF capacitors should have low effective series resistance
(ESR) and low effective series inductance (ESI), such as is typical
of common ceramic or surface-mount types of capacitors.
Capacitors with low ESR and low ESI provide a low impedance
path to ground at high frequencies, which allows them to
handle transient currents due to internal logic switching.
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7273/AD7274
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This design
facilitates using ground planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All AGND pins of the AD7273/
AD7274 should be sunk into the AGND plane. Digital and
analog ground planes should be joined in only one place. If the
AD7273/AD7274 are in a system where multiple devices require
an AGND-to-DGND connection, the connection should be
made at only one point, a star ground point, established as close
as possible to the ground pin on the AD7273/AD7274.
EVALUATING THE AD7273/AD7274 PERFORMANCE
The recommended layout for the AD7273/AD7274 is outlined
in the evaluation board documentation. The evaluation board
package includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from a
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the AD7273/AD7274
evaluation board, as well as many other Analog Devices evaluation
boards ending in the CB designator, to demonstrate/evaluate the
ac and dc performance of the AD7273/AD7274.
Avoid running digital lines under the device, because this
couples noise onto the die. However, the analog ground plane
should be allowed to run under the AD7273/AD7274 to avoid
noise coupling. The power supply lines to the AD7273/AD7274
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
To avoid radiating noise to other sections of the board,
components with fast-switching signals, such as clocks, should
be shielded with digital ground, and they should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. To reduce the effects of feedthrough within the board,
traces on opposite sides of the board should run at right angles
to each other. A microstrip technique is by far the best method,
but it is not always possible to use this approach with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, and signals are placed on the
solder side.
The software allows the user to perform ac (fast Fourier trans-
form) and dc (histogram of codes) tests on the AD7273/AD7274.
The software and documentation are on a CD shipped with the
evaluation board.
Rev. 0 | Page 24 of 28
AD7273/AD7274
OUTLINE DIMENSIONS
2.90 BSC
3.00
BSC
8
1
7
2
6
3
5
4
1.60 BSC
2.80 BSC
8
1
5
4
4.90
BSC
3.00
BSC
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
PIN 1
*
0.90
0.87
0.84
0.65 BSC
1.10 MAX
*
0.15
0.00
0.20
0.08
1.00 MAX
0.60
0.45
0.30
0.80
8°
4°
0°
8°
0°
0.60
0.40
0.38
0.22
0.38
0.22
0.23
0.08
0.10 MAX
SEATING
PLANE
COPLANARITY
0.10
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 40. 8-Lead Thin Small Outline Transistor Package [TSOT]
Figure 41. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
(UJ-8)
Dimensions shown in millimeters
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Linearity
Package
Model
Error (LSB)1
Package Description
Option
RM-8
RM-8
RM-8
UJ-8
Branding
AD7274BRM
AD7274BRMZ2
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
1 max
1 max
1 max
1 max
1 max
1 max
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
8-Lead Thin Small Outline Transistor Package (TSOT)
8-Lead Thin Small Outline Transistor Package (TSOT)
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
8-Lead Thin Small Outline Transistor Package (TSOT)
8-Lead Thin Small Outline Transistor Package (TSOT)
Evaluation Board
C1V
C34
C34
C1V
C34
C34
C33
C33
C1U
C33
AD7274BRMZ-REEL2
AD7274BUJ-500RL7
AD7274BUJZ-500RL72
AD7274BUJZ-REEL72
AD7273BRMZ2
AD7273BRMZ-REEL2
AD7273BUJ-REEL7
AD7273BUJZ-500RL72
EVAL-AD7274CB3
EVAL-AD7273CB3
EVAL-CONTROL BRD24
UJ-8
UJ-8
0.5 max
0.5 max
0.5 max
0.5 max
RM-8
RM-8
UJ-8
UJ-8
Evaluation Board
Control Board
1 Linearity error refers to integral nonlinearity.
2 Z = Pb-free part.
3 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.
4 This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards that end in a CB designator. To order a complete
evaluation kit, the particular ADC evaluation board (such as EVAL-AD7273CB/AD7274CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the
relevant evaluation board technical note for more information.
Rev. 0 | Page 25 of 28
AD7273/AD7274
NOTES
Rev. 0 | Page 26 of 28
AD7273/AD7274
NOTES
Rev. 0 | Page 27 of 28
AD7273/AD7274
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04973–0–9/05(0)
Rev. 0 | Page 28 of 28
相关型号：
AD7274BUJ-500RL7
1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MO-193-BA, TSOT-8
ROCHESTER
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