AD7274BUJ-REEL [ADI]
3MSPS,10-/12-Bit ADCs in 8-Lead TSOT; 3MSPS ， 10位/ 12位ADC，采用8引脚TSOT
| 型号： | AD7274BUJ-REEL |
| 厂家： | 
ADI |
| 描述： | 3MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| 文件： | 总20页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARYTECHNICALDATA
3MSPS,10-/12-Bit
a
Preliminary Technical Data
ADCs in 8-Lead TSOT
AD7273/AD7274
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast Throughput Rate: 3MSPS
Specified for VDD of 2.35 V to 3.6V
Low Power:
13.5 mW max at 3MSPS with 3V Supplies
Wide Input Bandwidth:
V
GND
DD
70dB SNR at 1MHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPITM/QSPITM/MICROWIRETM/DSPCompatible
Power Down Mode: 1µA max
8-Lead TSOT Package
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
V
T/H
IN
REF
8-Lead MSOP Package
SCLK
CONTROL
LOGIC
SDATA
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
AD7273/AD7274
MobileCommunications
Instrumentation and Control Systems
Data Acquisition Systems
High-SpeedModems
GND
Optical Sensors
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7273/AD7274 are 10-bit and 12-bit, high speed,
low power, successive-approximation ADCs respectively.
The parts operate from a single 2.35V to 3.6 V power
supply and feature throughput rates up to 3 MSPS. The
parts contain a low-noise, wide bandwidth track/hold am-
plifier which can handle input frequencies in excess of
TBD MHz.
1. 3MSPS ADCs in an 8-lead TSOT package.
2. High Throughput with Low Power Consumption.
3. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. This allows the average
power consumption to be reduced when a power-down
mode is used while not converting. The AD7273/
AD7274 features a power down mode to maximize
power efficiency at lower throughput rates. Current con-
sumption is 1 µA max when in Power Down mode.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. The conversion rate is deter-
mined by the SCLK. There are no pipeline delays associ-
ated with the part.
4. Reference can be driven up to the power supply.
5. No Pipeline Delay.
The AD7273/AD7274 use advanced design techniques to
achieve very low power dissipation at high throughput
rates.
The parts feature a standard successive-approximation
ADC with accurate control of the sampling instant via a
CS input and once-off conversion control.
The reference for the parts is applied externally and can
be in the range of 1.2V to VDD. This allows the widest
dynamic input range to the ADC.
REV. PrB (6/04)
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights ofAnalog Devices.Trademarks
and registered tradermarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
Analog Devices, Inc., 2004
PRELIMINARYTECHNICALDATA
(VDD=+2.35 V to +3.6 V, VREF= +2.5V , fSCLK=52 MHz, fSAMPLE=3 MSPS unless other-
wise noted; TA=TMIN to TMAX, unless otherwise noted.)
AD7273-SPECIFICATIONS
Parameter
B Grade1
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
fIN = 1 MHz Sine Wave
61
-73
-74
dB min
dB max
dB max
-82
-82
TBD
TBD
TBD
TBD
TBD
dB typ
dB typ
ns typ
fa= TBD kHz, fb= TBD kHz
fa= TBD kHz, fb= TBD kHz
ps typ
MHz typ
MHz typ
dB typ
@ 3 dB
@ 0.1dB
Full Power Bandwidth
Power Supply Rejection Ratio (PSRR)
DC ACCURACY
Resolution
10
0.5
0.5
1
TBD
1
Bits
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error2
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB typ
LSB max
Guaranteed No Missed Codes to 10 Bits
Gain Error2
TBD
TBD
Total Unadjusted Error (TUE)2
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
0 to VREF
0.5
TBD
Volts
µA max
pF typ
REFERENCE INPUT
VREF Input Voltage Range
DC leakage Current
Input Capacitance
1.2 to VDD
TBD
TBD
Vmin/Vmax
µA max
pF max
Input Impedance
TBD
kΩ typ
LOGIC INPUTS
Input High Voltage, VINH
0.7(VDD) V min
V min
0.2(VDD) V max
2.35Vр Vdd р2.7V
2.7V< Vdd р 3.6V
2.35VрVdd< 2.7V
2
Input Low Voltage, VINL
0.8
0.5
TBD
10
V max
2.7V рVddр 3.6V
Typically TBD nA, VIN= 0 V or VDD
Input Current, IIN, SCLK Pin
µA max
µA max
pF max
Input Current, IIN, CS Pin
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDD - 0.2
0.2
1
10
V min
ISOURCE= 200 µA,VDD= 2.35 V to 3.6 V
ISINK= 200µA
V max
µA max
pF max
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
230
50
3
ns max
ns max
MSPS max
12 SCLK cycles with SCLK at 52 MHz
Track/Hold Acquisition Time2
Throughput Rate
N O T E S
1Temperature range from –40°C to +85°C.
2See Terminology.
3Guaranteed by Characterization.
Specifications subject to change without notice.
REV. PrB
–2–
PRELIMINARYTECHNICALDATA
(VDD=+2.35 V to +3.6 V, VREF= +2 .5V, fSCLK=52 MHz, fSAMPLE=3MSPS unless
otherwise noted; TA=TMIN to TMAX, unless otherwise noted.)
AD7273-SPECIFICATIONS
Parameter
B Grade1
Units
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.35/3.6
V min/Vmax
ID D
Digital I/Ps= 0V or VDD
Normal Mode(Static)
Normal Mode (Operational)
Full Power-Down Mode (Static)
Full Power-Down Mode (Dynamic)
2.5
4.5
1
mA typ
mA max
µA max
mA typ
VDD= 2.35V to 3.6V, SCLK On or Off
VDD= 2.35V to 3.6V, fSAMPLE = 3MSPS
SCLK On or Off, typically TBD nA
VDD= 3V, fSAMPLE = 1MSPS
TBD
Power Dissipation4
Normal Mode (Operational)
Full Power-Down
13.5
3
mW max
µW max
VDD=3V, fSAMPLE = 3MSPS
VDD=3V
N O T E S
1Temperature range from –40°C to +85°C.
2See Terminology.
3Guaranteed by Characterization.
4See Power Versus Throughput Rate section.
Specifications subject to change without notice.
REV. PrB
–3–
PRELIMINARYTECHNICALDATA
(VDD=+2.35 V to +3.6 V, VREF= +2.5V, fSCLK=52 MHz, fSAMPLE=3MSPS unless otherwise
AD7274-SPECIFICATIONS noted; TA=TMIN to TMAX, unless otherwise noted.)
Parameter
B Grade1
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Term
Aperture Delay
Aperture Jitter
Full Power Bandwidth
fIN = 1 MHz Sine Wave
70
71
-80
-82
dB min
dB min
dB typ
dB typ
-84
-84
TBD
TBD
TBD
TBD
TBD
dB typ
dB typ
ns typ
ps typ
fa= TBD kHz, fb= TBD kHz
fa= TBD kHz, fb= TBD kHz
MHz typ @ 3 dB
MHz typ @ 0.1dB
dB typ
Full Power Bandwidth
Power Supply Rejection Ratio (PSRR)
DC ACCURACY
Resolution
12
1
1
Bits
LSB max
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error2
LSB max Guaranteed No Missed Codes to 12 Bits
TBD LSB max
TBD LSB max
TBD LSB max
Gain Error2
Total Unadjusted Error (TUE)2
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
0 to VREF
0.5
TBD
Volts
µA max
pF typ
REFERENCE INPUT
VREF Input Voltage Range
DC leakage Current
Input Capacitance
1.2 to VDD Vmin/Vmax
TBD
TBD
TBD
µA max
pF max
kΩ typ
Input Impedance
LOGIC INPUTS
Input High Voltage, VINH
0.7(VDD
2
0.2(VDD
0.8
)
)
V min
V min
V max
V max
2.35Vр Vdd р2.7V
2.7V < Vddр 3.6V
2.35VрVdd< 2.7V
2.7V рVddр 3.6V
Input Low Voltage, VINL
Input Current, IIN,SCLK Pin
0.5
µA max Typically TBD nA, VIN= 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, CIN
TBD
10
µA max
pF max
3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDD - 0.2
V min
V max
µA max
pF max
ISOURCE= 200 µA;VDD= 2.35 V to 3.6 V
ISINK=200 µA
0.2
1
10
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
270
50
3
ns max
ns max
14 SCLK Cycles with SCLK at 52 MHz
Track/Hold Acquisition Time2
Throughput Rate
MSPS max See Serial Interface Section
N O T E S
1Temperature range from –40°C to +85°C.
2See Terminology.
3Guranteed by Characterization.
Specifications subject to change without notice.
REV. PrB
–4–
PRELIMINARYTECHNICALDATA
(VDD=+2.35 V to +3.6 V, VREF= + 2.5V, fSCLK=52 MHz, fSAMPLE=3MSPS unless
otherwise noted; TA=TMIN to TMAX, unless otherwise noted.)
AD7274 SPECIFICATIONS
Parameter
B Grade1
Units
Test Conditions/Comments
POWER REQUIREMENTS
VDD
IDD
2.35/3.6
V min/Vmax
mA typ
Digital I/Ps= 0V or VDD
VDD= 2.35V to 3.6V,SCLK On or Off
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode(Static)
Full Power-Down Mode(Dynamic)
2.5
4.5
1
mA max VDD= 2.35V to 3.6V, fSAMPLE=3MSPS
µA max
mA typ
SCLK On or Off, typically TBD nA
DD= 3V, fSAMPLE=1MSPS
TBD
V
Power Dissipation4
Normal Mode (Operational)
Full Power-Down
13.5
3
mW max VDD= 3 V, fSAMPLE= 3MSPS
µW max VDD= 3 V
N O T E S
1Temperature range from –40°C to +85°C.
2See Terminology.
3Guranteed by Characterization.
4
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
REV. PrB
–5–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
TIMING SPECIFICATIONS1
(VDD= +2.35 V to +3.6 V; VREF = 2.5V, TA= TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX
Parameter
AD7273/AD7274
Units
Description
2
fSCLK
20
52
KHz min3
MHz max
tCONVERT
14 x tSCLK
12 x tSCLK
AD7274
AD7273
tQUIET
TBD
ns min
Minimum Quiet Time required between Bus Relinquish
and start of Next Conversion
t1
10
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
µs max
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS Until SDATA Three-State Disabled
Data Access Time After SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State
SCLK Falling Edge to SDATA Three-State
Power Up Time from Full Power-down
t24
t34
t4
TBD
TBD
TBD
0.4tSCLK
0.4tSCLK
TBD
TBD
TBD
TBD
t5
t64
t75
t8
6
tpower-up
N O T E S
1Guaranteed by Characterization. All input signals are specified with tr=tf=5ns (10% to 90% of VDD) and timed from a voltage level of 1.6Volts.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Minimum fsclk at which specifications are guaranteed.
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage.
5t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
6See Power-up Time section.
Specifications subject to change without notice.
I
OL
200µA
t
7
SCLK
TO
OUTPUT
PIN
+1.6V
C
L
25pF
SDATA
V
IH
200µA
I
OH
V
IL
Figure 3. Hold time after SCLK falling edge
Figure 1. Load Circuit for Digital Output
Timing Specifications
t
t
8
4
SCLK
SCLK
SDATA
SDATA
1.6 V
V
IH
V
IL
Figure 2. Access time after SCLK falling edge
Figure 4. SCLK falling edge to SDATA Three-State
REV. PrB
–6–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
Figures 5 and 6 show some of the timing parameters from the Timing Specifications table.
t1
tconvert
t2
t6
B
SCLK
3
1
2
4
5
13
15
16
14
t5
t7
t8
tquiet
t3
t4
DB9
DB1
Z
ZERO
DB11
DB10
DB0
ZERO
ZERO
SDATA
THREE-
STATE
THREE-STATE
2 TRAILING
ZERO’S
2 LEADING
ZERO’S
1/ THROUGHPUT
Figure 5. AD7274 Serial Interface Timing Diagram
Timing Example 1
From Figure 6, having fSCLK = 52 MHz and a throughput of 3MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ
333 ns. With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ
=
.
Figure 6 shows that, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a value of TBD
ns for tQUIET satisfying the minimum requirement of TBD ns.
Timing Example 2
Having fSCLK = 20 MHz and a throughput of 1.5 MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 666 ns.
With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ. From
Figure 6, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a values of TBD ns for
tQUIET satisfying the minimum requirement of TBD ns.
t1
tconvert
t2
B
SCLK
3
4
5
1
2
14
15
16
12
13
t8
tquiet
12.5(1/fSCLK)
tacquisition
1/THROUGHPUT
Figure 6. Serial Interface Timing Example
REV. PrB
–7–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
8-lead MSOP Package
VDD to GND......................................-0.3 V to TBD V
Analog Input Voltage to GND......–0.3 V to VDD + 0.3 V
Reference Input Voltage to GND...–0.3 V to VDD + 0.3 V
Digital Input Voltage to GND..............–0.3 V to TBD V
Digital Output Voltage to GND....–0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2.......... 10 mA
θJA Thermal Impedance.................................205.9°C/W
θJC Thermal Impedance...............................43.74°C/W
Lead Temperature Soldering
Reflow (10-30 secs)....................................+TBD°C
ESD..................................................................TBDKV
N O T E S
Operating Temperature Range
1Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Commercial (B Grade)......................–40°C to +85°C
Storage Temperature Range..............–65°C to +150°C
Junction Temperature..........................................150°C
8-lead TSOT Package
2Transient currents of up to 100 mA will not cause SCR latch up.
θJA Thermal Impedance.................................TBD°C/W
θJC Thermal Impedance................................TBD°C/W
PIN CONFIGURATION
AD7273/AD7274
V
V
1
2
3
4
8
7
6
5
1
8
7
6
5
GND
V
DD
DD
IN
AD7273/
AD7274
AD7273/
AD7274
GND
SDATA
2
3
4
SDATA
SCLK
GND
SCLK
TOP VIEW
TOP VIEW
V
GND
V
V
IN
REF
REF
(Not to Scale)
(Not to Scale)
8-lead MSOP
8-lead TSOT
ORDERING GUIDE
Temperature
Range
Linearity
Package
Option
Package
Description
Branding
Information
Model
Error (LSB)1
AD7274BUJ-REEL
AD7274BRM
AD7273BUJ-REEL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
1 max
1 max
0.5 max
UJ-8
RM-8
UJ-8
TSOT
MSOP
TSOT
MSOP
TBD
TBD
TBD
TBD
AD7273BRM
0.5 max
RM-8
N O T E S
1Linearity error here refers to integral nonlinearity.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7273/AD7274 feature proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrB
–8–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
C S
Chip Select. Active low logic input. This input provides the dual function of initiating
conversion on the AD7273/AD7274 and also frames the serial data transfer.
VD D
Power Supply Input. The VDD range for the AD7273/AD7274 is from +2.35V to +3.6V.
Analog Ground. Ground reference point for all circuitry on the AD7273/AD7274. All
analog input signals should be referred to this GND voltage.
GND
VIN
Analog Input. Single-ended analog input channel. The input range is 0 to VREF.
VREF
Voltage Reference Input. This pin becomes the reference voltage input and an external
reference should be applied at this pin. The external reference input range is 1.2V to VDD. A
TBD µF capacitor should be tied between this pin and AGND.
SDATA
SCLK
Data Out. Logic output. The conversion result from the AD7273/AD7274 is provided on
this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK
input. The data stream from the AD7274 consists of two leading zeros followed by the 12
bits of conversion data followed by two trailing zeros, which is provided MSB first. The data
stream from the AD7273 consists of two leading zeros followed by the 10 bits of conversion
data followed by four trailing zeros, which is provided MSB first.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part.
This clock input is also used as the clock source for the AD7273/AD7274's conversion
process.
REV. PrB
–9–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
TERMINOLOGY
Integral Nonlinearity (INL)
Total Harmonic Distortion (THD)
This is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
For the AD7273/AD7274, the endpoints of the transfer
function are zero scale, a 1/2 LSB below the first code
transition, and full scale, a point 1/2 LSB above the last
code transition.
Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. It is defined as:
2
2
2
V2 +V32 +V 4 +V52 +V 6
THD (dB ) = 20 log
V1
Differential Nonlinearity (DNL)
This is the difference between the measured and the
ideal 1 LSB change between any two adjacent codes in
the ADC.
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Offset Error
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
This is the deviation of the first code transition (00 . . .
000) to (00 . . . 001) from the ideal, i.e, AGND + 0.5 LSB
.
Gain Error
This is the deviation of the last code transition (111 . . .
110) to (111 . . . 111) from the ideal, i.e, VREF
–
1.5LSB after the offset error has been adjusted out.
Total Unadjusted Error (TUE)
This is a comprehensive specification which includes gain,
linearity and offset errors.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
Track/Hold Acquisition Time
The Track/Hold acquisition time is the time required
for the output of the track/hold amplifier to reach its
final value, within 0.5 LSB, after the end of
conversion. See Serial Interface section for more details.
mfa
nfb where m, n ꢀ ꢁ, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Signal to Noise Ratio (SNR)
This is the measured ratio of signal to noise at the
output to the A/D converter. The signal is the rms value
of the sine wave input. Noise is the rms quantization
error within the Nyquist bandwitdh (fs/2). The rms
value of a sine wave is one half its peak to peak value
divided by √2 and the rms value for the quantization
noise is q/√12. The ratio is dependant on the number of
quantization levels in the digitization process; the more
levels, the smaller the quantization noise. For an ideal
N-bit converter, the SNR is defined as:
The AD7273/AD7274 are tested using the CCIF standard
where two input frequencies are used (see fa and fb in the
specification page). In this case, the second order terms
are usually distanced in frequency from the original sine
waves while the third order terms are usually at a fre-
quency close to the input frequencies. As a result, the
second and third order terms are specified separately. The
calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of
the sum of the fundamentals expressed in dBs.
SNR = 6.02 N + 1.76 dB
Power Supply Rejection Ratio (PSRR)
Thus for a 12-bit converter this is 74 dB, for a 10-bit
converter it is 62 dB.
Practically, though, various error sources in the ADC
cause the measured SNR to be less than the theoretical
value. These errors occur due to integral and differential
nonlinearities, internal AC noise sources, etc.
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the
power of a 2ꢁꢁ mV p-p sine wave applied to the ADC VDD
supply of frequency fs.
PSRR (dB) ꢀ 1ꢁ log (Pf/ Pfs)
Signal-to- (Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal to (noise +
distortion) at the output of the A/D converter. The
signal is the rms value of the sine wave and noise is the
rms sum of all nonfundamentals signals up to half the
sampling frequency (fs/2), including harmonics but
excluding dc.
Pf is the power at frequency f in the ADC output; Pfs is
the power at frequency fs coupled onto the ADC VDD
supply.
Aperture Delay
This is the measured interval between the leading edge of the
sampling clock and the point at which the ADC actually takes
the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective point
in time at which the sample is taken.
REV. PrB
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PRELIMINARYTECHNICALDATA
Preliminary Technical Data
CIRCUIT INFORMATION
AD7273/AD7274
The AD7273/AD7274 are high speed, low power, 1ꢁ-/12-
Bit, single supply, analog-to-digital converters (ADC)
respectively. The parts can be operated from a +2.35V to
+3.6V supply. When operated from any supply voltage
within this range, the AD7273/AD7274 are capable of
throughput rates of 3 MSPS when provided with a 52
MHz clock.
When the ADC starts a conversion, see Figure 8, SW2
will open and SW1 will move to position B causing the
comparator to become unbalanced. The Control Logic
and the Charge Redistribution DAC are used to add and
subtract fixed amounts of charge from the sampling ca-
pacitor to bring the comparator back into a balanced con-
dition. When the comparator is rebalanced the conversion
is complete. The Control Logic generates the ADC out-
put code. Figure 9 shows the ADC transfer function.
The AD7273/AD7274 provide the user with an on-chip
track/hold, A/D converter, and a serial interface housed in
an 8-lead TSOT or an 8-lead MSOP package, which
offers the user considerable space saving advantages over
alternative solutions. The serial clock input accesses data
from the part but also provides the clock source for the
successive-approximation A/D converter. The analog
input range is ꢁ to VREF. An external reference is required
by the ADC and this reference can be in the range of 1.2V
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
A
V
IN
CONTROL
LOGIC
SW1
SW2
B
CONVERSION
PHASE
to VDD
.
COMPARATOR
The AD7273/AD7274 also feature a Power-Down option
to allow power saving between conversions. The power
down feature is implemented across the standard serial
interface as described in the Modes of Operation section.
V
/ 2
DD
AGND
Figure 8. ADC Conversion Phase
CONVERTER OPERATION
The AD7273/AD7274 is a successive-approximation ana-
log-to-digital converter based around a charge redistribu-
tion DAC. Figures 7 and 8 show simplified schematics of
the ADC. Figure 7 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in position A, the com-
ADC TRANSFER FUNCTION
The output coding of the AD7273/AD7274 is straight
binary. The designed code transitions occur midway
between succesive integer LSB values, i.e, ꢁ.5LSB,
1.5LSBs, etc. The LSB size is VREF/4ꢁ96 for the AD7274,
VREF/1ꢁ24 for the AD7273. The ideal transfer characteris-
tic for the AD7273/AD7274 is shown in Figure 9.
CHARGE
REDISTRIBUTI ON
DAC
SAMPLI NG
CAPACI TOR
111...111
111...110
A
V
I N
CONTROL
LOGIC
SW1
B
SW2
1LSB = V
1LSB = V
/4096 (AD7274)
/1024 (AD7273)
ACQUI SI TI ON
PHASE
REF
111...000
011...111
COMPARATOR
REF
AGND
V
/ 2
DD
000...010
000...001
000...000
Figure 7. ADC Acquisition Phase
0.5LSB
+V
-1.5LSB
DD
0V
ANALOG INPUT
Figure 9. AD7273/AD7274 Transfer Characteristic
REV. PrB
–11–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
PERFORMANCE CURVES
Dynamic Performance curves
DC Accuracy curves
TPC 1 and TPC 2 show typical FFT plots for the AD7274
and AD7273 respectively, at 3 MSPS sample rate and TBD
KHz input tone.
TPC 8and TPC 9 show typical INL and DNL performance
for the AD7276.
TPC 3 shows the Signal-to-(Noise+Distortion) Ratio
performance versus Input frequency for various supply
voltages while sampling at 3 MSPS with a SCLK frequency
of 52 MHz for the AD7274.
TP1ꢁ and TPC11 show Change in DNL and INL versus
Reference Voltage when using a supply voltage of 3V.
Power Requirements curves
TPC12 shows Maximum current versus Supply voltage for
the AD7274 with different SCLK frequencies.
TPC 4 shows the Signal to Noise Ratio (SNR) performance
versus Input frequency for various supply voltages while
sampling at 3 MSPS with a SCLK frequency of 52 MHz for
the AD7274.
See also Power versus Throughput Rate.
TPC 5 shows a graph of the Total Harmonic Distortion
(THD) versus Analog input signal frequency for various
supply voltages while sampling at 3 MSPS with a SCLK
frequency of 52 MHz for the AD7274.
TPC 6 shows a graph of the Total Harmonic Distortion
(THD) versus Analog input frequency for different source
impedances when using a supply voltage of TBD V, SCLK
frequency of 52 MHz and sampling at a rate of 3 MSPS for
the AD7274. See Analog Input section.
TPC 7 shows the Power Supply Rejection Ratio (PSRR)
versus Supply Ripple Frequency for the AD7274 when no
decoupling is used. See PSRR in the Terminology section.
TypicalPerformanceCharacteristics
TBD
TBD
0
0
0
0
TITLE
TITLE
TPC 2. AD7273 Dynamic performance at 3 MSPS
TPC 1. AD7274 Dynamic performance at 3 MSPS
REV. PrB
–12–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
TBD
TBD
0
0
0
0
TITLE
TITLE
TPC 6. THD vs. Analog Input Frequency
for various Source Impedance
TPC 3. AD7274 SINAD vs Analog Input Frequency
at 3 MSPS for various Supply Voltages
TBD
TBD
0
0
0
0
TITLE
TITLE
TPC 4. AD7274 SNR vs Analog Input Frequency
at 3 MSPS for various Supply Voltages
TPC 7. Power Supply Rejection Ratio (PSRR)
versus Supply Ripple Frequency
TBD
TBD
0
0
0
0
TITLE
TITLE
TPC 5. THD vs. Analog Input Frequency at 3 MSPS
for various Supply Voltages
TPC 8. AD7276 INL performance
REV. PrB
–13–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
TBD
TBD
0
0
0
0
TITLE
TITLE
TPC 9. AD7276 DNL performance
TPC 12. Maximum current vs Supply voltage for
different SCLK frequencies.
TBD
0
0
TITLE
TPC 10. Change in INL versus Reference Voltage
TBD
0
0
TITLE
TPC 11. Change in DNL versus Reference Voltage
REV. PrB
–14–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
TYPICAL CONNECTION DIAGRAM
AD7273/AD7274
Figure 1ꢁ shows a typical connection diagram for the
AD7273/AD7274. An external reference must be applied
to the ADC. This reference can be in the range of 1.2V to
VDD. A precision reference like the REF19X family or the
ADR421 can be used to supply the reference voltage to the
AD7273/AD7274.
The conversion result is output in a 16-bit word with two
leading zeros followed by the 12-bit or 1ꢁ-bit result. The
12-bit result from the AD7274 will be followed by two
trailing zeros and the 1ꢁ-bit result from the AD7273 will
be followed by four trailing zeros.
Voltage
Reference
AD7274 SNR Performance
TBD kHz Input
AD78ꢁ@2.5V
REF192
ADR421
TBD dB
TBD dB
TBD dB
TBD dB
ADR291
Table I. AD7274 performance for various Voltage
References IC
Table I provides some typical performance data with
various references under the same set-up conditions.
0.1µF
+3.6V
SUPPLY
10µF
TBD mA
0V toV
REF
INPUT
V
V
V
DD
IN
SCLK
SDATA
DSP/
µC/µP
+2.5V
AD7274/
AD7273
REF192
REF
GND
1µF
TANT
0.1µF
SERIAL
INTERFACE
Figure 10. AD7273/AD7274 Typical Connection Diagram
Analog Input
Figure 11 shows an equivalent circuit of the analog input
structure of the AD7273/AD7274. The two diodes D1 and
D2 provide ESD protection for the analog inputs. Care
must be taken to ensure that the analog input signal never
exceeds the supply rails by more than 3ꢁꢁmV. This will
cause these diodes to become forward biased and start
conducting current into the substrate. 1ꢁmA is the maxi-
mum current these diodes can conduct without causing
irreversable damage to the part. The capacitor C1 in
Figure 11 is typically about 4pF and can primarily be
attributed to pin capacitance. The resistor R1 is a lumped
component made up of the on resistance of a switch. This
resistor is typically about TBDΩ. The capacitor C2 is the
ADC sampling capacitor and has a capacitance of TBD
pF typically. For ac applications, removing high
V
DD
D1
D2
C2
TBD PF
R1
V
IN
C1
4pF
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
frequency components from the analog input signal is
recommended by use of a bandpass filter on the relevant
analog input pin. In applications where harmonic distor-
tion and signal to noise ratio are critical, the analog input
should be driven from a low impedance source. Large
source impedances will significantly affect the ac perfor-
mance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op-amp will be a
function of the particular application.
Figure 11. Equivalent Analog Input Circuit
REV. PrB
–15–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
Table II provides some typical performance data with
various op-amps used as the input buffer under the same
set-up conditions.
MODES OF OPERATION
The mode of operation of the AD7273/AD7274 is se-
lected by controlling the logic state of the CS signal
during a conversion. There are two possible modes of
operation, Normal Mode and Power-Down Mode. The
point at which CS is pulled high after the conversion has
been initiated will determine whether the AD7273/
AD7274 will enter Power-Down Mode or not. Similarly,
if already in Power-Down then CS can control whether
the device will return to Normal operation or remain in
Power-Down. These modes of operation are designed to
provide flexible power management options. These op-
tions can be chosen to optimize the power dissipation/
throughput rate ratio for different application
Op-amp in the
input buffer
AD7274 SNR Performance
TBD kHz Input
AD851ꢁ
AD861ꢁ
AD8ꢁ38
AD8519
TBD dB
TBD dB
TBD dB
TBD dB
requirements.
Table II. AD7274 performance for various Input Buffers
Normal Mode
This mode is intended for fastest throughput rate perfor-
mance as the user does not have to worry about any
power-up times with the AD7273/AD7274 remaining fully
powered all the time. Figure 12 shows the general dia-
gram of the operation of the AD7273/AD7274 in this
mode.
When no amplifier is used to drive the analog input, the
source impedance should be limited to low values. The
maximum source impedance will depend on the amount
of total harmonic distortion (THD) that can be
tolerated. The THD will increase as the source
impedance increases and performance will degrade. See
TPC6.
The conversion is iniated on the falling edge of CS as
described in the Serial Interface section. To ensure the
part remains fully powered up at all times CS must remain
low until at least 1ꢁ SCLK falling edges have elapsed after
the falling edge of CS. If CS is brought high any time
after the 1ꢁth SCLK falling, the part will remain powered
up but the conversion will be terminated and SDATA will
go back into three-state.
Digital Inputs
The digital inputs applied to the AD7273/AD7274 are not
limited by the maximum ratings which limit the analog
inputs. Instead, the digitals inputs applied can go to TBD
V and are not restricted by the VDD + ꢁ.3V limit as on the
analog inputs. For example, if the AD7273/AD7274 were
operated with a VDD of 3V then 5V logic levels could be
used on the digital inputs. However, it is important to
note that the data output on SDATA will still have 3V
logic levels when VDDꢀ 3V. Another advantage of SCLK
and CS not being restricted by the VDD + ꢁ.3V limit is
the fact that power supply sequencing issues are avoided.
If CS or SCLK are applied before VDD then there is no
risk of latch-up as there would be on the analog inputs if a
For the AD7274 a minimum of 14 serial clock cycles are
required to complete the conversion and access the
complete conversion result. For the AD7273 a minimum
of 12 serial clock cycles are required to complete the con-
version and access the complete conversion result.
CS may idle high until the next conversion or may idle
low until CS returns high sometime prior to the next
conversion (effectively idling CS low).
signal greater than ꢁ.3V was applied prior to VDD
.
Once a data transfer is complete (SDATA has returned to
three-state), another conversion can be initiated after the
quiet time, tQUIET, has elapsed by bringing CS low again.
AD7273/74
SCLK
12
10
14
1
16
SDATA
VALID DATA
Figure 12. Normal Mode Operation
REV. PrB
–16–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
Power-Down Mode
In order to exit this mode of operation and power the
AD7273/AD7274 up again, a dummy conversion is per-
formed. On the falling edge of CS the device will begin to
power up, and will continue to power up as long as CS is
held low until after the falling edge of the 1ꢁth SCLK.
The device will be fully powered up once 16 SCLKs have
elapsed and valid data will result from the next conversion
as shown in Figure 14. If CS is brought high before the
1ꢁth falling edge of SCLK, then the AD7273/AD7274
will go back into Power- Down again. This avoids acci-
dental power up due to glitches on the CS line or an inad-
vertent burst of 8 SCLK cycles while CS is low. So,
although the device may begin to power up on the falling
edge of CS, it will power down again on the rising edge
of CS as long as it occurs before the 1ꢁth SCLK falling
edge.
This mode is intended for use in applications where
slower throughput rates are required; either the ADC is
powered down between each conversion, or a series of
conversions may be performed at a high throughput rate
and then the ADC is powered down for a relatively long
duration between these bursts of several conversions.
When the AD7273/AD7274 is in Power-Down, all analog
circuitry is powered down.
To enter Power-Down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the 1ꢁth falling edge of
SCLK as shown in Figure 13. Once CS has been brought
high in this window of SCLKs, then the part will enter
Power-Down and the conversion that was intiated by the
falling edge of CS will be terminated and SDATA will go
back into three-state. If CS is brought high before the
second SCLK falling edge, then the part will remain in
Normal Mode and will not power-down. This will avoid
accidental power-down due to glitches on the CS line.
SCLK
2
16
1
10
THREE-STATE
SDATA
INVALID DATA
Figure 13. Entering Power Down Mode
THE PART IS FULLY
POWERED UPWITH V
THE PART BEGINS
TO POWER UP
IN
FULLY ACQUIRED
A
16
16
SCLK
10
1
1
SDATA
INVALID DATA
VALID DATA
Figure 14. Exiting Power Down Mode
REV. PrB
–17–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
Power-up Time
This means, assuming one has the facility to monitor the
ADC supply current, if the ADC powers up in the desired
mode of operation and thus a dummy cycle is not required
to change mode, then neither is a dummy cycle required
to place the track and hold into track.
The power-up time of the AD7273/AD7274 is TBD ns,
which means that with any frequency of SCLK up to 52
MHz, one dummy cycle will always be sufficient to allow
the device to power up. Once the dummy cycle is com-
plete, the ADC will be fully powered up and the input
signal will be acquired properly. The quite time tQUIET
must still be allowed from the point where the bus goes
back into three-state after the dummy conversion, to the
next falling edge of CS. When running at 3 MSPS
throughput rate, the AD7273/AD7274 will power up and
acquire a signal within ꢁ.5 LSB in one dummy cycle,
i.e. TBD ns.
POWER VERSUS THROUGHPUT RATE
By using the Power-Down mode on the AD7273/AD7274
when not converting, the average power consumption of
the ADC decreases at lower throughput rates. Figure 15
shows how as the throughput rate is reduced, the device
remains in its Power-Down state longer and the average
power consumption over time drops accordingly.
When powering up from the Power-Down mode with a
dummy cycle, as in Figure 14, the track and hold which
was in hold mode while the part was powered down,
returns to track mode after the first SCLK edge the part
receives after the falling edge of CS. This is shown as
point A in Figure 14. Although at any SCLK frequency
one dummy cycle is sufficient to power the device up and
acquire VIN, it does not necessarily mean that a full
dummy cycle of 16 SCLKs must always elapse to power
up the device and acquire VIN fully; TBD ns will be suffi-
cient to power the device up and acquire the input signal.
If, for example, a 25 MHz SCLK frequency was applied
to the ADC, the cycle time would be 64ꢁ ns. In one
dummy cycle, 64ꢁ ns, the part would be powered up and
VIN acquired fully. However after TBD ns with a 25 MHz
SCLK only TBD SCLK cycles would have elapsed. At
this stage, the ADC would be fully powered up and the
signal acquired. So, in this case the CS can be brought
high after the 1ꢁth SCLK falling edge and brought low
again after a time tQUIET to initiate the conversion.
For example, if the AD7273/AD7274 is operated in a
continuous sampling mode with a throughput rate of
5ꢁꢁKSPS and a SCLK of 52MHz (VDDꢀ 3V), and the
device is placed in the Power-Down mode between
conversions, then the power consumption is calculated as
follows. The power dissipation during normal operation is
13.5 mW (VDDꢀ 3V). If the power up time is one dummy
cycle, i.e. 333ns, and the remaining conversion time is
another cycle, i.e. 333ns, then the AD7273/AD7274 can
be said to dissipate 13.5mW for 666ns during each conver-
sion cycle.If the throughput rate is 5ꢁꢁKSPS, the cycle
time is 2µs and the average power dissipated during each
cycle is (666/2ꢁꢁꢁ) x (13.5 mW)ꢀ 4.5mW.
Figure 15 shows the Power vs. Throughput Rate when
using the Power-Down mode between conversions at 3V.
The Power-Down mode is intended for use with
throughput rates of approximately TBD MSPS and under
as at higher sampling rates there is no power saving made
by using the Power-Down mode.
When power supplies are first applied to the AD7273/
AD7274, the ADC may either power up in the Power-
Down mode or in Normal mode. Because of this, it is best
to allow a dummy cycle to elapse to ensure the part is fully
powered up before attempting a valid conversion. Like-
wise, if it is intended to keep the part in the Power-Down
mode while not in use and the user wishes the part to
power up in Power-Down mode, then the dummy cycle
may be used to ensure the device is in Power-Down by
executing a cycle such as that shown in Figure 13. Once
supplies are applied to the AD7273/AD7274, the power
up time is the same as that when powering up from the
Power-Down mode. It takes approximately TBD ns to
power up fully if the part powers up in Normal mode. It is
not necessary to wait TBD ns before executing a dummy
cycle to ensure the desired mode of operation. Instead, the
dummy cycle can occur directly after power is supplied to
the ADC. If the first valid conversion is then performed
directly after the dummy conversion, care must be taken to
ensure that adequate acquisition time has been allowed. As
mentioned earlier, when powering up from the Power-
Down mode, the part will return to track upon the first
SCLK edge applied after the falling edge of CS.
TBD
0
0
TITLE
Figure 15. Power vs Throughput
However, when the ADC powers up initially after supplies
are applied, the track and hold will already be in track.
REV. PrB
–18–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
SERIAL INTERFACE
return to three-state on the 16th SCLK falling edge, as
shown in Figure 17.
Figures 16 and 17 show the detailed timing diagram for
serial interfacing to the AD7274 and AD7273 respec-
tively. The serial clock provides the conversion clock and
also controls the transfer of information from the
AD7273/AD7274 during conversion.
If the user considers a 14 SCLKs cycle serial interface for
the AD7273/AD7274, CS needs to be brought high after
the 14th SCLK falling edge, the last two trailing zeros
will be ignored and SDATA will go back into three-state.
In this case, a 45 MHz serial clock would allow to achieve
3MSPS throughput rate.
The CS signal initiates the data transfer and conversion
process. The falling edge of CS puts the track and hold
into hold mode, takes the bus out of three-state and the
analog input is sampled at this point. The conversion is
also initiated at this point.
CS going low clocks out the first leading zero to be read
in by the microcontroller or DSP. The remaining data is
then clocked out by subsequent SCLK falling edges
beginning with the 2nd leading zero. Thus, the first fall-
ing clock edge on the serial clock has the first leading
zero provided and also clocks out the second leading zero.
The final bit in the data transfer is valid on the 16th fall-
ing edge, having being clocked out on the previous (15th)
falling edge.
For the AD7274 the conversion will require 14 SCLK
cycles to complete. Once 13 SCLK falling edges have
elapsed the track and hold will go back into track on the
next SCLK rising edge as shown in Figure 16 at point B.
If the rising edge of CS occurs before 14 SCLKs have
elapsed then the conversion will be terminated and the
SDATA line will go back into three-state. If 16 SCLKs
are considered in the cycle, the last two bits will be zeros
and SDATA will return to three-state on the 16th SCLK
falling edge as shown in Figure 16.
In applications with a slower SCLK, it is possible to read
in data on each SCLK rising edge. In that case, the first
falling edge of SCLK will clock out the second leading
zero and it could be read in the first rising edge. However,
the first leading zero that was clocked out when CS went
low will be missed unless it was not read in the first falling
edge. The 15th falling edge of SCLK will clock out the
last bit and it could be read in the 15th rising SCLK edge.
For the AD7273 the conversion will require 12 SCLK
cycles to complete. Once 11 SCLK falling edges have
elapsed, the track and hold will go back into track on the
next SCLK rising edge, as shown in Figure 17 at point B.
If the rising edge of CS occurs before 12 SCLKs have
elapsed then the conversion will be terminated and the
SDATA line will go back into three-state. If 16 SCLKs
are considered in the cycle, the AD7273 will clock out
four trailing zeros for the last four bits and SDATA will
If CS goes low just after one the SCLK falling edge has
elapsed, CS will clock out the first leading zero as before
and it may be read in the SCLK rising edge. The next
SCLK falling edge will clock out the second leading zero
and it could be read in the following rising edge.
t1
tconvert
t2
t6
B
SCLK
1
2
3
4
5
13
15
14
t5
16
t7
t8
tquiet
t3
t4
DB9
DB1
Z
ZERO
DB11
DB10
DB0
ZERO
ZERO
SDATA
THREE-
STATE
THREE-STATE
2 TRAILING
ZERO’S
2 LEADING
ZERO’S
1/ THROUGHPUT
Figure 16. AD7274 Serial Interface Timing Diagram
t1
tconvert
t2
t6
B
SCLK
3
1
2
4
10
11
12
13
15
16
14
t7
t8
t5
tquiet
t3
t4
DB8
DB9
DB1
Z
ZERO
DB0
ZERO
ZERO
ZERO
ZERO
SDATA
THREE-
STATE
THREE-STATE
4TRAILING ZERO’S
2 LE ADI NG
ZERO’S
1/ THROUGHPUT
Figure 17. AD7273 Serial Interface Timing Diagram
REV. PrB
–19–
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
OUTLINE DIMENSIONS
Dimensions shown in millimiters
8-Lead Thin Small Outline Transistor Package [TSOT]
(UJ- 8)
2.90 BSC
8
1
7
6
3
5
4
2.80 BSC
1.60 BSC
PIN 1
2
0.65 BSC
1.95
BSC
0.90
0.87
0.84
0.20
0.08
1.00 MAX
0.55
0.45
0.35
8°
4°
0°
0.38
0.22
0.10 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-193BA
8-Lead Mini Small Outline Package [MSOP]
(RM - 8)
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
1
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.60
0.40
8°
0°
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
REV. PrE
–20–
相关型号：
AD7276BRM-REEL
IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MO-187AA, MSOP-8, Analog to Digital Converter
ADI
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