AD1877 [ADI]
Single-Supply 16-Bit Stereo ADC; 单电源， 16位立体声ADC
| 型号： | AD1877 |
| 厂家： | 
ADI |
| 描述： | Single-Supply 16-Bit Stereo ADC |
| 文件： | 总18页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Supply
a
16-Bit ⌺⌬ Stereo ADC
AD1877*
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single 5 V Power Supply
Single-Ended Dual-Channel Analog Inputs
92 dB (Typ) Dynamic Range
90 dB (Typ) S/(THD+N)
0.006 dB Decimator Passband Ripple
Fourth-Order, 64-Times Oversampling ⌺⌬ Modulator
Three-Stage, Linear-Phase Decimator
256
؋
FS or 384 ؋
FS Input Clock Less than 100 W (Typ) Power-Down Mode
Input Overrange Indication
CLOCK
CLKIN
28
LRCK
WCLK
BCLK
1
2
DIVIDER
SERIAL OUTPUT
INTERFACE
TAG
27
26
25
24
23
3
SOUT
THREE-STAGE FIR
DECIMATION
FILTER
THREE-STAGE FIR
DECIMATION
FILTER
DV
2
4
DV
1
DD
DD
DGND1
RDEDGE
S/M
5
DGND2
6
RESET
On-Chip Voltage Reference
Flexible Serial Output Interface
28-Lead SOIC Package
D
A
C
D
A
C
D
A
C
D
A
C
7
22 MSBDLY
21 RLJUST
8
384/256
APPLICATIONS
AV
DD
20
9
AGND
Consumer Digital Audio Receivers
Digital Audio Recorders, Including Portables
CD-R, DCC, MD and DAT
Multimedia and Consumer Electronic Equipment
Sampling Music Synthesizers
Digital Karaoke Systems
V
R
V
L
10
19
18
17
16
15
IN
IN
CAPR1
CAPR2
AGNDR
CAPL1 11
CAPL2
AGNDL
12
13
14
SINGLE TO
SINGLE TO
DIFFERENTIAL INPUT DIFFERENTIAL INPUT
CONVERTER
CONVERTER
VOLTAGE
REFERENCE
V
R
V
L
REF
REF
AD1877
PRODUCT OVERVIEW
The AD1877 is a stereo, 16-bit oversampling ADC based on
Sigma Delta (∑∆) technology intended primarily for digital
audio bandwidth applications requiring a single 5 V power supply.
Each single-ended channel consists of a fourth-order one-bit
noise shaping modulator and a digital decimation filter. An on-
chip voltage reference, stable over temperature and time, defines
the full-scale range for both channels. Digital output data from
both channels are time-multiplexed to a single, flexible serial
interface. The AD1877 accepts a 256 × FS or a 384 × FS input
clock (FS is the sampling frequency) and operates in both serial
port “master” and “slave” modes. In slave mode, all clocks must
be externally derived from a common source.
one-bit comparator’s quantization noise out of the audio pass-
band. The high order of the modulator randomizes the modulator
output, reducing idle tones in the AD1877 to very low levels.
Because its modulator is single-bit, AD1877 is inherently
monotonic and has no mechanism for producing differential
linearity errors.
The input section of the AD1877 uses autocalibration to correct
any dc offset voltage present in the circuit, provided that the inputs
are ac coupled. The single-ended dc input voltage can swing
between 0.7 V and 3.8 V typically. The AD1877 antialias input
circuit requires four external 470 pF NPO ceramic chip filter
capacitors, two for each channel. No active electronics are
needed. Decoupling capacitors for the supply and reference pins
are also required.
Input signals are sampled at 64 × FS onto internally buffered
switched-capacitors, eliminating external sample-and-hold ampli-
fiers and minimizing the requirements for antialias filtering at the
input. With simplified antialiasing, linear phase can be preserved
across the passband. The on-chip single-ended to differential signal
converters save the board designer from having to provide them
externally. The AD1877’s internal differential architecture provides
increased dynamic range and excellent power supply rejection
characteristics. The AD1877’s proprietary fourth-order differen-
tial switched-capacitor ∑∆ modulator architecture shapes the
The dual digital decimation filters are triple-stage, finite impulse
response filters for effectively removing the modulator’s high
frequency quantization noise and reducing the 64 × FS single-bit
output data rate to an FS word rate. They provide linear phase
and a narrow transition band that properly digitizes 20 kHz signals
at a 44.1 kHz sampling frequency. Passband ripple is less than
0.006 dB, and stopband attenuation exceeds 90 dB.
*Protected by U.S. Patent Numbers 5055843, 5126653, and others pending.
(Continued on Page 6)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD1877–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
5.0
25
12.288
991.768
–0.5
V
°C
MHz
Ambient Temperature
Input Clock (FCLKIN) [256 × FS]
Input Signal
Hz
dB Full Scale
Measurement Bandwidth
23.2 Hz to 19.998 kHz
Load Capacitance on Digital Outputs 50
pF
V
V
Input Voltage HI (VIH)
Input Voltage LO (VIL)
2.4
0.8
Master Mode, Data I2S-Justified (Refer to Figure 14).
Device Under Test (DUT) bypassed and decoupled as shown in Figure 3.
DUT is antialiased and ac coupled as shown in Figure 2. DUT is calibrated.
Values in bold typeface are tested, all others are guaranteed but not tested.
ANALOG PERFORMANCE
Min
Typ
Max
Unit
Resolution
16
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
Without A-Weight Filter
With A-Weight Filter
Signal to (THD + Noise)
Signal to THD
87
90
86.5
92
92
94
90
94
dB
dB
dB
dB
Analog Inputs
Single-Ended Input Range ( Full Scale)*
Input Impedance at Each Input Pin
VREF
VREF – 1.55
VREF
32
2.25
VREF + 1.55
2.55
V
kΩ
V
2.05
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Midscale Offset Error (After Calibration)
Midscale Drift
0.5
0.01
115
3
15
–99
؎2.5
%
dB
ppm/°C
LSBs
ppm/°C
dB
؎20
Crosstalk (EIAJ Method)
–90
*VIN p-p = VREF × 1.333.
–2–
REV. A
AD1877
DIGITAL I/O
Min
2.4
Typ
Max
Unit
Input Voltage HI (VIH)
Input Voltage LO (VIL)
Input Leakage (IIH @ VIH = 5 V)
Input Leakage (IIL @ VIL = 0 V)
Output Voltage HI (VOH @ IOH = –2 mA)
Output Voltage LO (VOL @ IOL = 2 mA)
Input Capacitance
V
V
µA
µA
V
V
pF
0.8
10
10
2.4
0.4
15
DIGITAL TIMING (Guaranteed over 0°C to 70°C, DVDD = AVDD = 5 V 5%. Refer to Figures 17–19.)
Min
Typ
Max
Unit
tCLKIN
FCLKIN
tCPWL
tCPWH
tRPWL
tBPWL
tBPWH
CLKIN Period
48
1.28
15
15
50
15
15
81
12.288
780
20.48
ns
MHz
ns
ns
ns
ns
ns
CLKIN Frequency (1/tCLKIN
CLKIN LO Pulsewidth
CLKIN HI Pulsewidth
RESET LO Pulsewidth
BCLK LO Pulsewidth
BCLK HI Pulsewidth
)
tDLYCKB
tDLYBLR
tDLYBWR
tDLYBWF
tDLYDT
tSETLRBS
tDLYLRDT
CLKIN Rise to BCLK Xmit (Master Mode)
BCLK Xmit to LRCK Transition (Master Mode)
BCLK Xmit to WCLK Rise
15
15
10
10
10
ns
ns
ns
ns
ns
ns
BCLK Xmit to WCLK Fall
BCLK Xmit to Data/Tag Valid (Master Mode)
LRCK Setup to BCLK Sample (Slave Mode)
LRCK Transition to Data/TAG Valid (Slave Mode)
No MSB Delay Mode (for MSB Only)
WCLK Setup to BCLK Sample (Slave Mode)
Data Position Controlled by WCLK Input Mode
BCLK Xmit to DATA/TAG Valid (Slave Mode)
All Bits Except MSB in No MSB Delay Mode
All Bits in MSB Delay Mode
10
10
40
ns
ns
tSETWBS
tDLYBDT
10
ns
POWER
Min
Typ
Max
Unit
Supplies
Voltage, Analog and Digital
Analog Current
Analog Current—Power Down (CLKIN Running)
Digital Current
Digital Current—Power Down (CLKIN Running)
Dissipation
4.75
5
35
6
16
13
5.25
43
26
20
39
V
mA
µA
mA
µA
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
Power Down—Both Supplies (CLKIN Running)
Power Down—Both Supplies (CLKIN Not Running)
Power Supply Rejection (See TPC 5)
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
Stopband (≥0.55 × FS)—any 300 mV p-p Signal
255
175
80
95
5
315
215
100
325
mW
mW
mW
µW
µW
76
71
80
dB
dB
dB
REV. A
–3–
AD1877
TEMPERATURE RANGE
Min
Typ
Max
Unit
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
°C
°C
0
–60
70
+100
DIGITAL FILTER CHARACTERISTICS
Min
Typ
Max
Unit
Decimation Factor
64
Passband Ripple
0.006
21.6
20
dB
dB
Stopband1 Attenuation
90
48 kHz FS (at Recommended Crystal Frequencies)
Passband
Stopband
44.1 kHz FS (at Recommended Crystal Frequencies)
Passband
Stopband
0
26.4
kHz
kHz
0
kHz
kHz
24.25
32 kHz FS (at Recommended Crystal Frequencies)
Passband
Stopband
Other FS
Passband
Stopband
Group Delay
Group Delay Variation
0
17.6
14.4
0.45
kHz
kHz
0
0.55
FS
FS
s
36/FS
0
µs
NOTES
1Stopband repeats itself at multiples of 64 × FS, where FS is the output word rate. Thus the digital filter will attenuate to 0 dB across the frequency spectrum except
for a range 0.55 × FS wide at multiples of 64 × FS.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Min
Typ
Max
Unit
DVDD1 to DGND1 and DVDD2 to DGND2
AVDD to AGND/AGNDL/AGNDR
Digital Inputs
Analog Inputs
AGND to DGND
0
0
6
6
V
V
V
V
V
DGND – 0.3
AGND – 0.3
–0.3
DVDD + 0.3
AVDD + 0.3
+0.3
Reference Voltage
Soldering (10 sec)
Indefinite Short Circuit to Ground
300
°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1877 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Package
Description
Package
Option
Model
Temperature
AD1877JR
0°C to 70°C
SOIC
R-28
–4–
REV. A
AD1877
PIN FUNCTION DESCRIPTIONS
Pin
Signal to Total Harmonic Distortion (S/THD)
The ratio of the rms value of the fundamental input signal to the
rms sum of all harmonically related spectral components in the
passband, expressed in decibels.
Input/
Pin
Output Name
Description
1
2
3
4
5
6
7
8
I/O
I/O
I/O
I
I
I
I
I
I
I
O
O
I
O
O
I
O
O
I
I
I
I
I
LRCK
WCLK
BCLK
DVDD1
DGND1
Left/Right Clock
Word Clock
Bit Clock
5 V Digital Supply
Digital Ground
Passband
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Passband Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the passband,
expressed in decibels.
RDEDGE Read Edge Polarity Select
S/M
384/256
AVDD
VINL
CAPL1
CAPL2
AGNDL
Slave/Master Select
Clock Mode
5 V Analog Supply
Left Channel Input
Left External Filter Capacitor 1
Left External Filter Capacitor 2
Left Analog Ground
Left Reference Voltage Output
Right Reference Voltage Output
Right Analog Ground
Stopband
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by “stopband
attenuation.”
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Gain Error
With a near full-scale input, the ratio of actual output to
expected output, expressed as a percentage.
V
V
REFL
REFR
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
AGNDR
CAPR2
CAPR1
VINR
AGND
RLJUST
Right External Filter Capacitor 2
Gain Drift
ght External Filter
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Ri
Capacitor 1
Right Channel Input
Analog Ground
Right/Left Justify
Midscale Offset Error
Output response to a midscale dc input, expressed in least-
significant bits (LSBs).
MSBDLY Delay MSB One BCLK Period
Midscale Drift
RESET
DGND2
DVDD2
SOUT
TAG
Reset
Change in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) per °C.
I
I
O
O
I
Digital Ground
5 V Digital Supply
Serial Data Output
Serial Overrange Output
Master Clock
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
CLKIN
Power Supply Rejection
DEFINITIONS
Dynamic Range
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
The ratio of a full-scale output signal to the integrated output
noise in the passband (20 Hz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[THD+N]) 60 dB. Note that spurious har-
monics are below the noise with a –60 dB input, so the noise
level establishes the dynamic range. The dynamic range is speci-
fied with and without an A-Weight filter applied.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds
(ms). More precisely, the derivative of radian phase with respect
to radian frequency at a given frequency.
Group Delay Variation
Signal to (Total Harmonic Distortion + Noise)
(S/(THD + N))
The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all other spectral components
in the passband, expressed in decibels (dB).
The difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the passband, expressed in microseconds (µs).
–5–
REV. A
AD1877
(
Continued from Page 1 )
offset and indirect dependence on temperature and time as it
affects dc offset. The AD1877 suppresses idle tones 20 dB or
better below the integrated noise floor.
The flexible serial output port produces data in twos-comple-
ment, MSB-first format. The input and output signals are TTL
compatible. The port is configured by pin selections. Each 16-bit
output word of a stereo pair can be formatted within a 32-bit
field of a 64-bit frame as either right-justified, I2S-compatible,
Word Clock controlled or left-justified positions. Both 16-bit
samples can also be packed into a 32-bit frame, in left-justified
and I2S-compatible positions.
The AD1877’s modulator was designed, simulated, and exhaus-
tively tested to remain stable for any input within a wide tolerance
of its rated input range. The AD1877 is designed to internally
reset itself should it ever be overdriven, to prevent it from going
instable. It will reset itself within 5 µs at a 48 kHz sampling
frequency after being overdriven. Overdriving the inputs will
produce a waveform “clipped” to plus or minus full scale.
The AD1877 is fabricated on a single monolithic integrated circuit
using a 0.8 µm CMOS double polysilicon, double metal process,
and is offered in a plastic 28-lead SOIC package. Analog and
digital supply connections are separated to isolate the analog cir-
cuitry from the digital supply and reduce digital crosstalk.
See TPCs 1 through 16 for illustrations of the AD1877’s
typical analog performance as measured by an Audio Precision
System One. Signal-to(distortion + noise) is shown under a
range of conditions. Note that there is a small variance between
the AD1877 analog performance specifications and some of the
performance plots. This is because the Audio Precision System
One measures THD and noise over a 20 Hz to 24 kHz band-
width, while the analog performance is specified over a 20 Hz to
20 kHz bandwidth (i.e., the AD1877 performs slightly better
than the plots indicate). The power supply rejection (TPC 5)
graph illustrates the benefits of the AD1877’s internal differen-
tial architecture. The excellent channel separation shown in
TPC 6 is the result of careful chip design and layout.
The AD1877 operates from a single 5 V power supply over the
temperature range of 0°C to 70°C, and typically consumes less
than 260 mW of power.
THEORY OF OPERATION
⌺⌬ Modulator Noise-Shaping
The stereo, internally differential analog modulator of the
AD1877 employs a proprietary feedforward and feedback archi-
tecture that passes input signals in the audio band with a unity
transfer function yet simultaneously shapes the quantization
noise generated by the one-bit comparator out of the audio
band. See Figure 1. Without the ∑∆ architecture, this quantiza-
tion noise would be spread uniformly from dc to one-half the
oversampling frequency, 64 × FS.
Digital Filter Characteristics
The digital decimator accepts the modulator’s stereo bitstream
and simultaneously performs two operations on it. First, the
decimator low-pass filters the quantization noise that the modu-
lator shaped to high frequencies and filters any other out-of
audio-band input signals. Second, it reduces the data rate to an
output word rate equal to FS. The high frequency bitstream is
decimated to stereo 16-bit words at 48 kHz (or other desired
FS). The out-of-band one-bit quantization noise and other high
frequency components of the bitstream are attenuated by at
least 90 dB.
؉V
IN
DAC
MODULATOR
BITSTREAM
OUTPUT
V
IN
SINGLE TO
DIFFERENTIAL
CONVERTER
The AD1877 decimator implements a symmetric Finite Impulse
Response (FIR) filter which possesses a linear phase response.
This filter achieves a narrow transition band (0.1 × FS), high
stopband attenuation (> 90 dB), and low passband ripple
(< 0.006 dB). The narrow transition band allows the unattenu-
ated digitization of 20 kHz input signals with FS as low as
44.1 kHz. The stopband attenuation is sufficient to eliminate
modulator quantization noise from affecting the output. Low
passband ripple prevents the digital filter from coloring the
audio signal. See TPC 7 for the digital filter’s characteristics.
The output from the decimator is available as a single serial
output, multiplexed between left and right channels.
DAC
؊V
IN
Figure 1. Modulator Noise-Shaper (One Channel)
∑∆ architectures “shape” the quantization noise-transfer function
in a nonuniform manner. Through careful design, this transfer
function can be specified to high-pass filter the quantization
noise out of the audio band into higher frequency regions. The
AD1877 also incorporates a feedback resonator from the fourth
integrator’s output to the third integrator’s input. This resonator
does not affect the signal transfer function but allows the flexible
placement of a zero in the noise transfer function for more effec-
tive noise shaping.
Note that the digital filter itself is operating at 64 × FS. As a
consequence, Nyquist images of the passband, transition band,
and stopband will be repeated in the frequency spectrum at
multiples of 64 × FS. Thus the digital filter will attenuate to
greater than 90 dB across the frequency spectrum except for a
window 0.55 × FS wide centered at multiples of 64 × FS. Any
input signals, clock noise, or digital noise in these frequency
windows will not be attenuated to the full 90 dB. If the high
frequency signals or noise appear within the passband images
within these windows, they will not be attenuated at all, and
therefore input antialias filtering should be applied.
Oversampling by 64 simplifies the implementation of a high per-
formance audio analog-to-digital conversion system. Antialias
requirements are minimal; a single pole of filtering will usually
suffice to eliminate inputs near FS and its higher multiples.
A fourth-order architecture was chosen both to strongly shape
the noise out of the audio band and to help break up the idle
tones produced in all ∑∆ architectures. These architectures have
a tendency to generate periodic patterns with a constant dc input, a
response that looks like a tone in the frequency domain. These
idle tones have a direct frequency dependence on the input dc
–6–
REV. A
AD1877
Sample Delay
For the AD1877, the input clock operates at either 256 × FS or
384 × FS as selected by the 384/256 pin. When 384/256 is HI,
the 384 mode is selected and when 384/256 is LO, the 256
mode is selected. In both cases, the clock is divided down to
obtain the 64 × FS clock required for the modulator. The out-
put word rate itself will be at FS. This relationship is illustrated
for popular sample rates below:
The sample delay or “group delay” of the AD1877 is dominated
by the processing time of the digital decimation filter. FIR fil-
ters convolve a vector representing time samples of the input
with an equal-sized vector of coefficients. After each convolu-
tion, the input vector is updated by adding a new sample at one
end of the “pipeline” and discarding the oldest input sample at
the other. For an FIR filter, the time at which a step input appears
at the output will be when that step input is half way through
the input sample vector pipeline. The input sample vector
is updated every 64 × FS. The equation which expresses the
group delay for the AD1877 is:
256 Mode
CLKIN
384 Mode
CLKIN
Modulator
Sample Rate Rate
Output Word
12.288 MHz
11.2896 MHz 16.9344 MHz 2.822 MHz
8.192 MHz 12.288 MHz 2.048 MHz
18.432 MHz 3.072 MHz
48 kHz
44.1 kHz
32 kHz
Group Delay (sec) = 36/FS (Hz)
For the most common sample rates this can be summarized as:
The AD1877 serial interface will support both master and slave
modes. Note that in slave mode it is required that the serial
interface clocks are externally derived from a common source.
In master mode, the serial interface clock outputs are internally
derived from CLKIN.
FS
Group Delay
48 kHz
44.1 kHz
32 kHz
750 µs
816 µs
1125 µs
Reset, Autocalibration and Power Down
The active LO RESET pin (Pin 23) initializes the digital deci-
mation filter and clears the output data buffer. While in the reset
state, all digital pins defined as outputs of the AD1877 are
driven to ground (except for BCLK, which is driven to the state
defined by RDEDGE (Pin 6)). Analog Devices recommends
resetting the AD1877 on initial power up so that the device is
properly calibrated. The reset signal must remain LO for the
minimum period specified in “Specifications” above. The reset
pulse is asynchronous with respect to the master clock, CLKIN.
If, however, multiple AD1877s are used in a system, and it is
desired that they leave the reset state at the same time, the
common reset pulse should be made synchronous to CLKIN
(i.e., RESET should be brought HI on a CLKIN falling edge).
Due to the linear phase properties of FIR filters, the group
delay variation, or differences in group delay at different fre-
quencies is essentially zero.
OPERATING FEATURES
Voltage Reference and External Filter Capacitors
The AD1877 includes a +2.25 V on-board reference that deter-
mines the AD1877’s input range. The left and right reference
pins (14 and 15) should be bypassed with a 0.1 µF ceramic chip
capacitor in parallel with a 4.7 µF tantalum as shown below in
Figure 3. Note that the chip capacitor should be closest to the
pin. The internal reference can be overpowered by applying an
external reference voltage at the VREFL (Pin 14) and VREF
R
(Pin 15) pins, allowing multiple AD1877s to be calibrated to
the same gain. It is not possible to overpower the left and right
reference pins individually; the external reference voltage
should be applied to both Pin 14 and Pin 15. Note that the ref-
erence pins must still be bypassed as shown in Figure 3.
Multiple AD1877s can be synchronized to each other by using
a single master clock and a single reset signal to initialize all
devices. On coming out of reset, all AD1877s will begin sam-
pling at the same time. Note that in slave mode, the AD1877 is
inactive (and all outputs are static, including WCLK) until the
first rising edge of LRCK after the first falling edge of LRCK.
This initial low going then high going edge of LRCK can be used
to “skew” the sampling start-up time of one AD1877 relative to
other AD1877s in a system. In the Data Position Controlled by
WCLK Input mode, WCLK must be HI with LRCK HI, then
WCLK HI with LRCK LO, then WCLK HI with LRCK HI
before the AD1877 starts sampling.
It is possible to bypass each reference pin (VREFL and VREFR)
with a capacitor larger than the suggested 4.7 µF, however it is
not recommended. A larger capacitor will have a longer charge-
up time which may extend into the autocalibration period, yield-
ing incorrect results.
The AD1877 requires four external filter capacitors on Pins 11,
12, 17 and 18. These capacitors are used to filter the single-to
differential converter outputs, and are too large for practical
integration onto the die. They should be 470 pF NPO ceramic
chip type capacitors as shown in Figure 3, placed as close to the
AD1877 package as possible.
The AD1877 achieves its specified performance without the
need for user trims or adjustments. This is accomplished
through the use of on-chip automatic offset calibration that
takes place immediately following reset. This procedure nulls
out any offsets in the single-to-differential converter, the analog
modulator and the decimation filter. Autocalibration completes
in approximately 8192 × (1/(FLRCK) seconds, and need only be
performed once at power-up in most applications. [In slave
mode, the 8192 cycles required for autocalibration do not start
until after the first rising edge of LRCK following the first fall-
ing edge of LRCK.] The autocalibration scheme assumes that
the inputs are ac coupled. DC coupled inputs will work with the
AD1877, but the autocalibration algorithm will yield an incor-
rect offset compensation.
Sample Clock
An external master clock supplied to CLKIN (Pin 28) drives
the AD1877 modulator, decimator, and digital interface. As
with any analog-to-digital conversion system, the sampling clock
must be low jitter to prevent conversion errors. If a crystal oscil-
lator is used as the clock source, it should be bypassed with a
0.1 µF capacitor, as shown below in Figure 3.
–7–
REV. A
AD1877
The AD1877 also features a power-down mode. It is enabled by
the active LO RESET Pin 23 (i.e., the AD1877 is in powerdown
mode while RESET is held LO). The power savings are speci-
fied in the ‘’Specifications’’ section above. The converter is shut
down in the power-down state and will not perform conversions.
The AD1877 will be reset upon leaving the power-down state, and
autocalibration will commence after the RESET pin goes HI.
Analog Input Voltage Swing
The single-ended input range of the analog inputs is specified in
relative terms in the “Specifications” section of this data sheet.
The input level at which clipping occurs linearly tracks the voltage
reference level, i.e., if the reference is high relative to the typical
2.25 V, the allowable input range without clipping is corre-
spondingly wider; if the reference is low relative to the typical
2.25 V, the allowable input range is correspondingly narrower.
Power consumption can be further reduced by slowing down the
master clock input (at the expense of input passband width).
Note that a minimum clock frequency, FCLKIN, is specified for
the AD1877.
Thus the maximum input voltage swing can be computed using
the following ratio:
2.25 V (nominal reference voltage)
X Volts (measured reference voltage)
Tag Overrange Output
=
3.1V p−p nominal voltage swing
Y Volts (maximum swing without clipping)
)
(
The AD1877 includes a TAG serial output (Pin 27) which is
provided to indicate status on the level of the input voltage. The
TAG output is at TTL compatible logic levels. A pair of unsigned
binary bits are output, synchronous with LRCK (MSB then
LSB), that indicate whether the current signal being converted
is: more than 1 dB under full scale; within 1 dB under full scale;
within 1 dB over full scale; or more than 1 dB over full scale.
The timing for the TAG output is shown in TPCs 7 through 16.
Note that the TAG bits are not “sticky,” i.e., they are not peak
reading, but rather change with every sample. Decoding of these
two bits is as follows:
Layout and Decoupling Considerations
Obtaining the best possible performance from the AD1877
requires close attention to board layout. Adhering to the follow-
ing principles will produce typical values of 92 dB dynamic
range and 90 dB S/(THD+N) in target systems. Schematics and
layout artwork of the AD1877 Evaluation Board, which implement
these recommendations, are available from Analog Devices.
The principles and their rationales are listed below. The first
two pertain to bypassing and are illustrated in Figure 3.
4.7F
4.7F
TAG Bits
MSB, LSB
Meaning
0.1F
0.1F
5V
DIGITAL
470pF
NPO
470pF
NPO
470pF
NPO
0
0
1
1
0
1
0
1
More Than 1 dB Under Full Scale
Within 1 dB Under Full Scale
Within 1 dB Over Full Scale
13
15
16
AGNDR
14
18
17
0.1F
AGNDL
V
L
V
R
CAPR2 CAPR1
REF
REF
More Than 1 dB Over Full Scale
470pF
NPO
12 CAPL2
AD1877
CLKIN
OSCILLATOR
28
CAPL1
11
APPLICATIONS ISSUES
Recommended Input Structure
DGND2 DV
24
2
AGND AV
DD
DV 1 DGND1
DD
DD
20
4
9
5
25
The AD1877 input structure is single-ended to allow the board
designer to achieve a high level of functional integration. The
very simple recommended input circuit is shown in Figure 2.
Note the 1 µF ac coupling capacitor which allows input level
shifting for 5 V only operation, and for autocalibration to
properly null offsets. The 3 dB point of the single-pole antialias
RC filter is 240 kHz, which results in essentially no attenuation
at 20 kHz. Attenuation at 3 MHz is approximately 22 dB, which
is adequate to suppress FS noise modulation. If the analog inputs
are externally ac coupled, then the 1 µF ac coupling capacitors
shown in Figure 2 are not required.
10nF
10nF
0.1F
1F
1F
1F
5V
5V
5V
DIGITAL
ANALOG DIGITAL
Figure 3. Recommended Bypassing and Oscillator Circuits
There are two pairs of digital supply pins on opposite sides of
the part (Pins 4 and 5 and Pins 24 and 25). The user should
tie a bypass chip capacitor (10 nF ceramic) in parallel with a
decoupling capacitor (1 µF tantalum) on EACH pair of supply
pins as close to the pins as possible. The traces between these
package pins and the capacitors should be as short and as wide
as possible. This will prevent digital supply current transients
from being inductively transmitted to the inputs of the part.
300⍀
1F
RIGHT
INPUT
19
10
V
R
IN
2.2nF
NPO
AD1877
Use a 0.1 µF chip analog capacitor in parallel with a 1.0 µF
tantalum capacitor from the analog supply (Pin 9) to the analog
ground plane. The trace between this package pin and the
capacitor should be as short and as wide as possible.
300⍀
1F
LEFT
INPUT
V
L
IN
2.2nF
NPO
The AD1877 should be placed on a split ground plane. The
digital ground plane should be placed under the top end of the
package, and the analog ground plane should be placed under
the bottom end of the package as shown in Figure 4. The split
should be between Pins 8 and 9 and between Pins 20 and 21.
Figure 2. Recommended Input Structure for Externally
DC Coupled Inputs
–8–
REV. A
AD1877
drawn from the digital supply pins and help keep the IC sub-
strate quiet.
The ground planes should be tied together at one spot under-
neath the center of the package with an approximately 3 mm
trace. This ground plane technique also minimizes RF transmis-
sion and reception.
How to Extend SNR
A cost-effective method of improving the dynamic range and
SNR of an analog-to-digital conversion system is to use multiple
AD1877 channels in parallel with a common analog input. This
technique makes use of the fact that the noise in independent
modulator channels is uncorrelated. Thus every doubling of the
number of AD1877 channels used will improve system dynamic
range by 3 dB. The digital outputs from the corresponding deci-
mator channels have to be arithmetically averaged to obtain the
improved results in the correct data format. A microprocessor,
either general-purpose or DSP, can easily perform the averaging
operation.
CLKIN
27 TAG
LRCK
WCLK
BCLK
1
2
28
26
25
24
23
22
21
20
19
3
SOUT
DV
DD
2
4
DV
DD
1
DIGITAL GROUND PLANE
DGND1
RDEDGE
S/M
5
DGND2
RESET
MSBDLY
RLJUST
AGND
6
Shown below in Figure 5 is a circuit for obtaining a 3 dB
improvement in dynamic range by using both channels of a
single AD1877 with a mono input. A stereo implementation
would require using two AD1877s and using the recommended
input structure shown in Figure 2. Note that a single microproces-
sor would likely be able to handle the averaging requirements
for both left and right channels.
7
8
384/256
AV
DD
9
V
R
V
L
10
IN
IN
CAPR1
CAPR2
AGNDR
CAPL1 11
18
17
16
15
ANALOG GROUND PLANE
CAPL2
AGNDL
12
13
14
V
R
AD1877
RECOMMENDED
INPUT BUFFER
SINGLE
CHANNEL
OUTPUT
SINGLE
CHANNEL
INPUT
IN
DIGITAL
AVERAGER
AD1877
V
R
V
L
REF
REF
V
L
IN
Figure 5. Increasing Dynamic Range By Using Two
AD1877 Channels
Figure 4. Recommended Ground Plane
Each reference pin (14 and 15) should be bypassed with a 0.1 µF
ceramic chip capacitor in parallel with a 4.7 µF tantalum capaci-
tor. The 0.1 µF chip cap should be placed as close to the pack-
age pin as possible, and the trace to it from the reference pin
should be as short and as wide as possible. Keep this trace away
from any analog traces (Pins 10, 11, 12, 17, 18, 19)! Coupling
between input and reference traces will cause even order har-
monic distortion. If the reference is needed somewhere else on
the printed circuit board, it should be shielded from any signal
dependent traces to prevent distortion.
DIGITAL INTERFACE
Modes of Operation
The AD1877’s flexible serial output port produces data in
two’s-complement, MSB-first format. The input and output sig-
nals are TTL logic level compatible. Time multiplexed serial
data is output on SOUT (Pin 26), left channel then right chan-
nel, as determined by the left/right clock signal LRCK (Pin 1).
Note that there is no method for forcing the right channel to
precede the left channel. The port is configured by pin selec-
tions. The AD1877 can operate in either master or slave mode,
with the data in right-justified, I2S-compatible, Word Clock
controlled or left-justified positions.
Wherever possible, minimize the capacitive load on the digital
outputs of the part. This will reduce the digital spike currents
The various mode options are pin-programmed with the Slave/
Master Pin (7), the Right/Left Justify Pin (21), and the MSB
Delay Pin (22). The function of these pins is summarized as
follows:
–9–
REV. A
AD1877
S/M RLJUST MSBDLY WCLK
BCLK
LRCK
Serial Port Operation Mode
1
1
1
Output
Input
Input
Slave Mode. WCLK frames the data. The MSB is output on the
17th BCLK cycle. Provides right-justified data in slave mode
with a 64 × FS BCLK frequency. See Figure 7.
1
1
0
Input
Input
Input
Slave Mode. The MSB is output in the BCLK cycle after
WCLK is detected HI. WCLK is sampled on the BCLK active
edge, with the MSB valid on the next BCLK active edge. Tying
WCLK HI results in I2S-justified data. See Figure 8.
1
1
0
0
1
0
Output
Output
Input
Input
Input
Input
Slave Mode. Data left-justified with WCLK framing the data.
WCLK rises immediately after an LRCK transition. The MSB is
valid on the first BCLK active edge. See Figure 9.
Slave Mode. Data I2S-justified with WCLK framing the data.
WCLK rises in the second BCLK cycle after an LRCK transi-
tion. The MSB is valid on the second BCLK active edge. See
Figure 10.
0
0
1
1
1
0
Output
Output
Output Output
Output Output
Master Mode. Data right-justified. WCLK frames the data,
going HI in the 17th BCLK cycle. BCLK frequency = 64 × FS.
See Figure 11.
Master Mode. Data right-justified + 1. WCLK is pulsed in the
17th BCLK cycle, staying HI for only 1 BCLK cycle. BCLK
frequency = 64 × FS. See Figure 12.
0
0
0
0
1
0
Output
Output
Output Output
Output Output
Master Mode. Data left-justified. WCLK frames the data.
BCLK frequency = 64 × FS. See Figure 13.
Master Mode. Data I2S-justified. WCLK frames the data.
BCLK frequency = 64 × FS. See Figure 14.
Serial Port Data Timing Sequences
In the slave modes, the relationship between LRCK and BCLK
is not fixed, to the extent that there can be an arbitrary number
of BCLK cycles between the end of the data transmission and
the next LRCK transition. The slave mode timing diagrams are
therefore simplified as they show precise 32-bit fields and 64-bit
frames.
The RDEDGE input (Pin 6) selects the bit clock (BCLK) polarity.
RDEDGE HI causes data to be transmitted on the BCLK falling
edge and valid on the BCLK rising edge; RDEDGE LO causes
data to be transmitted on the BCLK rising edge and valid on
the BCLK falling edge. This is shown in the serial data output
timing diagrams. The term “sampling” is used generically to
denote the BCLK edge (rising or falling) on which the serial
data is valid. The term “transmitting” is used to denote the
other BCLK edge. The S/M input (Pin 7) selects slave mode (S/
M HI) or master mode (S/M LO). Note that in slave mode,
BCLK may be continuous or gated (i.e., a stream of pulses dur-
ing the data phase followed by periods of inactivity between
channels).
In two slave modes, it is possible to pack two 16-bit samples in
a single 32-bit frame, as shown in Figures 15 and 16. BCLK,
LRCK, DATA and TAG operate at one half the frequency
(twice the period) as in the 64-bit frame modes. This 32-bit
frame mode is enabled by pulsing the LRCK HI for a minimum
of one BCLK period to a maximum of sixteen BCLK periods.
The LRCK HI for one BCLK period case is shown in Figures
15 and 16. With a one or two BCLK period HI pulse on
LRCK, note that both the left and right TAG bits are output
immediately, back-to-back. With a three to sixteen BCLK period
HI pulse on LRCK, the left TAG bits are followed by one to
fourteen “dead” cycles (i.e., zeros) followed by the right TAG
bits. Also note that WCLK stays HI continuously when the
AD1877 is in the 32-bit frame mode. Figure 15 illustrates the
left-justified case, while Figure 16 illustrates the I2S-justified case.
In the master modes, the bit clock (BCLK), the left/right clock
(LRCK), and the word clock (WCLK) are always outputs, gen-
erated internally in the AD1877 from the master clock (CLKIN)
input. In master mode, a LRCK cycle defines a 64-bit “frame.”
LRCK is HI for a 32-bit “field” and LRCK is LO for a 32-bit
“field.”
In the slave modes, the bit clock (BCLK), and the left/right clock
(LRCK) are user-supplied inputs. The word clock (WCLK) is an
internally generated output except when S/M is HI, RLJUST is
HI, and MSBDLY is LO, when it is a user-supplied input which
controls the data position. Note that the AD1877 does not sup-
port asynchronous operation in slave mode; the clocks (CLKIN,
LRCK, BCLK and WCLK) must be externally derived from a
common source. In general, CLKIN should be divided down
externally to create LRCK, BCLK and WCLK.
In all modes, the left and right channel data is updated with the
next sample within the last 1/8 of the current conversion cycle (i.e.,
within the last 4 BCLK cycles in 32-bit frame mode, and within
the last 8 BCLK cycles in 64-bit frame mode). The user must
constrain the output timing such that the MSB of the right channel
is read before the final 1/8 of the current conversion period.
–10–
REV. A
AD1877
For both master and slave modes, BCLK must have a minimum
Two modes deserve special discussion. The first special mode,
“Slave Mode, Data Position Controlled by WCLK Input” (S/M
= HI, RLJUST = HI, MSBDLY = LO), shown in Figure 8, is
the only mode in which WCLK is an input. The 16-bit output
data words can be placed at user-defined locations within 32-bit
fields. The MSB will appear in the BCLK period after WCLK is
detected HI by the BCLK sampling edge. If WCLK is HI dur-
ing the first BCLK of the 32-bit field (if WCLK is tied HI for
example), then the MSB of the output word will be valid on the
sampling edge of the second BCLK. The effect is to delay the
MSB for one bit clock cycle into the field, making the output
data compatible at the data format level with the I2S data for-
mat. Note that the relative placement of the WCLK input can
vary from 32-bit field to 32-bit field, even within the same
64-bit frame. For example, within a single 64-bit frame, the left
word could be right justified (by pulsing WCLK HI on the 16th
BCLK) and the right word could be in an I2S-compatible data
format (by having WCLK HI at the beginning of the second field).
LO pulsewidth of tBPWL, and a minimum HI pulsewidth of tBPWH
.
The AD1877 CLKIN and RESET timing is shown in Figure
19. CLKIN must have a minimum LO pulsewidth of tCPWL, and
a minimum HI pulse width of tCPWH. The minimum period of
CLKIN is given by tCLKIN. RESET must have a minimum LO
pulsewidth of tRPWL. Note that there are no setup or hold time
requirements for RESET.
Synchronizing Multiple AD1877s
Multiple AD1877s can be synchronized by making all the
AD1877s serial port slaves. This option is illustrated in
Figure 6. See the “Reset, Autocalibration and Power Down”
section above for additional information.
CLOCK
SOURCE
In the second special mode “Master Mode, Right-Justified with
MSB Delay, WCLK Pulsed in 17th Cycle” (S/M = LO,
RLJUST = HI, MSBDLY = LO), shown in Figure 12, WCLK
is an output and is pulsed for one cycle by the AD1877. The
MSB is valid on the 18th BCLK sampling edge, and the LSB
extends into the first BCLK period of the next 32-bit field.
#1 AD1877
DATA
BCLK
WCLK
LRCK
SLAVE MODE
RESET
CLKIN
#2 AD1877
DATA
BCLK
WCLK
LRCK
Timing Parameters
SLAVE MODE
For master modes, a BCLK transmitting edge (labeled “XMIT”)
will be delayed from a CLKIN rising edge by tDLYCKB, as shown
in Figure 17. A LRCK transition will be delayed from a BCLK
transmitting edge by tDLYBLR. A WCLK rising edge will be
delayed from a BCLK transmitting edge by tDLYBWR, and a WCLK
falling edge will be delayed from a BCLK transmitting edge by
tDLYBWF. The DATA and TAG outputs will be delayed from a
RESET
CLKIN
#N AD1877
DATA
BCLK
WCLK
LRCK
SLAVE MODE
RESET
CLKIN
transmitting edge of BCLK by tDLYDT
.
For slave modes, an LRCK transition must be setup to a BCLK
sampling edge (labeled “SAMPLE”) by tSETLRBS. The DATA
and TAG outputs will be delayed from an LRCK transition by
tDLYLRDT, and DATA and TAG outputs will be delayed from
BCLK transmitting edge by tDLYBDT. For “Slave Mode, Data
Position Controlled by WCLK Input,” WCLK must be setup to
Figure 6. Synchronizing Multiple AD1877s
a BCLK sampling edge by tSETWBS
.
–11–
REV. A
AD1877–Typical Performance Characteristic Curves
0
؊80
؊82
؊84
؊86
؊88
؊90
؊92
؊94
؊96
؊98
؊100
؊20
؊40
؊60
؊80
؊100
؊120
؊140
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10 12 14 16 18 20 22
FREQUENCY – kHz
24
AMPLITUDE – dBFS
TPC 1. 1 kHz Tone at –0.5 dBFS (16k-Point FFT)
TPC 4. THD+N versus Amplitude at 1 kHz
0
–20
؊60
؊65
؊70
؊75
؊80
؊85
؊90
؊95
؊100
–40
–60
–80
–100
–120
–140
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10 12 14 16 18 20 22
24
AMPLITUDE – kHz
FREQUENCY – kHz
TPC 2. 1 kHz Tone at –10 dBFS (16k-Point FFT)
TPC 5. Power Supply Rejection to 300 mV p-p on AVDD
؊80
؊82
؊84
؊86
؊88
؊90
؊92
؊94
؊96
؊98
؊100
؊80
؊85
؊90
؊95
؊100
؊105
؊110
؊115
؊120
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY – kHz
FREQUENCY – kHz
TPC 3. THD+N versus Frequency at –0.5 dBFS
TPC 6. Channel Separation versus Frequency at –0.5 dBFS
–12–
REV. A
AD1877
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED F
S
TPC 7. Digital Filter Signal Transfer Function to FS
LRCK
INPUT
BCLK
RDEDGE = LO
31
32
1
2
15
16
17
18
19
32
1
2
15
16
17
18
19
32
1
2
INPUT
BCLK
RDEDGE = HI
PREVIOUS DATA
MSB-14 LSB
LEFT DATA
MSB
RIGHT DATA
MSB
SOUT
OUTPUT
ZEROS
ZEROS
ZEROS
LSB
LSB
MSB-1 MSB-2
MSB-1 MSB-2
WCLK
OUTPUT
LEFT TAG
MSB LSB
RIGHT TAG
MSB LSB
LEFT TAG
MSB LSB
TAG
OUTPUT
Figure 7. Serial Data Output Timing: Slave Mode, Right-Justified with No MSB Delay,
S/M = Hl, RLJUST = Hl, MSBDLY = Hl
LRCK
INPUT
BCLK
RDEDGE= LO
1
2
3
4
17
1
2
3
4
17
INPUT
BCLK
RDEDGE = HI
RIGHT DATA
MSB
LEFT DATA
MSB
SOUT
OUTPUT
ZEROS
ZEROS
ZEROS
LSB
LSB
MSB-1 MSB-2
MSB-1 MSB-2
WCLK
INPUT
LEFT TAG
MSB
RIGHT TAG
MSB
TAG
OUTPUT
LSB
LSB
Figure 8. Serial Data Output Timing: Slave Mode, Data Position Controlled by WCLK Input,
S/M = Hl, RLJUST= Hl, MSBDLY = LO
–13–
REV. A
AD1877
LRCK
INPUT
BCLK
RDEDGE = LO
INPUT
31
32
1
2
3
4
16
17
18
31
32
1
2
3
4
16
17
18
BCLK
RDEDGE = HI
LEFT DATA
RIGHT DATA
SOUT
OUTPUT
ZEROS
ZEROS
MSB
LSB
MSB
LSB
ZEROS
MSB-1 MSB-2
MSB-1 MSB-2
WCLK
OUTPUT
LEFT TAG
MSB LSB
RIGHT TAG
LSB
TAG
OUTPUT
MSB
Figure 9. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay, S/M = Hl,
RLJUST = LO, MSBDLY = Hl
LRCK
INPUT
BCLK
RDEDGE = LO
32
1
2
3
4
5
17
31
32
1
2
3
4
5
17
INPUT
BCLK
RDEDGE = HI
LEFT DATA
RIGHT DATA
SOUT
OUTPUT
ZEROS
ZEROS
ZEROS
MSB
LSB
MSB
LSB
MSB-1 MSB-2
MSB-1 MSB-2
WCLK
OUTPUT
LEFT TAG
MSB LSB
RIGHT TAG
MSB
TAG
OUTPUT
LSB
Figure 10. Serial Data Output Timing: Slave Mode, I2S-Justified, S/M = Hl, RLJUST = LO, MSBDLY = LO
LRCK
OUTPUT
BCLK
RDEDGE = LO
31
32
1
2
15
16
17
18
19
32
1
2
15
16
17
18
19
32
1
2
OUTPUT
BCLK
RDEDGE = HI
PREVIOUS DATA
MSB-14 LSB
LEFT DATA
RIGHT DATA
MSB
SOUT
OUTPUT
ZEROS
ZEROS
ZEROS
MSB
LSB
LSB
MSB-1 MSB-2
MSB-1 MSB-2
WCLK
OUTPUT
LEFT TAG
MSB LSB
RIGHT TAG
MSB LSB
LEFT TAG
MSB LSB
TAG
OUTPUT
Figure 11. Serial Data Output Timing: Master Mode, Right-Justified with No MSB Delay, S/M = LO,
RLJUST = Hl, MSBDLY = Hl
–14–
REV. A
AD1877
LRCK
OUTPUT
BCLK
RDEDGE = LO
OUTPUT
32
1
2
16
17
18
19
20
1
2
16
17
18
19
20
1
2
BCLK
RDEDGE = HI
PREVIOUS DATA
MSB-14 LSB
LEFT DATA
RIGHT DATA
SOUT
OUTPUT
ZEROS
ZEROS
ZEROS
MSB
LSB
MSB
LSB
MSB-1 MSB-2
MSB-1 MSB-2
WCLK
OUTPUT
LEFT TAG
MSB LSB
RIGHT TAG
MSB LSB
TAG
OUTPUT
Figure 12. Serial Data Output Timing. Master Mode, Right-Justified with MSB Delay,
WCLK Pulsed in 17th BCLK Cycle, S/M = LO, RLJUST = Hl, MSBDLY = LO
LRCK
OUTPUT
BCLK
RDEDGE = LO
OUTPUT
31
32
1
2
3
16
17
18
31
32
1
2
3
16
17
18
BCLK
RDEDGE = HI
LEFT DATA
RIGHT DATA
SOUT
OUTPUT
ZEROS
ZEROS
ZEROS
MSB
LSB
MSB
LSB
MSB-1 MSB-2
MSB-1 MSB-2
WCLK
OUTPUT
LEFT TAG
MSB LSB
RIGHT TAG
LSB
TAG
OUTPUT
MSB
Figure 13. Serial Data Output Timing: Master Mode, Left-Justified with No MSB Delay,
S/M = LO, RLJUST = LO, MSBDLY = Hl
LRCK
OUTPUT
BCLK
RDEDGE = LO
32
1
2
3
4
17
31
32
1
2
3
4
17
OUTPUT
BCLK
RDEDGE = HI
LEFT DATA
RIGHT DATA
SOUT
OUTPUT
ZEROS
ZEROS
ZEROS
MSB
LSB
MSB
LSB
MSB-1 MSB-2
MSB-1 MSB-2
WCLK
OUTPUT
LEFT TAG
MSB LSB
RIGHT TAG
MSB
TAG
OUTPUT
LSB
Figure 14. Serial Data Output Timing: Master Mode, I2S-Justified, S/M = LO, RLJUST = LO,
MSBDLY = LO
–15–
REV. A
AD1877
LRCK
INPUT
BCLK
RDEDGE = LO
31
32
1
2
3
4
5
16
17
18
19
20
21
32
1
2
INPUT
BCLK
RDEDGE = HI
PREVIOUS DATA
LSB
MSB-14
LEFT DATA
MSB-1 MSB-2 MSB-3 MSB-4
RIGHT DATA
LEFT DATA
MSB
SOUT
OUTPUT
MSB
LSB
MSB
LSB
MSB-1 MSB-2 MSB-3 MSB-4
MSB-1
WCLK
OUTPUT
HI
HI
LEFT TAG
LSB
RIGHT TAG
MSB LSB
LEFT TAG
TAG
OUTPUT
MSB
MSB
LSB
Figure 15. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay,
32-Bit Frame Mode, S/M = Hl, RLJUST = LO, MSBDLY = Hl
LRCK
INPUT
BCLK
RDEDGE = LO
32
1
2
3
4
5
6
17
18
19
20
21
22
1
2
3
INPUT
BCLK
RDEDGE = HI
PREVIOUS DATA
LSB
MSB-14
LEFT DATA
MSB-1 MSB-2 MSB-3 MSB-4
RIGHT DATA
LEFT DATA
MSB
SOUT
OUTPUT
MSB
LSB
MSB
LSB
MSB-1 MSB-2 MSB-3 MSB-4
MSB-1
WCLK
OUTPUT
HI
HI
LEFT TAG
MSB
RIGHT TAG
MSB LSB
LEFT TAG
MSB
RIGHT TAG
LSB MSB
TAG
OUTPUT
LSB
Figure 16. Serial Data Output Timing: Slave Mode, I2S-Justified, 32-Bit Frame Mode,
S/M = Hl, RLJUST= LO, MSBDLY = LO
CLKIN
INPUT
tDLYCKB
BCLK OUTPUT (64 x F
)
tBPWL
S
RDEDGE = LO
BCLK OUTPUT (64 x F
XMIT
XMIT
XMIT
XMIT
tBPWH
)
S
RDEDGE = HI
tBPWH
tBPWL
LRCK
OUTPUT
tDLYBWR
tDLYBWF
tDLYBLR
WCLK
OUTPUT
tDLYDT
DATA & TAG
OUTPUTS
Figure 17. Master Mode Clock Timing
–16–
REV. A
AD1877
tBPWL
tBPWH
BCLK INPUT
RDEDGE = LO
XMIT
SAMPLE
XMIT
SAMPLE
BCLK OUTPUT
RDEDGE = HI
tBPWH
tSETLRBS
tBPWL
LRCK
INPUT
tSETWBS
WCLK
INPUT
tDLYBDT
tDLYLRDT
DATA & TAG
OUTPUTS
MSB
MSB-1
Figure 18. Slave Mode Clock Timing
tCLKIN
tCPWH
CLKIN INPUT
RESET INPUT
tCPWL
tRPWL
Figure 19. CLKIN and RESET Timing
–17–
REV. A
AD1877
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
R-28 (S-Suffix)
28-Lead Wide-Body SO
SOL-28
28
15
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
PIN 1
0.3937 (10.00)
14
1
0.1043 (2.65)
0.7125 (18.10)
0.0926 (2.35)
0.0291 (0.74)
0.6969 (17.70)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8
؇
؇
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0
0.0500 (1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
–18–
REV. A
相关型号：
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