AD1879* [ADI]
High Performance 16-/18-Bit ## Stereo ADCs ; 高性能16位/ 18位##立体声模数转换器\n
| 型号： | AD1879* |
| 厂家： | 
ADI |
| 描述： | High Performance 16-/18-Bit ## Stereo ADCs
|
| 文件： | 总16页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance
16-/18-Bit ⌺⌬ Stereo ADCs
a
AD1878/AD1879*
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Fully Differential Dual Channel Analog Inputs
103 dB Signal-to-Noise (AD1879 typ)
–98 dB THD+N (AD1879 typ)
0.001 dB Passband Ripple and 115 dB Stopband
Attenuation
Fifth-Order, 64 Tim es Oversam pling ⌺⌬ Modulator
Single Stage, Linear Phase Decim ator
256
؋
FS Input Clock LRCK
BCK
S0
WCK
1
2
3
4
5
6
7
8
9
28
SERIAL OUTPUT
INTERFACE
27 DATA
DIGITAL
CHIP
26
CLOCK
S1
25
24
64/32
SINGLE-STAGE,
SINGLE-STAGE,
4k-TAP
FIR DECIMATION
FILTER
4k-TAP
FIR DECIMATION
FILTER
DV
DD
RESET
APPLICATIONS
DGND
NC
23 DGND
Digital Tape Recorders
Professional, DCC, and DAT
A/ V Digital Am plifiers
CD-R
ANALOG
CHIP
22 DV
DD
D
A
C
D
A
C
D
D
A
C
A
C
21
20
AV
1
AV
AV
1
2
SS
SS
Sound Reinforcem ent
AV
2
SS
DD
DD
19 AV
1
AGND 10
APD 11
P RO D UCT O VERVIEW
AGND
VINL–
VINL+
REFL
18
17
16
15
T he AD1879 is a two-channel, 18-bit oversampling ADC based
on ∑∆ technology and intended primarily for digital audio appli-
cations. T he AD1878 is identical to the 18-bit AD1879 except
that it outputs 16-bit data words. Statements in this data sheet
should be read as applying to both parts unless otherwise noted.
VINR–
VINR+
REFR
12
13
14
VOLTAGE
REFERENCE
Each input channel of these ADCs is fully differential. Each
data conversion channel consists of a fifth order one-bit noise
shaping modulator and a digital decimation filter. An on-chip
voltage reference provides a voltage source to both channels sta-
ble over temperature and time. Digital output data from both
channels is time-multiplexed to a single, flexible serial interface.
T he AD1878/AD1879 accepts a 256 × FS input master clock.
phase and a narrow transition band that permits the digitization
of 20 kHz signals while preventing aliasing into the passband
even when using a 44.1 kHz sampling frequency. Passband
ripple is less the 0.001 dB, and stopband attenuation exceeds
115 dB.
Input signals are sampled at 64 × FS on switched-capacitors,
eliminating external sample-and-hold amplifiers and minimizing
the requirements for antialias filtering at the input. With simpli-
fied antialiasing, linear phase can be preserved across the passband.
The AD1878/AD1879’s proprietary fifth-order differential
switched-capacitor modulator architecture shapes the one-bit
comparator’s quantization noise out of the audio passband. T he
high order of the modulator randomizes the modulator output,
reducing idle tones in the AD1878/AD1879 to very low levels.
T he AD1878/AD1879’s differential architecture provides in-
creased dynamic range and excellent common-mode rejection
characteristics. Because its modulator is single-bit, AD1878/
AD1879 is inherently monotonic and has no mechanism for
producing differential linearity errors.
T he flexible serial output port produces data in twos-complement,
MSB-first format. Input and output signals are to T T L and
CMOS-compatible logic levels. T he port is configured by pin
selections. T he AD1878/AD1879 can operate in either master
or slave mode. Each 16-/18-bit output word of a stereo pair can
be formatted within a 32-bit field as either right-justified, I2S-
compatible, or at user-selected positions. T he output can also be
truncated to 16-bits by formatting into a 16-bit field.
T he AD1878/AD1879 consists of two integrated circuits in a
single ceramic 28-pin DIP package. T he modulators and refer-
ence are fabricated in a BiCMOS process; the decimator and
output port, in a 1.0 µm CMOS process. Separating these func-
tions reduces digital crosstalk to the analog circuitry. Analog and
digital supply connections are separated to further isolate the
analog circuitry from the digital supplies.
T he digital decimation filters are single-stage, 4095-tap finite
impulse response filters for filtering the modulator’s high fre-
quency quantization noise and reducing the 64 × FS single-bit
output data rate to a FS word rate. T hey provide linear
T he AD1878/AD1879 operates from ±5 V power supplies over
the temperature range of –25°C to +70°C.
*P rotected by U.S. P atent Num bers 5055843, 5126653, and others pending.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD1878/AD1879–SPECIFICATIONS
TEST CO ND ITIO NS UNLESS O TH ERWISE NO TED
Supply Voltages
±5
V
Ambient T emperature
25
°C
Input Clock (FCLOCK
Input Signal
)
12.288
974
–0.5
MHz
Hz
dB Full Scale
All minimums and maximums tested except as noted.
ANALO G P ERFO RMANCE
Min
Typ
Max
Units
AD1879 Resolution
AD1878 Resolution
18
16
Bits
Bits
Clock Input Frequency Range
CLOCK Input (FCLOCK
Modulator Sample Rate (FCLOCK/4)
Output Word Rate (FS = FCLOCK/256)
)
0.01
0.0025
0.039
12.288
3.072
48
14.286
3.5715
55.8
MHz
MHz
kHz
AD1879 Dynamic Range (0 kHz to 20 kHz, –60 dB input)
Stereo Mode (No A-Weight Filter)
100
103
106
105
dB
dB
dB
Mono Mode1 (No A-Weight Filter)
Stereo Mode (with A-Weight Filter)
AD1879 T rimmed2 Signal to (Noise + Distortion)
Full Scale
–20 dB
93
91
98
83
dB
dB
AD1879 Untrimmed3 Signal to (Noise + Distortion)
Full Scale
–20 dB
96
83
dB
dB
AD1879 T rimmed2 Signal to T otal Harmonic Distortion
Full Scale
–20 dB
98
100
dB
dB
AD1878 Dynamic Range (0 kHz to 20 kHz, –60 dB 1.0936 kHz
Input Dithered with a –10 dB 21.873 kHz Sine Wave)
Stereo Mode (No A-Weight Filter)
AD1878 T rimmed2 Signal to (Noise + Distortion)
Full Scale
95
93
97
dB
95
77
dB
dB
–20 dB
AD1878 Untrimmed3 Signal to (Noise + Distortion)
Full Scale
91
94
77
dB
dB
–20 dB
AD1878 T rimmed2 Signal to T otal Harmonic Distortion
Full Scale
98
100
dB
dB
–20 dB
Analog Inputs
Differential Input Range4
Input Impedance at Each Input Pin
DC Accuracy
±5.985
±6.3
7.0
±6.615
V
kΩ
Gain Error
±1
±5
%
Interchannel Gain Mismatch
Gain Drift
AD1879 Midscale Offset Error
AD1878 Midscale Offset Error
Midscale Drift
Voltage Reference
Crosstalk (EIAJ Method)
Interchannel Phase Deviation
0.05
150
±200
±50
13
2.86
105
±0.001
0.15
dB
ppm/°C
18-Bit LSBs
16-Bit LSBs
ppm/°C
V
±750
±200
2.4
100
3.2
dB
Degrees
NOT ES
1Both channels connected together for mono operations as described below in “How to Extend SNR.”
2Differential gain imbalance manually trimmed to eliminate second harmonic. See “Applications Issues” below.
3T est performed without part-to-part trimming.
4T he differential input range is twice the range seen at each input pin. T he input range corresponds to the full-scale digital output range.
Specifications subject to change without notice.
REV. 0
–2–
AD1878/AD1879
D IGITAL INP UTS
Min
Max
Units
VIH
V
VIL
0.8
10
10
V
IIH @ VIH = 5 V
IIL @ VIL = 0 V
VOH @ IOH = 360 µA
VOL @ IOL = 1.6 mA
µA
µA
V
4.0
0.5
V
D IGITAL TIMING
Min
Typ
Max
Units
CLOCK
Period (TCLOCK = 1/FCLOCK
LO Pulse Width
HI Pulse Width
)
0.07
35
35
100
µs
ns
ns
BCK Pulse Width
2
CLOCK Periods
64-Bit Frame LRCK Pulse Width
32-Bit Frame LRCK Pulse Width
WCK Pulse Width
32
16
BCK Periods
BCK Periods
BCK Periods
1
tRSET
tRHLD
tRSLS
RESET Setup to CLOCK Rising
RESET Hold from CLOCK Rising
RESET Pulse Width
5
20
4
ns
ns
10 µs
CLOCK Periods
tWSET
tWHLD
tDLYCK
WCK to CLOCK Rising
5
20
ns
ns
ns
WCK Hold from CLOCK Rising
CLOCK to BCK/WCK/LRCK Delay
(Master Mode)
65
tSET
BCK/LRCK to CLOCK Falling
(Slave Mode)
BCK/LRCK Hold from CLOCK Falling
(Slave Mode)
5
ns
ns
tHLD
20
tDLYD, MSB
tDLYD
CLOCK Falling to MSB DAT A Delay
CLOCK Rising to DAT A Delay, Except MSB
65
70
ns
ns
P O WER
Min
Typ
Max
Units
Supplies
Voltage, DVDD/AVDD1/AVDD
Voltage, AVSS1/AVSS
Current, AVDD1/AVSS
Current, AVDD1/AVSS1—Power Down
2
4.75
–5.25
5
5.25
–4.75
92
23
10
V
V
mA
mA
mA
mA
2
–5
73
13
8
1
Current, AVDD2/AVSS
Current, DVDD
Dissipation
2
64
70
Operation
Operation—Analog Supplies
Operation—Digital Supplies
1,130
810
320
1,370
1,020
350
mW
mW
mW
mW
Power Down (All Supplies)
530
680
Power Supply Rejection
1 kHz 300 mV p-p Signal at Analog Supply Pins
Passband—Any 300 mV p-p Signal
Stopband—Any 300 mV p-p Signal
102
92
105
dBFS
dBFS
dBFS
TEMP ERATURE RANGE
Min
Typ
Max
Units
Specifications Guaranteed
Functionality Guaranteed
Storage
+25
°C
°C
°C
–25
–60
+70
+100
–3–
REV. 0
AD1878/AD1879
ABSO LUTE MAXIMUM RATINGS
Min
Typ
Max
Units
DVDD to DGND and AVDD1/AVDD2 to AGND
AVSS1/AVSS2 to AGND
0
–6
–0.3
–0.3
AVSS1 – 0.3
–0.3
6
0
V
V
V
V
V
V
AVSS2 to AVSS
1
Digital Inputs to DGND
Analog Inputs
AGND to DGND
Reference Voltage
Soldering
DVDD + 0.3
AVDD1 + 0.3
0.3
Indefinite Short Circuit to Ground
+300
10
°C
sec
D IGITAL FILTER CH ARACTERISTICS
Min
Typ
Max
Units
Decimation Factor
Passband Ripple
Stopband1 Attenuation
48 kHz FS (12.288 MHz CLOCK)
Passband
64
0.001
dB
dB
115
0
26.2
21.7
3,045
kHz
kHz
Stopband
44.1 kHz FS (11.2896 MHz CLOCK)
Passband
Stopband
0
24.1
20.0
2,798
kHz
kHz
32 kHz FS (8.192 MHz CLOCK)
Passband
Stopband
0
17.5
14.5
2,030
kHz
kHz
Other FS
Passband
Stopband
0
0.4535
63.4542
FS
FS
0.5458
Group Delay ([4096/2]/[64 × FS])
Group Delay Variation
32/FS
0
µs
NOT E
1Stopband repeats itself at multiples of 64 × FS, where FS is the output word rate. T hus the digital filter will attenuate to 115 dB across the frequency spectrum
except for a range ±0.5458 × FS wide at multiples of 64 × FS.
Specifications subject to change without notice.
O RD ERING GUID E
P ackage
D escription
P ackage
O ption
Model
Tem perature
AD1878JD
AD1879JD
–25°C to +70°C
–25°C to +70°C
Ceramic DIP
Ceramic DIP
D-28
D-28
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1878/AD1879 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. T herefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD1878/AD1879
D EFINITIO NS
Gr oup D elay Var iation
D ynam ic Range
T he difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the passband, expressed in microseconds (µs).
T he ratio of a full-scale output signal to the integrated output
noise in the passband (0 kHz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[T HD+N]) + 60 dB.
AD 1878/AD 1879 P IN LIST
Signal to (Noise + D istor tion)
P in Input/O utput P in Nam e D escription
T he ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all spectral components in the
passband, expressed in decibels (dB).
11 I/O
12 I/O
LRCK
BCK
S0
64/32
DVDD
DGND
N/C
Left/Right Clock
Bit Clock
Mode Select 0
Bit Rate Select
13
14
15
16
17
18
19
10
11
12
13
I
I
I
I
Signal to Total H ar m onic D istor tion (TH D )
T he ratio of the rms sum of all harmonically related spectral
components in the passband to the fundamental input signal,
expressed either as a percentage (%) or in decibels (dB).
+5 V Digital Supply
Digital Ground
No Connection; Do Not Connect
–5 V Analog Supply
–5 V Analog Logic Supply
Analog Ground
Analog Power Down
Right Inverting Input
Right Noninverting Input
Right Reference Capacitor
Left Reference Capacitor
Left Noninverting Input
Left Inverting Input
Analog Ground
+5 V Analog Supply
+5 V Analog Logic Supply
–5 V Analog Supply
+5 V Digital Supply
Digital Ground
P assband
I
I
I
I
I
I
AVSS
AVSS
1
2
T he region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
AGND
APD
P assband Ripple
VINR–
VINR+
REFR
REFL
VINL+
VINL–
AGND
T he peak-to-peak variation in amplitude response from equal
amplitude input signal frequencies within the passband, ex-
pressed in decibels.
14 I/O
15 I/O
Stopband
16
17
18
19
20
21
22
23
24
25
26
27
I
I
I
I
I
I
I
I
I
I
I
O
T he region of the frequency spectrum attenuated by the digi-
tal decimator’s filter to the degree specified by “stopband
attenuation.”
AVDD
AVDD
1
2
Gain Er r or
With a near full-scale input, the ratio of actual output to ex-
pected output, expressed as a percentage.
AVSS
1
DVDD
DGND
RESET
S1
CLOCK
DAT A
WCK
Inter channel Gain Mism atch
With near full-scale inputs, the ratio of outputs of the two stereo
channels, expressed in decibels.
Reset
Mode Select 1
Master Clock Input
Serial Data Output
Word Clock
Gain D r ift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
28 I/O
Midscale O ffset Er r or
Output response to a midscale input (i.e., zero volts dc), ex-
pressed in least-significant bits (LSBs).
TH EO RY O F O P ERATIO N
∑∆ Modulator Noise-Shaping
T he stereo, differential analog modulators of the AD1878/
AD1879 employ a proprietary feedforward and feedback archi-
tecture that passes input signals in the audio band with a unity
transfer function yet simultaneously shape the quantization
noise generated by the one-bit comparator out of the audio
band. See Figure 1. Without the ∑∆ architecture, this quantiza-
tion noise would be spread uniformly from dc to one-half the
oversampling frequency, 64 × FS. (Regardless of architecture,
64 times oversampling by itself significantly reduces the quanti-
zation noise in the audio band if the input is properly dithered.
However, the noise reduction is only [log2 64] × 3 dB = 18 dB.)
Midscale D r ift
Change in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) of full scale per °C.
Cr osstalk
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
Inter channel P hase D eviation
Difference in input sampling times between stereo channels, ex-
pressed as a phase difference in degrees between 1 kHz inputs.
P ower Supply Rejection
With analog inputs grounded, energy at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Gr oup D elay
Intuitively, the time interval required for an input pulse to ap-
pear at the converter’s output, expressed in milliseconds (ms).
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.
Figure 1. AD1878/AD1879 Modulator Noise-Shaper (One
Channel)
REV. 0
–5–
AD1878/AD1879
T he AD1878/AD1879’s patented ∑∆ architectures “shape” the
quantization noise-transfer function in a nonuniform manner.
T hrough careful design, this transfer function can be specified to
high-pass filter the quantization noise out of the audio band into
higher frequency regions. See Figure 27. T he Analog Devices’
AD1878/AD1879 also incorporates feedback resonators from
the third integrator’s output to the second integrator’s input and
from the fifth integrator’s output to the fourth integrators’ input.
T hese resonators do not affect the signal transfer function but
allow flexible placement of zeros in the noise transfer function.
For the AD1878/AD1879, these zeros were placed near the high
frequency end of the audio passband, reducing the quantization
noise in a region where it otherwise would have been increasing.
continuous-time modulators, which are very sensitive to the
exact location of sampling clock edges.
See Figures 20–23 for illustrations of the AD1878/AD1879’s
typical analog performance resulting from this design. Signal-
to-noise+distortion is shown under a range of conditions. Note
the very good linearity performance of the AD1878/AD1879 as
a consequence of its single-bit ∑∆ architecture in Figure 24.
T he common-mode rejection (Figure 25) graph illustrates the
benefits of the AD1878/AD1879’s differential architecture. T he
excellent channel separation shown in Figure 26 is the result of
careful chip design and layout. T he relatively small change in
gain over temperature (Figure 31) results from a robust refer-
ence design.
Oversampling by 64 simplifies the implementation of a high per-
formance audio analog-to-digital conversion system. Antialias
requirements are minimal; a single pole of filtering will usually
suffice to eliminate inputs near FS and its higher multiples.
T he output of the AD1878/AD1879 modulators is a stereo
bitstream at 64 × FS (3.072 MHz for FS = 48 kHz). Spectral
analysis of these bits would show that they contain a high qual-
ity replica of the input in the audio band and an enormous
amount of quantization noise at higher frequencies. T he input
signal can be recreated directly if these bits are fed into a prop-
erly designed analog low-pass filter.
A fifth-order architecture was chosen both to strongly shape the
noise out of the audio band and to help break up the idle tones
produced in all ∑∆ architectures. T hese architectures have a ten-
dency to generate periodic patterns with a constant dc input, a
response that looks like a tone in the frequency domain. T hese
idle tones have a direct frequency dependence on the input dc
offset and indirect dependence on temperature and time as it
affects dc offset. T he human ear operates effectively like a spec-
trum analyzer and can be sensitive to tones below the integrated
noise floor, depending on frequency and level. T he AD1878/
AD1879 suppresses idle tones typically 110 dB or better below
full-scale input levels.
D igital Filter Char acter istics
T he digital decimator accepts the modulators’ stereo bitstream
and simultaneously performs two operations on it. First, the
decimator low-pass filters the quantization noise that the modu-
lator shaped to high frequencies and filters any other out-of-
audio-band input signals. Second, it reduces the data rate to an
output word rate equal to FS. T he high frequency bitstream is
reduced to stereo 16-/18-bit words at 48 kHz (or other desired
FS). T he one-bit quantization noise, other high-frequency com-
ponents of the bitstream, and analog signals in the stopband are
attenuated by at least 115 dB.
Previously it was thought that higher-order modulators could
not be designed to be globally stable. However, the AD1878/
AD1879’s modulator was designed, simulated, and exhaustively
tested to remain stable for any input within a wide tolerance of
its rated input range. T he AD1878/AD1879 was designed to
reset itself should it ever be overdriven and go unstable. It will
reset itself within 5 µs at a 48 kHz sampling frequency. Any such
reset events will be invisible to the user since overdriving the in-
puts will produce a “clipped” waveform at the output.
T he AD1878/AD1879 decimator implements a symmetric Finite
Impulse Response (FIR) filter, resulting in its linear phase re-
sponse. T his filter achieves a narrow transition band (0.0923 ×
FS), high stopband attenuation (> 115 dB), and low passband
ripple (< 0.001 dB). T he narrow transition band allows the
unattenuated digitization of 20 kHz input signals with FS as low
as 44.1 kHz. T he stopband attenuation is sufficient to eliminate
modulator quantization noise from affecting the output. Low
passband ripple prevents the digital filter from coloring the
audio signal. For this level of performance, 4095 22-bit coeffic-
ients (taps) were required in each channel of this filter. T he
AD1878/AD1879’s decimator employs a proprietary single-
stage, multiplier-free structure developed in conjunction with
Ensoniq Corporation. See Figures 28 and 29 for the digital
filter’s characteristics.
T he AD1878/AD1879 modulator architecture has been imple-
mented using switched-capacitors. A systems benefit is that ex-
ternal sample-and-hold amplifiers are unnecessary since the
capacitors perform the sample-and-hold function Coefficient
weights are created out of varying capacitor sizes. T he dominant
noise source in this design is kT /C noise, and the input capaci-
tors are accordingly very large to achieve the AD1878/AD1879’s
performance levels. (Each 6 dB improvement in dynamic range
requires a quadrupling of input capacitor size, as well as an
increase in size of the op amps to drive them.) T his AD1878/
AD1879 thermal noise has been controlled to properly dither the
input to an 18-bit level. (Note that 16-bit results from either the
AD1878 or AD1879 will be underdithered.)
T he output from the decimator is available as a single serial
output, multiplexed between left and right channels.
Note that the digital filter itself is operating at 64 × FS. As a
consequence, Nyquist images of the passband, transition band,
and stopband will be repeated in the frequency spectrum at
multiples of 64 × FS. T hus the digital filter will attenuate to
115 dB across the frequency spectrum except for a window
±0.5458 × FS wide centered at multiples of 64 × FS. Any input
signals, clock noise, or digital noise in these frequency windows
will not be attenuated to the full 115 dB. If the high frequency
signals or noise appear within the passband images within these
windows, they will not be digitally attenuated at all.
With capacitors of adequate size and op amps of adequate drive,
a well-designed switched-capacitor modulator will be relatively
insensitive to jitter on the sampling clock. T he key issue is
whether the capacitors have had sufficient time to charge or
discharge during the clock period. A properly designed switched
capacitor modulator should be no more sensitive to clock jitter
than are traditional nonoversampled ADCs. T his contrasts with
–6–
REV. 0
AD1878/AD1879
Sam ple D elay
T he AD1878/AD1879 decimator makes use of dynamic logic to
minimize die area. T here is, therefore, a minimum clock fre-
quency that the AD1878/AD1879 will support specified in
“Specifications” above. Operation of the AD1878/AD1879 at
lower frequencies will cause the device to consume excessive
power and may damage the converter.
T he sample delay or “group delay” of the AD1878/AD1879 is
dominated by the processing time of the digital decimation fil-
ter. FIR filters convolve a vector representing time samples of
the input with an equal-sized vector of coefficients. After each
convolution, the input vector is updated by adding a new
sample at one end of the “pipeline” and eliminating the oldest
input sample at the other. For an FIR filter, the time at which a
step input appears at the output will be approximately when that
step input is halfway through the input sample vector pipeline.
T he input sample vector is updated every 64 × FS. T hus, the
sample delay will be given by the equation,
Reset
T he active LO RESET pin (Pin 24) allows initializing the
AD1879. T his is of value only for synchronizing multiple
AD1878/AD1879s in Master Mode—WCK Output. Unless you
are interested in synchronizing multiple AD1878/AD1879s, we
recommend tying RESET HI. T he reset function is useful for
nothing else. In fact, there is a maximum specification on
RESET LO; excessive power consumption may occur with loss
of reliability if left LO too long due to the dynamic logic on the
chip.
Group Delay = (4096Ϭ 2) /(64 × FS) = 32 / FS
For the most common sample rates this can be summarized as:
FS
Group D elay
Figure 14 illustrates the timing parameters for RESET to
accomplish synchronization of multiple Master Mode—Word
Clock Output ADCs. (T his sequence is not necessary for syn-
chronizing multiple AD1878/AD1879s in other modes. See
“Synchronizing Multiple AD1878/AD1879s” below.) Note that
RESET first has to be LO for at least four CLOCK periods
(three CLOCKs plus tRSET plus tRHLD, to be more precise).
T hen RESET must be HI for a minimum of one CLOCK and a
maximum of two CLOCKs. T hen RESET must he LO for at
least another four CLOCKs. From the time when RESET goes
HI again, exactly 127 CLOCKs will occur before LRCK goes
LO.
48 kHz
44.1 kHz
32 kHz
667 µs
725 µs
1000 µs
Due to the linear phase properties of FIR filters, the group delay
variation, or differences in group delay at different frequencies is
zero.
O P ERATING FEATURES
Voltage Refer ence
T he AD1878/AD1879 includes a +3 V on-board reference
which determines the AD1878/AD1879’s input range. T his ref-
erence is buffered to both channels of the AD1878/AD1879’s
modulator, providing a well-matched reference to minimize
interchannel gain mismatch. T he reference should be bypassed
with 10 µF tantalum capacitors as shown in Figure 2. T he inter-
nal reference can be overpowered by applying an external refer-
ence at the REFR (Pin 14) and REFL (Pin 15) pins, allowing
multiple AD1878/AD1879s to be calibrated to the same gain.
Note that the reference pins still must be bypassed as shown.
Analog P ower D own
T he AD1878/AD1879 features a power-down mode that
reduces current to the analog modulator. It is controlled by
the active HI APD (Pin 11). T he power savings are specified in
“Specifications.” T he converter is still “alive” in the power-
down state but will not produce valid results for all audio-band
inputs.
Power consumption can be further reduced by slowing down
the master clock input to the minimum clock frequency,
Sam ple Clock
An external master clock supplied to CLOCK (Pin 26) drives
the AD1878/AD1879 modulator, decimator, and digital inter-
face. As with any analog-to-digital conversion system, the sam-
pling clock must be low jitter to prevent conversion errors.
FCLOCK, specified for the AD1878/AD1879.
AP P LICATIO NS ISSUES
Recom m ended Input Str uctur e
T he AD1878/AD1879 input structure is fully differential for
improved common-mode rejection properties and increased
dynamic range. Since each input pin sees ±3 V swings, each
channel’s input signal effectively swings ±6 V, i.e., across a
12 V range.
T he input clock operates at 256 × FS. T he clock is divided down
to obtain the 64 × FS clock required for the modulator. T he out-
put word rate will be at FS itself. T his relationship is illustrated
for popular sample rates below:
AD 1879
CLO CK Input
Modulator
Sam ple Rate
O utput Word
Rate
In most cases, a single-ended-to-differential input circuit is
required. Shown in Figure 2 is our recommended circuit, based
on extensive experimentation. Note that to maximize signal
swing, the op amps in this circuit are powered by ±12 V or
greater supplies. T he AD1878/AD1879 itself requires ±5 V
supplies. If ±5 V supplies are not already available in your sys-
tem, Figure 3 illustrates our recommended circuit for generat-
ing these supplies.
12.288 MHz
11.2896 MHz
8.192 MHz
3.072 MHz
2.822 MHz
2.048 MHz
48 kHz
44.1 kHz
32 kHz
T he AD1878/AD1879 serial interface supports both “master”
and “slave” modes. Note that even in slave mode it is presumed
that the serial interface clocks are derived from the master clock
input, CLOCK. Slave mode does not support asynchronous
data transfers, since asynchronous data transfers would compro-
mise the performance of any high performance converter.
REV. 0
–7–
AD1878/AD1879
the input structure shown in Figure 2. T he trimmed specifica-
tions are based on a part-by-part trim of this differential gain to
eliminate the second harmonic.
100pF
249kΩ
5.76kΩ
NE5532 OR
OP-275
.1µF
10µF
T he input circuit of Figure 2 could be implemented with a
single pair of operational amplifiers per channel, one inverting
and one noninverting. T he recommended architecture shown in
Figure 2 using three inverting op amps per channel provides iso-
lation of the op amp inputs from charge dumped back from the
AD1878/AD1879’s input capacitors when these large capacitors
switch. T he performance from a two op amp per channel input
structure is not quite as good as the structure recommended,
but it is close and may be adequate in many applications.
V
CC
RIGHT INPUT
.01µF
NPO
5.62kΩ
51Ω
200Ω
14
5.62kΩ
100kΩ
.1µF
.0047 µF
NPO
REFR
5.62kΩ
V
SS
51Ω
AD1878/79
.01µF
NPO
.1µF
5.62kΩ
5.49kΩ
12
13
16
17
VINR–
VINR+
VINL+
VINL–
V
249kΩ
SS
Layout and D ecoupling Consider ations
100pF
NE5532 OR OP-275
Obtaining the best possible performance from a state-of-the-art
data converter like the AD1878/AD1879 requires close atten-
tion to board layout. From extensive experimentation, we have
discovered principles that produce typical values of 103 dB dy-
namic range and 98 dB S/(THD+N) in your system. Schematics
of our AD1878/AD1879 Evaluation Board, which implements
these recommendations, are available from Analog Devices.
100pF
V
CC
249kΩ
.1µF
.01µF
NPO
5.36kΩ
5.62kΩ
51Ω
REFL
100kΩ
5.62kΩ
V
15
.0047 µF
NPO
CC
.1µF
200Ω
T he principles and their rationales are listed below in descend-
ing order of importance. T he first two pertain to bypassing and
are illustrated in Figure 4.
LEFT
INPUT
5.62kΩ
51Ω
.1µF
10µF
.01µF
NPO
5.62kΩ
–5V
+5V
V
SS
ANALOG
ANALOG
10µF
5.90kΩ
NE5532 OR
OP-275
10µF
249kΩ
100pF
8
21
19
10
1 AGND AGND
DD
18
+5V DIGITAL
OSCILLATOR
AV
1
AV
1
AV
SS
SS
Figure 2. AD1878/AD1879 Recom m ended Input Structure
0.1µF
26
CLKIN
AD1878/ 79
+5V ANALOG
7805
V
IN
OUT
CC
AV
2
AV
2
DV
DGND DGND DV
DD
GND
SS
DD
DD
22
10µF
10µF
0.1µF
0.1µF
0.1µF
0.1µF
+5V DIGITAL
22µF
–5V
ANALOG
23
9
20
5
6
AGND
22µF
GND
V
0.1µF
IN
10µF
0.1µF
10µF
OUT
7905
SS
–5V
V
+5V
ANALOG
DD
10µF
+12V < V < +18V
CC
ANALOG
0.1µF
22µF
–12V > V > – 18V
SS
+5V
DIGITAL
+5V
DIGITAL
DGND
Figure 4. AD1878/AD1879 Recom m ended Bypassing and
Oscillator Circuits
Figure 3. AD1878/AD1879 Recom m ended Power Condi-
tioning Circuit (If ±5 V Supplies Are Not Already Available)
•
T he digital bypassing of the AD1878/AD1879 is the most
critical item on the board layout. T here are two pairs of digi-
tal supply pins of the part, each pair on opposite sides (Pins 5
and 6 and Pins 22 and 23). T he user should tie a bypass ca-
pacitor set (0.1 µF ceramic and 10 µF tantalum) on EACH
pair of supply pins as close to the pins as possible. T he traces
between these package pins and the capacitors should be as
short and as wide as possible. T his will prevent digital supply
current transients from being inductively transmitted to the
inputs of the part.
T he trim potentiometers shown in Figure 2 connecting the
minus (–) inputs of the driving op amps permit trimming out dc
offset, if desired.
Note that the driving op amp feedback resistors are all slightly
different values. T hese values produce a slight differential gain
imbalance and were derived empirically to minimize second
harmonic distortion on average and produce the best overall
T HD without part-by-part trimming. Replacing one of these
feedback resistors in each channel with a trim potentiometer
allows trimming the differential gain imbalance for part-by-part
optimal performance. We have done this in the lab by parallel-
ing 100 kΩ trim potentiometers around the 5.49 kΩ and
5.36 kΩ input feedback resistors for the VIN plus (+) signals
that can be found in Figure 2. By trimming gain imbalance, sec-
ond harmonic distortion can always be eliminated. In “Specifi-
cations,” a distinction is drawn between trimmed and untrimmed
signal-to (noise + distortion) and trimmed and untrimmed total
harmonic distortion. T he untrimmed specifications are tested to
•
T he analog input bypassing is the second most critical item.
Use 0.01 µF NPO ceramic capacitors from each input pin to
the analog ground plane, with a clear ground path from the
bypass capacitor to the AGND pin on the same side of the
package (Pins 10 and 18). T he trace between this package
pin and the capacitor should be as short and as wide as pos-
sible. A 0.0047 µF NPO ceramic capacitor should be placed
–8–
REV. 0
AD1878/AD1879
between each set of input pins (12 to 13, and 17 to 16) to
complete the input bypassing. T his input bypassing mini-
mizes the RF transmission and reception capability of the
AD1878/AD1879 inputs.
be more effective.) T his technique makes use of the fact that the
noise in independent modulator channels is uncorrelated. T hus
every doubling of the number of AD1879 channels used will im-
prove system dynamic range by 3 dB. T he digital outputs from
the corresponding decimator channels have to be arithmetically
averaged to obtain the improved results in the correct data for-
mat. A digital processor, either general-purpose or DSP, can
easily perform the averaging operation.
•
•
For best performance, do not use a socket with the AD1878/
AD1879. If you must socket the part, use pin clips to keep
the part flush with the board, thus keeping bypassing as
close to the chip as possible.
Shown below in Figure 6 is a circuit for obtaining a 3 dB im-
provement in dynamic range by using both channels of a single
AD1879 with a mono input. T he minus (–) output from the in-
put buffer is sent to both right and left minus AD1879 inputs;
the plus (+) output from the input buffer is sent to both right
and left plus AD1879 inputs. A stereo implementation would
require using two AD1879s and using the full recommended in-
put structure shown above in Figure 2. Note that a single digital
processor would likely be able to handle the averaging require-
ments for both left and right channels.
T he AD1878/AD1879 should be placed on a split ground
plane as illustrated in Figure 5. T he digital ground plane
should be placed under the top end of the package and the
analog ground plane should be placed under the bottom end
of the package as shown in Figure 5. T he split should be be-
tween Pins 7 and 8 and between Pins 21 and 22. T he
ground planes should be tied together at one spot under-
neath the center of the package. T his ground plane tech-
nique also minimizes RF transmission and reception.
LRCK
BCK
S0
28
WCK
1
2
3
4
5
6
7
8
9
27 DATA
DIGITAL GROUND
PLANE
26
CLK
Figure 6. Increasing Dynam ic Range by Using Two
AD1879 Channels
S1
25
24
64/32
DV
DD
RESET
D IGITAL INTERFACE
Modes of O per ation
DGND
NC
23 DGND
22 DV
DD
T he AD1878/AD1879’s flexible serial output port produces
data in twos-complement, MSB-first format. Output signals are
to T T L/CMOS logic levels. T he port is configured by pin selec-
tions. T he AD1879 can operate in either master or slave modes.
Each 16-/18-bit output word of a stereo pair can be formatted
within a 32-bit field as right-justified, as I2S-compatible, or at
user-selected positions. T he two 32-bit fields constitute a 64-bit
frame (64-bit mode). T he output can also be truncated to 16
bits and formatted in a 16-bit field with two 16-bit fields in a
32-bit frame (32-bit mode).
21
20
19
18
17
16
15
AV
1
AV
AV
1
2
SS
SS
ANALOG GROUND
PLANE
AV
AV
2
SS
DD
1
AGND 10
APD 11
DD
AGND
VINL–
VINL+
REFL
VINR–
VINR+
REFR
12
13
14
T he various mode options are pin-programmed with the S0
Mode Select Pin (3), the S1 Mode Select Pin (25), and the
64/32 Bit Rate Select Pin (4). T he function of these pins is
summarized:
Figure 5. AD1878/AD1879 Recom m ended Ground Plane
•
•
Each reference pin (14 and 15) should be bypassed with a
resistor and a capacitor. One end of the resistor should be
placed as close to the package pin as possible, and the trace
to it from the reference pin should be as short and as wide as
possible. Keep this trace away from input pin traces! Cou-
pling between input and reference traces will cause second
harmonic distortion. T he resistor is used to reduce the high
frequency coupling into the references from the board.
Serial P ort O peration Mode
64/32 S0 S1
64-Bit Master Mode—Word Clock Output
64-Bit Master Mode—Word Clock Input
64-Bit Slave Mode
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
Reserved
32-Bit Master Mode—Word Clock Out HI
32-Bit Master Mode—Word Clock Ignored
32-Bit Slave Mode
Wherever possible, minimize the capacitive load on digital
outputs of the part. T his will reduce the digital spike cur-
rents drawn from the digital supply pins.
Reserved
Ser ial P or t D ata Tim ing Sequences
H ow to Extend SNR
In the “master modes,” the bit clock (BCK) and left/right clock
(LRCK) are always outputs, generated internally in the AD1878/
AD1879 from the master clock (CLOCK) input. T he word
clock (WCK) may either be an internally generated output or a
user-supplied input, depending on the pin-programmed mode
selected.
A cost-effective method of improving the dynamic range and
SNR of an analog-to-digital conversion system is to use mul-
tiple AD1879 channels in parallel with a common analog input.
(T he same technique would work with the AD1878. However,
this would be of little value since using a single AD1879 would
REV. 0
–9–
AD1878/AD1879
In the “slave modes,” the bit clock (BCK), the word clock
(WCK), and the left/right clock (LRCK) are user-supplied in-
puts. Note that, for performance reasons, the AD1878/AD1879
does not support asynchronous operation; these clocks must be
externally derived from the master clock (CLOCK). T he func-
tional sequence of the signals in the slave modes is identical to
the master modes with word clock input, and they share the
same sequence timing diagrams.
options are illustrated in Figures 9, 10, 11, and 12. For all op-
tions, the first occurrence in a 32-bit field when the word clock
(WCK) is HI on a bit clock (BCK) falling edge will cause the
beginning of data transmission. T he MSB on DAT A will be
valid at the next BCK rising edge. Again, the LRCK output dis-
criminates the left from the right output fields.
Figure 9 illustrates the general case for 64-bit frame modes with
word clock input where the MSB is valid on the rising edge of
the Nth bit clock (BCK). Figures 10 and 11 illustrate the limits.
If WCK is still LO at the falling edge of the 14th bit clock (BCK)
for the AD1879 or 16th bit clock (BCK) for the AD1878, then the
MSB of the current word will be output anyway, valid at the ris-
ing edge of the 15th bit clock (BCK) in the field for the AD1879,
17th for the AD1878. T his limit insures that all 16/18 bits will
be output within the current field. T he effect is to right-justify
the data.
In 64-Bit Master Mode with Word Clock Output, the 16-/18-bit
words are right-justified in 32-bit fields as shown in Figures 7
and 8. T he WCK output goes HI approximately with the falling
edge of the BCK output, indicating that the MSB on DAT A will
be externally valid at the next BCK rising edge. T he LRCK out-
put discriminates the left from the right output fields.
In 64-bit frame modes with word clock (WCK) is an input, the
16-/18-bit words can be placed in user-defined locations within
32-bit fields. T his is true in both master and slave modes. T he
32
1
2
3
14 15
16
17
18
29
30
31
32
1
2
3
14
15 16
17
18
29
30
31
32
1
BCK
OUTPUT
WCK
OUTPUT
LRCK
OUTPUT
RIGHT DATA
PREVIOUS DATA
LEFT DATA
MSB MSB–1 MSB–2 MSB–3
DATA
ZEROS
ZEROS
LSB
LSB–3 LSB–2 LSB–1 LSB
MSB MSB–1 MSB–2 MSB–3
LSB–3 LSB–2 LSB–1 LSB
OUTPUT
Figure 7. AD1879 64-Bit Output Tim ing with WCK as Output (Master Mode Only)
32
1
2
3
14 15
16 17
18
29
30
31 32
1
2
3
14 15
16
17
18
29 30
31
32
1
BCK
OUTPUT
WCK
OUTPUT
LRCK
OUTPUT
RIGHT DATA
PREVIOUS DATA
LEFT DATA
DATA
OUTPUT
ZEROS
ZEROS
LSB
MSB MSB–1
LSB–3 LSB–2 LSB–1 LSB
MSB MSB–1
LSB–3 LSB–2 LSB–1 LSB
Figure 8. AD1878 64-Bit Fram e Output Tim ing with WCK as Output (Master Mode Only)
32
1
N–1
N
N+1
N+14 N+15 N+16 N+17
31
32
1
N–1
N
N+1
N+14 N+15 N+16 N+17
31
32
1
BCK I/O
WCK INPUT
LRCK I/O
RIGHT DATA
LEFT DATA
ZEROS
ZEROS
AD1879
DATA OUTPUT
ZEROS
ZEROS
ZEROS
ZEROS
MSB MSB–1
LSB–3 LSB-2 LSB–1 LSB
LSB–1 LSB
MSB MSB–1
LSB–3 LSB-2 LSB–1 LSB
LSB–1 LSB
LEFT DATA
RIGHT DATA
AD1878
DATA OUTPUT
MSB MSB–1
MSB MSB–1
Figure 9. AD1878/AD1879 64-Bit Fram e Output Tim ing with WCK as Input: WCK Transitions HI Before 16th BCK
(AD1878)/14th BCK (AD1879) (Master Mode or Slave Mode)
–10–
REV. 0
AD1878/AD1879
32
1
2
3
14 15
16
17
18
19
20
31
32
1
2
3
14 15
16
17
18
19
20
31
32
1
BCK I/O
WCK INPUT
LRCK I/O
LEFT DATA
MSB MSB–1 MSB–2 MSB–3
PREVIOUS DATA
RIGHT DATA
MSB MSB–1 MSB–2 MSB–3
AD1878
DATA OUTPUT
ZEROS
ZEROS
LSB
LSB–1 LSB
LSB–1 LSB
Figure 10. AD1878 64-Bit Fram e Output Tim ing with WCK as Input: WCK Held LO Until 16th BCK
(Master Mode or Slave Mode)
32
1
2
3
14 15
16
17
18
19
20
31
32
1
2
3
14
15
16
17
18
19
20
31
32
1
BCK I/O
WCK INPUT
LRCK I/O
PREVIOUS DATA
LEFT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
RIGHT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
AD1879
DATA OUTPUT
ZEROS
ZEROS
LSB
LSB–1 LSB
LSB–1 LSB
Figure 11. AD1879 64-Bit Fram e Output Tim ing with WCK as Input: WCK Held LO Until 14th BCK
(Master Mode or Slave Mode)
32
1
2
3
16
17
18
19 20
21 22
31 32
1
2
3
16
17
18
19
20
21 22
31 32
1
BCK I/O
WCK INPUT
LRCK I/O
LEFT DATA
RIGHT DATA
AD1879
DATA OUTPUT
ZEROS
ZEROS
ZEROS
ZEROS
ZEROS
ZEROS
MSB MSB–1
LSB–3 LSB-2 LSB–1 LSB
LSB–1 LSB
MSB MSB–1
LSB–3 LSB-2 LSB–1 LSB
LSB–1 LSB
LEFT DATA
RIGHT DATA
AD1878
DATA OUTPUT
ZEROS
ZEROS
MSB MSB–1
MSB MSB–1
Figure 12. AD1878/AD1879 64-Bit Output Fram e Tim ing with WCK as Input: WCK Hl During 1st BCK
(Master Mode or Slave Mode)
16
1
2
3
4
5
6
15 16
1
2
3
4
5
6
15 16
1
BCK I/O
LRCK I/O
LEFT DATA
RIGHT DATA
AD1879
DATA OUTPUT
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB–3 LSB–2 MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB–3 LSB–2
LSB-1 LSB
LEFT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
RIGHT DATA
LSB-1 LSB MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
AD1878
DATA OUTPUT
Figure 13. AD1878/AD1879 32-Bit Output Fram e Tim ing (Master Mode or Slave Mode)
At the other limit, if the word clock (WCK) is HI during the first
bit clock (BCK) of the field, then the MSB of the output word
will be valid on the rising edge of the 2nd bit clock (BCK) as
shown in Figure 12. T he effect is to delay the MSB for one bit
clock cycle into the field, making the output data compatible at
the data format level with the I2S data format.
In 64-bit frame modes with word clock (WCK) as an input, the
relative placement of the word clock (WCK) input can vary
from 32-bit field to 32-bit field, even within the same 64-bit
frame. For example, within a single 64-bit frame the left word
could be right-justified (by keeping WCK LO) and the right
word could be in an I2S-compatible data format (by having
WCK HI at the beginning of the second field).
REV. 0
–11–
AD1878/AD1879
Also available with the AD1878/AD1879 is a 32-bit frame mode
where the 1879’s 18-bit output is truncated to 16-bit words and
for both parts the output packed “tightly” into two 16-bit fields
in the 32-bit frame as shown in Figure 13. Note that the bit
clock (BCK) and data transmission (DAT A) are operating at
one-half the rate as they would in the 64-bit frame modes. T he
distinction between master and slave modes still holds in the
32-bit frame modes, though the word clock (WCK) becomes ir-
relevant. If “32-Bit Master Mode With Word Clock Out HI” is
selected, the word clock (WCK) will stay in a constant HI state.
If “32-Bit Master Mode With Word Clock Ignored” is selected,
the word clock pin (WCK) will be three-stated and any input to
it is ignored as meaningless. (However, such an input should be
tied off to HI or LO and not left to float.)
delayed from a master clock input (CLOCK) rising edge by
tDLYCK as shown in Figure 15. T he MSB of the DAT A output
will be delayed from a falling edge of master clock (CLOCK) by
t
DLYD,MSB. Subsequent bits of the DAT A output in contrast will
be delayed from a rising edge of master clock (CLOCK) by
DLYD. (T he MSB is valid one-half CLOCK period less than the
t
subsequent bits.)
For master modes with word clock (WCK) inputs, bit clock
(BCK) and left/ right clock (LRCK) will be delayed from a
master clock input (CLOCK) rising edge by tDLYCK as shown in
Figure 16, the same delay as with word clock output modes.
T he word clock (WCK) input, however, now has a setup time
requirement, tWSET, to the rising edge of master clock (CLOCK
at “W”) and a corresponding hold time, tWHLD, from the rising
of the third rising edge of CLOCK (W+3) after the setup edge.
See Figure 16. As in the Master Mode—Word Clock Output
case, the MSB of the DAT A output will be delayed from a fall-
ing edge of master clock (CLOCK) by tDLYD,MSB. Subsequent
bits of the DAT A output in contrast will be delayed from a ris-
In both 32-bit master modes, the left/right clock (LRCK) will be
an output, indicating the difference between the left word/field
and right word/field. In 32-Bit Slave Mode, the left/right clock
(LRCK) is an input.
Tim ing P ar am eter s
ing edge of master clock (CLOCK) by tDLYD
For slave modes, bit clock (BCK) and left/right clock (LRCK)
will be inputs with setup time, tSET , and hold time tH LD
.
T he AD1878/AD1879 uses its master clock, CLOCK to resyn-
chronize all inputs and outputs. T he discussion above presumed
that most timing parameters are relative to the bit clock, BCK.
T his is approximately true and provides an accurate model of
the sequence of timing events. However, to be more precise, we
have to specify all setup and hold times relative to CLOCK.
T hese are illustrated in Figures 15, 16, and 17.
,
requirements to the falling edges of CLOCK as shown in Fig-
ure 17. Note that both edges of BCK and of LRCK have setup
and hold time requirements. Note also that LRCK is setup to
the falling edge of the “L” CLOCK, coincident with the CLOCK
edge to which a falling edge of BCK is setup (B+3). LRCK’s
hold time requirements are relative to the falling edge of the
“L + 31” CLOCK edge.
For master modes with word clock (WCK) output, bit clock
(BCK), left/right clock (LRCK), and word clock (WCK) will be
MIN 1 CLK
MAX 2 CLKS
FOR SYNCH
MIN 4 CLKS
FOR SYNCH
MIN 4 CLKS
FOR SYNCH
1
2
3
4
126 127 128
CLOCK INPUT
RESET
tRSET
tRHLD
tRPLS
LRCK OUTPUT
BCK OUTPUT
Figure 14. AD1878/AD1879 RESET Clock Tim ing for Synchronizing Master Mode WCK Output
CLOCK INPUT
tDLYCK
1
14
15
16
17
BCK OUTPUT (64•F )
S
tDLYCK
tDLYCK
tDLYCK
LRCK & WCK OUTPUTS
DATA OUTPUT
PREVIOUS
NEW
tDLYD
tDLYD,MSB
ZEROS
tDLYD
MSB
MSB–1
MSB–2
Figure 15. AD1878/AD1879 Master Mode Clock Tim ing: WCK Output
–12–
REV. 0
AD1878/AD1879
W
W+1 W+2 W+3
CLOCK INPUT
tDLYCK
1
BCK OUTPUT (64•F
)
S
tDLYCK
tDLYCK
tWSET
tDLYCK
PREVIOUS
NEW
LRCK OUTPUT
WCK INPUT
tWHLD
tDLYD,MSB
tDLYD
tDLYD
DATA OUTPUT
MSB
MSB–1
MSB–2
ZEROS
Figure 16. AD1878/AD1879 Master Mode Clock Tim ing: WCK Input
B
B+1 B+2 B+3
L+1
L+30 L+31
L
W
W+1 W+2 W+3
CLOCK INPUT
tHLD
tHLD
tSET
tSET
BCK INPUT (64•F )
S
tHLD
tSET
LRCK INPUT
WCK INPUT
tWSET
tWHLD
tDLYD,MSB
ZEROS
tDLYD
tDLYD
DATA OUTPUT
MSB
MSB–1
MSB–2
Figure 17. AD1878/AD1879 Slave Mode Tim ing
For slave modes, the word clock (WCK) input has the same
setup time requirement, tWSET, to the rising edge of master
clock (CLOCK at “W” ) as in Figure 16 and a corresponding
hold time, tWHLD, from the rising edge of CLOCK (W+3) after
the setup edge. T he MSB of the DAT A output will be delayed
Word Clock Output. T hus, the AD1878/AD1879 is the master
of the serial interface. T he AD1878/AD1879 operates indepen-
dently from the DSµPs clock. T he DSP56001 serial port is
configured to operate in synchronous mode with the AD1878/
AD1879 connected to its synchronous serial interface (SSI) port.
from a falling edge of master clock (CLOCK) by tDLYD,MSB
Subsequent bits of the DAT A output in contrast will be delayed
.
CLOCK
SOURCE
CLOCK
SOURCE
from a rising edge of master clock (CLOCK) by tDLYD
.
Synchr onizing Multiple AD 1878/AD 1879s
DATA
BCK
WCK
LRCK
DATA
BCK
WCK
LRCK
#1 AD1879
#1 AD1879
SLAVE MODE
Multiple AD1878/AD1879s can be synchronized either by
making all AD1878/AD1879s serial port slaves or by making
one AD1879 the serial port master and all other AD1879s
slaves. T hese two options are illustrated in Figure 18.
MASTER MODE
CLK
CLK
DATA
BCK
WCK
LRCK
DATA
BCK
WCK
LRCK
#2 AD1879
SLAVE MODE
#2 AD1879
SLAVE MODE
As a third alternative, it is possible to synchronize multiple mas-
ters all in Master Mode—Word Clock Output mode. See the
“Reset” discussion above in the “Operating Features” section
for timing considerations.
CLK
CLK
DATA
BCK
WCK
LRCK
DATA
BCK
WCK
LRCK
#N AD1879
SLAVE MODE
#N AD1879
SLAVE MODE
AD 1878/AD 1879 to D SP 56001 Inter face
T he 18-bit AD1878/AD1879 can be interfaced quite simply to
the DSP56001 Digital Signal Processor. Figure 19 illustrates
one method of connection. In this implementation, the AD1878/
AD1879 is configured to operate in 64-Bit Master Mode With
CLK
CLK
Figure 18. Synchronizing Multiple AD1878/AD1879s
REV. 0
–13–
AD1878/AD1879
AD 1878/AD 1879 P ERFO RMANCE GRAP H S
DATA
SRD
SCK
SC2
SC1
DSP56001
BCK
AD1879
0
–20
WCK
LRCK
–40
Figure 19. AD1879 to DSP56001 Interface
T o configure the DSP56001 for proper operation, the CRA
register must he programmed for a 24-bit receive data register
(RX). T he CRB register must be programmed with the follow-
ing conditions: receiver enabled, normal mode, continuous
clock, word length frame synch, MSB first, SCK an input, SC1
an input and SC2 an input. T he PCC register must be pro-
grammed to set the SCK, SC1, SC2, and SRD pins of Port C
to operate as a serial interface rather than in general-purpose
parallel I/O mode.
–60
–80
–100
–120
–140
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k
FREQUENCY – Hz
When SSI detects the rising edge of the AD1878/AD1879’s
word clock (WCK), the next 24-bits on the AD1878/AD1879’s
DAT A pin will be clocked into the DSP56001’s SSI receive
shift register on the falling edges of the inverted bit-clock
(BCK) signal. T his data is then transferred to the RX register.
T he 16-/18-bit word from the AD1879 will be located in Bits 8
through 23/21 of the RX register. Bits 0 through 7 will be
zero-filled. T he user may poll Bit 7 (RDF) of the SSI status
register (SSISR) to detect when the data has been transferred
to RX. Alternatively, the RIE bit can be set, allowing an inter-
rupt to occur when the data has been transferred.
Figure 20. AD1879 S/(THD+N)—1 kHz Tone at –0.5 dBFS
(4k-Point FFT)
0
T o differentiate left and right data, the SC1 pin of the SSI is an
input and is connected to the LRCK of the AD1878/AD1879.
After a data word is transferred to the RX register, the software
reads the IF1 bit in the SSISR, which contains the left/right in-
formation. In order to use the SC1 pin as indicated, the SSI
must operate in synchronous mode. An DSP56001 assembly
code fragment for this approach (with polling) is shown in
T able I.
–
–
–
FREQUENCY – Hz
Figure 21. AD1879 S/(THD+N)—1 kHz Tone at –10 dBFS
(4k-Point FFT)
Table I. D SP 56001 Assem bly Code for AD 1878/AD 1879 D ata
Transfer
0
poll jclr
movep
# 7,X:$FFEE,poll :loop until RX reg. has data
X:$FFEF,al: :transfer ADC to al register
# I:X:$FFEE,left :if LRCK=1, save left else
jset
move
jmp
a1,X:$C000
poll
:store right channel
:wait for next input
:store left channel
left move
a1,Y:$C000
jump poll
If the SSI is set up for asynchronous operation, the SC0 and
SC1 pins are unavailable for left/right detection. If asynchro-
nous operation is essential, left/right information can be ob-
tained by synchronizing the AD1878/AD1879 with a software
reset. Coming out of reset, the AD1878/AD1879 will transmit
left channel data first. A flag maintained in software can main-
tain the synchronization.
FREQUENCY – Hz
Figure 22. AD1879 S/(THD+N)—1 kHz Tone at –60 dBFS
(4k-Point FFT)
–14–
REV. 0
AD1878/AD1879
–100
–105
–110
–115
–120
–125
–130
–135
–140
–140
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k
FREQUENCY – Hz
20
100
1k
10k
20k
FREQUENCY – Hz
Figure 26. AD1878/AD1879 Channel Separation—0 kHz to
20 kHz
Figure 23. AD1879 S/(THD+N)—10 kHz Tone at –10 dBFS
(4k-Point FFT)
1e–2
1M
1e–4
1e–5
1u
–
–
–
–
–
1e–7
1e–8
1e1
1e2
1k
1e4
1e5
1M
AMPLITUDE – dBFS
FREQUENCY – Hz
Figure 24. AD1879 Linearity Test—10 kHz Tone Fade to
Noise
Figure 27. AD1878/AD1879 Modulator Noise Transfer
Function—0 MHz to 1 MHz
10
–10
–64
–66
–68
–70
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
–30
–50
–70
–90
–110
–130
–150
20
100
1k
10k
100k
1e1
1e2
1k
1e4
1e5
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 25. AD1878/AD1879 Com m on-Mode Rejection
Ratio—0 kHz to 20 kHz
Figure 28. AD1878/AD1879 Digital Filter Signal Transfer
Function—0 MHz to 1 MHz
REV. 0
–15–
AD1878/AD1879
1.012
1.011
0
–10
1.010
1.009
1.008
1.007
–20
–30
–40
–50
1.006
–60
1.005
1.004
–70
1.003
1.002
1.001
1.000
0.999
–80
–90
–100
–110
–120
–130
0.998
0.997
21.5 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 26.0 26.5
–30
–10
10
30
50
70
90
110
130
FREQUENCY – kHz
TEMPERATURE – °C
Figure 29. AD1878/AD1879 Digital Filter Signal Transfer
Function— Transition Band: 21.5 kHz to 26.5 kHz
Figure 30. AD1878/AD1879 Typical Gain Over
Tem perature— –30°C to +130°C
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
D -28
28-Lead Side Brazed Ceram ic D IP
0.005 (0.13) MIN
0.100 (2.54) MAX
15
28
0.610 (15.49)
0.500 (12.70)
PIN 1
14
1
0.060 (1.52)
0.015 (0.38)
0.620 (15.75)
0.590 (14.99)
1.490 (37.85) MAX
0.225
(5.72)
MAX
0.200 (5.08)
0.150
(3.81)
MIN
0.018 (0.46)
0.008 (0.20)
0.125 (3.18)
0.026 (0.66)
0.014 (0.36)
0.110 (2.79)
0.090 (2.29)
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
–16–
REV. 0
相关型号：
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