AD1882AJCPZ-RL [ADI]
High Definition Audio SoundMAX Codec; 高清晰度音频编解码器的SoundMAX型号: | AD1882AJCPZ-RL |
厂家: | ADI |
描述: | High Definition Audio SoundMAX Codec |
文件: | 总20页 (文件大小:336K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
High Definition Audio
SoundMAX Codec
AD1882A
Stereo digital microphone
FEATURES
Two 192 kHz digital microphone channels
Supports 1 or 2 microphones on 1 pin
Selectable bit clock rates of 1.5 MHz, 2.0 MHz, and 3.0 MHz
All sample rates, 8 kHz through 192 kHz
16-, 20-, and 24-bit resolution
Six 192 kHz, 95 dB DACs
All independent sample rates, 8 kHz through 192 kHz
16-, 20-, and 24-bit PCM resolution
Selectable stereo mixer on outputs
Four 192 kHz, 90 dB ADCs
Simultaneous record of up to 2 stereo channels
All independent sample rates, 8 kHz through 192 kHz
16-, 20-, and 24-bit resolution
Microsoft Vista Premium® logo for notebook and desktop
Impedance and presence detection on all jack pins
2 general-purpose digital I/O (GPIO) pins
Advanced power management modes
S/PDIF output
EAPD control for internal speakers
Supports all sample rates 44.1 kHz through 192 kHz
16-, 20-, and 24-bit data widths; PCM and AC3 formats
Digital PCM gain control
3.3 V analog and digital supply voltage
1.5 V and 3.3 V HD Audio link signaling
Very low power consumption in D3 state
Dedicated auxiliary pins
Stereo CD input w/GND sense
Mono out pin for internal speaker with EAPD support
Analog PCBeep input pin
S/PDIF Tx
S/PDIF OUT
AD1882A
DIGITAL
BEEP
DAC0
DAC1
DAC2
PORT F
⌺
H
D
HP
PORT D
PORT G
⌺
⌺
⌺
⌺
A
U
D
I
MONO OUT
PORT A
O
HP
DM_CLK
DIGITAL
MICROPHONE
I
DM_DATA
N
T
E
R
F
A
C
E
⌺
⌺
PORT C
PORT E
⌺
ADC0
PCBEEP
PORT B
CD IN
ADC1
Figure 1. AD1882A Block Diagram
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD1882A
CONTENTS
Features ................................................................. 1
Contents ................................................................ 2
Revision History ...................................................... 2
General Description ................................................. 3
Special Software Features ........................................ 3
Additional Information .......................................... 3
Jack Configuration ................................................ 3
Specifications .......................................................... 4
Test Conditions .................................................... 4
Performance ........................................................ 4
General Specifications ............................................ 4
HD Audio Link Specifications .................................. 6
Power-Down States ............................................... 6
Absolute Maximum Ratings .................................... 7
ESD Caution ........................................................ 7
Environmental Conditions ...................................... 7
Pin Configuration and Function Descriptions ................. 8
Digital Microphone Interface Timing Specifications ....... 11
HD Audio Parameters ............................................. 12
Widget Parameters ................................................. 13
HD Audio Widgets ................................................ 14
Connection List ..................................................... 15
Default Configuration Bytes ..................................... 16
Outline Dimensions ............................................... 17
Ordering Guide ..................................................... 17
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0
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August 2008
AD1882A
GENERAL DESCRIPTION
The AD1882A audio codec and SoundMAX® software provides
superior HD audio quality that exceeds Vista Premium perfor-
mance. The AD1882A has six DACs and four ADCs, two stereo
headphone ports, C/LFE swapping, digital and analog PCBeep,
and S/PDIF output, making the AD1882A the right choice for
desktop and notebook PCs where performance is the primary
consideration.
JACK CONFIGURATION
The guidelines shown in Table 1 through Table 4 should be
used when selecting ports for particular functions.
Table 1. Typical Desktop Configuration with Discrete Jacks
Port
Function
The jack retasking feature on this product supports various con-
figurations including platforms for 5.1 on 5 or 3 jacks, and front
panel jack retasking.
The AD1882A is available in a 48-lead Pb-free lead frame chip
scale package in both reels and trays. See Ordering Guide on
Page 17.
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Front Panel Headphone
Front Panel Microphone
Rear Panel Line-In
Rear Panel Line-Out/Headphone
Rear Panel Microphone
Rear Panel Surround
Rear Panel C/LFE
SPECIAL SOFTWARE FEATURES
Table 2. Typical Desktop Configuration with 5.1 on 3 Jacks
The AD1882A audio codec also supports the following addi-
tional software features:
• BlackHawk® and SoundMAX GUI contain all user audio
controls
• Voice input enhancements: Andrea Electronics best-in-
class noise reduction, beam forming, and echo cancellation
Port
Function
Front Panel Headphone
Front Panel Microphone
Rear Panel Line-In/Surround
Rear Panel Line-Out/Headphone
Rear Panel Microphone/C/LFE
Port A
Port B
Port C
Port D
Port E
• Output enhancements: Sensaura/Sonic Focus, spread-
ing/downmixing, MP3 refinement, adaptive dynamics,
compressor/limiter, speaker/graphic EQ, Voice Clarity/
Table 3. Typical Notebook Configuration
TM
X-Matrix , AGC, UI tuning tools
Port
Function
Headphone
Microphone
Internal Microphone
Internal Stereo Speakers
Docking Station Line/Microphone In
• DTS®, SRS®, EAX for gaming
Port A
Port B
Port C
Port D
Port E
ADDITIONAL INFORMATION
This data sheet provides a general overview of the AD1882A
SoundMAX codec’s architecture and functionality. Additional
information on the AD1882A is available in the AD1882A Pro-
grammers Reference Manual. Please contact your local Analog
Devices, Inc., sales representative for more information. For
information on SoundMAX codecs and software, see Analog
Devices website at http://www.analog.com/soundMAX.
Table 4. Typical Notebook Configuration with Digital
Microphone
Port
Port A
Port B
Function
Headphone
Microphone
Digital Microphone Internal Microphone
Port D
Port E
Internal Stereo Speakers
Docking Station Line/Microphone In
Rev. 0
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August 2008
AD1882A
SPECIFICATIONS
TEST CONDITIONS
Parameter
Test Condition
Temperature
25°C
Digital Supply
Analog Supply
MIC_BIAS_IN (via Low-Pass Filter)
Sample Rate fS
3.3 V
3.3 V
5.0 V
48 kHz
Input Signal (Frequency Sine Wave) 1008 Hz
Amplitude for THD + N
Analog Output Pass Band
DAC
–3.0 dB Full Scale
20 Hz to 20 kHz
10 kΩ Output Load: Line-Out Tests
32 Ω Output Load: Headphone Tests
0 dB Gain
ADC
PERFORMANCE
Parameter
Min
Typ
Max
Unit
Line-Out Drive (10 kΩ Loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in Ref to fS A-Weighted)
Signal-to-Noise Ratio
–85
95
95
dB
dB
dB
Headphone Drive (32 Ω Loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in Ref to fS A-Weighted)
Signal-to-Noise Ratio
–83
95
95
dB
dB
dB
Input Ports (Pin to ADC, Mic Boost = 0 dB)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in Ref to fS A-Weighted)
Signal-to-Noise Ratio
–81
90
90
dB
dB
dB
GENERAL SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
DIGITAL DECIMATION AND INTERPOLATION FILTERS—fS = 8 kHz to 96 kHz1
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Rejection
0
0.4 fS
0.005
Hz
dB
Hz
dB
1/fS
μs
0.6 fS
Group Delay
+20
0
–100
Group Delay Variation Over Pass Band
ANALOG-TO-DIGITAL CONVERTERS
Resolution
24
Bits
%
dB
mV
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)2
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error1
10
0.5
5
ADC Crosstalk1
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line Inputs to Other
–85
–100
dB
dB
–80
Rev. 0
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August 2008
AD1882A
Parameter
Min
Typ
Max
Unit
DIGITAL-TO-ANALOG CONVERTERS
Resolution
24
Bits
%
dB
dB
dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)1
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk
10
0.5
(Input L, Zero R, Read R_OUT; Input R, Zero L, Read L_OUT)1
DAC VOLUMES
Step Size (DAC0, DAC1, DAC2)
Output Gain/Attenuation Range
Mute Attenuation of 0 dB Fundamental1
ADC VOLUMES
Step Size (ADCSEL-0, ADCSEL-1)
PGA Gain/Attenuation Range
Mute Attenuation of 0 dB Fundamental1
ANALOG MIXER
–95
1.5
dB
dB
dB
–58.5
–58.5
0
–80
1.5
dB
dB
dB
+22.5
–80
Signal-to-Noise Ratio (SNR) Input to Output
Step Size: All Mixer Inputs
Input Gain/Attenuation Range: All Mixer Inputs
ANALOG LINE LEVEL OUTPUTS
Full-Scale Output Voltage
95
1.5
dB
dB
dB
–34.5
+12.0
1.0
2.83
V rms3
V p-p
Ω
kΩ
pF
Ports C, E, F, and G Mono Out
Output Impedance1
300
External Load Impedance1
10
Output Capacitance1
15
15
External Load Capacitance1
ANALOG HP DRIVE OUTPUTS
Full-Scale Output Voltage
1000
pF
1.0
2.83
V rms3
V p-p
Ω
Ω
pF
Ports A and D
Output Impedance1
0.5
External Load Impedance1
32
Output Capacitance1
External Load Capacitance1
ANALOG INPUTS
1000
pF
CD, Port D (When Used as Input)
1
2.83
1
V rms3
V p-p
V rms3
V p-p
V rms3
V p-p
V rms3
V p-p
V rms3
V p-p
kΩ
Microphone Boost Amplifier, Ports B, C, Boost = 0 dB
or E (When Used as Inputs)
2.83
0.316
0.894
0.1
0.283
0.032
0.089
20
Boost = 10 dB
Boost = 20 dB
Boost = 30 dB
Input Impedance1
Input Capacitance1
5
7.5
pF
DIGITAL GPIO PINS: GPIO_0, GPIO_1/EAPD
Input Signal High (VIH)
DVGPIO × 0.60
DVGPIO
V
Input Signal Low (VIL)
0
DVGPIO × 0.24
V
Input Leakage Current (Signal High), (IIH)
Input Leakage Current (Signal Low), (IIL)
Output Signal High (VOH)
Output Signal Low (VOL)
DM_CLK
150
50
nA
μA
V
IOUT = –500 μA
IOUT = +1500 μA
DVGPIO × 0.72
0
DVGPIO
DVGPIO × 0.10
V
Output Signal High (VOH)
Output Signal Low (VOL)
IOUT = –500 μA
IOUT = +1500 μA
DVGPIO × 0.72
0
DVGPIO
DVGPIO × 0.10
V
V
Rev. 0
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Page 5 of 20
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August 2008
AD1882A
Parameter
Min
Typ
Max
Unit
DM_DATA
Input Signal High (VIH)
Input Signal Low (VIL)
Input Leakage Current (Signal High) (IIH)
Input Leakage Current (Signal Low) (IIL)
S/PDIF_OUT
DVGPIO × 0.60
0
DVGPIO
DVGPIO × 0.24
V
V
nA
nA
–150
–50
Output Signal High (VOH)
Output Signal Low (VOL)
POWER SUPPLY
IOUT = –500 μA
IOUT = +1500 μA
DVGPIO × 0.72
0
DVGPIO
DVGPIO × 0.10
V
V
Analog (AVDD) 3.3 V 5%
Power Supply Range
Power Dissipation
3.13
2.97
2.97
2.97
2.97
3.30
116
35
3.46
3.63
3.63
3.63
3.63
V
mW
mA
Supply Current
Digital (DVDD) 3.3 V 10%
Power Supply Range
Power Dissipation
3.30
162
49
V
mW
mA
Supply Current
Digital I/O (DVIO) 3.3 V 10%
Power Supply Range
Power Dissipation
3.30
3.96
1.20
V
mW
mA
Supply Current
Digital I/O (DVIO) 1.5 V 5.5%
Power Supply Range
Power Dissipation
3.30
3.96
1.20
V
mW
mA
Supply Current
Digital GPIO (DVGPIO) 3.3 V 10%
Power Supply Range
Power Dissipation
3.30
3.63
1.10
80
V
mW
mA
dB
Supply Current
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1
1 Guaranteed but not tested.
2 Measurements reflect main ADC.
3 RMS values assume sine wave input.
HD AUDIO LINK SPECIFICATIONS
HD Audio signals comply with the High Definition Audio spec-
ifications. Please refer to these specifications at:
http://www.intel.com/standards/hdaudio/
POWER-DOWN STATES
Table 5. Power-Down States
Parameter
IDVDD Typ
IAVDD Typ
Unit
Function Node In D0, All Nodes Active
Function Node in D3
Codec in RESET
49
16
3
35
0.7
3
mA
mA
mA
Individual Block Power Savings
DAC Pair Powered Down Saves (Each)
ADC Pair Powered Down Saves (Each)
Mixer Power Control (and Associated Amps) Saves
MIC_BIAS Powered Down Saves1
6
5
0
0
6
4.4
3
mA
mA
mA
mA
1.0
1 Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits, setting them to the high-Z state.
Rev. 0
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August 2008
AD1882A
ABSOLUTE MAXIMUM RATINGS
ENVIRONMENTAL CONDITIONS
Stresses greater than those listed below may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Ambient Temperature Rating:
T
T
AMB = TCASE – (PD × θCA)
CASE = case temperature in °C
PD = power dissipation in W
θCA = thermal resistance (case-to-ambient)
θJA = thermal resistance (junction-to-ambient)
θJC = thermal resistance (junction-to-case)
Parameter
Rating
All measurements per EIA-JESD51 with 2S2P test board per
EIA-JESD51-7.
Digital (DVDD)
–0.30 V to +3.65 V
–0.30 V to +3.65 V
–0.30 V to +3.65 V
–0.30 V to +3.65 V
Digital I/O (DVIO)
Digital GPIO (DVGPIO
Analog (AVDD)
)
Package
θJA
θJC
θCA
32
Unit
°C/W
LFCSP_VQ
47
15
Input Current (Except Supply Pins) 10.0 mA
Analog Input Voltage (Signal Pins) –0.30 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins) –0.30 V to DVIO + 0.3 V
Ambient Temperature (Operating) 0°C to +70°C
Storage Temperature
–65°C to +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev. 0
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August 2008
AD1882A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
PORT-D_R
36
35
34
33
32
31
30
29
28
27
26
25
DV
CORE
1
2
3
PORT-D_L
GPIO_0
SENSE_B/SRC_A
DV
GPIO
MIC_BIAS_IN
RESERVED (NC)
MIC_BIAS-E
DV
IO
4
5
6
7
8
9
SDATA_OUT
BIT_CLK
AD1882AJCPZ
TOP VIEW
RESERVED (NC)
MIC_BIAS-C
DV
SS
(NotTo Scale)
SDATA_IN
MIC_BIAS-B
DV
DD
VREF_FLT
SYNC
RESET
10
11
12
AV
SS
DD
AV
PCBEEP
13 14
15
16
17
18
19
20
21
22
23 24
Figure 2. AD1882A 48-Lead Package and Pinout
Rev. 0
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August 2008
AD1882A
Table 6. AD1882A Pin Descriptions
Mnemonic
Pin No. Function
Description
DIGITAL INTERFACE
SDATA_OUT
I
Link Serial Data Output. AD1882A input stream. Clocked on both edges of the
BIT_CLK.
5
BIT_CLK
SDATA_IN
SYNC
I
Link Bit Clock. 24.000 MHz serial data clock.
Link Serial Data Input. AD1882A output stream clocked only on one edge of BIT_CLK.
Link Frame Sync.
6
8
10
11
I/O
I
I
RESET
Link Reset. AD1882A master hardware reset
DIGITAL I/O
GPIO_0
GPIO_1/EAPD
2
47
I/O
I/O
General-Purpose Input/Output. Supports S/PDIF output as primary function.
General-Purpose Input/Output Pin/EAPD Pin. Digital signal used to control external
circuitry. By default pin is in a high-Z state. When used as EAPD: high-Z = amp-on,
DVSS = amp off.
S/PDIF_OUT
DM_DATA
DM_CLK
48
45
46
O
I
O
S/PDIF output.
Digital Microphone Data Input. Support for 2 digital microphones
Digital Microphone Clock Output.
JACK SENSE AND EAPD
SENSE_A/SRC_B
SENSE_B/SRC_A
ANALOG I/O
PCBEEP
PORT-E_L
PORT-E_R
PORT-F_L
PORT-F_R
13
34
I/O
I/O
JACK SENSE A-D Input/Sense B Drive.
JACK SENSE E-H Input/Sense A Drive.
12
14
15
16
17
18
19
LI
Monaural Input from System for Analog PCBeep.
LI, MIC, LO, SWAP Auxiliary Input/Output Left Channel.
LI, MIC, LO, SWAP Auxiliary Input/Output Right Channel.
I/O
I/O
LI
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
CD Audio Left Channel.
CD Audio Analog Ground Reference (for Differential CD Input). Must be connected to
AGND via 0.1 μF capacitor if not in use as CD_GND.
CD Audio Right Channel.
Front Panel Stereo MIC/Line-In.
Front Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Headphone/Line-Out.
Rear Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
Front Panel Headphone/Line-Out.
CD_L
CD_GND
LI
CD_R
20
21
22
23
24
35
36
39
40
41
43
44
LI
PORT-B_L
PORT-B_R
PORT-C_L
PORT-C_R
PORT-D_L
PORT-D_R
PORT-A_L
MONO_OUT
PORT-A_R
PORT-G_L
PORT-G_R
FILTER/REFERENCE
MIC_BIAS-B
MIC_BIAS-C
MIC_BIAS-E
DVCORE
LI, MIC, HP, LO
LI, MIC, HP, LO
LI, MIC, LO
LI, MIC, LO
LI, HP, LO
LI, HP, LO
LI, MIC, HP, LO
LO
LI, MIC, HP, LO
LO, SWAP
LO, SWAP
Rear Panel C/LFE Output.
Rear Panel C/LFE Output.
28
29
31
1
O
O
O
O
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
Switchable Microphone Bias. For use with Port E (Pins 14, 15).
CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!
Filter connection for internal core voltage regulator.
This pin must be connected to filter caps: 10 μF, 1.0 μF, and 0.1 μF connected in
parallel between Pin 1 and DVSS (Pin 4).
VREF_FLT
27
O
Voltage Reference Filter. This pin must be connected to filter caps: 1.0 μF and 0.1μF
connected in parallel between Pin 27 and AVSS (Pins 26, 42).
The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving
headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically
used to support C/LFE or shared C/LFE function).
Rev. 0
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August 2008
AD1882A
Table 6. AD1882A Pin Descriptions (Continued)
Mnemonic
Pin No. Function
Description
POWER AND GROUND
DVIO 3.3 V 10%
or
4
I
Connect to the I/O Voltage Used for the HD Audio Controller Signals.
DVIO 1.5 V 5.5%
DVGPIO
DVSS
DVDD (3.3 V)
3
7
9
I
I
I
Connect to 3.3 V digital supply to power the GPIO and S/PDIF pins.
Digital Supply Return (Ground).
Digital Supply Voltage 3.3 V. This is regulated down to DVCORE on Pin 1 to supply the
internal digital core internal to the AD1882A.
AVDD (3.3 V)
MIC_BIAS_IN
AVSS
25, 38
I
I
I
CAUTION: DO NOT APPLY 5.0 V TO THESE PINS!
Analog Supply Voltage 3.3 V ONLY.
Note: AVDD supplies should be well regulated and filtered as supply noise degrades
audio performance.
Source Power for Microphone Bias Circuitry. Connect this pin to 5.0 V via a low-pass
filter. When connected this way, the AD1882A is capable of providing 3.9 V as a mic
bias to all of the MIC_BIAS pins. If 5 V is not available, connect this pin to 3.3 V (AVDD)
via a low-pass filter.
33
26, 42
Analog Supply Return (Ground). AVSS should be connected to DVSS using a
conductive trace under, or close to, the AD1882A.
The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving
headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically
used to support C/LFE or shared C/LFE function).
Rev. 0
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August 2008
AD1882A
DIGITAL MICROPHONE INTERFACE TIMING SPECIFICATIONS
The digital microphone interface can support one or two digital
microphones using two or three codec pins. Both uniplex (one
microphone per data pin) and multiplex (two microphones
sharing the same data pin) are supported. The timing for these
configurations are shown in Figure 3 and Figure 4. The interface
can generate a microphone clock at 1.5 MHz, 2.0 MHz, or
3.0 MHz to suit quality and power requirements.
Table 7. Microphone Timing Parameters
Parameter
Min
Typ
Max
Unit
Timing Requirements
t0
t0
t0
DM_CLK (1.5 MHz) Period
Duty Cycle
DM_CLK (2.0 MHz) Period
Duty Cycle
DM_CLK (3.0 MHz) Period
Duty Cycle
667
50/50
500
50/50
333
ns
%
ns
%
ns
%
50/50
t1
t2
t3
t4
DM_CLK Rise Time
DM_CLK Fall Time
Data Setup to DM_CLK Edge
Data Hold from DM_CLK Edge
5
5
ns
ns
ns
ns
100
5
t0
t2
t1
t3
t4
DM_CLK
DM_DATA
Figure 3. Uniplex Microphone Timing
t0
t1
t2
DM_CLK
t3
t4
t3
t4
DM_DATA
RIGHT DATA VALID
LEFT DATA VALID
LEFT DATA VALID
Figure 4. Multiplex Microphone Timing
Rev. 0
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August 2008
AD1882A
HD AUDIO PARAMETERS
The SSID value is set on codec power-up only. SSID is not reset
by link or soft reset in order to preserve modifications by BIOS
control.
Table 8. Root and Function Node Parameters
Sub Node
Count
04
Func. Group Audio F.G.
Vendor ID
00
Revision ID
Type
05
Caps
08
GPIO Caps
11
Node ID
Name
01
021
03
00
01
ROOT
FUNCTION
11D4882A
00100100
00010001
0002003B
00000001
00010C0C
40000002
1 Subject to change with silicon stepping.
Table 9. SubSystem ID 1
31:16
SSID
BFD2
15:8
SKU
00
7:0
Asm ID
00
Node ID
01
Name
FUNCTION
Value
BFD20000
1 The default SSID is overwritten by platform BIOS after power on. It is preserved across HD Audio link reset and verb reset.
Rev. 0
|
Page 12 of 20
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August 2008
AD1882A
WIDGET PARAMETERS
Table 10. Widget Parameters
Widget
Capabilities
09
PCM Size,
Rate
0A
Stream
Formats
0B
Pin
Capabilities
0C
Input Amp
Capabilities
0D
ConnList
Length
0E
Output Amp
Power States Capabilities
Node ID
0F
12
01
02
03
04
05
08
09
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1E
1F
20
21
22
23
24
26
27
29
2A
2C
2D
2F
37
39
3A
3C
0x0000 0480
0x0003 031D 0x000E 07E0 0x0000 0005
0x000E 07FF 0x0000 0001
0x80000000
0x0000 0009 0x0005 2727
0x8005 2727
0x0000 0009 0x0005 2727
0x0000 0009 0x0005 2727
0x0000 0009 0x0005 2727
0x0000 0009
0x0000 0001
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0001
0x0000 0001
0x0000 0008
0x0000 0008
0x0000 0000
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0000
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0000
0x0000 0002
0x0000 0000
0x0000 0001
0x0000 0002
0x0000 0000
0x0000 0008
0x0000 0001
0x0000 0002
0x0000 0008
0x0000 0001
0x0000 0002
0x0000 0002
0x0000 0002
0x0000 0002
0x0000 0002
0x0000 0001
0x0000 0003
0x0000 0002
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0405
0x0000 0405
0x0000 0405
0x0010 0501
0x0010 0501
0x0030 010D
0x0030 010D
0x0070 000C
0x0040 058D
0x0040 058D
0x0040 050C
0x0040 0081
0x0040 018D
0x0040 058D
0x0040 098D
0x0040 0081
0x0050 0500
0x0040 0000
0x0040 0301
0x0020 0103
0x0040 000B
0x0020 010B
0x0030 010D
0x0020 0103
0x00F0 0100
0x0040 098D
0x0020 0103
0x0020 0103
0x0020 0103
0x0020 0103
0x0020 0103
0x0020 0100
0x00F0 0100
0x0030 0101
0x0030 010D
0x0030 010D
0x0030 010D
0x000E 07FF 0x0000 0001
0x000E 07FF 0x0000 0001
0x000E 07FF 0x0000 0001
0x000E 07FF 0x0000 0001
0x000E 07FF 0x0000 0001
0x0000 0009
0x8005 3627
0x8005 3627
0x800B 0F0F
0x8000 0000
0x0000 373F
0x0001 003F
0x0001 0010
0x0000 3727
0x0000 3737
0x0001 0017
0x0000 3737
0x0000 0024
0x0000 0009 0x8000 0000
0x0000 0009 0x8005 1F1F
0x8000 0000
0x0000 0009 0x8000 0000
0x8000 0000
0x0000 0009
0x0000 0020
0x0000 0010
0x8000 0000
0x0017 0300
0x8005 1F17
0x0000 0020
0x8005 1F1F
0x8000 0000
0x8000 0000
0x0000 0017
0x8000 0000
0x8000 0000
0x8000 0000
0x8000 0000
0x8000 0000
0x0027 0300
0x0027 0300
0x0027 0300
Rev. 0
|
Page 13 of 20
|
August 2008
AD1882A
HD AUDIO WIDGETS
In the following table, node IDs that are not shown are reserved
for future use.
Table 11. HD Audio Widgets
Node ID Name
Type ID
Type
Description
00
01
02
03
04
05
08
09
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1E
1F
20
21
22
23
24
26
27
29
2A
2C
2D
2F
37
39
3A
3C
ROOT
FUNCTION
S/PDIF DAC
DAC_0
DAC_1
DAC_2
ADC_0
ADC_1
ADC Selector 0
ADC Selector 1
Digital Beep
Port A (Headphone)
Port D (Front L/R)
Mono Out
Port B (Front Mic)
Port C (Line In)
Port F (Surr Back)
Port E (Rear Mic)
CD In
x
x
Root
Function
Device Identification
Designates this Device as an Audio Codec
S/PDIF Digital Stream Output Interface
0
0
0
0
1
1
3
3
7
4
4
4
4
4
4
4
4
5
4
4
2
4
2
3
2
F
4
2
2
2
2
2
2
F
3
3
3
3
Audio Output
Audio Output
Audio Output
Audio Output
Audio Input
Audio Input
Audio Selector
Audio Selector
Beep Generator
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Power Widget
Pin Complex
Pin Complex
Audio Mixer
Pin Complex
Audio Mixer
Audio Selector
Audio Mixer
Vendor Defined
Pin Complex
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Vendor Defined
Audio Selector
Audio Selector
Audio Selector
Audio Selector
Headphone/Surround Side (7.1) Channel Digital/Audio Converters
Stereo Front Channel Digital/Audio Converters
Stereo C/LFE Channel Digital/Audio Converters
Stereo Record Channel 1 Audio/Digital Converters
Stereo Record Channel 2 Audio/Digital Converters
Selects and Amplifies/Attenuates the Input to ADC0
Selects and Amplifies/Attenuates the Input to ADC1
Internal Digital PCBeep Signal
Front Panel Headphone/Microphone Jack
Rear Panel Front/Headphone Jack
Monorail Output Pin (Internal Speakers or Telephony System)
Front Panel Microphone/Headphone Jack
Rear Panel Line-In Jack
Rear Panel Surround-Rear (5.1) Jack
Rear Panel Mic Jack
Analog CD Input
Powers Down the Analog Mixer and Associated Amps
External Analog PCBeep Signal Input
S/PDIF Output Pin
Selects Which Source Drives the Mono Out Signal
Digital Microphone Interface
Mixes Individually Gainable Analog Inputs
Attenuates the Mixer Output to Drive the Port Mixers
Mixes the Port A Selected DAC and Mixer Output Amps to Drive Port A
Powers Down the Internal and External VREF Circuitry
Rear Panel C/LFE Jack
Mixes DAC1 and Mixer Output Amps to Drive Port E
Mixes DAC1 and Mixer Output Amps to Drive Port G
Mixes DAC0 and Mixer Output Amps to Drive Port D
Mixes DAC2 and Mixer Output Amps to Drive Port F
Mixes the Port C Selected DAC and Mixer Output Amps to Drive Port C
Mixes the Stereo L/R Channels to Drive Mono Output
Powers Down the Internal MIC_BIAS_IN and all MIC_BIAS Pins
Selects the Port A DAC (0, 1)
Mixer Power Down
Analog PCBeep
S/PDIF Out
Mono Out Mixer
Digital Microphone
Analog Mixer
Mixer Output Atten
Port A Mixer
VREF Power Down
Port G (C/LFE)
Port E Mixer
Port G Mixer
Port D Mixer
Port F Mixer
Port C Mixer
Stereo Mix Down
BIAS Power Down
Port A Out Selector
Port B Boost
Port C Boost
Port E Boost
Microphone Boost Amp for Port B
Microphone Boost Amp for Port C
Microphone Boost Amp for Port E
Rev. 0
|
Page 14 of 20
|
August 2008
AD1882A
CONNECTION LIST
Table 12. Connection List
Connections
[4–7]
0
1
2
3
4
5
6
7
Node ID [0–3]
0x0000 001D
NID
1D
I
NID
I
NID
I
NID
I
NID
I
NID
I
NID
I
NID
02
03
04
05
08
09
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1E
1F
20
21
22
23
24
26
27
29
2A
2C
2D
2F
37
39
3A
3C
0x0000 000C
0x0000 000D
0x18BC 3911 0x2012 3B1F 0x11
0x18BC 3911 0x2012 3B1F 0x11
0x0C
0x0D
0x39
0x39
1
1
0x3C
0x3C
0x18
0x18
0x1F
0x1F
0x3B
0x3B
0x12
10x2
0x20
0x20
0x0000 0022
0x0000 0029
0x0000 002D
0x22
0x29
0x2D
0x0000 002C
0x0000 002A
0x0000 0026
0x2C
0x2A
0x26
0x0000 2120
0x20
0x21
0x0000 0002
0x0000 2104
0x02
0x04
0x21
0x3A
0x1211 3A39 0x1A18 3B3C 0x39
0x0000 0020
0x0000 2137
0x11
0x20
0x12
0x22
0x3C
0x24
0x3B
0x2E
0x18
0x30
0x1A
0x3C
0x20
0x37
0x21
0x18
0xA220 9811 0xBC30 AE24 0x11 1
1
1
1
0x0000 0027
0x0000 2105
0x0000 2105
0x0000 2104
0x0000 2103
0x0000 2103
0x0000 001E
0x0017 1514
0x0000 0403
0x0000 0014
0x0000 0015
0x0000 0017
0x27
0x05
0x05
0x04
0x03
0x03
0x1E
0x14
0x03
0x14
0x15
0x17
0x21
0x21
0x21
0x21
0x21
0x15
0x04
0x17
Rev. 0
|
Page 15 of 20
|
August 2008
AD1882A
DEFAULT CONFIGURATION BYTES
In Table 13, default configuration values are set on codec
power-up only. Default configuration values are not reset by
link or soft reset to preserve modifications by BIOS control.
Table 13. Default Configuration Bytes
31:30
29:28
Location
Connectivity Chassis Position Def. Device Conn Type Color
27:24
23:20
19:16
15:12
8
7:4
3:0
Misc.
JD
Name
Value
Def Assn Sequence
Port A (Headphone) 0x0221 401F Jack
Port D (Front L/R) 0x0101 4010 Jack
External Front
External Rear
Internal N/A
External Front
External Rear
External Rear
External Rear
Internal Special 3 CD
Internal N/A
External Rear
HP Out
Line Out
Speaker
Mic In
Line In
Line Out
Mic In
1/8” Jack
1/8” Jack
Other Analog Unknown 1
1/8” Jack
1/8” Jack
1/8” Jack
1/8” Jack
ATAPI
Green
Green
0
0
1
1
F
F
2
1
2
2
F
F
F
1
F
0
0
0
1
2
0
E
0
0
0
1
Mono Out
0x9017 01F0 Fixed
Port B (Front Mic) 0x02A1 90F0 Jack
Pink
Blue
Black
Pink
0
0
0
0
Port C (Line In)
Port F (Surr Back)
Port E (Rear Mic)
CD IN
Analog PCBeep
S/PDIF Out
0x0181 3021 Jack
0x0101 1012 Jack
0x01A1 9020 Jack
0x9933 012E Fixed
0x90F7 01F0 Fixed
0x0145 11F0 Jack
Unknown 1
Other
SPDIF Out Optical
Other Digital Unknown 1
1/8” Jack Orange
Other Analog Unknown 1
Black
1
Digital Microphone 0x97A6 09F0 Fixed
Port G (C/LFE) 0x0101 6011 Jack
Internal Special 1 Mic In
External Rear Line Out
0
Rev. 0
|
Page 16 of 20
|
August 2008
AD1882A
OUTLINE DIMENSIONS
Dimensions are shown in millimeters.
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
*
EXPOSED
PAD
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO VSS.
*
NOTE:
THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A VSS PCB LAND THAT IS THE SAME SIZE
AS THE EXPOSED PAD. THE VSS PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE VSS PLANE IN THE PCB
WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE.
Figure 5. 48-Lead, Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm x 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
0°C to 70°C
0°C to 70°C
Package Description
48-Lead LFCSP_VQ
48-Lead LFCSP_VQ, 13” Tape and Reel
Package Option
CP-48-1
CP-48-1
AD1882AJCPZ1
AD1882AJCPZ-RL1
1 Z = RoHS Compliant Part.
Rev. 0
|
Page 17 of 20
|
August 2008
AD1882A
Rev. 0
|
Page 18 of 20
|
August 2008
AD1882A
Rev. 0
|
Page 19 of 20
|
August 2008
AD1882A
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07549-0-8/08(0)
Rev. 0
|
Page 20 of 20
|
August 2008
相关型号:
AD1882JCPZ
IC SPECIALTY CONSUMER CIRCUIT, QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48, Consumer IC:Other
ADI
AD1882JCPZ-RL
IC SPECIALTY CONSUMER CIRCUIT, QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48, Consumer IC:Other
ADI
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