LT8697 [ADI]
5V 3A Output, 42V Input USB Charger with Cable Drop Compensation and Dataline Protection;
| 型号： | LT8697 |
| 厂家： | 
ADI |
| 描述： | 5V 3A Output, 42V Input USB Charger with Cable Drop Compensation and Dataline Protection |
| 文件： | 总40页 (文件大小：4381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT8698S/LT8698S-1
5V 3A Output, 42V Input USB Charger with
Cable Drop Compensation and Dataline Protection
FEATURES
DESCRIPTION
The LT®8698S is a compact, high efficiency, synchronous
monolithic step-down switching regulator designed to
n
Wide V Range Up to 42V
IN
n
Programmable Cable Drop Compensation Provides
Accurate 5V Regulation to Remote USB Sockets
High Speed USB 2.0 Compliant Dataline Switches
Selectable Charger Profiles Including Major
Vendors’ and USB BC 1.2 Profiles
power the 5V USB V
rail with up to 3A from an input
BUS
n
n
voltage as high as 42V. Programmable cable drop com-
pensation maintains accurate 5V V regulation even for
BUS
USB sockets separated from the LT8698S by a long cable
such as an automobile wiring harness. Silent Switcher
Technology and selectable spread-spectrum modulation
provide ultralow EMI/EMC.
Silent Switcher®2 Technology and Selectable Spread-
Spectrum Modulation Provide Ultralow EMI
Robust Dataline Protection
n
n
n
Tolerant of Short Condition Up to 20V
The LT8698S supports a wide variety of portable device
charger profiles including USB BC 1.2 CDP, DCP, and SDP
as well as common proprietary profiles. Integrated V
n
ESD Protected Up to IEC61000-4-2 8kV
Contact Discharge and 15kV Air Discharge
Available Status and Fault Output Pins
Programmable and Synchronizable Switching
Frequency 300kHz to 3MHz
Selectable Forced Continuous or Pulse-Skipping Modes
Small 4mm × 6mm × 0.94mm LQFN Package with
BUS
n
n
reset and V
regulator disable functions support USB
BUS
OTG functionality.
n
n
The LT8698S’s robust high speed USB 2.0 data line
switches protect the upstream USB host µController
from short-circuit conditions up to 20V and ESD events
up to IEC61000-4-2 8kV contact discharge and 15kV air
0.75mm Spacing from V to GND Pins
AEC-Q100 Qualified for Automotive Applications
IN
n
discharge levels. Further V
monitor and fault protec-
BUS
tion features eliminate the need for a USB power switch.
The LT8698S includes two parallel 10nF capacitors from
IN
APPLICATIONS
n
Automotive USB
V
to PGND for improved EMI/EMC performance. The
n
Industrial USB
LT8698S-1 does not include these capacitors.
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Automotive Charger with High Speed Dataline Protection and Cable Drop Compensation
USB BC1.2 CDP Session
V
IN
6V TO 42V
V
IN
EN/UV
SW
INTV
CC
LT8698S
ꢀ
BUS
ꢀ.ꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢃ
ꢀAꢁꢂꢃꢄ
FLT
STATUS
OUT/ISP
BUS/ISN
USB5V
HIGH SPEED
USB 2.0 HOST
µCONTROLLER
3 METER
USB
USB CABLE
SOCKET
SEL1-3
0.1Ω
ꢁ
ꢂ
V
D
BUS
ꢀ ꢂ ꢀ
+
+
–
+
LD
D
D
+
ꢀꢁꢂꢃꢄꢁ
HD
–
–
–
D
LD
HD
0.1Ω
CLAMP
GND PGND
RCBL
RT
ꢀꢁAꢁꢂꢀ
ꢀꢁꢂꢃꢄꢁ
GND
ꢀꢁꢂꢀꢃ ꢄAꢅꢆꢇ
IMON
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
8698S TA01
Rev. A
1
Document Feedback
For more information www.analog.com
LT8698S/LT8698S-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ꢊꢋꢌ ꢍꢎꢏꢐ
V , EN/UV, OUT/ISP, BUS/ISN, USB5V ....................42V
IN
+
–
HD , HD , CLAMP.....................................................20V
SYNC/MODE, FLT, STATUS,
SEL1, SEL2, SEL3, LD , LD .......................................6V
RCBL, RT ....................................................................2V
Operating Junction Temperature Range (Note 2)
ꢁꢄ
ꢁꢂ
ꢁꢃ ꢂꢄ
ꢂꢅ ꢆꢂ
ꢂꢈ
ꢗꢔꢙ
ꢗꢔꢙ
ꢗꢔꢙ
+
–
ꢣꢤꢊ
ꢀ
ꢂ
ꢂꢇ
ꢤꢐ
ꢎꢔꢊꢍ
ꢕꢕ
ꢁꢁ
ꢗꢔꢙ
ꢁꢆ
ꢗꢔꢙ
ꢂꢆ
ꢤꢐ
ꢏꢔꢡꢨꢍ
LT8698SE .......................................... –40°C to 125°C
LT8698SJ .......................................... –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Peak Package Body Reflow Temperature..............260°C
ꢁ
ꢂꢁ
ꢗꢔꢙ
FLT
ꢤꢊAꢊꢨꢤ
ꢤꢏꢑꢀ
ꢆ
ꢂꢂ
ꢋꢨꢊꢡꢎꢤꢌ
ꢣꢨꢤꢡꢎꢤꢔ
ꢨꢤꢣꢇꢍ
Rꢕꢣꢑ
ꢕꢑAꢥꢌ
ꢗꢔꢙ
ꢇ
ꢁꢇ
ꢗꢔꢙ
ꢁꢈ
ꢗꢔꢙ
ꢂꢀ
ꢈ
ꢂꢃ
ꢤꢏꢑꢂ
ꢅ
ꢀꢄ
ꢤꢏꢑꢁ
ꢉ
ꢁꢅ
ꢗꢔꢙ
ꢁꢉ
ꢗꢔꢙ
ꢀꢉ
Rꢊ
ꢄ
ꢀꢅ
ꢤꢧꢔꢕꢡꢥꢋꢙꢏ
ꢗꢔꢙ
ꢀꢃ
ꢆꢃ
ꢗꢔꢙ
ꢆꢀ
ꢀꢀ ꢀꢂ ꢀꢁ ꢀꢆ ꢀꢇ ꢀꢈ
ꢑꢒꢓꢔ ꢌAꢕꢖAꢗꢏ
ꢁꢂꢘꢑꢏAꢙ ꢚꢈꢛꢛ ꢜ ꢆꢛꢛ ꢜ ꢃ.ꢄꢆꢛꢛꢝ
θ
ꢟ ꢂꢂꢠꢕꢡꢐꢢ ꢚꢣAꢤꢏꢙ ꢋꢔ ꢙꢏꢥꢋꢣꢋARꢙꢝ
ꢞA
ꢗꢔꢙ Aꢔꢙ ꢌꢗꢔꢙ ꢌꢎꢔꢤ ꢀꢢ ꢀꢀꢢ ꢀꢆꢢ ꢀꢅꢢ ꢂꢁꢢ ꢂꢅꢢ ꢁꢂ Aꢔꢙ ꢁꢁꢘꢆꢂ
ARꢏ ꢤꢦꢋRꢊꢏꢙ ꢎꢔꢊꢏRꢔAꢑꢑꢧ Aꢔꢙ ꢥꢨꢤꢊ ꢣꢏ ꢤꢋꢑꢙꢏRꢏꢙ ꢊꢋ ꢌꢕꢣ ꢗꢔꢙ
ORDER INFORMATION
PART MARKING
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)
PART NUMBER
PAD OR BALL FINISH
DEVICE
FINISH CODE
LT8698SEV#PBF
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 150°C
8698V
LT8698SJV#PBF
LQFN (Laminate Package
with QFN Footprint)
Au (RoHS)
e4
3
LT8698SEV-1#PBF
LT8698SJV-1#PBF
AUTOMOTIVE PRODUCTS**
LT8698SEV#WPBF
LT8698SJV#WPBF
LT8698SEV-1#WPBF
LT8698SJV-1#WPBF
8698S1
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 150°C
8698V
LQFN (Laminate Package
with QFN Footprint)
Au (RoHS)
e4
3
8698S1
• Device temperature grade is indicated by a label on the shipping container. • Recommended PCB Assembly and Manufacturing Procedures.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Package and Tray Drawings
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. A
2
For more information www.analog.com
LT8698S/LT8698S-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
= 0.25V, V = 12V
MIN
TYP
MAX
UNITS
V
IN
V
IN
Shutdown Current
V
EN/UV
0.1
1
µA
IN
l
l
Current in Regulation
I
I
= 0A, V
= 0A, V
= 0V, V = 12V (Note 4)
= Open, V = 12V (Note 4)
2.5
23
4
36
mA
mA
LOAD
LOAD
SYNC/MODE
SYNC/MODE
IN
IN
l
l
l
V
CHG
Regulator Output Voltage at
BUS/ISN
I
I
I
= 0A, R = 3.57k (Note 4)
CBL
4.925
5.52
5.93
5.00
5.61
6.05
5.063
5.680
6.13
V
V
V
LOAD
LOAD
LOAD
= 2.4A, R
= 3.57k (Note 4)
CBL
= 0A, V
= 0V (Note 4)
USB5V
l
l
l
USB5V Voltage
V
= 5V to 42V
4.915
4.99
7
5.053
10
V
%
IN
Upper FLT Threshold Offset
Lower FLT Threshold Offset
FLT Threshold Hysteresis
Regulator Output Current Limit
Latch-On Time in Current Limit
Latch-Off Time in Current Limit
Percentage of V
Percentage of V
Percentage of V
, V
Falling
Rising
4
4
USB5V USB5V
, V
7
10
%
USB5V USB5V
3
%
USB5V
I
V
V
V
= 4.5V, R
= 0.2V
= 10mΩ
2.55
3.4
48
2.65
4.2
59
100
2.75
5
A
CDP
BUS/ISN
BUS/ISN
BUS/ISN
BUS/ISN
SEN
SEN
ms
ms
mA
T
= 0.2V
70
SHTDWN_REC
Regulator Output Current STATUS
Threshold
I
Falling, R
= 10mΩ
20
180
Regulator Output Current STATUS
Threshold Hysteresis
R
SEN
= 10mΩ
20
mA
Regulator Output Sink Current
V
= 6.3V (Note 4)
–2.9
–2.3
–1.7
A
BUS/ISN
l
l
R
CBL
Monitor Voltage
I
I
= 0A, R = 10mΩ
SEN
0
1.05
2
1.10
50
1.15
mV
V
LOAD
LOAD
= 2.4A, R
= 10mΩ
SEN
l
l
l
Oscillator Frequency
R = 9.09k
1.8
255
2.7
2
300
3
2.2
345
3.3
MHz
kHz
MHz
T
R = 66.5k
T
R = 5.76k
T
l
l
l
l
l
SYNC/MODE Low Threshold for
Pulse-Skip Operation
V
Rising
0.3
0.7
1.1
V
SYNC/MODE
SYNC/MODE Input High for Synced
Operation
1.5
V
SYNC/MODE Input Low for Synced
Operation
0.4
3.7
6.5
7
V
SYNC/MODE High Threshold for
Spread Spectrum Operation
V
V
Rising
= 2V
2.7
2
3.2
V
SYNC/MODE
SYNC/MODE Pull Up Current for
Forced Continuous Operation
4.25
µA
SYNC/MODE
Top Switch Max Current Limit
Top Switch On Resistance
Bottom Switch On Resistance
SW Leakage Current
5
6
75
A
mΩ
mΩ
µA
I
I
= 1A
= 1A
SW
75
SW
–1
0
1
l
EN/UV Threshold
V
V
Falling
1.17
1.31
150
1.45
V
EN/UV
EN/UV Threshold Hysteresis
EN/UV Current
mV
nA
= 2V
–100
100
EN/UV
Rev. A
3
For more information www.analog.com
LT8698S/LT8698S-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
300
1
UNITS
Ω
l
l
l
l
l
FLT Pull Down Resistance
FLT Leakage
V
V
V
V
V
= 0.1V
= 4V
150
FLT
FLT
µA
Ω
STATUS Pull Down Resistance
STATUS Leakage
= 0.1V
= 4V
150
300
1
STATUS
STATUS
µA
V
SEL1-3 Low Threshold
SEL1-3 Low Threshold Hysteresis
SEL1-3 High Threshold
SEL1-3 High Threshold Hysteresis
SEL1-3 Float Voltage
Rising
0.48
1.31
0.9
0.58
35
0.68
SEL
mV
V
V
SEL
Falling
1.41
35
1.51
1.1
mV
V
1.0
SEL1-3 Input Current
V
SEL
V
SEL
= 4V
= 0V
45
–15
µA
µA
SEL1-3 De-bounce Time
Soft Start Time
1.25
0.7
1.5
1.1
1.75
1.6
ms
ms
DATALINE SWITCHES
l
V , V
OL OH
Signal Range
0
3.6
V
+
–
+
+
–
–
+
–
–
Off HD , HD Current
V
V
, V
HD
, V
HD
= 3.6V, V , V
= 0V
= 0V
–1
0
0.75
1
1
µA
mA
HD
HD
LD
LD
+
= 20V, V , V
LD
LD
+
–
+
+
–
–
+
–
Off LD , LD Current
V
V
, V
, V
= 0V, V , V
= 3.6V
–1
–1
0
0
1
1
µA
µA
HD
HD
HD
HD
LD
LD
+
–
= 20V, V , V
= 0V
LD
LD
+
+
+
–
–
–
On Leakage Current
On Resistance
V
HD
V
HD
V
HD
, V
, V
, V
= 3.6V, 0V
–100
0
3
100
nA
Ω
HD
HD
HD
+
–
= 0V, 3.6V, I , I
= 20mA
LD LD
On Capacitance to Ground
= 200mV , 400mV , 480MHz (Note 5)
6.1
pF
DC
P-P
V
DISCHARGE
BUS
BUS/ISN Discharge Current Sink
V
V
= 5V
6
9
12
mA
V
BUS/ISN
V
BUS/ISN Discharge Status
Threshold
Falling
0.5
0.7
BUS_LKG
BUS/ISN
BUS/ISN Discharge Status
Threshold Hysteresis
0.35
V
T
T
Maximum BUS/ISN Discharge Time
Minimum BUS/ISN Low Time
STATUS Oscillation Period
V
V
= 1V
= 1V
400
120
9
500
ms
ms
ms
VLD_VLKG
BUS/ISN
BUS/ISN
100
7.5
VBUS_REAPP
10.5
V
BUS
OFF
I
Regulator Output Leakage Current
Regulator Output Resistance
V
V
= 0V
= 5V
–70
10
–0.1
15
µA
µA
VBUS_LKG_
SRC
BUS/ISN
BUS/ISN
80
R
V
= 0.75V
350
kΩ
OTG_VBUS
BUS/ISN
Rev. A
4
For more information www.analog.com
LT8698S/LT8698S-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
0.25
2.0
TYP
MAX
UNITS
USB BCS 1.2 CHARGING DOWNSTREAM PORT PROFILE
+
+
V
HD Data Detect Voltage
V
Rising
HD
0.32
45
0.40
V
mV
V
DAT_REF
+
HD Data Detect Hysteresis
+
–
V
V
V
V
HD , HD Logic High
IH
+
–
HD , HD Logic Low
0.8
2.0
0.7
175
0.15
20
V
IL
+
–
HD , HD Logic Threshold
0.8
0.5
25
1.4
0.6
V
LGC
–
–
+
HD Voltage Source
I
= –100µA, V = 0.6V
HD
V
DM_SRC
DP_SINK
HD
+
+
I
HD Current Source
V
= 0.6V
= 25µA
100
0.06
0.5
µA
V
HD
+
+
V
HD Data Sink Voltage
I
HD
DAT_SINK
–
+
T
T
HD Voltage Source Enable Time
V
V
= 0.6V
= 2V
ms
ms
VDMSRC_EN
HD
HD
+
+
HD Current Source Connect Disable
0.75
10
CON_IDPSNK_
Time
DIS
+
+
T
Minimum Accepted HD Voltage
V
= 0.6V
32
40
ms
VDPSRC_ON
VDMSRC_DIS
HD
Source On Time
–
+
+
T
HD Voltage Source Disable Time
V
V
= 0V
= 0V
0.5
32
20
40
ms
ms
HD
HD
+
Minimum Accepted HD Source
Voltage Off Time
+
–
T
PWD
Maximum Accepted USB Connect
Time
V
= 0V
1
1.15
s
SVLD_CON_
HD , HD
USB BCS 1.2 DEDICATED CHARGING PORT PROFILE
+
–
R
R
Dataline Short Resistance
V
= 0.6V, I = –2.5mA
HD
85
200
Ω
DCP_DAT
DAT_LKG
HD
Dataline Short Pull Down Resistance
300
500
kΩ
USB BCS 1.2 STANDARD DOWNSTREAM PORT PROFILE
R
R
,
Dataline Termination Resistor
14.25
20
24.8
kΩ
DP_DWN
DM_DWN
2.4A CHARGER PROFILE
+
HD Voltage
V
V
= 5V
= 5V
2.60
2.60
2.68
23
2.76
2.76
V
kΩ
V
BUS/ISN
BUS/ISN
+
HD Output Resistance
–
HD Voltage
2.68
23
–
HD Output Resistance
kΩ
2.1A CHARGER PROFILE
+
HD Voltage
V
= 5V
= 5V
2.60
1.94
2.68
23
2.76
2.06
V
kΩ
V
BUS/ISN
BUS/ISN
+
HD Output Resistance
–
HD Voltage
V
2.00
30
–
HD Output Resistance
kΩ
Rev. A
5
For more information www.analog.com
LT8698S/LT8698S-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
1.94
2.60
TYP
MAX
2.06
2.76
UNITS
1A CHARGER PROFILE
+
HD Voltage
V
V
= 5V
= 5V
2.00
30
V
kΩ
V
BUS/ISN
BUS/ISN
+
HD Output Resistance
–
HD Voltage
2.68
23
–
HD Output Resistance
kΩ
2A CHARGER PROFILE
+
–
HD , HD Voltage
V
= 5V
1.2
1.25
7.5
1.35
V
BUS/ISN
+
–
HD , HD Output Resistance
kΩ
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
temperature (T in °C) is calculated from the ambient temperature (T in
°C) and power dissipation (PD in Watts) according to the formula:
J
A
T = T + (P • θ )
JA
J
A
D
where θ (in °C/W) is the package thermal impedance.
JA
Note 2: The LT8698SE and LT8698SE-1 are guaranteed to meet
performance specifications from 0˚C to 125°C junction temperature.
Specifications over the −40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LT8698SJ and LT8698SJ-1 are
guaranteed over the full −40°C to 150°C operating temperature range.
High junction temperatures degrade operating lifetime. Operating lifetime
is de-rated at junction temperatures greater than 125°C. The junction
Note 3: This IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
will reduce lifetime.
Note 4: DUT configured in closed loop test circuit similar to page 36 CDP
charger application circuit.
Note 5: Parameter not tested in production.
Note 6: θ values are determined by simulation per JESD51 conditions,
except θ value is determined by simulation with demo board. See
JA
Applications Information section for more information on PCB layout
considerations and example thermal data.
Rev. A
6
For more information www.analog.com
LT8698S/LT8698S-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V unless otherwise noted.
VBUS vs Temperature
VBUS vs VIN
VBUS vs IBUS
ꢀ.ꢁ
ꢀ.ꢁꢁ
ꢀ.ꢁꢀ
ꢀ.ꢀꢁ
ꢀ.ꢁꢀ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢁꢀ
ꢀ.ꢁꢁꢂ
ꢀ.ꢁꢂꢀ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢀꢀ
ꢀ.ꢁꢀꢂ
ꢀ.ꢁꢂꢀ
ꢀ.ꢁꢂꢃ
ꢀ
ꢀ ꢁ.ꢂA
= 10mΩ
ꢀ ꢁ.ꢂꢃ
ꢀ ꢁꢂ
ꢀꢁAꢂ
ꢀ
ꢀ ꢁ.ꢂA
R
R
R
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ
ꢀ ꢁA
ꢀꢁꢂ
ꢀ
ꢀ ꢁA
ꢀꢁꢂ
R
= 10mΩ
ꢀꢁꢂ
R
R
= 10mΩ
ꢀꢁꢂ
ꢀ ꢁ.ꢂꢃ
ꢀꢁꢂ
R
R
ꢀ ꢁ.ꢂꢃ
ꢀꢁꢂ
ꢀ ꢁꢂ
ꢀꢁꢀ
R
ꢀ ꢁꢂ
ꢀꢁꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀAꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
Sense Voltage (VISP – VISN
)
Output Current Load Line
vs Temperature
RCBL Voltage vs Load
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁꢀ
ꢀ.ꢀꢁ
ꢀ.ꢁꢀ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢁ
ꢀꢁ.ꢂ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ
ꢀ
ꢀ
ꢀ ꢁ.ꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ ꢁꢂ
R
R
R
R
ꢀꢁꢂꢃ R =10mΩ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ.ꢂꢂꢃꢄ R =10mΩ
ꢀꢁꢂ
R
= 10mΩ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ R =10mΩ
ꢀꢁꢂ
R
ꢀ ꢁ.ꢂꢃ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁ.ꢂꢂꢃꢄ R =8mΩ
ꢀꢁꢂ
R
ꢀ ꢁꢂ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀAꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢄAꢅ
ꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢁ
Efficiency at TA = 25°C
Efficiency at TA = 90°C
No Load Input Current vs VIN
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀ.ꢁꢂ
ꢀ.ꢀꢁ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢀ
ꢀ.ꢁꢂ
ꢀ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀ.ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁ ꢂAꢀꢃꢄꢅꢄꢆꢇꢇꢇꢈ R = 8mΩ
ꢀ ꢁ ꢂAꢀꢃꢄꢅꢄꢆꢇꢇꢇꢈ R = 8mΩ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢉ ꢊꢋꢆAꢌ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢉ ꢊꢂꢇ
ꢀ.ꢀꢁ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢀ
ꢀ.ꢁꢂ
ꢀ
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ
ꢀꢁꢂꢃR ꢄꢁꢅꢅ
ꢀꢁꢂꢃR ꢄꢁꢅꢅ
ꢀ
ꢀ
ꢀ
ꢀ
ꢃ ꢄꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢃ ꢄꢀ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢃ ꢄꢅꢀ
ꢃ ꢄꢅꢀ
ꢃ ꢄꢅꢀ
ꢃ ꢄꢅꢀ
ꢃ ꢄꢅꢀ
ꢃ ꢄꢅꢀ
ꢀ
ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
ꢀꢁAꢂ ꢃꢄRRꢅꢆꢇ ꢈAꢉ
ꢀꢁAꢂ ꢃꢄRRꢅꢆꢇ ꢈAꢉ
ꢀꢁꢂꢀꢃ ꢄꢅꢀ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢀꢃ ꢄꢅꢂ
Rev. A
7
For more information www.analog.com
LT8698S/LT8698S-1
TA = 25°C, VIN = 12V unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
No Load Input Current
Bottom FET Positive Current Limit
vs Temperature
Top FET Current Limit
vs Temperature
ꢀ.ꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁꢂ ꢃꢄ
ꢀꢁꢂ ꢃꢄ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ ꢁ ꢂ.ꢂꢃꢄ
ꢀ ꢁ.ꢂꢁꢃ
R
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢉ ꢊꢋꢆAꢌ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢉ ꢆꢊꢈꢂ
ꢀ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢅ
Top FET Negative Current Limit
Top FET/ Bottom FET Drop
Top FET Minimum On-Time
ꢀꢁ.ꢂꢂ
ꢀꢁ.ꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁ.ꢂꢂ
ꢀꢁ.ꢁꢂ
ꢀꢁ.ꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁ.ꢂꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢃ ꢄA
ꢃ ꢄA
ꢃ ꢄA
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢀ
ꢄ ꢅ.ꢆꢇA
ꢄ ꢅA
ꢁꢂꢃ
ꢀꢁꢂ ꢃꢄ
ꢀꢁꢂ ꢃꢄ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
Minimum Off-Time
vs Temperature
Switching Frequency
vs Temperature
V
IN - VBUS Dropout
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ ꢁ ꢂAꢀꢃꢄꢅꢄꢆꢇꢇꢇꢈ R
= 10mΩ
ꢀꢁꢂ
R
ꢀ
ꢀ ꢁ.ꢂꢁꢃ
ꢀ
ꢀ
ꢀ
ꢄ ꢅ.ꢆA
ꢄ ꢅA
ꢄ ꢅA
ꢁꢂꢃ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢀ ꢁ.ꢂA
ꢀ ꢁA
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢀꢃ ꢄꢅꢁ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢀ
Rev. A
8
For more information www.analog.com
LT8698S/LT8698S-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V unless otherwise noted.
Switching Frequency
vs Load Current
Switch Rising Edge
Soft-Start vs Time
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢀ
ꢀ.ꢁꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀꢁ
A
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀꢁꢂ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁA
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢉ ꢊꢋꢆAꢌ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢉ ꢊꢆꢋ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁRRꢂꢃꢄ ꢅAꢆ
ꢀꢁꢂ
ꢀꢁꢂꢀꢃ ꢄꢅꢂ
Minimum VIN for Full Frequency
Regulation @ 2MHz with 400mΩ
Cable Drop Compensation
Load Transient Response Through
Cable
Start-Up/Dropout
ꢀ.ꢁꢁ
ꢀ.ꢁꢀ
ꢀ.ꢀꢁ
ꢀ.ꢁꢀ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁ
ꢀRꢁꢂꢃ ꢄAꢅꢆ ꢇꢈRꢇꢉꢈꢃ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ
ꢀ ꢁ
ꢀ ꢁ.ꢂA
ꢀ
ꢄ ꢅA
ꢀꢁ
ꢀꢁꢂ
ꢁꢂꢃ
ꢀAꢁꢂꢃ ꢄ ꢅꢆ Aꢇꢈꢉꢊ ꢀ.ꢁ
400mΩ CABLE COMP
ꢀ
ꢁꢂ
ꢀ
ꢄ ꢅꢆꢇ
ꢁꢂAꢃ
ꢀ ꢁ ꢂAꢀꢃꢄꢅꢄꢆꢇꢇꢇ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ
R
ꢀꢁꢂ
= 10mΩ
ꢀ
ꢀ
ꢀꢁ
ꢀ ꢁ
ꢀꢁꢂ
ꢀ ꢁA
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ ꢁ ꢀ ꢁ.ꢂA
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢁꢂAꢃ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ ꢁ
ꢀꢁꢂ
ꢀ ꢁA
ꢀꢁꢂ
ꢀꢁꢂAꢃꢄꢅ
ꢀꢁꢂꢀꢃ ꢄꢅꢅ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
Load Transient Response Through
Cable
USB5V (Feedback) Shorted to
Ground Transient
Output Current Limit Transient
ꢀ.ꢁꢁ
ꢀ.ꢁꢀ
ꢀ.ꢀꢁ
ꢀ.ꢁꢀ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁ
ꢀ
ꢁꢂꢃ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ
ꢀ
ꢁꢂꢃ
R
SEN
R
CDC
= 10mΩ
= 0Ω
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃꢄꢁ
ꢁꢂAꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂRꢃꢀAꢄ ꢀꢁꢂRꢃꢀAꢄ
Aꢀꢀꢁꢂꢃꢄ RꢀꢁꢀAꢂꢀꢃ
ꢀRꢁꢂꢃ ꢄAꢅꢆ ꢇꢈRꢇꢉꢈꢃ
ꢄ ꢅA
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀRꢁꢂꢃ ꢄAꢅꢆ ꢇꢈRꢇꢉꢈꢃ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢁ
ꢀAꢁꢂꢃꢄ
ꢀꢁꢂAꢃꢄꢅ
ꢀAꢁꢂꢃ ꢄ ꢅꢆ Aꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢄ ꢅꢆꢇ
ꢁꢂAꢃ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
Rev. A
9
For more information www.analog.com
LT8698S/LT8698S-1
TA = 25°C, VIN = 12V unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
STATUS IBUS Threshold
FLT Deglitching
Latch-Off and Auto-Retry
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄꢅ Aꢆꢆꢁꢂꢇꢈ
ꢀꢁ ꢂꢃꢄꢅꢆ ꢇꢈꢉ
ꢀꢁꢂ
ꢀꢁꢂ
FLT
FLT
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁꢂ ꢄ ꢅ
ꢀꢁꢂ ꢄ ꢅ
ꢀꢁꢂ ꢄ ꢅ
ꢀꢁꢂ ꢄ ꢅ
Rꢀꢁꢀꢂꢃ
Rꢀꢁꢀꢂꢃ
ꢀAꢁꢁꢂꢃꢄ
ꢀAꢁꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢁ
ꢀꢀꢁ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂRꢃꢀAꢄ
ꢀꢁꢂRꢃꢀAꢄ
Aꢀꢀꢁꢂꢃꢄ
Rꢀꢁꢂꢃꢀꢄ
ꢀAꢁꢂꢃ
ꢀAꢁꢂꢃꢄꢅꢆꢆ
ꢀ
ꢁꢂꢃ
ꢀAꢁꢂꢃꢄ
ꢀꢁꢂꢀꢃ ꢄꢅꢀ
ꢀꢁꢂꢀꢃ ꢄꢅꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
STATUS VBUS Threshold
SEL1-3 High and Low Threshold
SEL1-3 Deglitching
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀAꢁꢁꢂꢃꢄ
ꢀ
RISING
FALLING
FLOAT
RISING
FALLING
ꢁꢂꢃ
ꢀAꢁꢂꢃꢄ
A
ꢀꢁꢂꢀꢃ ꢄꢅꢅ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
–50 –25
0
25 50 75 100 125 150
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
TEMPERATURE (˚C)
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
8698S G32
Dataline Switch Capacitance to
Ground, Switch On
INTVCC Voltage vs Temperature
Dataline Switch RDS(ON)
ꢀ.ꢁꢂꢂ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢁ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢁꢁ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢂ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
ꢀ
ꢀ
ꢀ
ꢀ
+
–
+
–
D
AT 4V
D
D
D
AT 4V
AT –0.1V
AT –0.1V
ꢀꢁꢂꢀ ꢂꢃꢄꢅAꢆ ꢇꢈꢈꢉꢊ ꢊ Aꢀ ꢇꢍꢈꢎꢏꢐ
ꢋꢌꢋ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
–50 –25
0
25 50 75 100 125 150
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢂꢁꢃ ꢂꢁꢄꢅ ꢆꢁꢇꢈAꢉꢅ ꢊꢆꢋ
TEMPERATURE (˚C)
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢁ
8698S G35
Rev. A
10
For more information www.analog.com
LT8698S/LT8698S-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V unless otherwise noted.
Radiated EMI Performance, (CISPR25 Radiated Emission with Peak Detector and Class 5 Peak Limit)
DC2688A Demo Board with EMI Filter Installed, VIN = 14V, IVBUS = 2.5A, fSW = 2MHz,
L = XFL4020-222, CVIN2 and CVIN3 Populated, LT8698S Only
Horizontal Polarization
Vertical Polarization
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁAꢂꢂ ꢃ ꢄꢅAꢆ ꢁꢇꢈꢇꢉ
ꢀꢁRꢂAꢃ ꢀꢁꢂꢄꢅRꢆꢇ ꢇꢈꢃꢂ
ꢀꢁꢂꢃꢄ ꢀRꢃꢅꢆꢃꢇꢈꢉ ꢊꢋꢄꢃ
ꢀꢁAꢂꢂ ꢃ ꢄꢅAꢆ ꢁꢇꢈꢇꢉ
ꢀꢁRꢂAꢃ ꢀꢁꢂꢄꢅRꢆꢇ ꢇꢈꢃꢂ
ꢀꢁꢂꢃꢄ ꢀRꢃꢅꢆꢃꢇꢈꢉ ꢊꢋꢄꢃ
ꢀ
ꢀ
ꢀ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢁꢁ
ꢀ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢁꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢀ
Conducted EMI Performance
DC2688A Demo Board with EM Filter Installed, VIN = 14V, IVBUS = 2.5A, fSW = 2MHz,
L = XFL4020-222, CVIN2 and CVIN3 Populated, LT8698S Only
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁRꢂAꢃ ꢀꢁꢂꢄꢅRꢆꢇ ꢇꢈꢃꢂ
ꢀꢁꢂꢃꢄ ꢀRꢃꢅꢆꢃꢇꢈꢉ ꢊꢋꢄꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢀꢃ ꢄꢅꢂ
High Speed USB 2.0 Eye Diagram
DC2688A Demo Board, Measured at Test Plane 2 with Template 1 Waveform Requirements
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
Rev. A
11
For more information www.analog.com
LT8698S/LT8698S-1
PIN FUNCTIONS
GND (Pins 1, 11, 14, 17, 23): The GND pins are the
return side of the internal control circuits and must be
tied to ground. All GND and PGND pins are internally
shorted together.
RT (Pin 9): RT is the switching frequency programming
pin. Tie a resistor from RT to ground to select the switch-
ing frequency. See the Applications Information section
for additional information.
INTV (Pin 2): INTV is the bypass pin of the internal 4V
SYNC/MODE (Pin 10): SYNC/MODE is the clock synchro-
nization and mode selection input pin. Ground SYNC/
MODE for pulse-skipping mode. Tie to a clock source
for synchronization to an external frequency and forced
continuous mode. Float for forced continuous mode with
RT programing the switching frequency. Tie to INTVCC for
forced continuous mode with spread-spectrum modula-
tion of the switching frequency for improved EMI/EMC
performance.
CC
linear regulator. This CpCin powers the internal power switch
gate drivers and control circuits. INTV may be loaded
CC
by external termination resistors up to 1mA. For reliable
operation, do not overload INTVCC. Bypass this pin to
ground with a 1µF low ESR ceramic capacitor placed close
to the LT8698S.
EN/UV (Pin 3): EN/UV is the enable and programmable
undervoltage lockout pin. The LT8698S is shut down
when the EN/UV pin is below its threshold and enabled
when above. The threshold voltage is 1.46V with EN/UV
rising and 1.31V with EN/UV falling. EN/UV below 0.25V
reduces the VIN current to <1μA. An external resistor
LD+ (Pin 12): LD+ is the low voltage host side of the
+
internal USB D dataline switch. Float this pin if not used.
LD– (Pin 13): LD– is the low voltage host side of the
–
internal USB D dataline switch. Float this pin if not used.
divider from V can be used to program an undervolt-
IN
HD– (Pin 15): HD– is the high voltage USB cable and
age lockout threshold below which the LT8698S will shut
–
device side of the internal USB D dataline switch. Both
down. See the Applications Information section for addi-
–
dataline switches are disconnected if HD > 4.5V. Float
tional information. Tie EN/UV to V if not used.
IN
this pin if not used.
FLT (Pin 4): FLT is the open drain output of the internal
fault logic. FLT pulls low after 4.2ms of a sustained fault
condition in which the output voltage is not is regulation.
HD+ (Pin 16): HD+ is the high voltage USB cable and
+
device side of the internal USB D dataline switch. Both
+
dataline switches are disconnected if HD > 4.5V. Float
FLT pulls low immediately if INTV < 3.6V or if the inter-
CC
this pin if not used.
nal thermal shutdown feature activates. FLT transitions to
high impedance after 4.2ms in the sustained absence of
CLAMP (Pin 18): Bypass CLAMP with a 0.1µF 20V or
greater low ESR capacitor to ground.
a fault condition. FLT is valid when V > 4.5V and EN/UV
IN
> 1.46V. Float FLT if not used.
RCBL (Pin 19): RCBL is the cable drop compensation pro-
STATUS (Pin 5): STATUS is an open drain output indicator.
The STATUS pin function depends on the state selected by
the SEL1-3 pins. Refer to Table 6 for more information.
gramming pin. A resistor R
tied from RCBL to ground
CBL
programs the cable drop compensation by setting the
USB5V input current. RCBL can source 2mA. Excessive
capacitive loading on RCBL can degrade load transient
response. Isolate load capacitance on this pin by tying a
100k resistor between RCBL and the capacitive load. The
RCBL load monitor output is valid when the LT8698S is
enabled; otherwise the output is low. See the Applications
Information section for additional information.
STATUS is de-bounced for 4.2ms and is valid when V >
IN
4.5V and EN/UV > 1.46V. Float STATUS if not used.
SEL1, SEL2, SEL3 (Pins 6-8): SEL1-3 are tristate input
pins used to select the desired USB functionality of the
LT8698S. Refer to Table 6 in the Applications Information
section for detailed information. Tie below 0.58V for logic
low, above 1.41V for logic high and float for tristate. Keep
leakage currents under 1µA for robust tristate detection.
The SEL1-3 pins are de-bounced for 1.5ms for robust
transitions between USB states.
Rev. A
12
For more information www.analog.com
LT8698S/LT8698S-1
PIN FUNCTIONS
USB5V (Pin 20): USB5V is the 5V regulator feedback pin.
switching regulator inductor. This node should be kept
small on the PCB for good performance.
For cable drop compensation, the USB5V pin input cur-
rent is proportional to the sensed output current. Tie R
CDC
BST (Pin 26): BST provides a drive voltage, higher than
the input voltage, to the top side power switch. Leave
BST floating.
from USB5V to the BUS/ISN output for 5V regulation plus
cable drop compensation. Tie C from USB5V to BUS/
CDC
ISN to limit the cable drop compensation loop bandwidth.
Short USB5V to VBUS if no cable drop compensation is
desired.
PGND (Pins 27, 32): The PGND pins are the return path
of the internal bottom side power switch and must be tied
together. Place negative terminal of the input capacitors
as close as possible to the PGND pins. See Applications
Information section for a sample layout. All GND and
PGND pins are internally shorted together.
BUS/ISN (Pin 21): BUS/ISN is the USB VBUS output and
negative current sense input pin. BUS/ISN provides an
additional input to the error amplifier to ensure the maxi-
mum output regulation voltage does not exceed 6.05V.
In addition, BUS/ISN provides the negative input to the
internal current sense amplifier. BUS/ISN must be tied
V (Pins 29, 30): The V pins are the input path of the
IN
IN
internal top side power switch and must be tied together.
The LT8698S requires a minimum of 2µF local input
bypass capacitance to PGND. A single 2.2µF capacitor
to the R
sense resistor for cable drop compensation
SEN
and output current limit. Kelvin connect the BUS/ISN pin
to the sense resistor to separate regulator output cur-
rent from the BUS/ISN PCB trace. See the Applications
Information section for additional operation and PCB lay-
out information.
may be placed between V and PGND. Best practice for
IN
low EMI/EMC is to tie two additional 0.1µF input bypass
capacitors to V . One 0.1µF capacitor should be placed
IN
between V and pin 27 PGND. A second 0.1µF capacitor
IN
of equal value should be placed between V and pin 32
IN
OUT/ISP (Pin 22): OUT/ISP is the switching regulator
output. OUT/ISP must be tied to the inductor terminal
opposite the SW and must be bypassed by the output
capacitor. Also, the OUT/ISP pin is the noninverting input
to the current sense amplifier and must be tied to the
RSEN sense resistor for cable drop compensation and
output current limit. Kelvin connect the OUT/ISP pin to
the sense resistor to separate regulator output current
from the OUT/ISP trace. See the Applications Information
section for additional information.
PGND. These capacitors should be placed as close as pos-
sible to the LT8698S. See Application Information section
for a sample layout.
Exposed Pads (Pins 33–38): The exposed pads must be
connected to ground. Keep the top layer PCB connection
to these pins large to lower the thermal resistance from
the LT8698S package to ambient. See the Applications
Information section for detailed recommendations.
Corner Support Pads (Pins 39–42): The four pads at
each corner of the package are support pads intended to
improve board level mechanical reliability. These pads are
tied to ground internally to the LT8698S. The pads must
be tied to PCB ground.
SW (Pins 24, 25): SW is the output node of the inter-
nal top and bottom side power switches. Connect to the
Rev. A
13
For more information www.analog.com
LT8698S/LT8698S-1
BLOCK DIAGRAM
LT8698S Only
V
IN
V
IN
C1 2x
10nF
V
IN
C
VIN
R
R
1.2V
–
+
INTV
EN1
ꢀꢁꢂꢃ
CC
INTERNAL REFERENCE
AND 4V REGULATOR
EN/UV
C2
0.1μF
C
INTVCC
EN2
BST
C3
VC
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
0.1µF
R
SEN
L1
SW
V
BUS
USB5V
1.2V
DRIVER
+
–
C
OUT
PULSE
SKIP
LOGIC
USBFB
C
R
CDC
CDC
PGND
BUS/ISN
1.2V
+
–
OUT/ISP
BUS/ISN
SLOPE
COMP
1.2V
+
–
R
R
VMON
USB5V
4V
+
–
1.12V
FLT
FAULT
LOGIC
USBFB
+
–
+
–
VMON
1.30V
46R
RCBL
RT
2.8V
R
CBL
R
T
OSCILLATOR
300kHz TO 3MHz
BUS/ISN
5µA
SYNC/MODE
INTV
10mA
CC
STATUS
SEL1
INTV
CC
CHARGER
CONTROL
SEL2
SEL3
INTV
CC
CHARGER
PROFILE
MUX
CLAMP
INTV
CC
C4
C
CLMP
FIXED
0.1μF
OSCILLATOR
+
+
HD
LD
DATA LINES
TO USB SOCKET
DATA LINES
TO µCONTROLLER
–
–
LD
HD
GND
8698S BD
Rev. A
14
For more information www.analog.com
LT8698S/LT8698S-1
OPERATION
The LT8698S is a highly efficient synchronous, monolithic
USB charger with cable drop compensation and robust USB
dataline protection. As such, the LT8698S includes a switch-
The “S” in the LT8698S part name refers to the second
generation Silent Switcher Technology. This technology
allows fast switching edges for high switching regulator
efficiency at high switching frequency, while simultane-
ously achieving good EMI performance. This technology
includes the integration of ceramic capacitors into the
ing regulator optimized for powering the 5V USB V
rail
BUS
and two analog switches that tie to the high speed USB 2.0
datalines to provide fault and ESD protection to the upstream
USB host IC. Finally, the LT8698S includes many USB charger
profiles to allow high current charging of portable devices.
package for the V , INTV and BST (C1 to C4 in the
IN
CC
Block Diagram). These capacitors keep all of the AC cur-
rent loops small which improves EMI performance. The
LT8698S-1 does not include integrated ceramic capaci-
The LT8698S regulator is a monolithic, constant frequency,
peak current mode step-down DC/DC converter. An oscillator,
with frequency set using a resistor on the RT pin, turns on the
internal top power switch at the beginning of each clock cycle.
Current in the inductor then increases until the top switch
current comparator trips and turns off the top power switch.
The peak inductor current at which the top switch turns off is
tors tied to V .
IN
An EN/UV pin voltage above 1.46V enables the switch-
ing regulator, dataline switches and associated circuitry.
An EN/UV pin voltage below 1.31V stops switching and
opens the dataline switches. EN/UV pin voltage below
controlled by the voltage on the V node. The error amplifier
0.25V reduces V current to <1µA.
C
IN
compares the output voltage on the USB5V pin through an
The LT8698S operates primarily in forced continuous
mode (FCM) for fast transient response and full frequency
operation over a wide load range. To improve regulator
efficiency at light load, the LT8698S can operate in pulse-
skip mode (PSK). PSK reduces the switching frequency
at light load current and reduces VIN quiescent current
between pulses. Ground the SYNC/MODE pin for PSK
operation, float it for FCM operation or apply a DC voltage
higher than 3.2V to use FCM with spread spectrum modu-
lation (SSM). If a clock is applied to the SYNC/MODE pin,
the internal oscillator will synchronize to the external clock
frequency and operate in FCM. While in FCM the oscilla-
tor operates continuously and rising SW transitions are
aligned to the clock. During light loads, the inductor cur-
rent is allowed to go negative to maintain the programmed
switching frequency. The LT8698S can sink current from
the output, improving the load step response. Minimum
current limits for both power switches are enforced to
prevent large negative inductor current from flowing back
into the input. SSM dithers the switching frequency from
the programmed value set by the RT pin up to 20% higher
than the programmed value to spread out the switching
energy in the frequency domain.
internal resistor divider to an internal reference and servos
the V node to regulate the USB5V pin to 5V. When the load
C
current increases it causes a reduction in the feedback voltage
relative to the reference leading the error amplifier to raise
the VC voltage until average inductor current matches the
new load current. When the top power switch turns off, the
synchronous bottom power switch turns on until the next
clock cycle begins or inductor current falls to zero when not
in forced continuous mode. If overload conditions result in a
current higher than the bottom switch current limit flowing
in the bottom switch, the next clock cycle will be delayed
until switcher current returns to a safe level. In addition, dur-
ing a fault condition in which USB5V is shorted to ground,
the BUS/ISN voltage is regulated to 6.05V to limit the output
voltage to a safe level for connected devices. Finally, during
an output fault condition, the LT8698S provides an accurate,
average output current limit using an external sense resistor
connected across the OUT/ISP and BUS/ISN pins.
The LT8698S includes cable drop compensation to provide
5V regulation of the V
rail at the end of a long, resistive
BUS
cable even with high load current. To implement cable
drop compensation, the LT8698S drives the RCBL pin to
46 • (VOUT/ISP - VBUS/ISN). Current sourced from the RCBL
Comparators monitoring the USB5V pin voltage will pull
the FLT pin low if the output voltage varies more than
7% (typical) from the set point, or if a power supply fault
condition is present.
pin through the R
resistor is derived from the USB5V
CBL
pin, creating an output offset across the RCDC resistor
above the 5V USB5V pin voltage that is proportional to
the R /R
resistor ratio.
CDC CBL
Rev. A
15
For more information www.analog.com
LT8698S/LT8698S-1
OPERATION
Dataline analog switches allow connection and disconnec-
to the device plugged into the USB socket in some active
manner. The profile allows the device plugged into the
USB socket to identify a high current charger and draw
+
+
tion between the HD pin and the LD pin and between the
–
–
HD pin and the LD pin. When connected, the switches
provide low resistance over the full 0V to 3.6V common
more current from V
than the 0.5A that would usually
BUS
+ –
mode range and can block 0V to 20V on the HD / side
be allowed from a standard USB 2.0 socket.
+ –
and 6V on the LD / side. High speed circuitry discon-
SEL1-3 pins are tristate inputs that allow the host
µController to control the behavior of the LT8698S.
Internal resistive dividers bias these pins to 1V when a
high Z input is applied. The SEL1-3 pins are de-bounced
for 1.5ms prior to allowing a state change to the LT8698S.
nects the switches in the event of a fault or ESD on the
+ –
HD / side.
The LT8698S includes many charger profiles including
USB BC 1.2 CDP, DCP, and SDP as well as common pro-
prietary profiles. Each profile ties various components
to the datalines. This could be resistive dividers, a short
between the datalines, or voltage sources and current
sources. These profiles might be passive or could react
The STATUS pin is an open drain output whose function is
determined by the state selected by the SEL1-3 pins. This
pin can output high or low or oscillate with a 9ms period.
APPLICATIONS INFORMATION
Cable Drop Compensation
The current flowing into the USB5V pin through R is iden-
tical to the current flowing through R . While CthDeC ratio of
The LT8698S includes the necessary circuitry to imple-
ment cable drop compensation. Cable drop compensa-
tion allows the regulator to maintain 5V regulation on the
CBL
these two resistors should be chosen per the equation above,
choose the absolute values of these resistors to keep this
current between 30µA and 1200µA at full load current. This
USB V
rail despite high cable resistance. The LT8698S
BUS
increases its local output voltage (V
) above 5V as
BUS/ISN
restriction results in R and R
values between 1k and
CDC
40.2k. If IUSB5V is tooClBoLw, capacitive loading on the RCBL
pin will degrade the load step transient performance of the
regulator. If IUSB5V is too high, the RCBL pin will go into current
limit and the cable drop compensation feature will not work.
the load increases to keep VBUS regulated to 5V. This
compensation does not require running an additional pair
of Kelvin sense wires from the regulator to the load, but
does require the system designer to know the cable resis-
tance R
as the LT8698S does not sense this value.
CABLE
Capacitance across the remote load to ground downstream
Program the cable drop compensation using the ratio of
Equation 1.
of R forms a left half plane zero in the LT8698S device's
SEN
feedback loop due to cable drop compensation. C and the
BUS
⎛
⎜
⎝
⎞
⎟
⎠
input capacitance of a portable device tied to the USB socket
RSEN •RCDC
RCABLE
(1)
RCBL =46•
typically form this zero. C reduces the cable drop compen-
CDC
sation gain at high frequency. The 4.7nF C
capacitor tied
CDC
across the 2k R
is required for stability of the LT8698S’s
is changed, C
where R
is a resistor tied between the regulator out-
CDC
CDC
output. If R
should also be changed
put and the USB5V pin, R
is a resistor tied between
CDC
CDC
the RCBL pin and GND, RCBL is the sense resistor tied
to maintain roughly the same 10µs RC time constant. If the
SEN
capacitance across the remote load is large compared to the
between the OUT/ISP and BUS/ISN pins in series between
LT8698S output capacitors C
and C , a longer R
•
the regulator output and the load, and RCABLE is the
OUT
BUS
CDC
C
CDC
time constant may be necessary for stability depending
cable resistance. R
must be 10mΩ for 2.4A applica-
tions and 8mΩ forS3ENA applications for the LT8698S to
function properly.
on the amount of cable drop compensation used. Output sta-
bility should always be verified in the end application circuit.
Rev. A
16
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
Short USB5V to the VBUS output if no cable drop com-
pensation is desired.
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
The LT8698S limits the maximum voltage of V by limiting
BUS
the voltage on the BUS/ISN pin to 6.05V. If the cable drop
compensation is programmed to compensate for more than
1.05V of cable drop at the maximum I , this limit will pre-
BUS
vent V
from rising higher and the voltage at the point
will drop below 5V. Equation 2 shows how to
BUS/ISN
of load V
BUS
ꢀ
ꢀ ꢁ.ꢂA
ꢀ ꢁ.ꢂꢃꢄ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢁꢂꢃ
ꢁꢂAꢃ
derive the LT8698S output voltage.
R
46•IBUS •RSEN •RCDC
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
(2)
VOUT =5V+
RCBL
ꢀꢁꢂꢀꢃ ꢄꢅꢆꢇ
(a) Cable Drop Compensation Through 3m of AWG 24 Twisted-
Pair Cable (490mΩ) without Temperature Compensation
Refer to Figure 1 for load lines of V
and V
to see
BUS
BUS/ISN
how cable drop compensation works.
ꢀ.ꢁꢂ
RCBL
ꢀ
ꢁꢂꢃ
ꢁꢂAꢃ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁꢀ
ꢀ.ꢀꢁ
ꢀ.ꢁꢀ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ
1.45k
1%
MURATA
11k
NCP15XC680E03RC
1%
68Ω THERMISTOR
8698S F02b
ꢀ
ꢃ ꢄꢅꢀ
ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
R
= 10mΩ
(b) RCBL Resistor Network for Matching Copper
Wire Temperature Coefficient
R
ꢀ ꢁ.ꢂꢃꢄ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁAꢂ ꢃꢄRRꢅꢆꢇ ꢈAꢉ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
Figure 1. Example Cable Drop Compensation Load Line
Cable Drop Compensation Over a Wide
Temperature Range
Cable drop compensation with zero temperature variation
may be used in many applications (see Figure 2a,b,c).
However, matching the cable drop compensation temper-
ature variation to the cable resistance temperature varia-
tion may result in better overall output voltage accuracy
over a wide operating temperature range. For example, in
an application with 0.49Ω of wire resistance and a maxi-
mum output current of 1.5A, cable drop compensation
adds 0.735V at 25°C to the output at max load for a fully
compensated wire resistance. If the wire in this example
is copper, the copper resistance temperature coefficient
ꢀ
ꢀ
ꢀ ꢁ.ꢂA
ꢁꢂꢃ
ꢁꢂAꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢀ
ꢀ
R
ꢀ ꢁꢂꢃꢄꢅe ꢆꢇ
ꢀ.ꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
(c) Cable Drop Compensation Through 3m of AWG
24 Twisted-Pair Cable (490Ω) with Temperature
Compensation Using NTC RCBL
Figure 2. Cable Drop Compensation Applications
Rev. A
17
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
of about 4000ppm/°C results in an output voltage error of
294mV at 125°C and 191mV at –40°C. Figure 2a shows
this behavior.
The NTC resistor does not give a perfectly linear transfer
function versus temperature. Here, for typical component
values, the worst case error is <20% of the cable compen-
sation output, or <4% of the total output voltage accuracy.
Better output voltage accuracy versus temperature can
be achieved if RCBL resistor values are optimized for a
narrower temperature range.
See Table 1 for a list of copper wire resistances vs gauge.
Table 1. Copper Wire Resistance vs Wire Gauge
AWG
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RESISTANCE OF CU WIRE AT 20°C (mΩ/m)
10.4
13.2
16.6
21.0
26.4
33.3
42.0
53.0
66.8
84.2
106
Effect of Cable Inductance on Load Step Transient
Response
The inductance of long cabling limits the peak-to-peak
transient performance of a 2-wire sense regulator to fast
load steps (see Figure 3). Since a 2-wire sense regulator
like the LT8698S detects the output voltage at its local
output and not at the point of load, the load step response
degradation due to cable inductance is present even with
cable resistance compensation. The local regulator output
capacitor and the input capacitor of the remote load form
a LC tank circuit through the inductive cabling between
them. Fast load steps through long cabling show a large
peak-to-peak transient response and ringing at the reso-
nant frequency of the circuit. This ringing is a property
of the LC tank circuit and does not indicate regulator
instability.
134
169
213
268
339
427
538
Figure 3a shows the LT8698S load step transient response
to a 125mA/µs, 0.5A load step. Two cable impedances are
compared: resistive only and then resistive plus inductive.
First, a surface mount 0.5Ω resistor is tied between the
LT8698S output and the load step generator. This resis-
tor stands in for a purely resistive “cable”. Second, AWG
24 twisted-pair cabling 3 meters long with 0.5Ω of total
resistance and about 0.8µH of inductance is connected
between the LT8698S output and the load step genera-
tor. Even though the resistance in these two circuits is
the same, the transient load step response in the cable
is worse due to the inductance. The degree that cable
inductance degrades LT8698S load transient response
performance depends on the inductance of the cable and
on the load step rate. Long cables have higher inductance
than short cables. Cables with less separation between
supply and return conductor pairs show lower inductance
per unit length than those with separated conductors. A
faster load step rate exacerbates the effect of inductance
679
856
1080
1360
1720
2160
2730
3440
Cable drop compensation can be made to vary positively
versus temperature with the addition of a negative tem-
perature coefficient (NTC) resistor as a part of the R
CBL
resistance. This circuit idea assumes the NTC resistor is
at the same temperature as the cable. Figure 2b shows
an example resistor network for R
that matches cop-
CBL
per resistance variation over a wide –40°C to 150°C tem-
perature range. Figure 2c shows the resultant cable drop
compensation output at several temperatures using R
with negative temperature variation.
CBL
on load step response.
Rev. A
18
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
the same current as the output. Since the local ground
at the LT8698S is separated by a current carrying cable
from the remote ground at the point of load, the ground
reference points for these two locations are different.
ꢀ
ꢄꢅꢆꢇꢈꢉꢅ
ꢁꢂAꢃ
0.5Ω Resistor
ꢀꢁꢁꢂꢃꢄꢅꢆꢃ
ꢀ
ꢄꢅꢆꢇꢈꢉꢅ
ꢁꢂAꢃ
0.5Ω Cable
Use a differential probe across the remote output at the
end of the cable to measure output voltage at that point,
as shown in Figure 4b. Do not simultaneously tie an oscil-
loscope’s probe ground leads to both the local LT8698S
ground and the remote point of load ground, as shown
in Figure 4a. Doing so will result in high current flow
in the probe ground lines and a strange and incorrect
measurement. Figure 4c shows this strange behavior. A
1.3A load step is applied to the LT8698S output through
3 meters of AWG 24 twisted-pair cable. On one curve, the
resultant output voltage is measured correctly using a dif-
ferential probe tied across the point of load. On the other
curve, the oscilloscope ground lead is tied to the remote
ground. This poor probing causes both a DC error due to
the lower ground return resistance and an AC error show-
ing increased overshoot. Do not add your oscilloscope,
lab bench, and input power supply ground lines into your
measurement of the LT8698S remote output.
ꢀꢁꢁꢂꢃꢄꢅꢆꢃ
ꢀ
ꢁꢂꢃ
ꢀ.ꢁAꢂꢃꢄꢅ
ꢀꢁꢂꢀꢃ ꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆꢇ
(a)
ꢀ
ꢄꢅꢆꢇꢈꢉꢆ
ꢁꢂAꢃ
ꢀꢁꢁꢂꢃꢄꢅꢆꢃ
ꢁꢂAꢃ
ꢀ
ꢀ
ꢄꢅꢆꢇ
ꢅꢆAꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢃ
ꢁꢂAꢃ
ꢀꢁꢂꢃ ꢄ
ꢀꢁAꢂ Aꢃ ꢄꢅꢂ ꢁꢆ ꢇꢈ Aꢉꢊ ꢋꢌ ꢍAꢎꢀꢄ
ꢀ
ꢁꢂAꢃ
ꢀꢁꢁꢂAꢃꢄꢅꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
(b)
Figure 3. Effect of Cable Inductance on Load Step
Transient Response
Reducing Output Overshoot
Figure 3b shows the effect of remote capacitance at the
load side of the cable on the LT8698S transient response.
The load step is a 60mA/µs, 0.5A load step through a 0.5Ω,
the load step location, there is no LC tank and thLeOreAfDore
no observed ringing. In this case, given 100% of the dI/dt
of the load step occurs across the cable resistance R and
A consequence of the use of cable drop compensation is
that the local output voltage at the LT8698S BUS/ISN pin
is regulated to a voltage that is higher than the remote
output voltage at the point of load. Several hundred mΩ
of line resistance can separate these two outputs, so at 2A
3 meter long cable. Without remote capacitance C
at
of load current, V
may be up to 1.05V higher than
BUS/ISN
inductance L, the peak to peak V
deviation is 300mV.
the nominal 5V output at the point of load. Ensure that any
components tied to the LT8698S output can withstand
this increased voltage.
When 10µF of remote C
is aLdOdAeDd at the load step loca-
LOAD
tion, the cable L and load capacitance form a tank circuit
leading to modest ringing. In this case, given the effective
dI/dt across the cable R and L is reduced, the peak to peak
The LT8698S has several features designed to mitigate
any effects of higher output voltage due to cable drop
compensation. First, the LT8698S error amplifier, in addi-
tion to regulating the voltage on the USB5V pin to 5V
for the primary output, also regulates the BUS/ISN pin
voltage to less than 6.05V. This 6.05V upper limit on the
maximum BUS/ISB voltage protects components tied to
the LT8698S output such as a portable device from an
overvoltage condition, but reduces the possible amount
of cable drop compensation to 1.05V.
V
LOAD
deviation is reduced to less than 250mV.
Probing a Remote Output Correctly
Take care when probing the LT8698S’s remote output
to obtain correct results. With cable drop compensation
the local regulator output has a different voltage than
the remote output at the end of a cable due to the cable
resistance and high load current. The same is true for the
ground return line which also has resistance and carries
Rev. A
19
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
ꢕRꢂꢅꢏ
sink current from the output when USB5V is too high
using FCM. Figure 5 shows the output voltage of the front
page application circuit with both FCM and PSK modes in
response to a fast, 1.3A load step through a 3m cable. The
load step response from high current to zero in PSK mode
is extremely slow and is limited by the OUT/ISP, BUS/ISN
and USB5V pin bias currents. However, with FCM enabled,
the output slews quickly back into regulation.
ꢁꢂꢍꢎ ꢈAꢅꢁꢏ
ꢕꢂꢖꢍꢗ
ꢄ
ꢅꢆꢇ
ꢀ
ꢈ
ꢅꢆꢇ
ꢉꢊꢊꢋꢌ
ꢐꢑꢒꢐꢇ ꢌꢊꢓꢔ
ꢕRꢂꢅꢏ
ꢎRꢂꢆꢍꢃ
ꢕꢂꢖꢍꢗ
(a) Incorrect Remote Output Probing
ꢀ
ꢄꢅ ꢆꢇꢈ
ꢁꢂAꢃ
ꢀꢁꢁꢂꢃꢄꢅꢆꢃ
ꢕRꢂꢅꢏ
ꢁꢂꢍꢎ ꢈAꢅꢁꢏ
ꢕꢂꢖꢍꢗ
ꢀ
ꢄꢅꢆ ꢇꢈꢉ
ꢀꢁꢁꢂꢃꢄꢅꢆꢃ
ꢁꢂAꢃ
ꢄ
ꢅꢆꢇ
ꢀ
ꢈ
ꢅꢆꢇ
ꢉꢊꢊꢋꢌ
ꢀ
ꢁꢂꢃ
ꢀAꢁꢂꢃꢄ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢐꢑꢒꢐꢇ ꢌꢊꢓꢔ
ꢕRꢂꢅꢏ
ꢕꢂꢖꢍꢗ
Figure 5. Load Step Response with and without
Forced Continuous Mode
(b) Correct Remote Output Probing
Lastly, the LT8698S positive switch peak current and
negative valley current limits exceed the positive output
current limit of 2.65A. This large current range allows the
LT8698S to slew the output capacitor quickly for cable
drop compensation during a transient load step.
ꢀ
ꢄꢅꢆꢇeꢈ
ꢁꢂAꢃ
ꢀꢁꢂꢂeꢃꢄꢅꢆ
ꢀꢁꢁꢂꢃꢄꢅꢆꢃ
ꢀ
ꢄꢅꢆꢇeꢈ
ꢁꢂAꢃ
ꢀꢁꢂꢃꢄꢄeꢂꢅꢆꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢃ
Output Current Limit
ꢀ
ꢁꢂꢃ
ꢀAꢁꢂꢃꢄ
In addition to regulating the output voltage, the LT8698S
limits the average output current with a current regulation
loop. Output current regulation limits power dissipation
in the case of a fault on the USB cable or of the device
plugged into the socket. The LT8698S measures the volt-
ꢀꢁꢂꢀꢃ ꢄꢅꢆꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
(c) Effect of Probing Remote Output Incorrectly
Figure 4. Probing a Remote Output Correctly
age drop across the external sense resistor R
using the
OUT/ISP and BUS/ISN pins. This resistor shSoEuNld be con-
Additionally, the LT8698S can sink current from the out-
put when in forced continuous mode (FCM). This feature
improves the step response for a load step from high to
low. Cable drop compensation adds voltage to the output
to compensate for voltage drop across the cable resis-
tance at high load. Since most DC/DC convertors can only
source current, a load step from high to near zero current
leaves the output voltage high and out of regulation. The
LT8698S fixes this problem by allowing the regulator to
nected on the load side of the output capacitor C , in
OUT
series with the load. The LT8698S control loop modulates
the cycle-by-cycle switch current limit such that the aver-
age voltage across the OUT/ISP to BUS/ISN pins does not
exceed its regulation point. When load current exceeds
the output current limit and current regulation is active,
the output voltage will drop below its regulation point.
The LT8698S also includes latch-off and auto-retry func-
tionality in the output current regulation loop. If the output
Rev. A
20
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
voltage is 7% below is regulation point for at least 4.2ms,
the LT8698S will stop switching for 59ms. After 59ms,
the LT8698S will start switching. If the output can return
to its nominal regulation point within 4.2ms after starting
to switch, then normal operation will resume. Otherwise,
if the output still remains more than 7% below its regu-
lation point, the LT8698S will again stop switching for
59ms and this sequence will repeat. This latch-off and
auto-retry feature reduces the power dissipation in a fault
condition to about an 7% duty cycle of what it otherwise
would have been.
Table 2 shows the ideal R value for a desired switching
T
frequency.
Table 2. Switching Frequency vs RT Value
Switching Frequency (MHz)
R (kΩ)
T
3
5.76
6.19
6.81
7.5
2.8
2.6
2.4
2.2
2
8.25
9.09
10.2
11.5
12.4
13.3
14.7
15.8
17.4
19.1
21.5
24.3
28
1.8
1.6
1.5
1.4
1.3
1.2
1.1
1
Using RCBL as an Output Current Monitor
The primary function of the RCBL pin is to set the cable
drop compensation as discussed in the Cable Drop
Compensation section. The secondary function of the
RCBL pin is to produce an output voltage that is propor-
tional to the output load current. The RCBL pin can there-
fore be used as an output load monitor. The voltage on the
RCBL pin obeys Equation 3 relation to USB load current.
0.9
0.8
0.7
0.6
0.5
0.4
0.3
V
= I
• R
• 46
(3)
RCBL LOAD
SEN
This formula is valid when the LT8698S is enabled.
32.4
39.2
49.9
66.5
Since the RCBL pin current is part of the cable drop com-
pensation control loop, excessive capacitive loading on
the RCBL pin can cause USB output voltage overshoot
during load steps. Keep the capacitive loading on the
RCBL pin below 100pF or isolate the load capacitance
with 100kΩ in series between the RCBL pin and the input
it is driving as shown in Figure 6.
R can also be found for the desired switching frequency
T
using Equation 4 where f is in MHz.
20.25
(4)
RT =
– 1.013k
f
Rꢄꢊꢋ
ꢀꢁꢁꢂ
Aꢃꢄ
Operating Frequency Selection and Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size and input voltage range. The
advantage of high frequency operation is that smaller
inductor and capacitor values may be used. The disadvan-
tages are lower efficiency and a smaller input voltage range.
R
ꢄꢊꢋ
ꢅꢆꢇꢅꢈ ꢉꢁꢆ
Figure 6. Using the RCBL Pin as Output Current Monitor
Setting the Switching Frequency
The highest switching frequency (f
) for a given
SW(MAX)
application before min on-time limited can be calculated
The LT8698S uses a constant frequency PWM architec-
ture that can be programmed to switch from 300kHz to
3MHz by using a resistor tied from the RT pin to ground.
using Equation 5.
VOUT/ISP
(5)
fSW(MAX)
=
•1000
tON(MIN)•V
IN(MAX)
Rev. A
21
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
where VIN(MAX) is the maximum input voltage without
For robust operation, use an inductor with value equal to
or greater than the value on Table 3.
skipped cycles, V
is the output voltage at OUT/ISP,
OUT/ISP
and tON(MIN) is the minimum top switch on-time of about
30ns. This equation shows that a slower switching frequency
Table 3. Inductor Value by Switching Frequency
SWITCHING FREQUENCY
(MHz)
MINIMUM NOMINAL INDUCTOR VALUE
(µH)
is necessary to accommodate a high V /V
ratio.
IN OUT/ISP
2.4 – 3.0
1.9 – 2.4
1.5
2.2
3.3
4.7
6.8
8.2
10
For transient operation, V may go as high as the abso-
IN
lute maximum rating of 42V regardless of the R value;
T
1.3 – 1.9
however the LT8698S will reduce switching frequency
as necessary to maintain control of inductor current to
assure safe operation.
0.89 – 1.3
0.61 – 0.89
0.51 – 0.61
0.30 – 0.51
The LT8698S is capable of a maximum duty cycle of
greater than 99%, and the V to V
dropout is lim-
ited by the RDS(ON) of the tIoNp swBitUcSh/.ISONperating in this
region results in lower switching frequency.
Table 4 lists inductor vendors and associated inductor
product series names that are recommended for use with
the LT8698S.
The highest switching frequency (f
) for a given
SW(MAX)
application before min off-time limited can be calculated
Table 4. Inductor Manufacturers
using Equation 6.
VENDOR
TDK
SERIES
WEBSITE
SLF, VLC, VLF
www.tdk.com
⎛
⎞
1
VOUT/ISP
⎜
⎟
(6)
fSW(MAX)
=
–
•1000
Sumida
Coilcraft
NIC
CRH, CDR, CDMC
XAL, XFL, MSS
NPIM, NPIS
www.sumida.com
www.coilcraft.com
www.niccomp.com
www.we-online.com
⎜
⎟
tOFF(MIN) tOFF(MIN)•V
IN(MIN)
⎝
⎠
where VIN(MIN) is the minimum input voltage without
Würth
TPC, SPC, PD, PDF, PD3
skipped cycles, V
is the output voltage at OUT/ISP,
and t
is OthUeT/ImSPinimum switch off-time of 40ns.
Input Capacitor
Note tOhFaFt(MhIiNg)her switching frequency will increase the
minimum input voltage for full frequency operation.
Bypass the input of the LT8698S circuit with a ceramic
capacitor with the appropriate temperature and voltage
rating, placed as close as possible to the V and PGND
IN
Inductor Selection and Maximum Output Current
pins. Y5V types have poor performance over temperature
and applied voltage, and should not be used. A 2.2μF
to 4.7μF ceramic capacitor is adequate to bypass the
LT8698S and will easily handle the ripple current. Note
that larger input capacitance is required when a lower
switching frequency is used. If the input power source has
high impedance, or there is significant inductance due to
long wires or cables, additional bulk capacitance may be
necessary. This can be provided with a low performance
electrolytic capacitor.
The LT8698S is designed to minimize solution size by
allowing the inductor to be chosen based on the output
load requirements of the application. During overload
or short-circuit conditions the LT8698S safely tolerates
operation with a saturated inductor through the use of a
high speed peak-current mode architecture.
Based on the desired switching frequency, pick an induc-
tor for the LT8698S according to Table 3.
Table 3 lists nominal values for inductors. Inductors are
typically de-rated versus current, versus temperature and
have a tolerance spec. This table assumes the inductance
in the application will not be 40% less than the nominal
value at worst case operating conditions and tolerance.
Step-down regulators draw current from the input supply in
pulses with very fast rise and fall times. The input capaci-
tor is required to reduce the resulting voltage ripple at the
LT8698S and to force this very high frequency switching
Rev. A
22
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
current into a tight local loop, minimizing EMI. A second
precaution regarding the ceramic input capacitor con-
cerns the maximum input voltage rating of the LT8698S.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank cir-
cuit. If the LT8698S circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possibly
exceeding the LT8698S’s voltage rating. This situation is
easily avoided (see ADI Application Note 88).
with extra COUT tied from either OUT/ISP to ground. There
must always be a minimum of 22µF capacitance tied from
OUT/ISP to ground.
Keep the capacitance tied to the BUS/ISN node lower in
magnitude than the capacitance tied to the OUT/ISP node.
Large BUS/ISN node capacitance to ground degrades the
regulator loop phase margin and gives poor cable drop
compensation transient response. If an output capaci-
tance much larger than 22µF is desired, tie this capacitor
to the OUT/ISP node, not to the BUS/ISN node.
Output Capacitor and Output Ripple
When choosing a capacitor, special attention should be
given to the effective capacitance under the relevant oper-
ating conditions of voltage bias and temperature. A physi-
cally larger capacitor or one with a higher voltage rating
may be required.
The output capacitor C
tied from the OUT/ISP pin to
OUT
ground has two essential functions. Along with the induc-
tor, it filters the square wave generated by the LT8698S
to produce the DC output. In this role it determines the
output ripple, thus low impedance at the switching fre-
quency is important. The second function is to store
energy in order to satisfy transient loads and stabilize
the LT8698S’s control loop. Ceramic capacitors have very
low equivalent series resistance (ESR) and provide the
best ripple performance. For good starting values, see
the Typical Applications section.
Ceramic Capacitors
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT8698S due to their piezoelectric
nature. In pulse-skipping mode operation, the LT8698S’s
switching frequency depends on the load current, and
at very light loads the LT8698S can excite the ceramic
capacitor at audio frequencies, generating audible noise.
Since the LT8698S operates at a lower current limit during
pulse-skipping operation, the noise is typically very quiet
to a casual ear. If this is unacceptable, use a high perfor-
mance tantalum or electrolytic capacitor at the output.
Low noise ceramic capacitors are also available.
On a switching regulator with fixed output voltage, tran-
sient performance can generally be improved with a
higher value output capacitor. However, the LT8698S’s
cable drop compensation feature changes the local output
voltage in response to a load step. Since transient load
steps require the LT8698S to slew C , larger C
in
this case can degrade transient respOoUnTse. Only remote
capacitance tied at the end of the cable near the USB
socket can improve transient response. The minimum
local output capacitance required for LT8698S loop stabil-
ity and for output voltage ripple requirements is the best
OUT
Table 5. Ceramic Capacitor Manufacturers
VENDOR
Taiyo Yuden
AVX
WEBSITE
www.ty-top.com
www.avxcorp.com
www.murata.com
www.tdk.com
choice for C . See the Typical Applications section in
OUT
this data sheet for suggested capacitor values.
Murata
TDK
The USB 2.0 specification document requires a minimum
of 120µF low-ESR capacitor be tied from V
on a hub. Since the downstream device fixed V
to ground
BUS
BUS
EN/UV Pin
capaci-
tance is limited to a maximum of 10µF, this minimum
The LT8698S is in shutdown when the EN/UV pin is
< 0.25V and active when the pin is high. The falling thresh-
old of the EN/UV comparator is 1.31V, with 150mV of
120µF VBUS capacitance prevents hot plugging of one
downstream device from glitching the V
and disrupt-
BUS
ing another connected device. If the LT8698S is powering
hysteresis. The EN/UV pin can be tied to V if the shut-
IN
VBUS on a hub, then this requirement can be satisfied
down feature is not used, or driven to the desired logic
Rev. A
23
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
level if shutdown control is required. The LT8698S EN/
UV pin has an internal 5.5V clamp in a series with an
approximately 1Meg resistor.
Soft-Start
The LT8698S includes an internal soft-start function. The
output voltage ramp-up takes 1.1ms. The purpose of this
soft start feature is to limit inrush current into the regu-
lator as it charges the output capacitors during startup.
Adding a resistor divider from VIN to EN/UV programs
the LT8698S to operate only when V is above a desired
IN
IN(EN)
voltage. Typically, this threshold, V
, is used in situ-
V undervoltage lockout, INTV under and overvoltage
IN
ations where the input supply is current limited, or has a
lockout, EN/UV low, thermal sChCutdown, output current
limit latch off, and the SEL1-3 pins selecting a state with
the switcher off all reset the soft start ramp.
relatively high source resistance. This threshold can be
adjusted by setting the values R
they satisfy Equation 7.
and R
such that
(7)
EN1
EN2
FLT Pin
⎛
⎜
⎝
⎞
R
R
EN1 –1 •1.46V
When the LT8689S’s output voltage is within a 7% win-
dow of the regulation point, which is a USB5V pin voltage
in the range of 4.64V to 5.34V (typical), the output voltage
is considered not to be in fault and the open-drain FLT pin
goes high impedance and is typically pulled high with an
external resistor. Otherwise, the internal pull-down device
will pull the FLT pin low. To prevent glitching, both the
upper and lower thresholds include 3% of hysteresis and
the output is de-bounced over 4.2ms.
V
=
⎟
IN(EN)
⎠
EN2
ꢋ
ꢏꢈ
ꢋ
ꢍR ꢋ
ꢐAꢎꢎ
ꢏꢈ
ꢌꢎꢀꢁꢂꢀꢃ
ꢇꢈꢉꢊꢋꢌꢍ
R
R
ꢇꢈꢑ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢇꢈꢒ
The FLT pin is also actively pulled low during several fault
Figure 7. UVLO Divider
conditions: V under voltage lockout, INTV under and
IN
CC
over voltage lockout, EN/UV low, and thermal shutdown.
Lastly, the FLT pin can pull low for 4.2ms at the end of
the bus reset state machine sequence if VBUS is held
above 0.5V.
where the LT8698S will remain off until VIN is above
VIN(EN). Due to the comparator’s hysteresis, switching
will not stop until the input falls slightly below V
.
IN(EN)
INTV Regulator
CC
Synchronization
An internal low dropout (LDO) regulator produces the 4V
To select pulse-skipping mode operation, tie the SYNC/
MODE pin below 0.3V. To select forced continuous mode
(FCM), float the SYNC/MODE pin. To select FCM with
spread spectrum modulation (SSM), tie the SYNC/MODE
supply from V that powers the drivers and the internal
IN
bias circuitry. The INTV LDO can supply enough cur-
CC
rent for the LT8698S’s circuitry and must be bypassed to
ground with a 1.0μF ceramic capacitor. Good bypassing is
necessary to supply the high transient currents required
by the power MOSFET gate drivers.
pin above 3.7V (SYNC/MODE can be tied to INTV ). To
CC
synchronize the LT8698S oscillator to an external fre-
quency connect a 20% to 80% duty cycle square wave to
the SYNC/MODE pin. The square wave amplitude should
have valleys that are below 0.4V and peaks above 1.5V.
When synchronized to an external clock the LT8698S will
use FCM.
Applications with high input voltage and high switching
frequency will increase die temperature because of the
higher power dissipation across the LDO. INTV can be
CC
loaded up to 1mA for such purposes as providing a resis-
tor pull-up to the STATUS and FLT open drain output pins.
The LT8698S may be synchronized over a 300kHz to
3MHz range. The RT resistor should be chosen to set
the LT8698S switching frequency equal to or below the
For reliable operation do not overload the INTVCC LDO
with >1mA.
Rev. A
24
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
lowest synchronization input. For example, if the synchro-
Output Short Circuit and Reverse Input Protection
nization signal will be 500kHz and higher, the R should
T
The LT8698S is robust to output short circuit conditions.
When operating with the output short circuited to ground,
the bottom switch current is monitored such that if induc-
tor current is beyond safe levels, switching of the top
switch will be delayed until such time as the inductor
current falls to safe levels.
be selected for nominal 500kHz.
A synchronizing signal that incorporates spread spectrum
may reduce EMI.
Forced Continuous Mode
Forced continuous mode (FCM) is activated by either
floating the SYNC/MODE pin, applying a DC voltage above
1.1V to the SYNC/MODE pin or applying an external clock
to the SYNC/MODE pin.
When operating with the output short circuited to a high
voltage, such as an automobile battery, the current flow
within the system will depend on the state of the LT8698S
input supply V . If V is disconnected, such as may
IN
IN
occur with the ignition switch in the off position, the
LT8698S will draw approximately 2.5mA of quiescent
current from the output if EN/UV is driven high and 0μA
While in FCM, discontinuous mode operation is disabled
and the inductor current is allowed to go negative so that
the regulator can switch at the programmed frequency all
the way down to 2.3A of negative output current. This has
the advantage of maintaining the programmed switching
frequency across the entire load range so that the switch
harmonics and EMI are consistent and predictable. Also,
the ability to sink current from the output improves load
release transient response when cable drop compensa-
tion is used. The disadvantage of FCM is that the light
load efficiency will be low compared to pulse-skip mode
operation.
if the EN/UV is low. If V is grounded or reverse con-
IN
nected, the body diode of the internal TOP power FET
allows uncontrolled current flow from the output (SW) to
the input (V ), potentially damaging the LT8698S. To pre-
IN
vent possible uncontrolled reverse current, see Figure 8.
ꢃꢄ
ꢀ
ꢁꢂ
ꢀ
ꢁꢂ
ꢅꢆꢇꢈꢉꢇꢊ
ꢋꢂꢌꢍꢀ
ꢐꢂꢃ
There are several operating conditions in which the
LT8698S does not maintain the full switching frequency
with FCM selected. For instance, FCM is disable in dropout
which occurs at very low input voltages. When operating
in dropout, the LT8698S skips off times, reducing the
switching frequency to improve regulation performance.
ꢇꢈꢉꢇꢊ ꢎꢏꢇ
Figure 8. Reverse VIN Protection
Output Cable Fault
The LT8698S is robust to cable faults on the V
out-
BUS
Spread Spectrum Modulation
put to either GND or up to 20V. Input reverse protection
described above must prevent excessive top switch body
Spread spectrum modulation (SSM) is activated by apply-
ing a DC voltage above 3.7V to the SYNC pin. This can
be accomplished by shorting the SYNC/MODE pin to the
diode current from SW to V if the output is held high.
IN
20V on V
is a fault condition that could damage a por-
BUS
table device plugged into the USB socket powered by the
LT8698S. While the LT8698S can survive this condition,
it will not prevent damage to the portable device.
INTV pin. SSM reduces the EMI emissions by modu-
CC
lating the switching frequency between the value pro-
grammed by RT to approximately 20% higher than that
value. For example, when the LT8698S is programmed
to 2MHz and the SSM feature is enabled, the switching
frequency will vary from 2MHz to 2.4MHz.
An output cable fault with a fast step to 20V can result
in ringing on V up to 40V due to energy built up in the
cable inductanIcNe and the switching regulator inductor.
The 42V V abs max withstands this ringing, but a cable
IN
Rev. A
25
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
fault above 20V could violate the V abs max spec and
Please refer to Table 6 for a lookup table linking the SEL1-3
pin states to the selected LT8698S states.
IN
damage the IC due to inductive ringing. This damage to
V can occur despite the 42V abs max rating of the V
IN
BUS
Dataline Switches
output pins OUT/ISP, BUS/ISN and USB5V. Figure 9 shows
a fast output hot plug to 20V.
The LT8698S includes two High Speed USB 2.0 compli-
ant analog switches. These switches are placed in series
with the USB D+ and D– datalines between the USB socket
+
ꢀ
ꢁꢂ
and the host µController. The switches connect the HD
ꢀꢁꢂꢃꢄꢅꢂ
+
–
–
ꢀꢁꢂ ꢃAꢄꢅꢆ Aꢇꢇꢅꢈꢉꢊ ꢆꢋ
ꢄꢅRꢆꢂꢇꢅ ꢈꢉ Aꢊꢇ
pin to the LD pin and the HD pin to the LD pin of the
LT8698S. The switches disconnect to protect the host
from an up to 20V fault or an ESD strike on the dataline.
The switches also disconnect when commanded to do so
by the SEL1-3 pin inputs, such as when muxing in one of
the various charger emulation profiles.
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢂ
ꢀꢁ ꢂꢃꢄꢅꢂꢆꢇ ꢈAꢄR ꢉAꢊꢋꢆ
ꢀꢁ
ꢂꢃꢄ
ꢀꢁAꢂꢃꢄꢅ
ꢀꢁ
ꢀ
ꢀꢁAꢂꢃꢄꢅ
ꢀꢁꢂꢀꢃ ꢄꢅꢂ
ꢀꢁꢂꢃꢄꢅꢆꢇ
+
Figure 9. 20V Fault on VBUS
The USB 2.0 specification document requires that the D
–
and D datalines maintain a characteristic impedance in
the PCB traces and be terminated for high speed 480Mb/s
communication. Specifically, the dataline single ended
impedance for D+ and D– to PCB ground is 45Ω and
Select Pins SEL1, SEL2, SEL3
The select pins SEL1-3 are tristate input pins intended to
interface with a USB host μController. These pins select
+
–
the differential impedance across D to D is 90Ω. The
LT8698S datalines switches and package have 3Ω typical
series resistance and present about 6pF parallel capaci-
tance at high frequency from each dataline to ground. The
3Ω of real resistance from the RDS(ON) of the switches
is small enough relative to the 45Ω termination to not
cause a signal integrity problem on the eye diagram. To
eliminate signal reflections on the dataline from the 6pF
capacitive discontinuity created by the dataline switches,
+
–
the operational state of the LT8698S's HD and HD pins
tied to the USB datalines D+ and D–. If dynamic state
changes are not desired, the select pins may individually
be tied low, high or left open to select a single LT8698S
state. The select pins also can disable the switching regu-
lator for USB On-The-Go (OTG) functionality and can initi-
ate a 9mA active discharge of the USB V
rail.
BUS
Each select pin has a resistive divider tied from INTV
CC
+
–
–
–
add four small inductors between HD , HD , LD and LD
to GND that biases the pin to 1V when left floating. Tie
and the corresponding dataline PCB trace. Place these
inductors as close as possible to the LT8698S. The total
series inductance on each dataline should be about 20nH
for good impedance matching, so 10nH on each dataline
below 0.48V for input low. Tie above 1.51V or to INTV
CC
for input high. Float with less than 1μA of leakage current
for the tristate, high Z input. The select pin inputs are de-
bounced for 1.5ms prior to passing the pin input state to
the internal state machine.
+
–
+
–
pin HD , HD , LD and LD is recommended. Minimum
10nH inductor tied in series to HD+, HD–, LD+ and LD– are
required for robustness to IEC61000-4-2 ESD strikes to
The function of the STATUS output pin depends on the
state selected by the SEL1-3 pins. The function of the FLT
pin also can depend on the state selected by the SEL1-3
pins. For the bus reset functions accessed by select state
5, 11, 14 and 20 with VBUS not powered, FLT can pull
+
–
the HD and HD pins.
To further ensure good high speed USB 2.0 signal integrity,
the dataline bandwidth is production-tested on all parts.
low due to V
pin function.
too high, in addition to the normal FLT
BUS
Rev. A
26
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
Table 6. Select Pin Lookup Table
SELECT PIN INPUT
SEL1 SEL2 SEL3 STATE
SELECT
VBUS
STATE
STATE NAME
HD+ STATE
HD– STATE
STATUS FUNCTION
LOW LOW LOW
TRI LOW LOW
HIGH LOW LOW
LOW TRI LOW
0
1
2
USB CDP 1
5V
5V
5V
CDP Sequence,
CDP Sequence,
Indicates CDP State
+
–
Short to LD
Short to LD
USB CDP 2
USB CDP 3
CDP Sequence with 20k to CDP Sequence with 20k to Indicates CDP State
GND, Then Short to LD
+
–
GND, Then Short to LD
+
–
Short to LD
Short to LD
Indicates Successful
CDP Negotiation
+
–
3
4
5
USB SDP 1
USB SDP 2
USB SDP 3
0V
5V
Short to LD , 20k to GND Short to LD , 20k to GND Indicates V
Voltage
Current
BUS
+
–
TRI
TRI LOW
Short to LD , 20k to GND Short to LD , 20k to GND Indicates I
BUS
+
–
HIGH TRI LOW
Discharge Short to LD , 20k to GND Short to LD , 20k to GND Indicates V
BUS
Discharge State
LOW HIGH LOW
TRI HIGH LOW
HIGH HIGH LOW
LOW LOW TRI
6
7
8
9
Null
Null
Null
5V
5V
5V
0V
Open
Open
Open
Open
Oscillates
Oscillates
Open
Open
Oscillates
+
+
+
–
–
–
V
V
Off with Data
Pass Through
Short to LD
Short to LD
Indicates V
Voltage
Current
BUS
BUS
TRI LOW TRI
HIGH LOW TRI
10
11
On with Data
Pass Through
5V
Short to LD
Short to LD
Short to LD
Short to LD
Indicates I
BUS
BUS
V
Off and
Discharge
Indicates V
BUS
Discharge State
BUS
Discharged with Data
Pass Through
LOW TRI
TRI TRI
TRI
TRI
12
13
V
Off
0V
5V
Open
Open
Open
Open
Indicates V Voltage
BUS
BUS
V
On without
Reset State, STATUS Pin
Indicates I
BUS
Data Pass Through
BUS
HIGH TRI
TRI
14
V
Off and
Discharge
Open
Open
Indicates V
BUS
Discharge State
BUS
Discharged without
Data Pass Through
LOW HIGH TRI
TRI HIGH TRI
HIGH HIGH TRI
LOW LOW HIGH
TRI LOW HIGH
HIGH LOW HIGH
15
16
17
18
19
20
Null
Null
5V
5V
Open
Open
Open
Open
Open
Open
Oscillates
Oscillates
Oscillates
Null
5V
USB SDP 4
USB SDP 5
USB SDP 6
0V
20k to GND
20k to GND
20k to GND
20k to GND
20k to GND
20k to GND
Indicates V
Voltage
Current
BUS
5V
Indicates I
BUS
Discharge
Indicates V
BUS
Discharge State
–
+
LOW TRI HIGH
21
22
USB DCP
5V
5V
Short to HD , 500k to GND
Short to HD
Short to HD
Indicates I
Indicates I
Current
Current
BUS
BUS
–
+
TRI
TRI HIGH
2.0A Charger
Short to HD , 1.25V
V
Divider
BUS
HIGH TRI HIGH
LOW HIGH HIGH
TRI HIGH HIGH
HIGH HIGH HIGH
23
24
25
26
Null
5V
5V
5V
5V
Open
Open
Oscillates
Indicates I
Indicates I
Indicates I
2.4A Charger
2.1A Charger
1.0 Charger
2.7V V
2.7V V
2.0V V
Divider
2.7V V
2.0V V
2.7V V
Divider
Divider
Divider
Current
Current
Current
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
Divider
Divider
Rev. A
27
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
Internal diodes are connected between each pin, HD+ and
–
HD , to both CLAMP and ground as shown in Figure 10. In
+
a similar way, internal diodes also connect each pin, LD
–
and LD to both INTV and ground. These diodes pro-
tect the host side dataline pins during ESD events. High
speed comparators on the HD and HD pins disconnect
the dataline switches if the voltage on the datalines is too
high. This disconnect threshold is a diode above 4.3V.
CC
ꢀ
ꢀꢁAꢂꢃ
ꢀꢁꢂꢃꢄꢁ
+
–
R
= 50Ω
ꢀꢁꢂ
ꢀꢁꢂꢀꢃ ꢄꢅꢅ
ꢀꢁꢂꢃꢄꢅꢆ
Figure 11. IEC61000-4-2 15kV Air Discharge ESD Strike
Tie a 0.1µF ceramic cap with at least a 25V rating from
the CLAMP pin to GND for robust ESD and DC fault
performance.
ꢀꢁꢂꢃꢄꢄ
ꢀꢁAꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃꢄꢄ
ꢀꢁꢂꢃ
ꢀ.ꢁꢂꢃ
Fast cable faults can result in overshoot over the fault
voltage on the HD+, HD– and CLAMP pins due to the cable
inductance. A zener clamp diode can also be added from
CLAMP to ground in parallel with the 0.1µF cap to limit
excessive voltage overshoot from a DC fault with a fast
step. Ensure that the zener breakdown voltage exceeds
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
LT8698S
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
+
the maximum desired DC fault voltage on the HD and
–
Figure 10. Dataline Switches
HD pins under all operating conditions for robust opera-
tion. Diodes Inc DFLT22A or equivalent is a good choice.
Figure 12a shows an example CLAMP circuit for robust
tolerance to fast 20V cable faults to HD+ and HD–. See
Figure 12b for a oscilloscope capture showing a fast 20V
fault applied to HD+ through 3m of AWG 24 twisted pair
cable with the Figure 12a CLAMP circuit.
An integrated charge pump provides the voltage required
to bias the NMOS gates of the dataline switches. This
charge pump takes about 1ms to fully turn on the data-
line switches after commanded to do so by the SEL1-3
pins state.
Clamp Pin
CDP Modes of Operation
The CLAMP pin connects to the cathodes of two large
diodes connected to HD+ and HD–. For positive ESD
strikes on the datalines, high ESD current is shunted
from the dataline through the diodes to the CLAMP pin.
The capacitor on the clamp pin absorbs this energy,
and a resistive divider on the CLAMP pin dissipates this
energy over about 10ms. For an 8kV Contact Discharge
IEC61000-4-2 ESD strike to HD or HD , the CLAMP pin
will increase in voltage momentarily from 4V to about 18V
and then decay back down to 4V. See Figure 11 for a oscil-
loscope capture of this ESD event. Window comparators
on the CLAMP pin disconnect the dataline switches if the
CLAMP voltage is > 4.3V.
The LT8698S integrates the necessary hardware to imple-
ment the USB BC 1.2 Charging Downstream Port (CDP)
charger profile. This mode of operation allows compliant
devices to draw high current of up to 1.5A from VBUS
while simultaneously communicating with the host at high
speed. CDP operates by inserting a simple handshake
sequence into the normal USB connection sequence
between a host and a portable device.
+
–
Per Table 6, select states 0, 1 and 2 operate CDP. Select
state 0 performs the CDP sequence with the dataline
switches closed and without termination. Select state 0
assumes the host µController will properly terminate the
datalines for a USB connection and will otherwise not
Rev. A
28
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
CDP connection in progress. While the STATUS pin oscil-
lates, the select pins are locked out from changing the
LT8698S state.
CLAMP
D
CLMP
C
CLMP
DFLT22A
0.1μF
8698S F12a
The device will then remove the voltage source from D+
–
and the current source from D and place a 100µA cur-
(a) CLAMP Circuit to Reduce Overshoot
+
–
rent source on D and a 0.6V voltage source on D for
40ms. The LT8698S will respond by removing the 0.6V
–
–
voltage source from D . The LT8698S will monitor D to
see if the 0.6V voltage source is present for 40ms. This
is secondary detection, and it indicates that the host port
is CDP capable. The STATUS pin will continue to oscillate
and the select pins will continue to be locked out.
ꢂ
20V FAULT APPLIED TO
ꢀꢁ
+
HD THROUGH 3m AWG
ꢀꢁꢂꢃꢄꢅꢂ
24 TWISTED PAIR CABLE
ꢀꢁAꢂꢃ
ꢀꢁꢂꢃꢄꢅꢂ
ꢀ
HD+
ꢀAꢁꢂꢃꢄ
The device can now charge from V
at up to 1.5A and
BUS
ꢀ
LD+
+
LD 50Ω TO GND
+
–
ꢀ.ꢁAꢂꢃꢄꢅ
proceed to enumerate, pulling either D or D above logic
high to initiate a USB connection and to indicate the speed
ꢀꢁꢂꢀꢃ ꢄꢅꢆꢇ
1μs/DIV
+
–
(b) 20V Fault on HD+
of the connection. When either D or D is pulled above
logic high, the LT8698S will remove the 100µA current
+
Figure 12. Cable Faults
source from D and the STATUS pin will stop oscillating
and stay high, indicating that the CDP sequence is done.
When STATUS is not oscillating, the select pins are no
longer locked out.
interfere with the LT8698S CDP sequence. Select state
0 keeps the dataline switches closed. Select state 1 per-
forms the CDP sequence with the dataline switches open
This enumeration must occur within 1s of the initial attach
+
–
and 20k termination resistors tied from HD and HD to
GND. Select state 1 allows the LT8698S to handle the CDP
sequence independently of the host µController and only
connects the dataline switches after the CDP sequence
is complete or the portable device attempts a connection
without CDP. In select state 1, after the CDP sequence
is complete, the internal 20k termination resistors are
removed from the datalines and the dataline switches
are closed.
+
when D is pulled to 0.6V or the LT8698S will stop the
CDP handshake and return to the initial CDP state, wait-
+
–
ing for a connection. If the device pulls D or D above
logic high during the CDP sequence before the sequence
is completed, the LT8698S will interpret that the device is
not CDP capable, will stop the CDP sequence, and indicate
that the CDP handshake failed.
+
–
D or D pulled above logic high will end the CDP hand-
shake sequence. To restart CDP, the select pins must input
any state other than select state 0, 1, or 2 and then be
returned to the desired CDP input state.
When CDP is selected with either select 0 or select 1
states, the LT8698S connects a 100µA current source to
+
D , asserts STATUS low and waits for a device to attach to
Select state 2 allows the user to query if the CDP hand-
shake sequence was successful or not. It is intended to
be used after a portable device connects during select state
0 or 1. It does not affect the datalines, but after a con-
nection, the STATUS pin will indicate if a successful CDP
sequence was completed. While select state 2 is selected,
STATUS high indicates a successful CDP connection, and
STATUS low indicates an unsuccessful CDP connection.
If select 2 is selected with neither select 0 nor 1 states
the USB socket. Once a device is attached, a CDP compli-
+
ant device will place a 0.6V voltage source on D and a
–
100µA current source on D for 40ms. The LT8698S will
recognize 0.6V on D+ and will apply a 0.6V voltage source
–
to D within 20ms. This is CDP primary detection, and
it indicates that the host port is either CDP or dedicated
charger Port (DCP) capable. The LT8698S will also start
to oscillate the STATUS pin with a 9ms period to indicate a
Rev. A
29
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
having been selected nor a USB connection made, select
2 cannot return a valid response. In this case, select state
2 indicates an invalid response with a 9ms oscillation on
the STATUS pin. Selecting any state other than select state
0, 1, or 2 clears the CDP connection information from the
internal register.
closed. These data pass through modes differ by allow-
ing the user to power V , not power V or discharge
BUS
BUS
BUS
V
. See Table 6.
For data pass through mode of operation with VBUS in reg-
ulation (select state 10), STATUS high indicates I load
BUS
> 120mA and STATUS low indicates I
load <100mA.
BUS
Refer to Figure 13 and Figure 14 for a timing diagram
of a successful CDP handshake sequence. Note, the
LT8698S will report an unsuccessful CDP session if a
portable device takes longer than 1 second to enumerate
and connect. Select 2 accuracy can depend on a portable
device's compliance to the USB specification, state, and
configuration.
For data pass through mode of operation with V
dis-
BUS
abled (select state 9), STATUS high indicates VBUS < 0.5V
and STATUS low indicates V > 0.85V. For data pass
BUS
through mode of operation with V
being discharged
BUS
(select state 11), the STATUS pin indicates the discharge
state. Refer to the Bus Reset Modes of Operation section
for more details.
SDP Modes of Operation
Charger Modes of Operation
The LT8698S implements the USB BC 1.2 Specification
Standard Downstream Port (SDP). This is the most com-
mon USB host configuration and allows a device to draw
up to 500mA of charge current. Select state 3, 4, 5, 18,
19 and 20 activate various versions of the LT8698S SDP
modes. What is common to these states is the termination
The LT8698S implements several common USB char-
ger profiles. These charger profiles have the datalines
switches open and do not allow data communication.
These charger profiles allow compatible devices to draw
I
current in excess of the 0.5A that a standard USB
BUS
socket allows. The LT8698S includes the USB BC 1.2
Dedicated Charger Port (DCP) profile and vendor propri-
etary 2.0A, 2.4A, 2.1A and 1.0A profiles. These profiles
tie various combinations of resistor dividers from VBUS to
the datalines or short the datalines together. See Table 6.
+
–
pull-down resistors that LT8698S places from D and D
to ground. The SDP modes differ by allowing the user to
open or close the dataline switches, to power V , not
BUS
power V
or discharge V . See Table 6.
BUS
BUS
For SDP modes of operation with VBUS in regulation
(select states 4 and 19), STATUS high indicates I load
Select state 21 accesses the USB BC 1.2 DCP profile. This
+
–
mode of operation connects a 100Ω short from D to D
BUS
>120mA and STATUS low indicates IBUS load <100mA.
and a 500kΩ resistor from D+ and D– to ground. This state
allows compatible devices to draw 1.5A of charge current.
For SDP modes of operation with V
disabled (select
states 3 and 18), STATUS high indiBcUatSes V
< 0.85V
BUS
Select state 22 accesses the 2.0A vendor charger profile.
and STATUS low indicates V
> 0.85V. For SDP modes
+
BUS
This mode of operation connects a 100Ω short from D
of operation with V
being discharged (select states 5
–
+
BUS
to D and a 1.25V resistive divider from V
to D and
BUS
and 20), the STATUS pin indicates the discharge state.
Refer to the Bus Reset Modes of Operation section for
more details.
–
D . This state allows compatible devices to draw 2.0A of
charge current.
Select State 24 accesses the 2.4A vendor charger profile.
This mode of operation connects two separate 2.7V resis-
Data Pass Through Modes of Operation
+
–
tive dividers from V
to D and D . This state allows
BUS
The LT8698S implements several modes of operation that
close the dataline switches to allow data to pass through
the LT8698S but otherwise do not tie any resistor termi-
nation to the datalines. Select states 9, 10 and 11 activate
various versions of the data pass through modes. What is
common to these states is that the dataline switches are
compatible devices to draw 2.4A of charge current.
Select State 25 accesses the 2.1A vendor charger profile.
This mode of operation connects a 2.7V resistive divider
+
from V
to D and a 2.0V resistive divider from V
BUS
BUS
Rev. A
30
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
ꢉꢘARꢙꢈꢏꢙ ꢆꢇꢀꢈꢉꢇ ꢑꢒRꢅ ꢄꢉꢆꢑꢊ ꢅꢈꢚꢈꢏꢙ ꢆꢈAꢙRAꢚ
ꢟꢀ
ꢍꢀ
ꢀ
ꢑꢒRꢅAꢁꢓꢇ
ꢆꢇꢀꢈꢉꢇ
ꢁꢂꢃ
ꢄAꢅ ꢆꢇꢀꢈꢉꢇꢊ
ꢌ.ꢟA
ꢠ.ꢟꢡA
ꢍA
ꢈ
ꢁꢂꢃ
ꢋ
ꢒꢢ
ꢒꢣꢣ
ꢆ
ꢌꢍꢍꢎA ꢈ
ꢃꢈꢏꢐ
ꢃꢈꢏꢐ
ꢤ
ꢒꢢ
ꢒꢣꢣ
ꢆ
ꢌꢍꢍꢎA ꢈ
ꢤ
ꢋ
ꢒꢢ
ꢒꢣꢣ
ꢆ
ꢦꢆ ꢑꢂꢓꢓꢂꢑ
ꢋ
ꢒꢢ
ꢒꢣꢣ
ꢆ
ꢍ.ꢕꢀ ꢀ
ꢃꢒꢂRꢉꢇ
ꢤ
ꢒꢢ
ꢒꢣꢣ
ꢆ
ꢍ.ꢕꢀ ꢀ
ꢃꢒꢂRꢉꢇ
ꢧꢨꢍꢡꢩ
ꢧꢨꢍꢡꢩ
ꢅꢈꢚꢇ
ꢪꢌꢩ
ꢋ
ꢆ
ꢠꢀ
ꢍ.ꢕꢀ
ꢍꢀ
ꢤ
ꢆ
ꢠꢀ
ꢍ.ꢕꢀ
ꢍꢀ
ꢒꢢ
ꢒꢣꢣ
ꢉꢆꢑꢌꢦꢠ
ꢉꢆꢑꢞ
ꢎꢉꢒꢏꢅRꢒꢓꢓꢇR
ꢈꢏꢑꢂꢅ ꢅꢒ
ꢓꢅꢔꢕꢖꢔꢃ
ꢃꢇꢓꢄꢗꢊ ꢑꢈꢏꢃ
ꢒꢢ
ꢒꢣꢣ
ꢋ
ꢒꢢ
ꢒꢣꢣ
ꢓꢅꢔꢕꢖꢔꢃ
ꢉꢘARꢙꢈꢏꢙ
ꢑꢒRꢅ
ꢆ
ꢌꢍꢍꢎA ꢈ
ꢃꢈꢏꢐ
ꢤ
ꢆ
ꢍ.ꢕꢀ ꢀ
ꢒꢢ
ꢒꢣꢣ
ꢃꢒꢂRꢉꢇ
ꢒꢢ
ꢒꢣꢣ
ꢆAꢅAꢓꢈꢏꢇ ꢚꢂꢗ
ꢒꢢ
ꢒꢣꢣ
ꢆAꢅAꢓꢈꢏꢇ ꢃꢛꢈꢅꢉꢘ
ꢄꢉꢆꢑꢠ ꢒꢏꢓꢥꢊ
ꢃꢅAꢅꢂꢃ
ꢒꢢ
ꢒꢣꢣ
ꢔꢕꢖꢔꢃ ꢝꢌꢌ
ꢪꢠꢍꢡꢩ
ꢫꢖꢡꢩ
ꢪꢌꢍꢡꢩ
ꢅꢈꢚꢇ
ꢉꢒꢚꢚꢇꢏꢅꢃ
ꢃꢅAꢅꢂꢃ ꢆꢉ ꢓꢒꢛ ꢈꢏꢆꢈꢉAꢅꢇꢃ ꢏꢒ
ꢉꢒꢏꢏꢇꢉꢅꢈꢒꢏ
ꢃꢅAꢅꢂꢃ ꢒꢃꢉꢈꢓꢓAꢅꢈꢏꢙ ꢈꢏꢆꢈꢉAꢅꢇꢃ
ꢉꢒꢏꢏꢇꢉꢅꢈꢒꢏ ꢈꢏ ꢑRꢒꢙRꢇꢃꢃꢜ
ꢃꢇꢓꢄꢗꢊ ꢑꢈꢏ ꢓꢒꢉꢐꢇꢆ ꢒꢂꢅ
ꢃꢅAꢅꢂꢃ ꢆꢉ ꢘꢈꢙꢘ ꢈꢏꢆꢈꢉAꢅꢇꢃ
ꢉꢒꢏꢏꢇꢉꢅꢈꢒꢏ ꢆꢒꢏꢇꢜ ꢉꢆꢑ
ꢉꢒꢚꢑꢒꢏꢇꢏꢅꢃ ꢓAꢅꢉꢘꢇꢆ ꢒꢝꢝ
ꢃꢅAꢅꢂꢃ ꢆꢉ ꢘꢈꢙꢘ ꢛꢈꢅꢘ ꢉꢆꢑꢞ
ꢃꢇꢓꢇꢉꢅꢇꢆ ꢈꢏꢆꢈꢉAꢅꢇꢃ ꢃꢂꢉꢉꢇꢃꢝꢂꢓ
ꢉꢆꢑ ꢉꢒꢏꢏꢇꢉꢅꢈꢒꢏ
Figure 13. CDP Timing Diagram
ꢀ.ꢁA ꢂꢃARꢄꢅꢆꢄ ꢂꢇRRꢈꢆꢉ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ ꢃꢄꢅꢅꢆ
ꢀꢁꢂ ꢃ.ꢄ
ꢀAꢁA
ꢀAꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ ꢁ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁAꢁꢂꢀ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
Figure 14. CDP Sequence
Rev. A
31
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
–
to D . This state allows compatible devices to draw 2.1A
To initiate a bus reset sequence, normally the LT8698S
is in a state with V powered up. The select pin's input
of charge current.
BUS
state is then changed to the desired BUS reset mode.
Select State 26 accesses the 1.0A vendor charger profile.
Within 1.5ms, switching stops and the LT8698S stops
This mode of operation connects a 2.0V resistive divider
delivering power to the V
output. Also, a 9mA current
+
BUS
from V
to D and a 2.7V resistive divider from V
BUS
BUS
sink is connected from BUS/ISN to GND. The LT8698S
will also start to oscillate the STATUS pin with a 9ms
period to indicate a bus reset sequence in progress. While
the STATUS pin oscillates, the select pins are locked out
from changing the LT8698S state.
–
D . This state allows compatible devices to draw 1.0A of
charge current.
For charger modes of operation (select states 21, 22, 24,
25 and 26), STATUS high indicates IBUS load >120mA and
STATUS low indicates I
load <100mA.
BUS
The LT8698S discharges VBUS with the 9mA current
sink for 400ms. After 400ms, the LT8698S turns off the
current sink and measures the resultant VBUS voltage
V
BUS
Only Modes of Operation
The LT8698S implements several modes of operation that
manipulate VBUS but leave the datalines switches open
and do not tie any resistor termination to the datalines.
Select states 12, 13 and 14 activate various versions of
for 120ms. If V
is < 0.5V for 120ms, the discharge
BUS
sequence is completed successfully. If V
is > 0.85V at
BUS
any point during this 120ms time, the discharge sequence
is completed unsuccessfully.
the V
only modes. What is common to these states
BUS
When the discharge sequence is complete, the STATUS
pin stops oscillating and pulls high, indicating that the
bus reset is done and that the select pins are no longer
locked out. If the bus reset was completed successfully,
the FLT pin does not change state. If the bus reset was not
completed successfully, the FLT pin pulls low for 4.2ms.
is that the dataline switches are open. These V
only
BUS
modes differ by allowing the user to power V , not
power V
BUS
or discharge V . See Table 6.
BUS
BUS
For the V
only modes of operation with V
in regu-
BUS
BUS
BUS
lation (select state 13), STATUS high indicates I
load
>120mA and STATUS low indicates IBUS load <100mA.
For VBUS only mode of operation with VBUS disabled
(select state 12), STATUS high indicates V
STATUS low indicates V
of operation with V
the STATUS pin indicates the discharge state. Refer to the
Bus Reset Modes of Operation section for more details.
Refer to Figure 15 and Figure 16 for a timing diagram of
unsuccessful and successful BUS reset sequences.
< 0.5V and
only mode
BUS
> 0.85V. For V
BUS
BUS
V
BUS
Off Modes of Operations
being discharged (select state 14),
BUS
The LT8698S is compatible with the USB On-The-Go
(OTG) and Embedded Host 2.0 Specification. This speci-
fication allows hosts and peripheral devices to exchange
Bus Reset Modes of Operation
roles. This role exchange means that V
may be driven
BUS
by the peripheral device on the B side of the USB con-
nection. The LT8698S offers VBUS off modes of operation
The LT8698S implements several modes of operation that
discharge V . Select states 5, 11, 14 and 20 activate
BUS
with a high input resistance on V
that allow a portable
BUS
various versions of this V
reset mode. What is com-
BUS
device to drive V . The LT8698S does not support the
BUS
mon to these states is that the switcher stops delivering
Attach Detect Protocol (ADP) on the A side, but as a piece
of the A side device the LT8698S is compatible with ADP
on the B side.
power to the V
output, a 9mA current sink is tied from
BUS
BUS/ISN to GND for 400ms, and the FLT pin can indicate
an unsuccessful discharge for 4.2ms at the end of the
discharge cycle. These V
reset modes differ by tying
Select state 3, 9, 12 and 18 activate various versions of
BUS
various resistor terminations to the datalines or by open-
the LT8698S V
off modes. What is common to these
BUS
ing or closing the dataline switches. See Table 6.
states is that switching is disabled and that the VBUS
input resistance is > 10kΩ. The V
off modes differ by
BUS
Rev. A
32
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
ꢃ
Rꢌꢆꢌꢎ ꢎꢈꢙꢈꢏꢋ ꢇꢈAꢋRAꢙ
ꢄꢅꢆ
ꢃ
ꢄꢅꢆ
ꢇꢈꢆꢉꢊARꢋꢌ
ꢑꢉꢀꢏꢎRꢀꢐꢐꢌR
ꢈꢏꢒꢅꢎ ꢎꢀ ꢐꢎꢓꢔꢕꢓꢆ
ꢆꢌꢐꢖꢗꢘ ꢒꢈꢏꢆ
ꢀꢁ
ꢀꢂꢂ
ꢆꢍꢈꢎꢉꢊꢈꢏꢋ RꢌꢋꢅꢐAꢎꢀR ꢀꢁ
ꢀꢂꢂ
ꢐꢎꢓꢔꢕꢓꢆ
ꢖꢚꢛA ꢈ
ꢀꢁ
ꢀꢂꢂ
ꢄꢅꢆ
ꢀꢁ
ꢀꢂꢂ
FLT
ꢀꢁ
ꢀꢂꢂ
ꢆꢎAꢎꢅꢆ
ꢜꢃ
ꢚꢃ
ꢃ
ꢄꢅꢆ
ꢣꢡꢛꢢ
ꢕꢛꢢ
ꢣꢠꢚꢚꢛꢢ
ꢣꢠ.ꢜꢛꢢ
ꢣꢡꢛꢢ
ꢕꢛꢢ
ꢎꢈꢙꢌ
ꢤꢜꢡꢚꢛꢢ
ꢅꢏꢆꢅꢉꢉꢌꢆꢆꢝꢅꢐ
ꢆꢎAꢎꢅꢆ ꢊꢈꢋꢊ ꢈꢏꢇꢈꢉAꢎꢌꢆ ꢃ
ꢇꢈꢆꢉꢊARꢋꢌ ꢉꢞꢉꢐꢌ ꢉꢀꢙꢒꢐꢌꢎꢌꢟ
FLT ꢒꢅꢐꢐꢆ ꢐꢀꢍ ꢝꢀR ꢠ.ꢡꢛꢢ ꢎꢀ
ꢆꢅꢉꢉꢌꢆꢆꢝꢅꢐ
Rꢌꢆꢌꢎ
ꢆꢎAꢎꢅꢆ ꢊꢈꢋꢊ ꢈꢏꢇꢈꢉAꢎꢌꢆ ꢃ
ꢄꢅꢆ
ꢉꢀꢙꢙꢌꢏꢎꢆ
ꢄꢅꢆ
ꢃ
Rꢌꢆꢌꢎ
ꢃ
ꢇꢈꢆꢉꢊARꢋꢌ ꢉꢞꢉꢐꢌ ꢉꢀꢙꢒꢐꢌꢎꢌꢟ
ꢄꢅꢆ
ꢄꢅꢆ
Aꢎꢎꢌꢙꢒꢎ
Aꢎꢎꢌꢙꢒꢎ
FLT ꢆꢎAꢞꢆ ꢊꢈꢋꢊ ꢎꢀ ꢈꢏꢇꢈꢉAꢎꢌ
ꢈꢏꢇꢈꢉAꢎꢌ ꢃ
ꢆꢅꢉꢉꢌꢆꢆꢝꢅꢐ
ꢇꢈꢆꢉꢊARꢋꢌ ꢏꢀꢎ
ꢃ
ꢇꢈꢆꢉꢊARꢋꢌ ꢆꢅꢉꢉꢌꢆꢆꢝꢅꢐ
ꢄꢅꢆ
ꢄꢅꢆ
Figure 15. VBUS RESET Diagram
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢇꢈꢆꢇ ꢉAꢈ
ꢀꢀꢁꢂ ꢃꢄꢅꢆꢄꢅ ꢇAꢆ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄꢁ
ꢀꢀꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢁ
ꢀꢀꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁAꢁꢂꢀ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁAꢁꢂꢀ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢀꢃ ꢄꢅꢁꢆ
ꢀꢁꢂꢀꢃ ꢄꢅꢁꢆ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
(b) Successful Bus Reset
(a) Unsuccessful Bus Reset
Figure 16. VBUS RESET Sequence
Rev. A
33
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
allowing the user terminate the datalines with 20k and
open or close the dataline switches in any combination.
See Table 6.
currents flow in the LT8698S’s V pins, PGND pins, and
IN
the input capacitors. The loop formed by the input capaci-
tor should be made as small as possible by placing the
capacitor adjacent to the V and PGND pins. When using
a physically large input caIpNacitor the resulting loop may
become too large in which case using a small case/value
For V
BUS
off modes of operation, STATUS high indicates
BUS
V
< 0.5V and STATUS low indicates V
> 0.85V.
BUS
capacitor placed close to the V and PGND pins plus a
IN
Null Modes of Operation
larger capacitor further away is preferred. These com
-
The LT8698S does not use all of the 27 possible select pin
tristate input combinations. The unused select states are
states 6, 7, 8, 15, 16, 17 and 23. These unused states are
called Null states in Table 6. These null states all behave
the same. The switching regulator is active and power-
ponents, along with the inductor and output capacitor,
should be placed on the same side of the circuit board,
and their connections should be made on that layer. Place
a local, unbroken ground plane under the application cir-
cuit on the layer closest to the surface layer. The SW and
BST nodes should be as small as possible. Finally, keep
the USB5V and RT nodes short and use ground traces
to shield them from the SW and BST nodes as needed.
ing V , the dataline switches are open with no resis-
BUS
tor termination tied to the datalines, and the STATUS pin
oscillates at 9ms indicating an invalid select state.
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LT8698S. The exposed pads on
the bottom of the package must be soldered to a ground
plane. This ground should be tied to large copper layers
below with thermal vias; these layers will spread heat
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 17 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
ꢀ
ꢁꢂꢃꢄ
ꢀ
ꢁꢂꢃꢄ
R
ꢀꢁꢂ
ꢀ
ꢀ
ꢁꢂꢃꢄ ꢁꢂꢃꢄ
ꢀ
ꢁꢂꢃꢄ
ꢀꢁ
ꢀ
ꢁꢂꢃꢄꢀꢀ
ꢀ
ꢀꢁꢀ
R
ꢀꢁꢀ
R
ꢀꢁꢂ
R
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢀꢃ ꢄꢅꢆ
Figure 17. Recommended PCB Layout
Rev. A
34
For more information www.analog.com
LT8698S/LT8698S-1
APPLICATIONS INFORMATION
dissipated by the LT8698S. Placing additional vias can
reduce thermal resistance further.
is exceeded. The thermal shutdown temperature is above
the maximum operating temperature and is only intended
to help protect the LT8698S during an overload condition.
Use good 4-point Kelvin PCB layout for the R
resistor
SEN
and the associated connections to OUT/ISP and BUS/ISN
pins. This resistor is only 8 to 10mΩ, so stray PCB resis-
tance can easily add a temperature dependent error to the
resistance seen by the OUT/ISP and BUS/ISN, producing
inaccurate cable drop compensation and output current
limit. Route the high current path from the inductor to
Temperature rise of the LT8698S is highest when operat-
ing at high load, high V , and high switching frequency.
IN
If the case temperature is too high for a given application,
then either V , switching frequency or load current can
IN
be decreased to reduce the temperature to an acceptable
level. Figure 18 shows the LT8698S junction temperature
under common operating conditions measured for a typi-
cal part using demo board DC2688A.
the R
resistor and from the R
resistor to the V
SEN
SEN BUS
power output separately from the OUT/ISP and BUS/ISN
pin connections. Keep high current off of the traces to the
OUT/ISP and BUS/ISN pins.
Since the LT8698S temperature rise depends on these
operating conditions and also on the PCB layout, airflow
over the IC, and possibly on other nearby heat sources
on the PCB, careful evaluation of a given application is
required to ensure that the LT8698S does not exceed its
maximum junction temperature rating.
The exposed pads act as a heat sink and are connected
electrically to ground. To keep thermal resistance low,
extend the ground plane as much as possible, and add
thermal vias under and near the LT8698S to additional
ground planes within the circuit board and on the bottom
side. See Figure 17 for example PCB layout.
ꢀꢁꢁ
ꢀ
ꢀꢁ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁ
High Temperature Considerations
The maximum load current the LT8698S delivers must
be de-rated as the ambient temperature approaches the
maximum junction temperature rating. Power dissipa-
tion within the LT8698S can be estimated by calculating
the total power loss from an efficiency measurement and
subtracting the inductor loss. The die temperature is cal-
culated by multiplying the LT8698S power dissipation by
the thermal resistance from junction to ambient.
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ ꢄ ꢅ
ꢀ ꢁꢂ ꢄ ꢅ
ꢀ ꢁꢂ ꢄ ꢅ
ꢀ ꢁꢂ ꢄ ꢅ
ꢀ ꢁA
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ ꢁA
ꢀ ꢁ.ꢂA
ꢀ ꢁ.ꢂA
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ
Aꢀꢁꢂꢃꢄꢅ ꢅꢃꢀꢆꢃRAꢅꢇRꢃ ꢈꢉꢊꢋ
ꢀꢁꢂꢀꢃ ꢄꢅꢀ
Figure 18. Junction Temperature Rise (DC2688A Demo
Board with RSEN = 8mΩ)
The LT8698S will stop switching and indicate a fault
condition if the internal thermal shutdown temperature
Rev. A
35
For more information www.analog.com
LT8698S/LT8698S-1
TYPICAL APPLICATIONS
Automotive USB BC1.2 CDP Charger with High Speed Dataline Protection and Cable Drop Compensation
V
IN
C
6V TO 42V
VIN
2.2µF
1206
L1
2.2µH
R
10m
SEN
V
IN
HIGH SPEED
USB HOST
µCONTROLLER
EN/UV
SW
C
OUT
INTV
CC
C
22µF
1206
INTVCC
1.0µF
R
100K
R
100K
STAT
FLT
LT8698S
I/O READ BACK FAULT
AND CDP STATE
FLT
OUT/ISP
BUS/ISN
STATUS
SEL1-3
R
CDC
USB5V
2k
C
4.7nF
CDC
3 METER
USB CABLE
R1
USB
SOCKET
I/O SELECT AND
OPERATE CDP
Z
= 90Ω
Z
= 90Ω
V
O
O
BUS
10nH
10nH
DIFFERENTIAL
DIFFERENTIAL
+
+
0.1Ω
+
+
LD
D
D
HD
–
–
–
–
LD
D
D
HD
10nH
R
R2
10nH
C
CLAMP
GND PGND
ADC READS I
BUS
RCBL
RT
GND
R
100k
0.1Ω
MON
IMON
0.46 V/A
R
9.09k
T
CBL
PINS NOT USED IN
THIS CIRCUIT:
BST
CLMP
5V V
CHARGES
1.5A USB BC1.2 CDP
COMPLIANT DEVICES
BUS
4.53k
0.1µF
f
V
= 2MHz FOR
= 7.3V TO 42V
SW
IN
8698S TA02
SYNC/MODE
2.4A/1.5A Automatic Profile Detection Charger with Current Monitor
V
IN
C
6V TO 42V
VIN
4.7µF
1206
L1
10µH
R
10m
SEN
V
IN
EN/UV
INTV
SW
+
C
OUT1
22µF
1206
C
CC
C
OUT2
INTVCC
1.0µF
R
100k
µCONTROLLER
R
STAT
100k
FLT
100µF
LT8698S
FLT
OUT/ISP
I/O READ BACK FAULT
AND CHARGER STATE
STATUS BUS/ISN
USB5V
3 METER
USB CABLE
0.1Ω
C
4.7nF
USB
SOCKET
CDC
R
CDC
I/O SELECT
2.4A, 1.5A,
SEL1-3
2k
DISCHARGE STATES
V
BUS
F
= 400kHz to 500kHz
R
SYNC/MODE
R1
SYNC
+
+
–
HD
D
D
–
MON
HD
100k
0.1Ω
CLAMP
RCBL
RT
ADC READS I
BUS
GND
GND PGND
R2
IMON
0.46 V/A
R
4.53k
PINS NOT USED IN
THIS CIRCUIT:
R
T
5V V
CHARGES
CBL
C
0.1µF
BUS
CLMP
51.1k
2.4A AND 1.5A DEVICES
BST
8698S TA03
+
–
f
V
= 400kHz to 500kHz FOR
= 6.8V TO 42V
LD
LD
SW
IN
Rev. A
36
For more information www.analog.com
LT8698S/LT8698S-1
TYPICAL APPLICATIONS
USB Dedicated Charge Port (DCP) VBUS Regulator with Spread Spectrum Modulation for Low EMI/EMC
V
IN
C
6V TO 42V
VIN
2.2µF
1206
L1
2.2µH
R
10m
SEN
V
IN
EN/UV
INTV
SW
C
OUT
CC
C
22µF
1206
INTVCC
1.0µF
LT8698S
OUT/ISP
BUS/ISN
R
CDC
2k
SYNC/MODE USB5V
C
4.7nF
CDC
5 METER
USB
SEL3
SEL2
SEL1
CABLE
SOCKET
0.15Ω
V
BUS
R1
+
+
–
HD
D
D
–
HD
f
V
= 2MHz to 2.4MHz FOR
= 7.5V TO 42V
0.15Ω
R2
SW
IN
CLAMP
GND PGND
RCBL
RT
GND
R
3.01k
R
9.09k
5V V
1.5A DEVICES
CHARGES
CBL
C
CLMP
0.1µF
T
BUS
PINS NOT USED IN
THIS CIRCUIT:
BST
8698S TA04
FLT
STATUS
+
LD
–
LD
USB 5V, 3A VBUS Regulator with Cable Drop Compensation and Low Quiescent Current
V
IN
C
6V TO 42V
VIN
2.2µF
1206
L1
2.2µH
R
8m
SEN
V
IN
EN/UV
INTV
SW
C
OUT
CC
C
22µF
1206
INTVCC
1.0µF
LT8698S
OUT/ISP
BUS/ISN
R
CDC
2k
USB5V
C
4.7nF
CDC
SYNC/MODE
METER
CABLE
USB
SOCKET
PINS NOT USED IN
THIS CIRCUIT:
BST
0.1Ω
V
BUS
f
V
and I
= 2MHz FOR
= 7.5V TO 42V
R1
SW
IN
+
–
D
D
FLT
STATUS
> 1A
0.1Ω
R2
BUS
CLAMP
GND PGND
RCBL
RT
GND
5V 3A
SEL1-3
+
HD
V
BUS
–
+
R
3.65k
R
CBL
C
CLMP
0.1µF
T
HD
9.09k
LD
LD
–
8698S TA05
Rev. A
37
For more information www.analog.com
LT8698S/LT8698S-1
PACKAGE DESCRIPTION
ꢛ
ꢧ
ꢣ
ꢙ ꢄ ꢄ ꢄ
ꢭ ꢭ ꢭ
× ꢤ ꢌ
ꢣ
ꢣ
ꢣ
ꢮ ꢮ ꢩ ꢩ ꢩ
ꢣ
ꢐ . ꢞ ꢍ ꢌ ꢌ
ꢌ . ꢫ ꢍ ꢌ ꢌ
ꢌ . ꢞ ꢍ ꢌ ꢌ
ꢌ . ꢌ ꢌ ꢌ ꢌ
ꢌ . ꢞ ꢍ ꢌ ꢌ
ꢌ . ꢫ ꢍ ꢌ ꢌ
ꢐ . ꢞ ꢍ ꢌ ꢌ
ꢨ ꢨ ꢨ
ꢣ
× ꢞ
Rev. A
38
For more information www.analog.com
LT8698S/LT8698S-1
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
02/21 AEC-Q100 statement updated.
1
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
39
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT8698S/LT8698S-1
TYPICAL APPLICATION
VBUS Regulator with USB On-The-Go Functionality and High Speed USB 2.0 Dataline Protection
V
IN
C
6V TO 42V
VIN
2.2µF
1206
L1
1.5µH
R
10m
SEN
V
IN
EN/UV
INTV
SW
HIGH SPEED
USB 2.0 HOST
µCONTROLLER
C
22µF
1206
OUT
CC
C
1.0µF
INTVCC
R
100K
R
100K
STAT
FLT
LT8698S
I/O READ BACK
STATE
FLT
STATUS
OUT/ISP
BUS/ISN
USB5V
V
BUS
USB
SOCKET
RESPOND TO
SEL1-3
USB OTG REQUEST
Z
= 90Ω
O
10nH
V
Z
= 90Ω
BUS
+
O
+
DIFFERENTIAL
+
10nH
10nH
D
LD
+
DIFFERENTIAL
10nH
HD
D
–
LD
R
100k
–
–
–
MON
D
D
HD
CLAMP
GND PGND
GND
RCBL
RT
ADC READS I
BUS
IMON
0.46 V/A
V
BUS
5V 2.5A OR OPEN.
DATA LINES HIGH
SPEED USB 2.0
R
T
R
CBL
C
CLMP
0.1µF
4.53k
5.62k
PINS NOT USED IN
THIS CIRCUIT:
BST
8698S TA06
f
V
= 3MHz FOR
= 7.5V TO 42V
SW
IN
SYNC/MODE
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
= 5V, V
LT8697
LT3697
LT8650S
LT8652S
LT8653S
LT8636
LT8648S
LT8611
5V USB, 42V Input, 2.5A, 95% Efficiency, 2.2MHz Synchronous
Step-Down DC/DC Converter with Cable Drop Compensation
V
= 42V, V
= 5.0V to 5.25V, I <1μA,
IN(MIN)
IN(MAX)
OUT(MIN) SD
3mm × 5mm QFN-24 Package
5V USB, 35V Input, 60V Transient, 2.5A, 2.2MHz Step-Down DC/DC
Converter with Cable Drop Compensation
V
= 5V, V
= 35V (Transient to 60V), V
= 5.0V to
IN(MIN)
IN(MAX)
OUT(MIN)
5.25V, ISD <1μA, MSOP-16E Package
42V Dual 4A, 95% Efficiency, 2.2MHz Synchronous Silent Switcher 2
Step-Down DC/DC Converter with I = 6.2μA
V
= 3V to 42V, V
= 0.8V, I = 6.2μA, I <2μA, 4mm × 6mm
Q SD
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
LQFN-32 Package
Q
18V Dual 8.5A, 94% Efficiency, 2.2MHz Synchronous Silent Switcher 2 V = 3V to 18V, V
Step-Down DC/DC Converter with I = 16μA
= 0.6V, I = 16μA, I <6μA, 4mm × 7mm
Q SD
IN
LQFN-36 Package
Q
42V Dual 2A, 94% Efficiency, 2.2MHz Synchronous Silent Switcher 2
Step-Down DC/DC Converter with I = 6.2μA
V
= 3V to 42V, V
= 0.8V, I = 6.2μA, I <2μA, 4mm × 3mm
Q SD
IN
LQFN-20 Package
Q
42V 5A, 95% Efficiency, 2MHz Synchronous Silent Switcher
Step-Down DC/DC Converter with I = 2.5μA
V
= 3.4V to 42V, V
= 0.97V, I = 2.5μA, I <1μA,
OUT(MIN) Q SD
IN
4mm × 3mm LQFN-20 Package
Q
42V 15A, 95% Efficiency, 2MHz Synchronous Silent Switcher 2
Step-Down DC/DC Converter with I = 6.2μA
V
IN
= 3V to 42V, V = 0.6V, I = 100μA in Burst Mode
OUT(MIN)
Q
Operation 7mm × 4mm LQFN-36 Package
= 3.4V, V = 42V, V = 0.985V, I = 2.5μA,
OUT(MIN) Q
Q
42V, 2.5A, 946% Efficiency, 2.2MHz Synchronous MicroPower
Step-Down DC/DC Converter with I = 2.5μA and Input/Output
V
SD
IN(MIN)
IN(MAX)
I
< 1μA, 3mm × 5mm QFN-24 Package
Q
Current Limit/Monitor
LT6110
LT4180
Cable/Wire Drop Compensator
V
= 2V, V
= 50V, V
= 0.4V, I = 16μA,
IN(MIN)
IN(MAX)
OUT(MIN) Q
SOT-8, 2mm × 2mm DFN-8 Packages
V = 3.1V, V = 50V, Transient to 80V, I = 1mA,
IN(MIN)
Virtual Remote Sense Controller
IN(MAX)
Q
SSOP-24 Package
Rev. A
02/21
www.analog.com
ANALOG DEVICES, INC. 2021
40
相关型号：
LT8697EUDD
USB 5V 2.5A Output, 42V Input Synchronous Buck with Cable Drop Compensation
LINEAR_DIMENS
LT8697IUDD
USB 5V 2.5A Output, 42V Input Synchronous Buck with Cable Drop Compensation
LINEAR_DIMENS
LT8698S
5V 3A Output, 42V Input USB Charger with Cable Drop Compensation and Dataline Protection
ADI
LT8698S-1
5V 3A Output, 42V Input USB Charger with Cable Drop Compensation and Dataline Protection
ADI
LT8698SEV
5V 3A Output, 42V Input USB Charger with Cable Drop Compensation and Dataline Protection
ADI
LT8698SEV-1
5V 3A Output, 42V Input USB Charger with Cable Drop Compensation and Dataline Protection
ADI
LT8698SJV
5V 3A Output, 42V Input USB Charger with Cable Drop Compensation and Dataline Protection
ADI
LT8698SJV-1
5V 3A Output, 42V Input USB Charger with Cable Drop Compensation and Dataline Protection
ADI
LT8711EFE#PBF
LT8711 - Micropower Synchronous Multitopology Controller with 42V Input Capability; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明