LT8705_技术文档

Electrical Specifications Subject to Change

LT8705

80V V and V

IN

OUT

Synchronous 4-Switch Buck-

Boost DC/DC Controller

FEATURES

DESCRIPTION

The LT^®8705 is a high performance buck-boost switch-

ing regulator controller that operates from input voltages

above, below or equal to the output voltage. The part has

integrated input current, input voltage, output current

and output voltage feedback loops. With a wide 2.8V to

80V input and 1.3V to 80V output range, the LT8705 is

compatible with most solar, automotive, telecom and

battery-powered systems.

n

Single Inductor Allows V Above, Below, or Equal

IN

to Regulated V

OUT

n

V Range 2.8V (Need EXTV > 6.4V) to 80V

IN

OUT

CC

n

V

Range: 1.3V to 80V

Quad N-Channel MOSFET Gate Drivers

Synchronous Rectification: Up to 98% Efficiency

Input and Output Current Monitor Pins

Synchronizable Fixed Frequency: 100kHz to 400kHz

Integrated Input Current, Input Voltage, Output

Current and Output Voltage Feedback Loops

Clock Output Usable To Monitor Die Temperature

Available in 38-Lead (5mm × 7mm) QFN and TSSOP

Packages with the TSSOP Modified for Improved

High Voltage Operation

The operating mode of the controller is determined

through the MODE pin. The MODE pin can select among

discontinuous mode, forced continuous mode and Burst

Mode^®operation.TheLT8705alsofeaturesprogrammable

UVLO and switching currents, along with input and output

current monitoring with programmable maximum levels.

n

L, LT, LTC, LTM, Linear Technology, Burst Mode, µModule and the Linear logo are registered

trademarks of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

APPLICATIONS

n

High Voltage Buck-Boost Converters

n

Input or Output Current Limited Converters

TYPICAL APPLICATION

Telecom Voltage Stabilizer

M1

×2

22µH

V

OUT

IN

M4

48V

36V TO

80V

+

5A

4.7µF

×4

220µF

×2

M3

×2

4.7µF

×6

220µF

×2

M2

TO

DIODE

TO

DIODE

1nF

10Ω

0.22µF

10mΩ

2Ω

×2

2Ω

×2

392k

Efficiency and Power Loss

100

6

5

4

3

2

1

0

TG1 BOOST1 SW1 BG1 CSP

CSNIN

CSPIN

CSN

GND BG2 SW2 BOOST2 TG2

CSPOUT

CSNOUT

95

90

85

80

V

EXTV

CC

IN

SHDN

SWEN

LDO33

MODE

FBIN

RT

FBOUT

100k

INTV

CC

10k

GATEV

CC

4.7µF

LT8705

SRVO_FBIN

SRVO_FBOUT

SRVO_IIN

4Ω

V

LOAD

= 48V

= 2A

OUT

I

71.5k

SS

SRVO_IOUT

IMON_IN

30

40

50

60

(V)

70

80

1µF

V

8705 TA01b

IN

TO

IMON_OUT

V

BOOST1 BOOST2

CLKOUT

202kHz

SYNC

C

20k

215k

56.2k

4.7µF

1µF

220pF

3.3nF

8705 TA01

8705p

1

For more information www.linear.com/8705

LT8705

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

V

-V , V

-V

,

FBIN, SHDN Voltage................................... –0.3V to 30V

CSP CSN CSPIN CSNIN

V

-V

...................................... –0.3V to 0.3V

CSNIN, CSPIN, CSPOUT, CSNOUT Voltage ..–0.3V to 80V

CSPOUT CSNOUT

SS, CLKOUT, CSP, CSN Voltage ................... –0.3V to 3V

V , EXTV Voltage .................................. –0.3V to 80V

IN

CC

V Voltage (Note 2)................................... –0.3V to 2.2V

SW1, SW2 Voltage......................................81V (Note 7)

BOOST1, BOOST2 Voltage ......................... –0.3V to 87V

BG1, BG2, TG1, TG2...........................................(Note 6)

Operating Junction Temperature Range

C

RT, LDO33, FBOUT Voltage.......................... –0.3V to 5V

IMON_IN, IMON_OUT Voltage..................... –0.3V to 5V

SYNC Voltage............................................ –0.3V to 5.5V

INTV , GATEV Voltage............................ –0.3V to 7V

LT8705E (Notes 1, 3) ......................... –40°C to 125°C

LT8705I (Notes 1, 3).......................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

CC

V

-V , V

-V

..................... –0.3V to 7V

BOOST1 SW1 BOOST2 SW2

SWEN, MODE Voltage.................................. –0.3V to 7V

SRVO_FBIN, SRVO_FBOUT Voltage........... –0.3V to 30V

SRVO_IIN, SRVO_IOUT Voltage................. –0.3V to 30V

FE Package .......................................................300°C

PIN CONFIGURATION

TOP VIEW

V

1

2

INTV

38

37

36

IN

CC

TOP VIEW

CSPIN

CSNIN

MODE

IMON_IN

SHDN

3

4

38 37 36 35 34 33 32

CSPOUT

CSNOUT

5

CSN

34

32

30

28

26

24

SHDN

CSN

1

2

3

4

5

6

7

8

9

31 CSPOUT

30 CSNOUT

6

CSP

EXTV

CC

29

28

7

LDO33

FBIN

LDO33

FBIN

SRVO_FBOUT

8

27 SRVO_IOUT

SRVO_IIN

EXTV

CC

9

FBOUT

IMON_OUT

FBOUT

IMON_OUT

26

39

10

11

12

13

14

15

16

17

18

19

GND

25 SRVO_FBIN

24 NC

BOOST1

TG1

V

C

V

C

SS

CLKOUT

SYNC

RT

SS

23 BOOST1

22 TG1

CLKOUT 10

SYNC 11

RT 12

21 SW1

SW1

20

NC

GND

13 14 15 16 17 18 19

SW2

BG1

22

21

20

TG2

GATEV

CC

BOOST2

BG2

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

= 125°C, θ = 34°C/W

FE PACKAGE

T

VARIATION: FE38(31)

38-LEAD PLASTIC TSSOP

JMAX

JA

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

T

= 125°C, θ = 25°C/W

JA

JMAX

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

8705p

2

For more information www.linear.com/8705

LT8705

ORDER INFORMATION

LEAD FREE FINISH

LT8705EUHF#PBF

LT8705IUHF#PBF

LT8705EFE#PBF

LT8705IFE#PBF

TAPE AND REEL

PART MARKING*

8705

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LT8705EUHF#TRPBF

LT8705IUHF#TRPBF

LT8705EFE#TRPBF

LT8705IFE#TRPBF

38-Lead (5mm × 7mm) Plastic QFN

38-Lead Plastic TSSOP

8705

LT8705FE

38-Lead Plastic TSSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, SHDN = 3V unless otherwise noted. (Note 3)

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Voltage Supplies and Regulators

l

V

Operating Voltage Range

EXTV = 0V

5.5

2.8

80

V

IN

CC

EXTV = 7.5V

CC

V

Quiescent Current

Not Switching, V

= 0

2.65

0

4.2

1

mA

µA

V

IN

EXTVCC

Quiescent Current in Shutdown

V

SHDN

= 0V

IN

l

EXTV Switchover Voltage

I

= 20mA, V Rising

EXTVCC

6.15

6.4

0.18

6.6

CC

INTVCC

EXTV Switchover Hysteresis

V

CC

INTV Current Limit

Maximum Current Draw from INTV and LDO33

CC

Pins Combined. Regulated from V or EXTV (12V)

IN

CC

l

INTV = 5.25V

90

28

127

42

165

55

mA

CC

INTV = 4.5V

CC

l

INTV Voltage

Regulated from V , I

= 20mA

6.15

6.35

6.55

V

CC

IN INTVCC

Regulated from EXTV (12V), I

= 20mA

CC

INTVCC

INTV Load Regulation

I

= 0mA to 50mA

INTVCC

–0.5

4.65

160

245

–1.5

4.85

%

V

CC

l

INTV , GATEV Undervoltage Lockout

INTV Falling, GATEV Connected to INTV

CC

4.45

CC

INTV , GATEV Undervoltage Lockout Hysteresis

GATEV Connected to INTV

CC

mV

V

CC

INTV Regulator Dropout Voltage

V -V

, I

= 20mA

CC

IN INTVCC INTVCC

l

LDO33 Pin Voltage

5mA from LDO33 Pin

= 0.1mA to 5mA

3.23 3.295 3.35

LDO33 Pin Load Regulation

LDO33 Pin Current Limit

I

–0.25

17.25

3.04

35

–1

22

%

LDO33

12

mA

V

LDO33 Pin Undervoltage Lockout

LDO33 Pin Undervoltage Lockout Hysteresis

Switching Regulator Control

LDO33 Falling

2.96

3.12

mV

l

Maximum Current Sense Threshold (V

– V

)

Boost Mode, Minimum M3 Switch Duty Cycle

Buck Mode, Minimum M2 Switch Duty Cycle

102

69

117

86

132

102

mV

CSP

CSN

– V

CSP

Gain from V to Maximum Current Sense Voltage

CSP CSN

Boost Mode

Buck Mode

150

–150

mV/V

C

(V -V ) (A5 in the Block Diagram)

l

SHDN Input Voltage High

SHDN Rising to Enable the Device

1.184 1.234 1.284

V

mV

V

SHDN Input Voltage High Hysteresis

SHDN Input Voltage Low

50

Device Disabled, Low Quiescent Current

0.35

8705p

3

For more information www.linear.com/8705

LT8705

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, SHDN = 3V unless otherwise noted. (Note 3)

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

SHDN Pin Bias Current

V

SHDN

V

SHDN

= 3V

= 12V

0

11

1

22

µA

l

SWEN Rising Threshold Voltage (Note 5)

SWEN Threshold Voltage Hysteresis (Note 5)

MODE Pin Forced Continuous Mode Threshold

MODE Pin Burst Mode Range

1.156 1.206 1.256

V

mV

V

22

l

0.4

1.0

1.7

2.3

25

V

MODE Pin Discontinuous Mode Threshold

Soft-Start Charging Current

V

= 0.5V

13

19

µA

SS

Soft-Start Discharge Current

= 0.5V

9.5

SS

Voltage Regulator Loops (Refer to Block Diagram to Locate Amplifiers)

l

Regulation Voltage for FBOUT

Regulation Voltage for FBIN

V = 1.2V

1.193 1.207 1.217

1.187 1.205 1.220

0.002 0.005

V

C

V = 1.2V

C

Line Regulation for FBOUT and FBIN Error Amp Reference

Voltage

V

= 12V to 80V

%/V

IN

FBOUT Pin Bias Current

Current Out of Pin

15

315

220

10

nA

µmho

V/V

FBOUT Error Amp EA4 g

m

FBOUT Error Amp EA4 Voltage Gain

FBIN Pin Bias Current

nA

FBIN Error Amp EA3 g

130

90

µmho

V/V

m

FBIN Error Amp EA3 Voltage Gain

SRVO_FBIN Activation Threshold (Note 5)

(V

FBOUT

Falling) – (Regulation Voltage for FBIN),

56

72

89

mV

FBIN

V

= V

= 0V

IMON_IN

IMON_OUT

SRVO_FBIN Activation Threshold Hysteresis (Note 5)

SRVO_FBOUT Activation Threshold (Note 5)

V

= V

= 0V

33

mV

FBOUT

IMON_IN

IMON_OUT

(V

V

Rising) – (Regulation Voltage for FBOUT),

–37

–29

–21

FBOUT

= 3V, V

= V

= 0V

FBIN

IMON_IN

IMON_OUT

SRVO_FBOUT Activation Threshold Hysteresis (Note 5)

SRVO_FBIN, SRVO_FBOUT Low Voltage (Note 5)

SRVO_FBIN, SRVO_FBOUT Leakage Current (Note 5)

V

= 3V, V

= 0V, V

= 0V

15

110

0

mV

µA

FBIN

IMON_IN

IMON_OUT

l

I = 100μA

330

1

V

= V

= 2.5V

SRVO_FBOUT

SRVO_FBIN

Current Regulation Loops (Refer to Block Diagram to Locate Amplifiers)

l

Regulation Voltages for IMON_IN and IMON_OUT

V = 1.2V

1.191 1.208 1.223

0.002 0.005

V

C

Line Regulation for IMON_IN and IMON_OUT Error Amp

Reference Voltage

V

= 12V to 80V

%/V

IN

CSPIN, CSNIN Bias Current

BOOST Capacitor Charge Control Block Not Active

I

+ I

, V

= V = 12V

CSNIN

31

µA

V

CSPIN

CSNIN CSPIN

l

CSPIN, CSNIN Common Mode Operating Voltage Range

CSPIN, CSNIN Differential Operating Voltage Range

1.5

80

–100

100

mV

V

to IMON_IN Amplifier A7 g

V

CSPIN

– V

= 50mV, V = 5.025V

CSPIN

0.95

0.94

1

1.05

1.06

mmho

CSPIN-CSNIN

m

CSNIN

l

IMON_IN Maximum Output Current

IMON_IN Overvoltage Threshold

100

µA

V

1.55

1.61

185

130

1.67

IMON_IN Error Amp EA2 g

µmho

V/V

m

IMON_IN Error Amp EA2 Voltage Gain

8705p

4

For more information www.linear.com/8705

LT8705

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, SHDN = 3V unless otherwise noted. (Note 2)

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

CSPOUT, CSNOUT Bias Current

BOOST Capacitor Charge Control Block Not Active

I

+ I

, V

= V

= 12V

45

4

µA

CSPOUT

CSNOUT CSPOUT

CSNOUT

, V

= 1.5V

l

CSPOUT, CSNOUT Common Mode Operating Voltage Range

CSPOUT, CSNOUT Differential Mode Operating Voltage Range

0

80

V

mV

–100

100

V

to IMON_OUT Amplifier A6 g

V

– V

= 50mV, V

= 5.052V

= 5.025V

0.95

0.94

0.65

0.55

1

1.05

mmho

CSPOUT-CSNOUT

m

CSPOUT

CSNOUT

CSPOUT

l

1.085 mmho

= 5mV, V

= 5.0025V

1.35

1.6

mmho

CSPOUT

l

IMON_OUT Maximum Output Current

IMON_OUT Overvoltage Threshold

100

µA

V

1.55

1.61

185

130

–49

1.67

IMON_OUT Error Amp EA1 g

µmho

V/V

m

IMON_OUT Error Amp EA1 Voltage Gain

SRVO_IIN Activation Threshold (Note 5)

(V

Rising) – (Regulation Voltage for

–60

–62

–37

–39

mV

IMON_IN

IMON_IN), V

= 3V, V

= 0V, V

= 0V

IMON_OUT

FBIN

FBOUT

SRVO_IIN Activation Threshold Hysteresis (Note 5)

SRVO_IOUT Activation Threshold (Note 5)

V

= 3V, V

= 0V, V = 0V

IMON_OUT

22

mV

FBIN

FBOUT

(V

OUT), V

Rising) – (Regulation Voltage for IMON_

–51

IMON_OUT

= 3V, V

= 0V, V

= 0V

IMON_IN

FBIN

FBOUT

SRVO_IOUT Activation Threshold Hystersis (Note 5)

SRVO_IIN, SRVO_IOUT Low Voltage (Note 5)

SRVO_IIN, SRVO_IOUT Leakage Current (Note 5)

NMOS Gate Drivers

V

= 3V, V

= 0V, V

= 0V

22

110

0

mV

µA

FBIN

FBOUT

IMON_IN

l

I = 100μA

330

1

V

= V

= 2.5V

SRVO_IOUT

SRVO_IIN

TG1, TG2 Rise Time

C

= 3300pF (Note 4)

= 3300pF Each Driver

20

ns

LOAD

TG1, TG2 Fall Time

BG1, BG2 Rise Time

20

BG1, BG2 Fall Time

20

TG1 Off to BG1 On Delay

100

80

BG1 Off to TG1 On Delay

TG2 Off to BG2 On Delay

100

80

BG2 Off to TG2 On Delay

Minimum On-Time for Main Switch in Boost Operation

Switch M3, C

Switch M2, C

Switch M3, C

Switch M2, C

= 3300pF

265

LOAD

(t

)

ON(M3,MIN)

Minimum On-Time for Synchronous Switch in Buck

Operation (t

260

245

ns

)

ON(M2,MIN)

Minimum Off-Time for Main Switch in Steady-State Boost

Operation

Minimum Off-Time for Synchronous Switch in

Steady-State Buck Operation

Oscillator

Switch Frequency Range

SYNCing or Free Running

R = 365k

100

400

kHz

l

Switching Frequency, f

102

170

310

120

202

350

142

235

400

kHz

OSC

T

R = 215k

T

R = 124K

T

8705p

5

For more information www.linear.com/8705

LT8705

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, SHDN = 3V unless otherwise noted. (Note 3)

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

l

SYNC High Level for Synchronization

SYNC Low Level for Synchronization

SYNC Clock Pulse Duty Cycle

Recommended Minimum SYNC Ratio f

CLKOUT Output Voltage High

CLKOUT Output Voltage Low

CLKOUT Duty Cycle

1.3

V

0.5

80

V

= 0V to 2V

20

%

SYNC

/f

3/4

2.45

25

SYNC OSC

1mA Out of CLKOUT Pin

1mA Into CLKOUT Pin

2.3

2.55

100

V

mV

T = –40°C

21.4

42.5

75

%

J

T = 25°C

J

T = 125°C

J

CLKOUT Rise Time

CLKOUT Fall Time

CLKOUT Phase Delay

C

= 200pF

30

25

ns

LOAD

l

SYNC Rising to CLKOUT Rising, f

= 100kHz

160

180

200

Deg

OSC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 5: This specification not applicable in the FE38 package.

Note 6: Do not apply a voltage or current source to these pins. They must

be connected to capacitive loads only, otherwise permanent damage may

occur.

Note 7: Negative voltages on the SW1 and SW2 pins are limited, in an

application, by the body diodes of the external NMOS devices, M2 and

M3, or parallel Schottky diodes when present. The SW1 and SW2 pins

are tolerant of these negative voltages in excess of one diode drop below

ground, guaranteed by design.

Note 2: Do not force voltage on the V pin.

C

Note 3: The LT8705E is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LT8705I is guaranteed over the full –40°C to 125°C junction temperature

range.

8705p

6

For more information www.linear.com/8705

LT8705

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise specified.}

Efficiency vs Output Current

(Boost Region-Figure 14)

Efficiency vs Output Current

(Buck-Boost Region-Figure 14)

Efficiency vs Output Current

(Buck Region-Figure 14)

100

90

100

90

100

90

80

70

60

80

70

60

80

70

60

50

40

50

40

50

40

V

= 36V

= 48V

BURST

V

= 48V

BURST

V

= 72V

= 48V

BURST

IN

OUT

IN

OUT

IN

OUT

30

20

10

0

30

20

10

0

30

20

10

0

CCM

DCM

CCM

DCM

CCM

DCM

10

1000

LOAD CURRENT (mA)

10000

10

1000

LOAD CURRENT (mA)

10000

10

1000

LOAD CURRENT (mA)

10000

100

8705 G01

8705 G02

8705 G03

Oscillator Frequency

Feedback Voltages

FBOUT Voltages (Five Parts)

1.23

1.22

1.21

1.20

1.23

1.22

1.21

1.20

1.19

1.18

1.17

400

350

300

250

200

150

100

50

V

= 1.2V

V

= 1.2V

C

R

T

= 124k

R

= 215k

= 365k

T

1.19

1.18

1.17

IMON_OUT

IMON_IN

FBOUT

FBIN

0

70 95

–55 –30 –5 20 45

120 145

50

100 125 150

–20

40 60

–50 –25

0

25

75

–40

0

20

80 100 120

TEMPERATURE (°C)

8705 G04

8795 G05

8705 G06

Maximum Inductor Current Sense

Voltage vs Duty Cycle

Inductor Current Sense Voltage at

Minimum Duty Cycle

Maximum Inductor Current Sense

Voltage at Minimum Duty Cycle

120

100

140

120

100

120

100

BOOST REGION

BUCK REGION

80

60

40

80

60

40

100

80

60

40

20

0

80

60

BUCK REGION

BOOST REGION

BUCK REGION

BOOST REGION

20

0

20

0

40

20

0

–20

–40

–60

–80

–20

–40

–60

–80

–40 –20

0

20 40 60 80 100 120

TEMPERATURE (°C)

8705 G09

20

40

60

100

0

80

0.5

1.5

2

1

V

(V)

M2 OR M3 DUTY CYCLE (%)

C

8705 G07

8705 G08

8705p

7

For more information www.linear.com/8705

LT8705

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise specified.}

Minimum Inductor Current Sense

Voltage in Forced Continuous Mode

INTV_CCLineRegulation

(EXTV_CC=0V)

INTV_CCLineRegulation

(V_IN=12V)

7.0

6.5

6.0

5.5

0

7.0

6.5

6.0

5.5

5.0

4.5

4.0

–20

BUCK REGION

BOOST REGION

–40

–60

EXTV RISING

CC

EXTV FALLING

CC

–80

–100

–120

–140

14 16

4

6

8

10 12

(V)

18 20

20

40

60

100

0

80

4

6

8

10

12

V

EXTV (V)

M2 OR M3 DUTY CYCLE (%)

IN

CC

8705 G11

8705 G10

8705 G12

V_INSupply Current vs Voltage

(Not Switching)

Maximum V_Cvs SS

IMONOutputCurrents

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

3.5

3.0

200

175

150

125

100

75

T = 25°C

J

GATEV CONNECTED TO INTV

CC

BOOST AND

BUCK-BOOST REGIONS

BUCK

REGION

2.5

2.0

1.5

1.0

0.5

50

25

125°C

25°C

–40°C

0

–25

15

25

5

35

45

55

65

75

0

0.4 0.6 0.8 1.0 1.2 1.4

SS (V)

0.2

–100 –50

0

50

200

100

150

V

(V)

CSPIN-CSNIN (mV)

CSPOUT-CSNOUT (mV)

IN

8705 G14

8705 G13

8705 G15

LDO33 Pin Regulation

(I_LDO33= 1mA)

SHDN and SWEN Pin Thresholds

CLKOUT Duty Cycle

vs Temperature

100

3.5

3.0

2.5

2.0

1.5

1.30

1.28

1.26

1.24

1.22

1.20

1.18

1.16

1.14

1.12

1.10

80

60

RISING

40

20

0

FALLING

125°C

25°C

SHDN

SWEN

–40°C

50

TEMPERATURE (°C)

4

4.5

–15

5

65 85 105

125 145

–50 –25

0

25

75 100 125 150

2.5

5

5.5

6

–55 –35

25 45

3

3.5

INTV (V)

TEMPERATURE (°C)

CC

8705 G16

8705 G17

8705 G18

8705p

8

For more information www.linear.com/8705

LT8705

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise specified.}

SRVO_xx Pin Activation

Thresholds

Internal V_INUVLO

SHDN and MODE Pin Currents

18

16

14

12

10

8

3.0

2.5

125

100

75

MODE

SHDN

2.0

1.5

50

FBIN

FBOUT

25

IMON_IN

IMON_OUT

6

0

1.0

0.5

0

4

–25

–50

–75

2

0

–2

0

3

6

9

12 15 18 21 24 27 30

PIN VOLTAGE (V)

8705 G19

–40 –20

0

20 40 60 80 100 120

TEMPERATURE (°C)

8705 G20

50 75

25

TEMPERATURE (°C)

–50 –25

0

100 125 150

8705 G21

SRVO_xx Pin Activation Threshold

Hysteresis

Forced Continuous Mode

(Figure 14)

Discontinuous Mode (Figure 14)

50

40

30

20

10

0

SW1

20V/DIV

SW1

50V/DIV

SW2

20V/DIV

SW2

50V/DIV

FBIN

FBOUT

I

L

2A/DIV

L

IMON_IN

IMON_OUT

2A/DIV

8705 G23

8705 G24

V

= 72V

5µs/DIV

V

= 36V

5µs/DIV

50

25

TEMPERATURE (°C)

–50 –25

0

75 100 125 150

IN

OUT

IN

OUT

= 48V

8705 G22

Forced Continuous Mode

(Figure 14)

Forced Continuous Mode

(Figure 14)

SW1

20V/DIV

SW1

20V/DIV

SW2

20V/DIV

SW2

20V/DIV

I

L

2A/DIV

8705 G25

8705 G26

V

= 48V

5µs/DIV

V

= 72V

5µs/DIV

IN

OUT

IN

OUT

= 48V

8705p

9

For more information www.linear.com/8705

LT8705

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise specified.}

Burst Mode Operation (Figure 14)

Load Step (Figure 14)

V

OUT

V

OUT

500mV/DIV

100mV/DIV

I

L

I

2A/DIV

L

5A/DIV

1A/DIV

8705 G28

8705 G27

8705 G29

V

= 72V

5ms/DIV

V

= 36V

2ms/DIV

V

= 36V

500µs/DIV

IN

OUT

IN

OUT

IN

OUT

= 48V

LOAD STEP = 1A TO 3A

Load Step (Figure 14)

5

0

m

V

/

U

V

2

A

/

I

VV

O

A

=

4

E

P

=

1A

T

50

3A

s

/

I

8

0

G

V

OUT

500mV/DIV

I

L

2A/DIV

8705 G31

8705 G30

V

= 72V

500µs/DIV

V

= 48V

OUT

LOAD STEP = 1A TO 3A

500µs/DIV

IN

OUT

IN

= 48V

LOAD STEP = 1A TO 3A

Line Transient (Figure 14)

V

IN

72V TO 36V

IN

36V TO 72V

V

C

V

C

0.5V/DIV

V

OUT

V

OUT

0.5V/DIV

I

L

2A/DIV

L

2A/DIV

8705 G32

8705 G33

2ms/DIV

8705p

10

For more information www.linear.com/8705

LT8705

(QFN/TSSOP)

PIN FUNCTIONS

SHDN (Pin 1/Pin 4): Shutdown Pin. Tie high to enable

device.Groundtoshutdownandreducequiescentcurrent

to a minimum. Do not float this pin.

RT(Pin12/Pin15):TimingResistorPin.Adjuststheswitch-

ing frequency. Place a resistor from this pin to ground to

set the free-running frequency. Do not float this pin.

CSN (Pin 2/Pin 5): The (–) Input to the Inductor Current

BG1, BG2 (Pins 14, 16/Pins 17, 19): Bottom Gate Drive.

Sense and Reverse-Current Detect Amplifier.

Drives the gates of the bottom N-channel MOSFETs be-

tween ground and GATEV .

CC

CSP (Pin 3/Pin 6): The (+) Input to the Inductor Current

Sense and Reverse-Current Detect Amplifier. The V pin

GATEV (Pin 15/Pin 18): Power Supply for Gate Drivers.

CC

C

voltage and built-in offsets between CSP and CSN pins, in

Must be connected to the INTV pin. Do not power from

CC

conjunction with the R

trip threshold.

resistor value, set the current

any other supply. Locally bypass to GND.

SENSE

BOOST1, BOOST2 (Pins 23, 17/Pins 28, 20): Boosted

Floating Driver Supply. The (+) terminal of the bootstrap

capacitor connects here. The BOOST1 pin swings from a

LDO33 (Pin 4/Pin7): 3.3V Regulator Output. Bypass this

pin to ground with a minimum 0.1μF ceramic capacitor.

diode voltage below GATEV up to V + GATEV . The

CC

IN

CC

FBIN (Pin 5/Pin 8): Input Feedback Pin. This pin is con-

nected to the input error amplifier input.

BOOST2 pin swings from a diode voltage below GATEV

CC

up to V

+ GATEV

OUT

CC

FBOUT (Pin 6/Pin 9): Output Feedback Pin. This pin

connects the error amplifier input to an external resistor

divider from the output.

TG1,TG2(Pins22,18/Pins26,21):TopGateDrive.Drives

the top N-channel MOSFETs with voltage swings equal

to GATEV superimposed on the switch node voltages.

CC

IMON_OUT(Pin7/Pin10):OutputCurrentMonitorPin.The

currentoutofthispinisproportionaltotheoutputcurrent.

See the Operation and Applications Information sections.

SW1, SW2 (Pins 21, 19/Pins 24, 22): Switch Nodes. The

(–) terminals of the bootstrap capacitors connect here.

SRVO_FBIN (Pin 25 QFN Only): Open-Drain Logic Out-

put. This pin is pulled to ground when the input voltage

feedback loop is active.

V (Pin 8/Pin 11): Error Amplifier Output Pin. Tie external

C

compensation network to this pin.

SS (Pin 9/Pin 12): Soft-Start Pin. Place at least 100nF of

capacitance here. Upon start-up, this pin will be charged

by an internal resistor to 2.5V.

SRVO_IIN (Pin 26 QFN Only): Open-Drain Logic Output.

The pin is pulled to ground when the input current loop

is active.

CLKOUT (Pin 10/Pin 13): Clock Output Pin. Use this pin to

synchronize one or more compatible switching regulator

ICs to the LT8705. CLKOUT toggles at the same frequency

as the internal oscillator or as the SYNC pin, but is ap-

proximately 180° out of phase. CLKOUT may also be used

as a temperature monitor since the CLKOUT duty cycle

varies linearly with the part’s junction temperature. The

CLKOUT pin can drive capacitive loads up to 200pF.

SRVO_IOUT (Pin 27 QFN Only): Open-Drain Logic Out-

put. The pin is pulled to ground when the output current

feedback loop is active.

SRVO_FBOUT (Pin 28 QFN Only): Open-Drain Logic Out-

put. This pin is pulled to ground when the output voltage

feedback loop is active.

EXTV (Pin29/Pin30):ExternalV Input.WhenEXTV

CC

SYNC (Pin 11/Pin 14): To synchronize the switching fre-

quency to an outside clock, simply drive this pin with a

clock. The high voltage level of the clock needs to exceed

1.3V, and the low level should be less than 0.5V. Drive this

pin to less than 0.5V to revert to the internal free-running

clock. See the Applications Information section for more

information.

exceeds 6.4V (typical), INTV will be powered from this

CC

pin. When EXTV is lower than 6.22V (typical), INTV

CC

will be powered from V .

IN

CSNOUT (Pin 30/Pin 32): The (–) Input to the Output Cur-

rent Monitor Amplifier. Connect this pin to V

when not

OUT

in use. See Applications Information section for proper

use of this pin.

8705p

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For more information www.linear.com/8705

LT8705

(QFN/TSSOP)

PIN FUNCTIONS

CSPOUT (Pin 31/Pin 34): The (+) Input to the Output

SWEN (Pin 36 QFN Only): Switch Enable Pin. Tie high

Current Monitor Amplifier. This pin and the CSNOUT pin

to enable switching. Ground to disable switching. Don’t

measure the voltage across the sense resistor, R

,

float this pin. This pin is internally tied to INTV in the

SENSE2

CC

to provide the output current signals. Connect this pin

TSSOP package.

to V

when not in use. See Applications Information

OUT

IMON_IN (Pin 38/Pin 3): Input Current Monitor Pin. The

current out of this pin is proportional to the input current.

See the Operation and Applications Information sections.

section for proper use of this pin.

CSNIN (Pin 32/Pin 36): The (–) Input to the Input Current

Monitor Amplifier. This pin and the CSPIN pin measure

MODE (Pin 37/Pin 2): Mode Pin. The voltage applied to

this pin sets the operating mode of the controller. When

the applied voltage is less than 0.4V, the forced continu-

ous current mode is active. When this pin is allowed to

float, Burst Mode operation is active. When the MODE pin

voltage is higher than 2.3V, discontinuous mode is active.

the voltage across the sense resistor, R

, to provide

IN

SENSE1

the input current signals. Connect this pin to V when not

in use. See Applications Information section for proper

use of this pin.

CSPIN (Pin 33/Pin 37): The (+) Input to the Input Cur-

rent Monitor Amplifier. Connect this pin to V when not

IN

GND (Pin 13, Exposed Pad Pin 39/Pin 16, Exposed Pad

Pin 39): Ground. Tie directly to local ground plane.

in use. See Applications Information section for proper

use of this pin.

V

(Pin 34/Pin 38): Main Input Supply Pin. It must be

IN

locally bypassed to ground.

INTV (Pin 35/Pin 1): Internal 6.35V Regulator Output.

CC

MustbeconnectedtotheGATEV pin.INTV ispowered

CC

from EXTV when the EXTV voltage is higher than

CC

6.4V, otherwise INTV is powered from V . Bypass this

CC

IN

pin to ground with a minimum 4.7μF ceramic capacitor.

8705p

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For more information www.linear.com/8705

LT8705

BLOCK DIAGRAM

V

IN

R

SENSE1

R

SENSE

SWEN

CSN

CSP

D

B1

BOOST1

TG1

C

B1

+

–

D1

(OPT)

M1

–

+

CSNIN

+

–

A8

SW1

A7

A5

M2

CSPIN

BUCK

LOGIC

GATEV

CC

V

IN

BG1

GND

IMON_IN

MODE

CLKOUT

SYNC

BOOST CAPACITOR

CHARGE CONTROL

BG2

M3

OSC

SW2

TG2

BOOST

LOGIC

D2

(OPT)

RT

M4

+

–

C

B2

D

BOOST2

A9

B2

2.5V

CSPOUT

CSNOUT

+

UV_INTV

CC

OT

OI_IN

OI_OUT

A6

R

SENSE2

–

V

OUT

STARTUP

AND FAULT

LOGIC

–

+

IMON_OUT

SS

FAULT_INT

EA1

EA2

UV_LDO33 UV_V

UV_GATEV

1.208V

IN

CC

+

–

R

SHDN1

SHDN

V

IN

+

–

IMON_IN

R

SHDN2

FBIN1

FBIN

1.234V

+

–

EA3

EA4

FBIN2

6.4V

+

–

1.205V

LDO

REG

3.3V

LDO

REG

EXTV

CC

V

IN

1.207V

FBOUT

+

–

6.35V

LDO

6.35V

EN

R

EN

INTERNAL

SUPPLY2

FBOUT1

LDO

REG

INTV

INTERNAL

SUPPLY1

CC

FBOUT2

V

C

LDO33

SRVO_IOUT

SRVO_IIN

SRVO_FBIN

SRVO_FBOUT

8705 F01

Figure 1. Block Diagram

8705p

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LT8705

OPERATION

Refer to the Block Diagram (Figure 1) when reading the

following sections about the operation of the LT8705.

The GATEV pin directly powers the bottom MOSFET

CC

drivers for switches M2 and M3. GATEV should always

CC

be connected to INTV and should not be powered or

CC

Main Control Loop

connected to any other source. Undervoltage lock outs

(UVLOs) monitoring INTV and GATEV disable the

CC

The LT8705 is a current mode controller that provides an

output voltage above, equal to or below the input voltage.

The LTC proprietary topology and control architecture

switchingregulatorwhenthepinsarebelow4.65V(typical).

The LDO33 pin is available to provide power to external

componentssuchasamicrocontrollerand/ortoprovidean

accurate bias voltage. Load current is limited to 17.25mA

(typical). As long as SHDN is high the LDO33 output is

employs a current-sensing resistor (R

) in buck or

SENSE

boost modes. The inductor current is controlled by the

voltage on the V pin, which is the diode-AND of error

C

amplifiersEA1-EA4.Inthesimplestform,wheretheoutput

is regulated to a constant voltage, the FBOUT pin receives

the output voltage feedback signal, which is compared to

theinternalreferencevoltagebyEA4.Lowoutputvoltages

linearly regulated from the INTV pin and is not affected

CC

by the INTV or GATEV UVLOs or the SWEN pin volt-

CC

age. LDO33 will remain regulated as long as SHDN is high

and sufficient voltage is available on INTV (typically >

CC

would create a higher V voltage, and thus more current

4.0V). An undervoltage lockout, monitoring LDO33, will

disable the switching regulator when LDO33 is below

3.04V (typical).

C

wouldflowintotheoutput. Conversely, higheroutputvolt-

ages would cause V to drop, thus reducing the current

C

fed into the output.

Start-Up

The LT8705 contains four error amplifiers (EA1-EA4) al-

lowing it to regulate or limit the output current (EA1), input

current (EA2), input voltage (EA3) and/or output voltage

(EA4). In a typical application, the output voltage might be

regulated using EA4, while the remaining error amplifiers

are monitoring for excessive input or output current or an

input undervoltage condition. In other applications, such

asabatterycharger,theoutputcurrentregulator(EA1)can

facilitate constant current charging until a predetermined

voltage is reached where the output voltage (EA4) control

would take over.

Figure 2 illustrates the start-up sequence for the LT8705.

The master shutdown pin for the chip is SHDN. When

driven below 0.4V the chip is disabled (chip off state) and

quiescentcurrentisminimal.IncreasingtheSHDNvoltage

can increase quiescent current but will not enable the chip

until SHDN is driven above 1.234V (typical) after which

the INTV and LDO33 regulators are enabled (switcher

CC

off state). External devices powered by the LDO33 pin can

become active at this time if enough voltage is available

on V or EXTV to raise INTV , and thus LDO33, to

IN

CC

an adequate voltage.

INTV /EXTV /GATEV /LDO33 Power

CC

Starting up the switching regulator happens after SWEN

(switcher enable) is also driven above 1.206V (typical),

INTV and GATEV haverisenabove4.81V(typical)and

Power for thetopand bottomMOSFET drivers, the LDO33

pin and most internal circuitry is derived from the INTV

CC

pin. INTV is regulated to 6.35V (typical) from either the

the LDO33 pin has risen above 3.08V (typical) (initialize

state). The SWEN pin is not available in the TSSOP pack-

age. In this package the SWEN pin is internally connected

CC

V or EXTV pin. When the EXTV pin is left open or

IN

CC

tied to a voltage less than 6.22V (typical), an internal low

dropout regulator regulates INTV from V . If EXTV

CC

to INTV .

CC

IN

CC

is taken above 6.4V (typical), another low dropout regula-

tor will instead regulate INTV from EXTV . Regulating

Start-Up: Soft-Start of Switch Current

CC

INTV from EXTV allows the power to be derived from

CC

In the initialize state, the SS (soft-start) pin is pulled low

toprepareforsoftstartingtheregulator. Ifforcedcontinu-

ous mode is selected (MODE pin low), the part is put into

discontinuous mode during soft-start to prevent current

8705p

the lowest supply voltage (highest efficiency) such as the

LT8705switchingregulatoroutput(seeINTV Regulators

CC

and EXTV Connection in the Applications Information

CC

section for more details).

14

For more information www.linear.com/8705

LT8705

OPERATION

T

< 160°C

JUNCTION

AND

SHDN > 1.234V AND V > 2.5V

IN

SHDN < 1.184V OR

< 2.5V OR

TYPICAL VALUES

AND

TYPICAL VALUES

V

IN

JUNCTION

(SWEN* < 1.184V OR (INTV AND GATEV < 4.65V)

CC

T

> 165°C

OR LDO33 < 3.04V)

CHIP OFF

SWITCHER OFF

• SWITCHER OFF

• LDOs OFF

• SWITCHER DISABLED

• INTV AND LDO33 OUTPUTS

CC

ENABLED

SHDN > 1.234V AND V > 2.5V

IN

AND SWEN* > 1.206V AND

TYPICAL VALUES

(INTV AND GATEV > 4.81V) AND

CC

LDO33 > 3.075V

INITIALIZE

• SS PULLED LOW

FAULT

• FORCE DISCONTINOUS

MODE UNLESS Burst Mode

OPERATION SELECTED

SS < 50mV

FAULT DETECTED

SOFT-START

FAULT

• SS CHARGES UP

• SWITCHER DISABLED

• CLKOUT DISABLED

• SS CHARGES UP

• SWITCHER ENABLED

SS > 1.6V AND

NO FAULT CONDITIONS

STILL DETECTED

NORMAL MODE

• NORMAL OPERATION

• WHEN SS > 1.6V ...

• CLKOUT ENABLED

• ENABLE FORCED

CONTINUOUS MODE

IF SELECTED

POST FAULT DELAY

FAULT

• SS SLOWLY DISCHARGES

SS < 50mV

*SWEN IS CONNECTED TO INTV IN THE TSSOP PACKAGE

CC

FAULT = OVERVOLTAGE (IMON_IN OR IMON_OUT > 1.61V TYP)

8705 F02

Figure 2. Start-Up and Fault Sequence

from being drawn out of the output and forced into the

input. After SS has been discharged to less than 50mV,

a soft-start of the switching regulator begins (soft-start

state). The soft-start circuitry provides for a gradual

ramp-up of the inductor current by gradually allowing the

is allowed to enter forced continuous mode (if MODE is

low)andaninternalregulatorpullsSSupquicklyto≅2.5V.

Typical values for the external soft-start capacitor range

from 100nF to 1μF. A minimum of 100nF is recommended.

Fault Conditions

V voltage to rise (refer to V vs SS Voltage in the Typical

C

PerformanceCharacteristics).Thispreventsabruptsurges

of current from being drawn out of the input power sup-

ply. An integrated 100k resistor pulls the SS pin to ≅2.5V.

The ramp rate of the SS pin voltage is set by this 100k

resistor and the external capacitor connected to this pin.

Once SS gets to 1.6V, the CLKOUT pin is enabled, the part

The LT8705 activates a fault sequence under certain op-

erating conditions. If any of these conditions occur (see

Figure 2) the CLKOUT pin and internal switching activity

are disabled. At the same time, a timeout sequence com-

mences where the SS pin is charged up to a minimum

of 1.6V (fault detected state). The SS pin will continue

8705p

15

For more information www.linear.com/8705

LT8705

OPERATION

is turned on first. Inductor current is sensed by amplifier

A5 while switch M2 is on. A slope compensation ramp is

addedtothesensedvoltagewhichisthencomparedbyA8

charging up to 2.5V and be held there in the case of a fault

eventthatpersists. Afterthefaultconditionhadendedand

SS is greater than 1.6V, SS will then slowly discharge to

50mV (post fault delay state). This timeout period relieves

the part and other downstream power components from

electrical and thermal stress for a minimum amount of

time as set by the voltage ramp rate on the SS pin. After

SS has discharged to < 50mV, the LT8705 will enter the

soft-start state and restart switching activity.

to a reference that is proportional to V . After the sensed

C

inductor current falls below the reference, switch M2 is

turned off and switch M1 is turned on for the remainder

of the cycle. Switches M1 and M2 will alternate, behaving

like a typical synchronous buck regulator.

CLOCK

Power Switch Control

SWITCH M1

SWITCH M2

Figure 3 shows a simplified diagram of how the four

power switches are connected to the inductor, V , V

IN OUT

OFF

SWITCH M3

and ground. Figure 4 shows the regions of operation for

ON

SWITCH M4

the LT8705 as a function of V -V or switch duty cycle

OUT IN

I

L

DC. The power switches are properly controlled so the

8705 F05

transfer between modes is continuous.

Figure 5. Buck Region (V_IN>> V_OUT

)

V

IN

V

OUT

The part will continue operating in the buck region over a

rangeofswitchM2dutycycles.ThedutycycleofswitchM2

in the buck region is given by:

TG1

BG1

M1

SW1

M4

TG2

BG2

L

SW2

M2

M3









V_OUT

DC_(M2,BUCK)= 1–

•100%





V

R

SENSE

IN

8705 F03

As V and V

get closer to each other, the duty cycle

IN

OUT

Figure 3. Simplified Diagram of the Output Switches

decreases until the minimum duty cycle of the converter

in buck mode reaches DC . If the duty

SWITCH

(ABSMIN,M2,BUCK)

M3 DC

MAX

cycle becomes lower than DC

will move to the buck-boost region.

the part

(ABSMIN,M2,BUCK)

M1 ON, M2 OFF

PWM M3, M4 SWITCHES

BOOST REGION

SWITCH

M3 DC

MIN

DC ≅ t

• f • 100%

ON(M2,MIN)

0

BUCK/BOOST REGION 4-SWITCH PWM

(ABSMIN,M2,BUCK)

SWITCH

M2 DC

MIN

where:

M4 ON, M3 OFF

BUCK REGION

PWM M1, M2 SWITCHES

t

istheminimumon-timeforthesynchronous

ON(M2,MIN)

SWITCH

8705 F04

M2 DC

MAX

switch in buck operation (260ns typical, see Electrical

Characteristics).

Figure 4. Operating Regions vs V_OUT-V_IN

f is the switching frequency

Power Switch Control: Buck Region (V >> V

)

OUT

IN

When V is much higher than V

the duty cycle of

IN

OUT

switch M2 will increase, causing the M2 switch off-time

to decrease. The M2 switch off-time should be kept above

245ns (typical, see Electrical Characteristics) to maintain

steady-state operation, avoid duty cycle jitter, increased

When V is significantly higher than V , the part will

IN

OUT

run in the buck region. In this region switch M3 is always

off. Also, switch M4 is always on unless reverse current is

detected while in Burst Mode operation or discontinuous

mode. At the start of every cycle, synchronous switch M2

output ripple and reduction in maximum output current.

8705p

16

For more information www.linear.com/8705

LT8705

OPERATION

Power Switch Control: Buck-Boost (V ≅ V

)

Power Switch Control: Boost Region (V << V

)

OUT

IN

OUT

IN

When V is close to V , the controller enters the buck-

When V

is significantly higher than V , the part will

IN

OUT

OUT IN

boost region. Figure 6 shows typical waveforms in this

region.Everycycle,ifthecontrollerstartswithswitchesM2

and M4 turned on, the controller first operates as if in the

buck region. When A8 trips, switch M2 is turned off and

M1 is turned on until the middle of the clock cycle. Next,

switch M4 turns off and M3 turns on. The LT8705 then

operates as if in boost mode until A9 trips. Finally switch

M3 turns off and M4 turns on until the end of the cycle.

run in the boost region. In this region switch M1 is always

on and switch M2 is always off. At the start of every

cycle, switch M3 is turned on first. Inductor current is

sensed by amplifier A5 while switch M3 is on. A slope

compensation ramp is added to the sensed voltage which

is then compared (A9) to a reference that is proportional

to V . After the sensed inductor current rises above the

C

reference voltage, switch M3 is turned off and switch M4

is turned on for the remainder of the cycle. Switches M3

and M4 will alternate, behaving like a typical synchronous

boost regulator.

If the controller starts with switches M1 and M3 turned

on, the controller first operates as if in the boost region.

When A9 trips, switch M3 is turned off and M4 is turned

on until the middle of the clock cycle. Next, switch M1

turns off and M2 turns on. The LT8705 then operates as

if in buck mode until A8 trips. Finally switch M2 turns off

and M1 turns on until the end of the cycle.

The part will continue operating in the boost region over

a range of switch M3 duty cycles. The duty cycle of

switch M3 in the boost region is given by:







V

IN

DC_(M3,BOOST)= 1–

•100%





V_OUT



CLOCK

SWITCH M1

As V and V

get closer to each other, the duty cycle

IN

OUT

decreases until the minimum duty cycle of the converter

in boost mode reaches DC . If the duty

(ABSMIN,M3,BOOST)

will move to the buck-boost region:

SWITCH M2

SWITCH M3

SWITCH M4

(ABSMIN,M3,BOOST)

cycle becomes lower than DC

the part

I

L

DC ≅ t

• f • 100%

ON(M3,MIN)

(ABSMIN,M3,BOOST)

8705 F06a

(6a) Buck-Boost Region (V_IN≥ V_OUT

)

where:

t

istheminimumon-timeforthemainswitch

ON(M3,MIN)

CLOCK

in boost operation (265ns typical, see Electrical Char-

acteristics)

SWITCH M1

SWITCH M2

f is the switching frequency

SWITCH M3

SWITCH M4

CLOCK

ON

SWITCH M1

OFF

I

SWITCH M2

L

8705 F06b

SWITCH M3

SWITCH M4

(6b) Buck-Boost Region (V_IN≤ V_OUT

)

Figure 6. Buck-Boost Region

I

L

8705 F07

Figure 7. Boost Region (V_IN<< V_OUT

)

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LT8705

OPERATION

When V

is much higher than V the duty cycle of

age current is delivered to the output. During soft-start,

when the SS pin is below 1.6V, the part will be forced

into discontinuous mode to prevent pulling current from

the output to the input. After SS rises above 1.6V, forced

continuous mode will be enabled.

OUT

IN

switch M3 will increase, causing the M3 switch off-time

to decrease. The M3 switch off-time should be kept above

245ns (typical, see Electrical Characteristics) to maintain

steady-state operation, avoid duty cycle jitter, increased

output ripple and reduction in maximum output current.

Voltage Regulation Loops

Light Load Current Operation (MODE Pin)

The LT8705 provides two constant-voltage regulation

loops, one for output voltage and one for input voltage.

Under light current load conditions, the LT8705 can be set

tooperateindiscontinuousmode,forcedcontinuousmode,

orBurstModeoperation.Toselectforcedcontinuousmode,

tie the MODE pin to a voltage below 0.4V (i.e., ground). To

select discontinuous mode, tie MODE to a voltage above

2.3V (i.e., LDO33). To select Burst Mode operation, float

the MODE pin or tie it between 1.0V and 1.7V.

A resistor divider between V , FBOUT and GND senses

OUT

the output voltage. As with traditional voltage regulators,

when FBOUT rises near or above the reference voltage of

EA4 (1.207V typical, see Block Diagram), the V voltage

C

is reduced to command the amount of current that keeps

V

OUT

regulated to the desired voltage.

Discontinuous Mode: When the LT8705 is in discontinu-

ous mode, synchronous switch M4 is held off whenever

reversecurrentintheinductorisdetected.Thisistoprevent

current draw from the output and/or feeding current to the

input supply. Under very light loads, the current compara-

tor may also remain tripped for several cycles and force

switches M1 and M3 to stay off for the same number of

cycles (i.e., skipping pulses). Synchronous switch M2 will

remain on during the skipped cycles, but since switch M4

is off, the inductor current will not reverse.

The input voltage can also be sensed by connecting a

resistor divider between V , FBIN and GND. When the

IN

FBIN voltage falls near or below the reference voltage of

EA3 (1.205V typical, see Block Diagram), the V voltage is

C

reduced to also reduce the input current. For applications

withahighinputsourceimpedance(i.e.,asolarpanel),the

inputvoltageregulationloopcanpreventtheinputvoltage

frombecomingtoolowunderhighoutputloadconditions.

Forapplicationswithalowerinputsourceimpedance(i.e.,

batteries and voltage supplies), the FBIN pin can be used

to stop switching activity when the input power supply

voltage gets too low for proper system operation. See the

Applications Information section for more information

about setting up the voltage regulation loops.

Burst Mode Operation: Burst Mode operation sets a

V level, with about 25mV of hysteresis, below which

C

switching activity is inhibited and above which switching

activity is re-enabled. A typical example is when, at light

outputcurrents,V

risesandforcestheV pinbelowthe

C

OUT

Current Monitoring and Regulation

threshold that temporarily inhibits switching. After V

OUT

dropsslightlyandV rises~25mVtheswitchingisresumed,

C

The LT8705 provides two constant-current regulation

loops, one for input current and one for output current. A

sensing resistor close to the input capacitor, sensed by

CSPIN and CSNIN, monitors the input current. A current,

initially in the buck-boost region. Burst Mode operation

canincreaseefficiencyatlightloadcurrentsbyeliminating

unnecessary switching activity and related power losses.

Burst Mode operation handles reverse-current detection

similar to discontinuous mode. The M4 switch is turned

off when reverse current is detected.

linearlyproportionaltothesensevoltage(V

-V

),

CSPIN CSNIN

is forced out of the IMON_IN pin and into an external re-

sistor. The resulting voltage V is therefore linearly

IMON_IN

proportional to the input current. Similarly, a sensing

resistor close to the output capacitor, and sensed by

CSPOUT and CSNOUT will monitor the output current and

IMON_OUT

to the output current.

Forced Continuous Mode: The forced continuous mode

allows the inductor current to reverse directions without

any switches being forced “off” to prevent this from hap-

pening. At very light load currents the inductor current

will swing positive and negative as the appropriate aver-

generate a voltage V

that is linearly proportional

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LT8705

OPERATION

When the input or output current causes the respective

its regulation voltage (≅1.2V typical). The SRVO pins can

therefore be used as indicators of when their respective

feedback loops are active. For example, the SRVO_FBOUT

pinpullslowwhenFBOUTrisestowithin29mV(typical,see

ElectricalCharacteristics)ofitsregulationvoltage(1.207V

typical). The pull-down turns off after FBOUT falls to more

than 44mV (typical) lower than its regulation voltage.

As another example, the SRVO_IOUT pin can be read to

determine when the output current has nearly reached its

predetermined limit. A logic “1” on SRVO_IOUT indicates

that the output current has not reached the current limit

and a logic “0” indicates that it has.

IMON_IN or IMON_OUT voltage to rise near or above

1.208V (typical), the V pin voltage will be pulled down to

C

maintainthedesiredmaximuminputand/oroutputcurrent

(seeEA1andEA2ontheBlockDiagram).Theinputcurrent

limit function prevents overloading the DC input source,

while the output current limit provides a building block

for battery charger or LED driver applications. It can also

serve as short-circuit protection for a constant-voltage

regulator.SeetheApplicationsInformationsectionformore

information about setting up the current regulation loops.

SRVO Pins

CLKOUT and Temperature Sensing

The QFN package has four open-drain SRVO pins:

SRVO_FBIN, SRVO_FBOUT, SRVO_IIN, SRVO_IOUT.

Place pull-up resistors from the desired SRVO pin(s) to a

power supply less than 30V (i.e., the LDO33 pin) to enable

readingoftheirlogicstates.TheSRVO_FBOUT,SRVO_IIN

and SRVO_IOUT pins are pulled low when their associ-

ated error amp (EA4, EA2, EA1) input voltages are near

or greater than their regulation voltages (≅1.2V typical).

SRVO_FBIN is pulled low when FBIN is near or lower than

The CLKOUT pin toggles at the LT8705’s internal clock

frequencywhethertheinternalclockissynchronizedtoan

externalsourceorisfree-runningbasedontheexternalR

resistor.TheCLKOUTpincanbeusedtosynchronizeother

devicestotheLT8705’sswitchingfrequency.Also,theduty

cycle of CLKOUT is proportional to the die temperature

and can be used to monitor the die for thermal issues.

T

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LT8705

APPLICATIONS INFORMATION

The first page shows a typical LT8705 application circuit.

Aftertheswitchingfrequencyisselected,externalcompo-

where f

is in kHz and R is in kΩ. Conversely, R (in

OSC T T

kΩ) can be calculated from the desired frequency (in

kHz) using:

nent selection continues with the selection of R

and

SENSE

theinductorvalue.Next,thepowerMOSFETsareselected.

Finally, C and C are selected. The following examples

and equations assume continuous conduction mode un-

less otherwise specified. The circuit can be configured

for operation up to an input and/or output voltage of 80V.





43,750

f_OSC

IN

OUT

R_T=

–1 kΩ









SYNC Pin and Clock Synchronization

TheoperatingfrequencyoftheLT8705canbesynchronized

to an external clock source. To synchronize to the external

source, simply provide a digital clock signal into the SYNC

pin. The LT8705 will operate at the SYNC clock frequency.

Operating Frequency Selection

The LT8705 uses a constant frequency architecture

between 100kHz and 400kHz. The frequency can be set

using the internal oscillator or can be synchronized to an

externalclocksource.Selectionoftheswitchingfrequency

is a trade-off between efficiency and component size.

Low frequency operation increases efficiency by reducing

MOSFET switching losses, but requires more inductance

and/or capacitance to maintain low output ripple voltage.

For high power applications, consider operating at lower

frequencies to minimize MOSFET heating from switching

losses. The switching frequency can be set by placing an

appropriate resistor from the RT pin to ground and tying

theSYNCpinlow. Thefrequencycanalsobesynchronized

to an external clock source driven into the SYNC pin. The

following sections provide more details.

The duty cycle of the SYNC signal must be between 20%

and 80% for proper operation. Also, the frequency of the

SYNC signal must meet the following two criteria:

1. SYNC may not toggle outside the frequency range of

100kHz to 400KHz unless it is stopped low to enable

the free-running oscillator.

2. The SYNC pin frequency can always be higher than the

free-running oscillator set frequency, f , but should

OSC

not be less than 25% below f

.

OSC

After SYNC begins toggling, it is recommended that

switching activity is stopped before the SYNC pin stops

toggling. Excess inductor current can result when SYNC

stops toggling as the LT8705 transitions from the external

SYNC clock source to the internal free-running oscillator

clock. Switching activity can be stopped by driving either

the SWEN or SHDN pin low.

Internal Oscillator

The operating frequency of the LT8705 can be set using

the internal free-running oscillator. When the SYNC pin

is driven low (<0.5V), the frequency of operation is set

by the value of a resistor from the RT pin to ground. An

internally trimmed timing capacitor resides inside the IC.

The oscillator frequency is calculated using the following

formula:

CLKOUT Pin and Clock Synchronization

The CLKOUT pin can drive up to 200pF and toggles at the

LT8705’sinternalclockfrequencywhethertheinternalclock

is synchronized to the SYNC pin or is free-running based













43,750

on the external R resistor. The rising edge of CLKOUT is

f_OSC

=

kHz

T

R + 1

T

approximately 180° out of phase from the internal clock’s

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LT8705

APPLICATIONS INFORMATION

rising edge or the SYNC pin’s rising edge if it is toggling.

CLKOUT toggles only in normal mode (see Figure 2).

a reduction of maximum inductor current in the boost

region, and an increase of the maximum inductor current

in the buck region. For example, refer to the Maximum

InductorCurrentSenseVoltagevsDutyCyclegraphinthe

Typical Performance Characteristics section. The graph

showsthat,withV_Catitsmaximumvoltage,themaximum

inductor sense voltage V_RSENSEis between 78mV and

117mV depending on the duty cycle. It also shows that

the maximum inductor valley current in the buck region

is 86mV increasing to ~130mV at higher duty cycles.

The CLKOUT pin can be used to synchronize other de-

vices to the LT8705’s switching frequency. For example,

the CLKOUT pin can be tied to the SYNC pin of another

LT8705 regulator which will operate approximately 180°

out of phase of the master LT8705 due to the CLKOUT

phase shift. The frequency of the master LT8705 can be

set by the external R resistor or by toggling the SYNC

T

pin. CLKOUTwillbeginoscillatingafterthemasterLT8705

enters normal mode (see Figure 2). Note that the RT pin

of the slave LT8705 must have a resistor tied to ground.

R

SENSE

Selection and Maximum Current

TheR

resistancemustbechosenproperlytoachieve

In general, use the same value R resistor for all of the

SENSE

T

thedesiredamountofoutputcurrent.Toomuchresistance

synchronized LT8705s.

can limit the output current below the application require-

The duty cycle of CLKOUT is proportional to the die tem-

perature and can be used to monitor the die for thermal

issues.SeetheJunctionTemperatureMeasurementsection

for more information.

ments.StartbydeterminingthemaximumallowedR

SENSE

resistanceintheboostregion, R

. Follow

SENSE(MAX,BOOST)

this by finding the maximum allowed R

resistance in

SENSE

the buck region, R

. The selected R

SENSE(MAX,BUCK)

SENSE

resistance must be smaller than both.

Boost Region: In the boost region, the maximum output

current capability is the least when V is at its minimum

Inductor Current Sensing and Slope Compensation

TheLT8705operatesusinginductorcurrentmodecontrol.

As described previously in the Power Switch Control sec-

tion,theLT8705measuresthepeakoftheinductorcurrent

waveformintheboostregionandthevalleyoftheinductor

current waveform in the buck region. The inductor current

IN

and V

is at its maximum. Therefore R

must be

OUT

SENSE

chosen to meet the output current requirements under

these conditions.

is sensed across the R

resistor with pins CSP and

Start by finding the boost region duty cycle when V is

IN

SENSE

CSN. During any given cycle, the peak (boost region) or

minimum and V

is maximum using:

OUT

valley (buck region) of the inductor current is controlled







V

IN(MIN)

by the V pin voltage.

C

DC_{(MAX,M3,BOOST)}≅ 1–

•100%



V



_OUT(MAX)

Slope compensation provides stability in constant-

frequencycurrentmodecontrolarchitecturesbyprevent-

ing subharmonic oscillations at high duty cycles. This

is accomplished internally by adding a compensating

ramp to the inductor current signal in the boost region,

or subtracting a ramp from the inductor current signal

in the buck region. At higher duty cycles, this results in

For example, an application with a V range of 12V to

IN

48V and V

set to 36V will have:

OUT

12V

36V





DC_{(MAX,M3,BOOST)}≅ 1–

•100%= 67%









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LT8705

APPLICATIONS INFORMATION

Referring to the Maximum Inductor Current Sense Volt-

age graph in the Typical Performance Characteristics

After the maximum ripple current is known, the maximum

allowed R

follows:

in the boost region can be calculated as

SENSE

section, the maximum R

voltage at 67% duty cycle

SENSE

is ≅93mV, or:

R_{SENSE(MAX,BOOST)}

=

V

≅93mV

RSENSE(MAX,BOOST, MAX)

2•V_{RSENSE(MAX,BOOST,MAX)}•V

IN(MIN)

Ω

for V = 12V, V

= 36V.

IN

OUT

2•I_{OUT(MAX,BOOST)}•V_OUT(MIN)+ ∆I

•V

IN(MIN)

(

) (

)

L(MAX,BOOST)

Next, the inductor ripple current in the boost region must

be determined. If the main inductor L is not known, the

where V

is the maximum inductor

RSENSE(MAX,BOOST,MAX)

currentsensevoltageasdiscussedintheprevioussection.

maximum ripple current ∆I

can be estimated

L(MAX,BOOST)

by choosing ∆I

to be 30% to 50% of the

L(MAX,BOOST)

Using values from the previous examples:

maximum inductor current in the boost region as follows:

2•93mV •12

2•2A •36V + 3A •12V

) (

R_{SENSE(MAX,BOOST)}

=

= 12.4mΩ

V_OUT(MAX)•I

^{OUT(MAX,BOOST)}A

(

)

∆I_L(MAX,BOOST)

≅

 100%



V

•

–0.5

IN(MIN)









%Ripple

BuckRegion:Inthebuckregion,themaximumoutputcur-

rent capability is the least when operating at the minimum

duty cycle. This is because the slope compensation ramp

where:

increases the maximum R

voltage with increasing

SENSE

I

is the maximum output load current

OUT(MAX,BOOST)

duty cycle. The minimum duty cycle for buck operation

can be calculated using:

required in the boost region

%Ripple is 30% to 50%

DC

≅ t

• f • 100%

ON(M2,MIN)

(MIN,M2,BUCK)

For example, using V

OUT(MAX,BOOST)

= 36V, V

= 12V,

IN(MIN)

OUT(MAX)

where t

is 260ns (typical value, see Electrical

ON(M2,MIN)

Characteristics)

I

=2Aand%Ripple=40%wecanestimate:

36V •2A

∆I_L(MAX,BOOST)

≅

= 3A

Before calculating the maximum R

however, the inductor ripple current must be determined.

If the main inductor L is not known, the ripple current

resistance,

100%

40%





SENSE

12V •

–0.5









Otherwise, if the inductor value is already known then

∆I can be more accurately calculated as

∆I

canbeestimatedbychoosing ∆I

L(MIN,BUCK)

L(MAX,BOOST)

to be 10% of the maximum inductor current in the buck

follows:

region as follows:

DC

_{(MAX,M3,BOOST)}





I

^{OUT(MAX,BUCK)}A

•V

∆I_L(MIN,BUCK)

≅

IN(MIN)





100%

f•L



100%

10%





–0.5

∆I_L(MAX,BOOST)

=

A









where:

DC

where:

is the maximum duty cycle percent-

I

is the maximum output load current

(MAX,M3,BOOST)

age in the boost region as calculated previously.

OUT(MAX,BUCK)

required in the buck region.

f is the switching frequency

L is the inductance of the main inductor

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LT8705

APPLICATIONS INFORMATION

If the inductor value is already known then ∆I

constant(frequency=350kHz,inductance=10μH,R

=

L(MIN,BUCK)

SENSE

can be calculated as follows:

10mΩ).Thisgraphisnormalizedandaccountsforchanges

inmaximumcurrentduetotheslopecompensationramps

and the effects of changing ripple current. The curve is

theoretical, but can be used as a guide to predict relative

changes in maximum output and inductor current over a

DC

_{(MIN,M2,BUCK)}





•V_OUT(MIN)





100%



∆I_L₍_MIN,BUCK

=

A

)

f•L

range of V /V

voltages.

IN OUT

where:

DC

is the minimum duty cycle percentage

(MIN,M2,BUCK)

in the buck region as calculated previously.

Reverse Current Limit

When the forced continuous mode is selected (MODE

pin low), inductor current is allowed to reverse directions

f is the switching frequency

and flow from the V

side to the V side. This can lead

OUT

IN

L is the inductance of the main inductor

After the inductor ripple current is known, the maximum

to current sinking from the output and being forced into

the input. The reverse current is at a maximum magni-

allowed R

follows:

in the buck region can be calculated as

SENSE

tude when V is lowest. The graph of Minimum Inductor

C

Current Sense Voltage in FCM in the Typical Performance

Characteristicssectioncanhelptodeterminethemaximum

reverse current capability.

2•86mV

R_{SENSE(MAX,BUCK)}

=

2•I

– ∆I

L(MIN,BUCK)

(

)

OUT(MAX,BUCK)

Inductor Selection

Final R

Value: The final R

value should be

SENSE(MAX,BUCK)

SENSE

lowerthanbothR

SENSE

For high efficiency, choose an inductor with low core

loss, such as ferrite. Also, the inductor should have low

andR

.

SENSE(MAX,BOOST)

A margin of 30% or more is recommended.

2

DC resistance to reduce the I R losses, and must be able

Figure 8 shows approximately how the maximum output

current and maximum inductor current would vary with

to handle the peak inductor current without saturating. To

minimize radiated noise, use a toroid, pot core or shielded

bobbin inductor.

V /V

IN OUT

while all other operating parameters remain

1.0

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. The following

sectionsdiscussseveralcriteriatoconsiderwhenchoosing

an inductor value. For optimal performance, choose an

inductor that meets all of the following criteria.

0.8

MAXIMUM

INDUCTOR

CURRENT

0.6

MAXIMUM

OUTPUT

CURRENT

0.4

Inductor Selection: Adequate Load Current in the

Boost Region

0.2

0

Small value inductors result in increased ripple currents

andthus,duetothelimitedpeakinductorcurrent,decrease

the maximum average current that can be provided to the

10

0.1

1

V

/V

(V/V)

IN OUT

8705 F08

load (I ) while operating in the boost region.

OUT

Figure 8. Currents vs V_IN/V_OUTRatio

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LT8705

APPLICATIONS INFORMATION

In order to provide adequate load current at low V volt-

In the boost region, if V

can be greater than twice V ,

IN

OUT IN

as follows:

ages in the boost region, L should be at least:

calculate L

(MIN2,BOOST)

L_(MIN1,BOOST)

≅

L_(MIN2,BOOST)

=



DC

_{(MAX,M3,BOOST)}















V

_IN(MIN)•V_OUT(MAX)

V

•

IN(MIN)

V

–

•R

SENSE









OUT(MAX)

100%



V

– V



_IN(MIN) _





OUT(MAX)



H





V_{RSENSE(MAX,BOOST,MAX)}I_OUT(MAX)•V_OUT(MAX)

0.08•f

2•f•

–





R_SENSE

V

IN(MIN)





In the buck region, if V can be greater than twice V

,

IN

OUT

calculate L

as follows:

where:

DC

(MIN1,BUCK)

L

=

is the maximum duty cycle per-

(MAX,M3,BOOST)

(MIN1,BUCK)

centage of the M3 switch (see R

Maximum Current section).

Selection and

SENSE





V

OUT(MAX)

V

• 1–

•R

SENSE

IN(MAX) 



V

– V

OUT(MIN)

f is the switching frequency





IN(MAX)

H

0.08 • f

V

isthemaximumcurrentsense

RSENSE(MAX,BOOST,MAX)

voltage in the boost region at maximum duty cycle (see

Selection and Maximum Current section)

R

Inductor Selection: Maximum Current Rating

SENSE

Negative values of L

indicate that the output

The inductor must have a rating greater than its peak

operating current to prevent inductor saturation resulting

in efficiency loss. The peak inductor current in the boost

region is:

(MIN1,BOOST)

can’t be delivered in the boost region

load current I

OUT

becausetheinductorcurrentlimitistoolow.IfL

(MIN1,BOOST)

is too large or is negative, consider reducing the R

SENSE

resistor value to increase the inductor current limit.

V

OUT(MAX)

I

≅ I

•

L(MAX,BOOST) OUT(MAX)

V

Inductor Selection: Subharmonic Oscillations

IN(MIN)

The LT8705’s internal slope compensation circuits will

prevent subharmonic oscillations that can otherwise oc-





DC





(MAX,M3,BOOST

V

•

IN(MIN)









100%





cur when V /V

is less than 0.5 or greater than 2. The

IN OUT

+

A

slopecompensationcircuitswillpreventtheseoscillations

provided that the inductance exceeds a minimum value

(seetheearliersectionInductorCurrentSensingandSlope

Compensation for more information). Choose an induc-

2 •L • f









where DC

percentage of the M3 switch (see R

Maximum Current section).

is the maximum duty cycle

(MAX,M3,BOOST)

tancegreaterthanalloftherelevantL

limitsdiscussed

(MIN)

Selection and

SENSE

below. Negative results can be interpreted as zero.

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LT8705

APPLICATIONS INFORMATION

The peak inductor current when operating in the buck

region is:

It is very important to consider power dissipation when

selecting power MOSFETs. The most efficient circuit will

use MOSFETs that dissipate the least amount of power.

Power dissipation must be limited to avoid overheating

that might damage the devices. For most buck-boost ap-

plications the M1 and M3 switches will have the highest

power dissipation where M2 will have the lowest unless

the output becomes shorted. In some cases it can be

helpful to use two or more MOSFETs in parallel to reduce

powerdissipationineachdevice.Thisismosthelpfulwhen

I_L(MAX,BUCK)≅ I_OUT(MAX)





DC









(MAX,M2,BUCK

V_OUT(MIN)

•









100%

+

A

2•L•f









2

power is dominated by I R losses while the MOSFET is

where DC

is the maximum duty cycle per-

(MAX,M2,BUCK)

centage of the M2 switch in the buck region given by:

“on”. The additional capacitance of connecting MOSFETs

inparallelcansometimesslowdownswitchingedgerates

and consequently increase total switching power losses.





V

OUT(MIN)

DC

≅ 1–

•100%





MAX,M2,BUCK

(

)

V

The following sections provide guidelines for calculating

power consumption of the individual MOSFETs. From a

known power dissipation, the MOSFET junction tempera-

ture can be obtained using the following formula:





IN(MAX)

Note that the inductor current can be higher during load

transients and if the load current exceeds the expected

maximum I . It can also be higher during start-

OUT(MAX)

T = T + P • R

J

A

TH(JA)

up if inadequate soft-start capacitance is used or during

output shorts. Consider using the output current limiting

topreventtheinductorcurrentfrombecomingexcessive.

Output current limiting is discussed later in the Input/

Output Current Monitoring and Limiting section. Care-

ful board evaluation of the maximum inductor current

is recommended.

where:

T is the junction temperature of the MOSFET

J

T is the ambient air temperature

A

P is the power dissipated in the MOSFET

R

TH(JA)

is the MOSFET’s thermal resistance from the

junction to the ambient air. Refer to the manufacturer’s

data sheet.

Power MOSFET Selection and Efficiency

Considerations

R

normally includes the R

for the device plus

TH(JC)

TheLT8705requiresfourexternalN-channelpowerMOS-

FETs,twoforthetopswitches(switchesM1andM4,shown

in Figure 3) and two for the bottom switches (switches

M2 and M3, shown in Figure 3). Important parameters for

TH(JA)

the thermal resistance from the case to the ambient tem-

perature R . Compare the calculated value of T to

TH(JC)

J

the manufacturer’s data sheets to help choose MOSFETs

that will not overheat.

the power MOSFETs are the breakdown voltage, V

,

BR,DSS

,reverse-

thresholdvoltage,V

,on-resistance,R

RSS

DS(MAX)

GS,TH

DS(ON)

Switch M1: The power dissipation in switch M1 comes

from two primary components: (1) I R power when the

switch is fully turned “on” and inductor current is flowing

through the drain to source connections and (2) power

transfercapacitance,C (gate-to-draincapacitance),and

2

maximum current, I

. The gate drive voltage is set

by the 6.35V GATEV supply. Consequently, logic-level

CC

threshold MOSFETs must be used in LT8705 applications.

8705p

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For more information www.linear.com/8705

LT8705

APPLICATIONS INFORMATION

dissipated while the switch is turning “on” or “off”. As the

switch turns “on” and “off” a combination of high current

and high voltage causes high power dissipation in the

MOSFET.Althoughtheswitchingtimesareshort,theaver-

age power dissipation can still be significant and is often

the dominant source of power in the MOSFET. Depending

on the application, the maximum power dissipation in

R

is the series gate resistance of the MOSFET

GATE

(usually < 1Ω—see manufacturer’s data sheet) plus

any additional resistance connected in series with the

MOSFET’s gate.

ρ is a normalization factor (unity at 25°C) accounting

τ

for the significant variation in MOSFET on-resistance

with temperature, typically about 0.4%/°C, as shown

in Figure 9. For a maximum junction temperature of

the M1 switch can happen in the buck region when V

IN

is highest, V

is highest, and switching power losses

OUT

125°C, using a value ρ = 1.5 is reasonable.

τ

are greatest or in the boost region when V is smallest,

IN

Since the switching power (P

look for MOSFETs with lower C

at a lower frequency to minimize power loss and increase

efficiency.

) often dominates,

V

OUT

is highest and M1 is always on. Switch M1 power

SWITCHING

or consider operating

consumption can be approximated as:

RSS

2

P_M1= P + P

I R

SWITCHING













 ²

V_OUT

2.0

1.5

1.0

0.5

0

≅

•I_OUT•R_DS(ON)•ρ_τ











V





IN

+ V •I

•f•t_RF1W

(

)

IN

OUT

where:

the P

term is 0 in the boost region

SWITCHING

t

is the average of the SW1 pin rise and fall times.

RF1

Typical values are 20ns to 40ns depending on the

MOSFET capacitance and V voltage. An estimate of

50

100

–50

150

0

IN

JUNCTION TEMPERATURE (°C)

t

canbecalculatedfromthefollowingequation.Verify

RF1

8705 F09

this with direct measurements. Since switching power

Figure 9. Normalized MOSFET R_DS(ON)vs Temperature

loss is proportional to t , this equation is useful to

RF1

understandhowcapacitanceandgateresistanceeffects

Switch M2: In most cases the switching power dissipa-

power loss in various MOSFETs:

2

tion in the M2 switch is quite small and I R power losses

R



_GATE

• 2+

 

2

dominate. I R power is greatest in the buck region where

t_RF1≅ V •C

IN

RSS





0.8

the switch operates as the synchronous rectifier. Higher

V and lower V

causes the M2 switch to be “on” for

IN

OUT

C

(gate-to-draincapacitance)isusuallyspecifiedby

RSS

the most amount of time, leading to the highest power

consumption. The M2 switch power consumption in the

buck region can be approximated as:

the MOSFET manufacturers. If C

is not specified,

RSS

but Q is, approximate C

as:

GD

RSS

Q_GD

V_DS













C_RSS

=

V – V

IN

OUT

P

≅

•I_OUT(MAX)²•R_DS(ON)•ρ_τW

(M2,BUCK)

V

IN

where V is the voltage specified for the given Q .

DS

GD

8705p

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LT8705

APPLICATIONS INFORMATION

Switch M3: Switch M3 operates in the boost and buck-

Gate Resistors: In some cases it can be beneficial to add

1Ω to 10Ω of resistance between some of the NMOS gate

pins and their respective gate driver pins on the LT8705

(i.e., TG1, BG1, TG2, BG2). Due to parasitic inductance

and capacitance, ringing can occur on SW1 or SW2 when

low capacitance MOSFETs are turned on/off too quickly.

The ringing can be of greatest concern when operating

the MOSFETs or the LT8705 near the rated voltage limits.

Additional gate resistance slows the switching speed,

minimizing the ringing.

boost regions as a control switch. Similar to the M1

2

switch, the power dissipation comes from I R power and

switchingpower.Themaximumpowerdissipationiswhen

V

is the lowest and V

is the highest. The following

IN

OUT

expression approximates the power dissipation in the M3

switch under those conditions:

2

P

= P + P

≅

M3

I R

SWITCHING





V

– V • V

(

)

IN

OUT

2

•I

•R

•ρ

τ

DS(ON)

OUT





2

V

Excessive gate resistance can have two negative side

effects on performance:





IN





t

RF2

2

1. Slowing the switch transition times can also increase

powerdissipationintheswitch.Thisisdescribedabove

in the Switch M1 and Switch M3 sections.

+ V

•I

• f •

W

OUT







V



IN

where the total power is 0 in the buck region.

2. Capacitive coupling from the SW1 or SW2 pin to the

switch gate node can turn it on when it’s supposed to

beoff,thusincreasingpowerdissipation.Withtoomuch

gate resistance, this would most commonly happen to

the M2 switch when SW1 is rising.

t

is the average of the SW2 pin rise and fall times

RF2

and, similar to t , is typically 20ns to 40ns or can be

RF1

estimated using:

R

0.8



_GATE



t_RF2≅ V_OUT•C_RSS• 2+







Careful board evaluation should be performed when

optimizing the gate resistance values. SW1 and SW2 pin

ringing can be affected by the inductor current levels,

therefore board evaluation should include measurements

at a wide range of load currents. When performing PCB

measurements of the SW1 and SW2 pins, be sure to use a

very short ground post from the PCB ground to the scope

probe ground sleeve in order to minimize false inductive

voltages readings.

As with the M1 switch, the switching power (P

often dominates. Look for MOSFETs with lower C

consideroperatingatalowerfrequencytominimizepower

loss and increase efficiency.

)

SWITCHING

or

RSS

Switch M4: In most cases the switching power dissipa-

2

tion in the M4 switch is quite small and I R power losses

2

dominate. I R power is greatest in the boost region where

the switch operates as the synchronous rectifier. Lower

V and higher V

increases the inductor current for a

IN

OUT

C and C

Selection

IN

OUT

given I , leading to the highest power consumption.

OUT

Input and output capacitance is necessary to suppress

voltage ripple caused by discontinuous current moving in

and out of the regulator. A parallel combination of capaci-

tors is typically used to achieve high capacitance and low

ESR (equivalent series resistance). Dry tantalum, special

The M4 switch power consumption in the boost region

can be approximated as:













V_OUT

P

≅

•I_OUT²•ρ_τ•R_DS(ON)

W

(M4,BOOST)

V

IN

8705p

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LT8705

APPLICATIONS INFORMATION

output ripple voltage. The steady-state output ripple due

to charging and discharging the bulk output capacitance

is given by the following equations:

polymer,aluminumelectrolyticandceramiccapacitorsare

all available in surface mount packages. Capacitors with

low ESR and high ripple current ratings, such as OS-CON

and POSCAP are also available.

I_OUT• V

– V

IN

(

)

V for V_OUT> V

OUT

∆V _BOOST,CAP

≅

IN

Ceramic capacitors should be placed near the regulator

input and output to suppress high frequency switching

spikes.Aceramiccapacitor,ofatleast1µFatthemaximum

(

)

C_OUT•V •f

IN









V_OUT

V

_OUT• 1–

V operating voltage, should also be placed from V to

IN





V

IN

GND as close to the LT8705 pins as possible. Due to their

excellent low ESR characteristics ceramic capacitors can

significantly reduce input ripple voltage and help reduce

power loss in the higher ESR bulk capacitors. X5R or X7R

dielectrics are preferred, as these materials retain their

capacitance over wide voltage and temperature ranges.

Many ceramic capacitors, particularly 0805 or 0603 case

sizes, have greatly reduced capacitance at the desired

operating voltage.

∆V

≅

V for V_OUT< V

IN

(BUCK,CAP)

8•L•f²•C_OUT

Themaximumoutputrippleduetothevoltagedropacross

the ESR is approximately:

V_OUT(MAX)•I

∆V

≅

^OUT(MAX)•ESR

(BOOST,ESR)

V

IN(MIN)

As with C , multiple capacitors placed in parallel may

IN

be needed to meet the ESR and RMS current handling

InputCapacitance:Discontinuousinputcurrentishighest

requirements.

inthebuckregionduetotheM1switchtogglingonandoff.

Make sure that the C capacitor network has low enough

IN

Schottky Diode (D1, D2) Selection

ESR and is sized to handle the maximum RMS current.

For buck operation, the input RMS current is given by:

The Schottky diodes, D1 and D2, shown in Figure 1, con-

duct during the dead time between the conduction of the

power MOSFET switches. They are intended to prevent

the body diodes of synchronous switches M2 and M4

from turning on and storing charge. For example, D2

significantly reduces reverse-recovery current between

switchM4turn-offandswitchM3turn-on,whichimproves

converterefficiency,reducesswitchM3powerdissipation

and reduces noise in the inductor current sense resistor

V_OUT

V

IN

V_OUT

I_RMS≅ I_OUT(MAX)

•

–1

V

IN

This formula has a maximum at V = 2V , where

IN

OUT

I

= I

/2. This simple worst-case condition

RMS

OUT(MAX)

is commonly used for design because even significant

deviations do not offer much relief.

The maximum input ripple due to the voltage drop across

the ESR is approximately:

(R

) when M3 turns on. In order for the diode to be

SENSE

effective, the inductance between it and the synchronous

switch must be as small as possible, mandating that these

components be placed adjacently.

V_IN(MAX)•I

^OUT(MAX)•ESR

V_OUT(MIN)

∆V

≅

(BUCK,ESR)

For applications with high input or output voltages (typi-

cally>40V)avoidSchottkydiodeswithexcessivereverse-

leakage currents particularly at high temperatures. Some

Output Capacitance: The output capacitance (C ) is

OUT

necessary to reduce the output voltage ripple caused by

discontinuities and ripple in the output and load currents.

The effects of ESR and the bulk capacitance must be

considered when choosing the right capacitor for a given

ultralowV diodeswilltradeoffincreasedhightemperature

F

leakage current for reduced forward voltage. Diode D1

8705p

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LT8705

APPLICATIONS INFORMATION

can have a reverse voltage up to V and D2 can have

Boost Diodes D and D : Although Schottky diodes

B1 B2

IN

a reverse voltage up to V . The combination of high

have the benefit of low forward voltage drops, they can

exhibithighreversecurrentleakageandhavethepotential

for thermal runaway under high voltage and temperature

conditions. Silicon diodes are thus recommended for

OUT

reverse voltage and current can lead to self heating of

the diode. Besides reducing efficiency, this can increase

leakagecurrentwhichincreasestemperaturesevenfurther.

Choose packages with lower thermal resistance (θ ) to

minimize self heating of the diodes.

diodes D and D . Make sure that D and D have

JA

B1 B2 B1 B2

reverse breakdown voltage ratings higher than V

IN(MAX)

and V

and have less than 1mA of reverse leakage

OUT(MAX)

Topside MOSFET Driver Supply (C , D , C , D )

current at the maximum operating junction temperature.

Make sure that the reverse leakage current at high op-

erating temperatures and voltages won’t cause thermal

runaway of the diode.

B1 B1 B2 B2

ThetopMOSFETdrivers(TG1andTG2)aredrivendigitally

between their respective SW and BOOST pin voltages.

The BOOST voltages are biased from floating bootstrap

capacitors C and C , which are normally recharged

In some cases it is recommended that up to 5Ω of resis-

tance is placed in series with D and D . The resistors

B1

B2

through external silicon diodes D and D when the

B1

B2

B1

B2

respective top MOSFET is turned off. The capacitors are

reducesurgecurrentsinthediodesandcanreduceringing

at the SW and BOOST pins of the IC. Since SW pin ringing

is highly dependent on PCB layout, SW pin edge rates and

the type of diodes used, careful measurements directly

at the SW pins of the IC are recommended. If required, a

chargedtoabout6.3V(aboutequaltoGATEV )forcingthe

CC

V

and V

voltages to be about 6.3V.

The boost capacitors C and C need to store about 100

BOOST1-SW1

BOOST2-SW2

B1

B2

timesthegatechargerequiredbythetopswitchesM1and

M4. In most applications, a 0.1μF to 0.47μF, X5R or X7R

dielectric capacitor is adequate. The bypass capacitance

single resistor can be placed between GATEV and the

CC

common anodes of D and D (as in the front page

B1

B2

from GATEV to GND should be at least ten times the

application) or by placing separate resistors between the

CC

C

B1

or C capacitance.

cathodes of each diode and the respective BOOST pins.

B2

ExcessiveresistanceinserieswithD andD canreduce

B1

B2

BoostCapacitorChargeControlBlock:WhentheLT8705

operates exclusively in the buck or boost region, one of

the top MOSFETS, M1 or M4, can be constantly on. This

the BOOST-SW capacitor voltage when the M2 or M3

on-times are very short and should be avoided.

prevents the respective bootstrap capacitor, C or C ,

B1

B2

Output Voltage

from being recharged through the silicon diode, D or

B1

D . The Boost Capacitor Charge Control block (see Fig-

The LT8705 output voltage is set by an external feedback

resistivedividercarefullyplacedacrosstheoutputcapaci-

tor. The resultant feedback signal (FBOUT) is compared

with the internal precision voltage reference (typically

1.207V) by the error amplifier EA4. The output voltage is

given by the equation:

B2

ure 1) keeps the appropriate BOOST pin charged in these

cases. When the M1 switch is always on (boost region),

current is automatically drawn from the CSPOUT and/or

BOOST2 pins to charge the BOOST1 capacitor as needed.

When the M4 switch is always on (buck region) current

is drawn from the CSNIN and/or BOOST1 pins to charge

the BOOST2 capacitor. Because of this function, CSPIN

and CSNIN should be connected to a potential close to









R_FBOUT1

R

V_OUT= 1.207V • 1+



_FBOUT2

V . Tie both pins to V if they are not being used. Also,

IN

where R

and R

are shown in Figure 1.

FBOUT1

FBOUT2

CSPOUT and CSNOUT should always be tied to a potential

close to V , or be tied directly to V if not being used.

OUT

8705p

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APPLICATIONS INFORMATION

Input Voltage Regulation or Undervoltage Lockout

R

SENSE1

FROM DC

POWER SUPPLY

TO REMAINDER

OF SYSTEM

By connecting a resistor divider between V , FBIN and

IN

INPUT

CURRENT

GND, the FBIN pin provides a means to regulate the input

voltage or to create an undervoltage lockout function.

Referring to error amplifier EA3 in the Block Diagram,

CSPIN

CSNIN

LT8705

TO BOOST CAPACITOR

CHARGE CONTROL BLOCK

+

–

Ω

g

= 1m

A7

m

when FBIN is lower than the 1.205V reference V is pulled

C

low. For example, if V is provided by a relatively high

IN

impedancesource(i.e.,asolarpanel)andthecurrentdraw

–

+

1.61V 1.208V

+

–

pulls V below a preset limit, V will be reduced, thus

IN

C

FAULT

CONTROL

EA2

reducing current draw from the input supply and limiting

the voltage drop. Note that using this function in forced

continuous mode (MODE pin low) can result in current

being drawn from the output and forced into the input.

If this behavior is not desired then use discontinuous or

Burst Mode operation.

V

C

IMON_IN

R

C

IMON_IN

8705 F10

To set the minimum or regulated input voltage use:

Figure 10. Input Current Monitor and Limit





R_FBIN1

R

SENSE2

FROM

V

_IN(MIN)= 1.205V • 1+







CONTROLLER

TO SYSTEM V

OUT

_FBIN2

V

OUT

OUTPUT

CURRENT

where R

sure to select R

and R

are shown in Figure 1. Make

FBIN1

FBIN2

and R

CSPOUT CSNOUT

such that FBIN doesn’t

LT8705

TO BOOST CAPACITOR

CHARGE CONTROL BLOCK

FBIN1

FBIN2

exceed 30V (absolute maximum rating) under maximum

+

–

Ω

g

= 1m

A8

m

V conditions.

IN

This same technique can be used to create an undervolt-

age lockout if the LT8705 is NOT in forced continuous

mode. When in Burst Mode operation or discontinuous

–

+

1.61V 1.208V

+

–

FAULT

CONTROL

EA1

mode, forcing V low will stop all switching activity. Note

C

that this does not reset the soft-start function, therefore

resumption of switching activity will not be accompanied

by a soft-start.

V

IMON_OUT

C

R

C

IMON_OUT

Input/Output Current Monitoring and Limiting

8705 F11

The LT8705 has independent input and output current

monitor circuits that can be used to monitor and/or limit

the respective currents. The current monitor circuits work

as shown in Figures 10 and 11.

Figure 11. Output Current Monitor and Limit

all four of the current sense pins can draw bias current

under normal operating conditions. As such, do not place

resistors in series with any of the CSxIN or CSxOUT pins.

AsdescribedintheTopsideMOSFETDriverSupplysection,

the CSNIN and CSPOUT pins are also connected to the

Boost Capacitor Charge Control block (also see Figure 1)

and can draw current in certain conditions. In addition,

Also, becauseoftheirusewiththeBoostCapacitorCharge

Control block, tie the CSPIN and CSNIN pins to V and

IN

tie the IMON_IN pin to ground when the input current

8705p

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LT8705

APPLICATIONS INFORMATION

sensing is not in use. Similarly, the CSPOUT and CSNOUT

CurrentLimiting:AsshowninFigure10,IMON_INvoltages

pins should be tied to V

and IMON_OUT should be

exceeding1.208V(typical)causetheV voltagetoreduce,

OUT

C

grounded when not in use.

thuslimitingtheinductorandinputcurrents.R

be selected for a desired input current limit using:

can

IMON_IN

Theremainingdiscussionreferstotheinputcurrentmoni-

tor circuit. All discussion and equations are applicable to

the output current monitor circuit, substituting pin and

device names as appropriate.





1.208V





R_{IMON_IN}

=

Ω

A

V

I

_{RSENSE(LIMIT)}•1m •R







^SENSE1

Current Monitoring: For input current monitoring, cur-

rent flowing through R

develops a voltage across

SENSE1

For example, if R

is chosen to be 12.5mΩ and the

SENSE1

CSPIN and CSNIN which is multiplied by 1mA/V (typical),

converting it to a current that is forced out of the IMON_IN

desired input current limit is 4A then:

1.208V

pin and into resistor R

(Note: Negative CSPIN to

IMON_IN

R_{IMON_IN}

=

= 24.2kΩ

A

CSNIN voltages are not multiplied and no current flows

out of IMON_IN in that case). The resulting IMON_IN volt-

age is then proportional to the input current according to:

4A •1m •12.5mΩ

V

ReviewtheElectricalCharacteristicsandtheIMONOutput

Currents graph in the Typical Performance Characteris-

tics section to understand the operational limits of the

IMON_OUT and IMON_IN currents.

A

V







V

= I_RSENSE1• R_SENSE1•1m •R





IMON_IN

^IMON_IN

For accurate current monitoring, the CSPIN and CSNIN

voltagesshouldbekeptabove1.5V(CSPOUTandCSNOUT

pins should be kept above 0V). Also, the differential volt-

Overcurrent Fault: If IMON_IN exceeds 1.61V (typical), a

fault will occur and switching activity will stop (see Fault

Conditions earlier in the data sheet). The fault current is

determined by:

age V

should be kept below 100mV due to

CSPIN-CSNIN

the limited amount of current that can be driven out of

IMON_IN. Finally, the IMON_IN voltage must be filtered

1.61V



1.208V





I_{RSENSE1(FAULT)}

=

•I

^{RSENSE1(LIMIT)}

A





with capacitor C

because the input current often

IMON_IN

has ripple and discontinuities depending on the LT8705’s

For example, an input current limit set to 4A would have

a fault current limit of 5.3A.

region of operation. C

equation:

should be chosen by the

IMON_IN







100

Output Overvoltage

C_{IMON_IN}

>

F



f•R



_{IMON_IN}

If the output voltage is higher than the value set by the

FBOUTresistordivider,theLT8705willrespondaccording

to the mode and region of operation. In forced continu-

ous mode, the LT8705 will sink current into the input (see

the Reverse Current Limit discussion in the Applications

Information section for more information). In discontinu-

ous mode and Burst Mode operation, switching will stop

and the output will be allowed to remain high.

where f is the switching frequency, to achieve adequate

filtering. Additional capacitance, bringing the C

total to 0.1μF to 1μF, may be necessary to maintain loop

stability if the IMON_IN pin is used in a constant-current

regulation loop.

IMON_IN

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APPLICATIONS INFORMATION

The maximum current drawn through the INTV LDO

INTV Regulators and EXTV Connection

CC

occurs under the following conditions:

The LT8705 features two PNP LDOs (low dropout regu-

lators) that regulate the 6.35V (typical) INTV pin from

1. Large (capacitive) MOSFETs are being driven at high

frequencies.

CC

either the V or EXTV supply pin. INTV powers the

IN

CC

MOSFET gate drivers via the required GATEV connec-

CC

2. V and/or V

is high, thus requiring more charge to

IN

OUT

tion and also powers the LDO33 pin regulator and much

turn the MOSFET gates on and off.

of the LT8705’s internal control circuitry. The INTV

LDO selection is determined automatically by the EXTV

CC

3. The LDO33 pin output current is high.

pin voltage. When EXTV is lower than 6.22V (typical),

CC

4. In some applications, LDO current draw is maximum

when the part is operating in the buck-boost region

INTV is regulated from the V LDO. After EXTV rises

CC

IN

CC

above 6.4V (typical), INTV is regulated by the EXTV

CC

where V is close to V

since all four MOSFETs are

IN

OUT

LDO instead.

switching.

Overcurrent protection circuitry typically limits the

maximum current draw from either LDO to 127mA. When

Tocheckforoverheatingfindtheoperatingconditionsthat

consume the most power in the LT8705 (P ). This

will often be under the same conditions just listed that

maximize LDO current. Under these conditions monitor

theCLKOUTpindutycycletomeasuretheapproximatedie

temperature.SeetheJunctionTemperatureMeasurement

section for more information.

LT8705

GATEV and INTV are below 4.65V, during start-up or

CC

during an overload condition, the typical current limit is

reduced to 42mA. The INTV pin must be bypassed to

CC

ground with a minimum 4.7μF ceramic capacitor placed

as close as possible to the INTV and GND pins. An ad-

CC

ditional ceramic capacitor should be placed as close as

Powering INTV from V /EXTV can also provide

CC

OUT

CC

possible to the GATEV and GND pins to provide good

CC

enough gate drive when V drops as low as 2.8V. This

IN

bypassing to supply the high transient current required by

allows the part to operate with a reduced input voltage

the MOSFET gate drivers. 1μF to 4.7μF is recommended.

after the output gets into regulation.

Power dissipated in the INTV LDOs must be minimized

CC

The following list summarizes the three possible connec-

to improve efficiency and prevent overheating of the

tions for EXTV :

CC

LT8705. Since LDO power dissipation is proportional to

the input voltage and V can be as high as 80V in some

1. EXTV left open (or grounded). This will cause INTV

IN

CC

applications, the EXTV pin is available to regulate IN-

to be powered from V through the internal 6.35V

CC

IN

TV from a lower input voltage. The EXTV pin is con-

regulator at the cost of a small efficiency penalty.

CC

nected to V

in many applications since V

is often

OUT

2. EXTV connected directly to V

(V

> 6.4V). This

CC

OUT OUT

regulated to a much lower voltage than the maximum V .

IN

is the normal connection for the regulator and usually

provides the highest efficiency.

During start-up, power for the MOSFET drivers, control

circuits and the LDO33 pin is derived from V until V

/

IN

OUT

3. EXTV connected to an external supply. If an external

EXTV rises above 6.4V, after which the power is derived

CC

OUT

supply is available greater than 6.4V (typical) it may be

from V /EXTV . This works well, for example, in a

CC

used to power EXTV .

case where V

is regulated to 12V and the maximum

CC

OUT

V

voltage is 40V. EXTV can be floated or grounded

IN

CC

when not in use or can also be connected to an external

power supply if available.

8705p

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LT8705

APPLICATIONS INFORMATION

Loop Compensation

Table 1: Voltage Lockout Conditions

APPROXIMATE

Theloopstabilityisaffectedbyanumberoffactorsinclud-

ing the inductor value, output capacitance, load current,

VOLTAGE

CHIP STATE

CONDITION (FIGURE 2)

READ SECTION

V , V

and the V resistor and capacitors. The LT8705

IN OUT

C

V

<2.5V

<1.18V

<4.65V

Chip Off

Operation: Start-Up

IN

usesinternaltransconductanceerroramplifiersdrivingV

C

SHDN

INTV and

tohelpcompensatethecontrolloop.Formostapplications

Switcher

Off

CC

a 3.3nF series capacitor at V is a good value. The parallel

GATEV

CC

C

capacitor (from V to GND) is typically 1/10th the value

SWEN

LDO33

<1.18V

<3.04

Switcher

Off

C

of the series capacitor to filter high frequency noise. A

Switcher

Off

larger V series capacitor value may be necessary if the

C

output capacitance is reduced. A good starting value for

IMON_IN

IMON_OUT

FBIN

>1.61V

<1.205V

Fault

—

Operation: Fault Conditions

theV seriesresistoris20k.Lowerresistancewillimprove

C

stability but will slow the loop response. Use a trim pot

instead of a fixed resistor for initial bench evaluation to

determine the optimum value.

Applications Information:

Input Voltage Regulation or

Undervoltage Lockout

LDO33 Pin Regulator

Due to their accurate thresholds, configurable undervolt-

age lockouts (UVLOs) can be implemented using the

SHDN, SWEN and in some cases, FBIN pin. The UVLO

function sets the turn on/off of the LT8705 at a desired

minimum input voltage. For example, a resistor divider

The LT8705 includes a low dropout regulator (LDO) to

regulate the LDO33 pin to 3.3V. This pin can be used to

powerexternalcircuitrysuchasamicrocontrollerorother

desired peripherals. The input supply for the LDO33 pin

can be connected between V , SHDN and GND as shown

IN

regulatorisINTV .ThereforeINTV musthavesufficient

CC

in Figures 1 and 14. From the Electrical Characteristics,

SHDN has typical rising and falling thresholds of 1.234V

and 1.184V respectively. The falling threshold for turning

off switching activity can be chosen using:

voltage, typically >4.0V, to properly regulate LDO33. The

LDO33andINTV regulatorsareenabledbytheSHDNpin

CC

and are not affected by SWEN. The LDO33 pin regulator

has overcurrent protection circuitry that typically limits

the output current to 17.25mA. An undervoltage lockout

monitoring LDO disables switching activity when LDO33

falls below 3.04V (typical). LDO33 should be bypassed

locally with 0.1µF or more.

R_SHDN2• V

–1.184V

(

)

(IN,CHIP _OFF,FALLING)

R_SHDN1

=

Ω

1.184V

For example, choosing R

= 20k and a falling V

IN

SHDN2

Voltage Lockouts

threshold of 5.42V results in:

The LT8705 contains several voltage detectors to make

surethechipis underproperoperating conditions. Table 1

summarizesthepinsthataremonitoredandalsoindicates

the state that the LT8705 will enter if an under or overvolt-

age condition is detected.

20kΩ • 5.42V –1.184V

(

)

= 71.5kΩ

R_SHDN1

=

1.184V

The rising threshold for enabling switching activity would

be:

1.234V

1.184V

The conditions are listed in order of priority from top

to bottom. If multiple over/undervoltage conditions are

detected, the chip will enter the state listed highest on

the table.

V

_{(IN,CHIP _OFF,RISING)}= V

•

(IN,CHIP _OFF,FALLING)

or 5.65V in this example.

8705p

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LT8705

APPLICATIONS INFORMATION

Junction Temperature Measurement

Similarcalculationscanbeusedtoselectaresistordivider

connectedtoSWENthatwouldstopswitchingactivitydur-

ing an undervoltage condition. Make sure that the divider

doesn’t cause SWEN to exceed 7V (absolute maximum

ThedutycycleoftheCLKOUTsignalislinearlyproportional

tothediejunctiontemperature, T . Measurethedutycycle

J

of the CLKOUT signal and use the following equation to

rating) under maximum V conditions. Using the FBIN

IN

approximate the junction temperature:

pin as an undervoltage lockout is discussed in the Input

DC_CLKOUT–34.4%

Voltage Regulation or Undervoltage Lockout section.

T_J≅

°C

0.325%

Inductor Current Sense Filtering

where DC

is the CLKOUT duty cycle in % and T

CLKOUT

J

Certain applications may require filtering of the inductor

current sense signals due to excessive switching noise

is the die junction temperature in °C. The actual die tem-

perature can deviate from the above equation by 10°C

thatcanappearacrossR

. Higheroperatingvoltages,

SENSE

higher values of R

, and more capacitive MOSFETs

SENSE

Thermal Shutdown

will all contribute additional noise across R

when

SENSE

If the die junction temperature reaches approximately

165°C, the part will go into thermal shutdown. The power

switch will be turned off and the INTV and LDO33

regulators will be turned off (see Figure 2). The part will

be re-enabled when the die temperature has dropped by

~5°C (nominal). After re-enabling, the part will start in

the switcher off state as shown in Figure 2. The part will

then initialize, perform a soft-start, then enter normal

operation as long as the die temperature remains below

approximately 165°C.

the SW pins transition. The CSP/CSN sense signals can

be filtered by adding one of the RC networks shown in

Figures 12a and 12b. Most PC board layouts can be drawn

to accommodate either network on the same board. The

network should be placed as close as possible to the IC.

The network in Figure 12b can reduce common mode

noise seen by the CSP and CSN pins of the LT8705 at the

expense of some increased ground trace noise as current

passesthroughthecapacitors.Ashortdirectpathfromthe

capacitor grounds to the IC ground should be used on the

PC board. Resistors greater than 10Ω should be avoided

as this can increase offset voltages at the CSP/CSN pins.

The RC product should be kept to less than 30ns.

CC

Efficiency Considerations

Theefficiencyofaswitchingregulatorisequaltotheoutput

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting the efficiency and which change would produce

the most improvement. Although all dissipative elements

in the circuit produce losses, four main sources account

for most of the losses in LT8705 circuits:

10Ω

CSP

LT8705

R

SENSE

1nF

10Ω

CSN

8705 F12a

(12a)

1. Switching losses. These losses arises from the brief

amount of time switch M1 or switch M3 spends in the

saturatedregionduringswitchnodetransitions. Power

lossdependsupontheinputvoltage,loadcurrent,driver

strength and MOSFET capacitance, among other fac-

tors. See the Power MOSFET Selection and Efficiency

Considerations section for more details.

10Ω

CSP

CSN

LT8705

R

SENSE

1nF

10Ω

1nF

8705 F12b

(12b)

Figure 12. Inductor Current Sense Filter

8705p

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For more information www.linear.com/8705

LT8705

APPLICATIONS INFORMATION

2. DC I R losses. These arise from the resistances of the

2

• The high di/dt path formed by switch M1, switch M2,

MOSFETs, sensing resistors, inductor and PC board

traces and cause the efficiency to drop at high output

currents.

D1, R

and the C capacitor should be compact

SENSE IN

with short leads and PC trace lengths. The high di/dt

path formed by switch M3, switch M4, D2 and the C

OUT

capacitor also should be compact with short leads and

PC trace lengths. Two layout examples are shown in

Figures 13a and 13b.

3. INTV current. This is the sum of the MOSFET driver

CC

current, LDO33 pin current and control currents. The

INTV regulator’s input voltage times the current

CC

represents lost power. This loss can be reduced by

V

IN

SW1

SW2

V

OUT

supplyingINTV currentthroughtheEXTV pinfrom

CC

L

a high efficiency source, such as the output or alternate

supply if available. Also, lower capacitance MOSFETs

can reduce INTV current and power loss.

CC

4. C and C

loss. The input capacitor has the difficult

OUT

IN

D1

D2

C

job of filtering the large RMS input current to the regu-

lator in buck mode. The output capacitor has the more

difficult job of filtering the large RMS output current in

M1

M2

M3

M4

C

boost mode. Both C and C

are required to have

IN

OUT

IN

OUT

2

low ESR to minimize the AC I R loss and sufficient

capacitance to prevent the RMS current from causing

additional upstream losses in fuses or batteries.

R

SENSE

LT8705

CKT

GND

8705 F13a

5. Other losses. Schottky diodes D1 and D2 are respon-

sible for conduction losses during dead time and light

load conduction periods. Inductor core loss occurs

predominately at light loads.

(13a)

V

SW1

SW2

V

OUT

IN

L

D2

Whenmakingadjustmentstoimproveefficiency,theinput

current is the best indicator of changes in efficiency. If

one makes a change and the input current decreases, then

the efficiency has increased. If there is no change in input

current, then there is no change in efficiency.

M1

M4

D1

M2

M3

C

OUT

IN

Circuit Board Layout Checklist

The basic circuit board layout requires a dedicated ground

plane layer. Also, for high current, a multilayer board

provides heat sinking for power components.

R

SENSE

LT8705

CKT

GND

8705 F13b

• The ground plane layer should not have any traces and

should be as close as possible to the layer with the

power MOSFETs.

(13b)

Figure 13. Switches Layout

8705p

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LT8705

APPLICATIONS INFORMATION

• Connecttheinputcapacitors,C ,andoutputcapacitors,

• Avoid running signal traces parallel to the traces that

carry high di/dt current because they can receive in-

ductivelycoupledvoltagenoise. ThisincludestheSW1,

SW2, TG1 and TG2 traces to the controller.

IN

C

, closely to the power MOSFETs. These capacitors

OUT

carry the MOSFET AC current in the boost and buck

regions.

• Connect the FBOUT and FBIN pin resistor dividers to

• Useimmediateviastoconnectthecomponents(includ-

ing the LT8705’s GND pins) to the ground plane. Use

several vias for each power component.

the (+) terminals of C

and C respectively. Small

OUT

IN

FBOUT/FBIN bypass capacitors may be connected

closely to the LT8705’s GND pin if needed. The resistor

connections should not be along the high current or

noise paths.

• Minimize parasitic SW pin capacitance by removing

GND and V copper from underneath the SW1 and

IN

SW2 regions.

• Route current sense traces (CSP/CSN, CSPIN/CSNIN,

CSPOUT/CSNOUT) together with minimum PC trace

spacing. Avoid having sense lines pass through noisy

areas,suchasswitchnodes.Theoptionalfilternetwork

capacitor between CSP and CSN should be as close as

possibletotheIC. Ensureaccuratecurrentsensingwith

• Except under the SW pin regions, flood all unused

areas on all layers with copper. Flooding with copper

will reduce the temperature rise of power components.

Connect the copper areas to a DC net (e.g., quiet GND).

• Partition the power ground from the signal ground. The

small-signal component grounds should not return to

the IC GND through the power ground path.

Kelvin connections at the R

resistors.

SENSE

• Connect the V pin compensation network closely to

C

• PlaceswitchM2andswitchM3asclosetothecontroller

the IC, between V and the signal ground pins. The

C

as possible, keeping the GND, BG and SW traces short.

capacitor helps to filter the effects of PCB noise and

output voltage ripple voltage from the compensation

loop.

• Minimize inductance from the sources of M2 and M3

to R

by making the trace short and wide.

SENSE

• Connect the INTV and GATEV bypass capacitors

CC

• Keep the high dV/dT nodes SW1, SW2, BOOST1,

BOOST2,TG1andTG2awayfromsensitivesmall-signal

nodes.

close to the IC. The capacitors carry the MOSFET driv-

ers’ current peaks.

• Theoutputcapacitor(–)terminalsshouldbeconnected

as closely as possible to the (–) terminals of the input

capacitor.

Design Example

V = 8V to 25V

IN

V

I

= 12V

OUT

• Connect the top driver boost capacitor, C , closely

B1

= 5A

to the BOOST1 and SW1 pins. Connect the top driver

OUT(MAX)

boost capacitor, C , closely to the BOOST2 and SW2

B2

f = 350kHz

pins.

Maximum ambient temperature = 60°C

8705p

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LT8705

APPLICATIONS INFORMATION

R Selection: Choose the R resistor for the free-running

Now calculate the maximum R

values in the boost

SENSE

T

oscillator frequency using:

and buck regions to be:

R_{SENSE(MAX,BOOST)}

=





43,750

f_OSC

43,750

350





R_T=

–1 kΩ =

–1 = 124kΩ















2•V_{RSENSE(MAX,BOOST,MAX)}•V

IN(MIN)

Ω

2•I_{OUT(MAX,BOOST)}•V_OUT(MIN)+ ∆I

•V

IN(MIN)

(

) (

)

L(MAX,BOOST)

R

Selection: Start by calculating the maximum duty

SENSE

cycle in the boost region:

2•107mV •8V

=

= 11.4mΩ





2•5A •12V + 3.75A •8V

(

) (

)

V

IN(MIN)

DC

≅ 1–

•100%





(MAX,M3,BOOST)

V





OUT(MAX)

2•86mV

R_{SENSE(MAX,BUCK)}

=

Ω

2•I

– ∆I

L(MIN,BUCK)

(

)

OUT(MAX,BUCK)

8V









= 1–

•100% = 33%





12V

2•86mV

=

= 18.2mΩ

Next, from the Maximum Inductor Current Sense Voltage

vs Duty Cycle graph in the Typical Performance Charac-

teristics section:

2•5A –0.53A

(

)

Adding an additional 30% margin, choose R

11.4mΩ/1.3 = 8.7mΩ.

to be

SENSE

V

≅ 107mV

RSENSE(MAX,BOOST,MAX)

Inductor Selection: With R

known, we can now

SENSE

Next, estimate the maximum and minimum inductor cur-

rent ripple in the boost and buck regions respectively:

determine the minimum inductor value that will provide

adequate load current in the boost region using:

V_OUT(MAX)•I

L_(MIN1,BOOST)

≅

∆I_L(MAX,BOOST)

≅

^{OUT(MAX,BOOST)}A

 100%



V

•

–0.5

IN(MIN)

DC_{(MAX,M3,BOOST)}

100%









%Ripple

V

•

IN(MIN)

H

12V •5A





V_{RSENSE(MAX,BOOST,MAX)}I_OUT(MAX)•V_OUT(MAX)

=

= 3.75A

2•f•

–





100%

40%





R_SENSE

V

IN(MIN)





8V •

–0.5









33%

100%

107mV 5A •12V

8.7mV





I

8V •









∆I_L(MIN,BUCK)

≅

^{OUT(MAX,BUCK)}A

=

= 0.8µH

100%

10%









–0.5









2•350kHz •

–









8V

5A

100%

10%

=

= 0.53A





–0.5









8705p

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LT8705

APPLICATIONS INFORMATION

To avoid subharmonic oscillations in the inductor current,

choose the minimum inductance according to:

2

Since maximum I R power dissipation in the boost region

happens when V is minimum, we can determine the

IN

maximum allowable R

for the boost region using:

DS(ON)





 ²



















V

_IN(MIN)•V_OUT(MAX)

V_OUT

V

–

•R

SENSE

2

P_M1= P

≅

•I_OUT•R_DS(ON)•ρ

W







OUT(MAX)

I R

^τ







V

– V





V



_IN(MIN) _





OUT(MAX)

IN





L_(MIN2,BOOST)

=

H

0.08•f

 ²





12V

8V



8V •12V

12V –8V

0.08•350kHz

1.3W ≅

•5A •R_DS(ON)•1.5 Wand therefore



















12V –

•8.7mΩ























= –3.7µH

R_DS(ON)< 15.4mΩ







V_OUT(MAX)

_IN(MAX)– V

V

_IN(MAX)•_1–

•R

SENSE

The Fairchild FDMS7672 meets the specifications with a

maximum R of ~6.9mΩ at V = 4.5V (~10mΩ at

V



_OUT(MIN)

L_(MIN1,BUCK)

=

DS(ON)

GS

0.12•f

125°C). Checking the power dissipation in the buck region

with V maximum and V

minimum yields:

12V

25V –12V





IN

OUT

25V • 1–

•8.7mΩ









2

P_M1= P_{I R}+ P_SWITCHING

=

= 0.6µH

0.08•350kHz



 ²





V_OUT

The inductance must be higher than all of the minimum

values calculated above. We will choose a 10μH standard

value inductor for improved margin.

≅

•I_OUT•R_DS(ON)•ρ + V •I

•f•t_RF1W





(

)

IN

OUT













V

^τ

IN







12V

25V



 ²

P_M1

•5A •6.9mΩ •1.5 + 25V •5A •350k •20ns

(

)





MOSFET Selection: The MOSFETs are selected based on













voltage rating, C

and R

value. It is important to

RSS

DS(ON)

ensure that the part is specified for operation with the

availablegatevoltageamplitude.Inthiscase,theamplitude

= 0.06W+ 0.88W = 0.94W

The maximum switching power of 0.88W can be reduced

by choosing a slower switching frequency. Since this

calculation is approximate, measure the actual rise and

fall times on the PCB to obtain a better power estimate.

is 6.35V and MOSFETs with an R

value specified at

DS(ON)

V

GS

= 4.5V can be used.

Select M1 and M2: With 25V maximum input voltage,

MOSFETs with a rating of at least 30V are used. As we do

not yet know the actual thermal resistance (circuit board

design and airflow have a major impact) we assume that

the MOSFET thermal resistance from junction to ambient

is 50°C/W.

ThemaximumdissipationinM2occursatmaximuminput

voltage when the circuit is operating in the buck region.

Using the 6.9mΩ Fairchild FDMS7672 the dissipation is:









V – V

IN

OUT

P

≅

•I_OUT(MAX)²•R_DS(ON)•ρ_τ

W

(M2,BUCK)





V

If we designfor amaximumjunction temperature, T

IN

J(MAX)

=125°C,themaximumallowablepowerdissipationcanbe

25V –12V

25V





calculated.First,calculatethemaximumpowerdissipation:

P

• 5A ²•6.9mΩ •1.5 = 0.13W

(

)







(M2,BUCK)



T

_J(MAX)–T_A(MAX)

P_D(MAX)

=

R_TH(JA)

125°C–60°C

50°C/W

P_D(MAX)

= 1.3W

8705p

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APPLICATIONS INFORMATION

Select M3 and M4: With 12V output voltage we need

MOSFETs with 20V or higher rating.

Capacitors: A low ESR (5mΩ) capacitor network for C

is selected. In this mode, the maximum ripple is:

IN

V

_IN(MAX)•I

The highest dissipation occurs in the boost region when

input voltage is minimum and output current is highest.

For switch M3 the dissipation is:

∆V

≅

^OUT(MAX)•ESR

(BUCK,ESR)

V_OUT(MIN)

25V •5A

2

P

= P + P

≅

∆V

≅

•5mΩ = 52mV

M3

I R

SWITCHING

(BUCK,ESR)

12V





V

– V • V

IN

OUT

(

)

OUT

assuming ESR dominates the ripple.

2

•I

•R

•ρ

τ

DS(ON)

OUT





2

V





IN

Having 5mΩ of ESR for the C

network sets the maxi-

OUT

mum output voltage ripple at:









t

RF2

2

+ V

•I

• f •

W

OUT



V_OUT(MAX)•I

V



^OUT(MAX)•ESR

IN

∆V

≅

(BOOST,ESR)

V

IN(MIN)

asdescribedinthePowerMOSFETSelectionandEfficiency

Considerations section.

12V •5A

∆V

≅

•5mΩ = 37.5mV

(BOOST,ESR)

8V

The maximum dissipation in switch M4 is:

assuming ESR dominates the ripple.





V

OUT(MAX)

2

P

≅

•I

•ρ •R

W



OUT

τ

DS(ON)



M4,BOOST

(

)

V





IN(MIN)

The Fairchild FDMS7672 can also be used for M3 and M4.

Assuming 20ns rise and fall times, the calculated power

loss at the minimum 8V input voltage is then 0.82W for

M3 and 0.39W for M4

Output Voltage: Output voltage is 12V. Select R

as

FBOUT2

20k. R

is:

FBOUT1

V_OUT•R_FBOUT2

R_FBOUT1

=

1.207V

SelectR

as200k.BothR

andR

should

FBOUT1

FBOUT2

have a tolerance of no more than 1%.

8705p

39

For more information www.linear.com/8705

LT8705

TYPICAL APPLICATIONS

L1

22µH

M1

V

48V

5A

OUT

M4

×2

V

IN

36V TO 80V

+

C

IN2

C

+

C

OUT2

C

OUT1

IN1

M3

M2

4.7µF

220µF

×2

×4

×6

×2

TO

DIODE D

TO

DIODE D

B1

B2

1nF

10Ω

0.22µF

9mΩ

2Ω**

2Ω*

392k

TG1 BOOST1 SW1 BG1 CSP

CSNIN

CSPIN

CSN

GND BG2 SW2 BOOST2 TG2

CSPOUT

CSNOUT

V

IN

EXTV

CC

SHDN

SWEN

LDO33

MODE

FBIN

RT

FBOUT

100k

INTV

10k

CC

GATEV

4.7µF

LT8705

SRVO_FBIN

SRVO_FBOUT

SRVO_IIN

4Ω

71.5k

SS

SRVO_IOUT

IMON_IN

D

B2

B1

4.7µF

TO

IMON_OUT

V

BOOST1 BOOST2

CLKOUT

202kHz

SYNC

C

20k

215k

56.2k

4.7µF

1µF

220pF

3.3nF

8705 F14a

C

, C

: 220µF, 100V

*2Ω FROM TG1 TO EACH SEPERATE M1 GATE

**2Ω FROM BG2 TO EACH SEPERATE M3 GATE

IN1 OUT2

C

, C

: 4.7µF, 100V, TDK C453X7S2A475M

IN2 OUT1

, D : CENTRAL SEMI CMMR1U-02-LTE

D

B1 B2

L1: 22µH, WÜRTH 74435572200 OR COILCRAFT SER2918H-223

M1, M3: FAIRCHILD FDMS86104

M2, M4: FAIRCHILD FDMS86101

Efficiency vs Output Current

(Buck Region)

(Boost Region)

100

90

V

= 36V

V

= 72V

IN

OUT

CCM

IN

OUT

CCM

90

= 48V

80

70

60

80

70

60

50

40

50

40

30

20

10

0

30

20

10

0

COILCRAFT SER2918H-223

WURTH 74435572200

COILCRAFT SER2918H-223

WURTH 74435572200

10

1000

LOAD CURRENT (mA)

10000

10

1000

LOAD CURRENT (mA)

10000

100

8705 F14b

8705 F14c

Note: See the front page and the Typical Performance Characteristics section for more curves from this application

circuit using the Coilcraft inductor. The smaller Würth inductor is also suitable in place of the Coilcraft inductor with

some loss in efficiency.

Figure 14. Telecom Voltage Stabilizer

8705p

40

For more information www.linear.com/8705

LT8705

APPLICATIONS INFORMATION

Supercapacitor Backup Supply

TO

LOADS

L1

2.2µH

D

IN

25mΩ

M4

M1

V

IN

12V

OUT

15V

+

C

IN2

×3

C

IN1

M2

M3

OUT1

OUT2

×2

×3

TO

DIODE D

TO

DIODE D

B1

0.22µF

B2

C

1.2k

SC

×6

0.22µF

×6

3mΩ

2Ω

115k

TG1 BOOST1 SW1 BG1 CSP CSN

CSNIN

CSPIN

GND BG2 SW2 BOOST2 TG2

CSPOUT

CSNOUT

V

EXTV

CC

IN

SHDN

SWEN

LDO33

MODE

FBIN

RT

FBOUT

INTV

10k

CC

100k

4.7µF

B2

GATEV

LT8705

4.7µF

SRVO_FBIN

SRVO_FBOUT

SRVO_IIN

4Ω

D

B1

TO

15V

1µF

113k

71.5k

20k

SS

SRVO_IOUT

IMON_IN

BOOST1 BOOST2

2N3904

20k

IMON_OUT

V

CLKOUT

SYNC

C

24k

1k

124k

14.3k

100nF

47.5k

350kHz

4.7µF

1µF

220pF

15nF

8705 TA02a

C

, C

: 100µF, 20V SANYO OS-CON 205A100M

: 22µF, 25V, TDK C4532X741E226M

D

: APPROPRIATE 2A SCHOTTKY DIODE OR IDEAL

DIODE SUCH AS LTC4358, LTC4412, LTC4352, ETC.

B1 B2

IN1 OUT2

IN

, C

IN2 OUT1

: 60F, 2.5V COOPER BUSSMAN HB1840-2R5606-R

, D : CENTRAL SEMI CMMR1U-02-LTE

SC

L1: 2.2µH, VISHAY IHLP-5050CE-01-2R2-M-01

M1-M4: FAIRCHILD FDMS7698

12V LOADS

LOADS

113k

POWER FLOW

25mΩ

D

IN

D

IN

25mΩ

0V

INPUT

12V

INPUT

C

1.2k

SC

C

1.2k

8705 TA02

SC

LIMIT

INPUT CURRENT

IN EXCESS OF 2A

WILL DRAW FROM

SUPER CAPS

115k

10k

113k

20k

CAPACITOR

CHARGING

CURRENT

TO 1A

REGULATE LOADS

TO 8V

20k

SC

115k

C

REGULATE CAPACITORS

TO 15V

10k

SC

8705 TA02

Charging V_OUTto 15V

with 1A Current

Remove V_IN. Loads (4A Draw)

Regulated to 8V from Supercaps

V

OUT

15V

5V/DIV

V

IN

5V/DIV

V

IN

8V

5V/DIV

OUT

5V/DIV

I

L

5A/DIV

8705 TA02d

8705 TA02e

20SEC/DIV

3SEC/DIV

8705p

41

For more information www.linear.com/8705

LT8705

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-ꢀ70ꢀ Rev C)

0.70 0.05

5.50 0.05

5.ꢀ5 0.05

4.ꢀ0 0.05

3.ꢀ5 0.05

3.00 REF

PACKAGE

OUTLINE

0.25 0.05

0.50 BSC

5.5 REF

6.ꢀ0 0.05

7.50 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN ꢀ NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

0.75 0.05

0.00 – 0.05

3.00 REF

5.00 0.ꢀ0

37

38

0.40 0.ꢀ0

PIN ꢀ

TOP MARK

ꢀ

2

(SEE NOTE 6)

5.ꢀ5 0.ꢀ0

5.50 REF

7.00 0.ꢀ0

3.ꢀ5 0.ꢀ0

(UH) QFN REF C ꢀꢀ07

0.200 REF 0.25 0.05

0.50 BSC

R = 0.ꢀ25

TYP

R = 0.ꢀ0

TYP

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

8705p

42

For more information www.linear.com/8705

LT8705

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

Package Variation: FE38 (31)

38-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1665 Rev B)

Exposed Pad Variation AB

4.75 REF

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

REF

38

20

6.60 0.10

4.50 REF

2.74 REF

SEE NOTE 4

6.40

REF (.252)

BSC

2.74

(.108)

0.315 0.05

1.05 0.10

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED

19

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.50

(.0196)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.17 – 0.27

(.0067 – .0106)

TYP

FE38 (AB) TSSOP REV B 0910

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

3. DRAWING NOT TO SCALE

8705p

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-

43

For more information www.linear.com/8705

tionthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

LT8705

TYPICAL APPLICATION

12V Output Converter Accepts 4V to 80V Input (5.5V Minimum to Start)

M1

×2

15µH

V

7mΩ

OUT

12V

M4

V

IN

4V TO 80V

(INCREASED

+

5.0A (V ≥ 5.5V)

IN

OUT3

M3

C

IN2

×6

C

OUT1B

×3

M2

C

IN1

4.5A (V ≥ 5.0V)

IN

C

×2

OUT1A

×2

TO DIODE

V

RIPPLE

OUT

4.0A (V ≥ 4.5V)

IN

D

+

FOR V > 60V)

IN

B1

B2

3.5A (V ≥ 4.0V)

C

OUT2

1nF

10Ω

×3

0.22µF

4mΩ

2Ω*

102k

TG1 BOOST1 SW1 BG1 CSP

CSNIN

CSPIN

CSN

GND BG2 SW2 BOOST2 TG2

CSPOUT

4.7µF

CSNOUT

V

IN

EXTV

CC

SHDN

SWEN

LDO33

MODE

FBIN

RT

FBOUT

100k

INTV

11.3k

CC

GATEV

4.7µF

LT8705

SRVO_FBIN

SRVO_FBOUT

SRVO_IIN

4Ω

C

: 220µF, 100V

IN1

IN2

38.3k

SS

SRVO_IOUT

IMON_IN

: 4.7µF, 100V, TDK C4532X7S2A475M

, C : 22µF, 25V, TDK C4532X7R1E226M

D

B2

B1

OUT1A OUT1B

: 100µF, 16V, SANYO OS-CON 16SA100M

: 470µF, 16V

4.7µF

OUT2

OUT3

TO

IMON_OUT

V

BOOST1 BOOST2

CLKOUT

202kHz

SYNC

C

D

, D : CENTRAL SEMI CMMR1U-02-LTE

B1 B2

20k

215k

16.5k

L1: 15µH, WURTH 7443631500

M1, M2: FAIRCHILD FDMS86101

M3, M4: FAIRCHILD FDMS7692

*2Ω FROM TG1 TO EACH SEPARATE M1 GATE

26.1k

22nF

4.7µF

1µF

220pF

10nF

8705 TA03a

Efficiency vs Output Current

Input Transient (4V to 80V)

100

95

90

85

80

V

OUT

200mV/DIV

V

IN

20V/DIV

V

= 60V

= 40V

= 20V

= 12V

= 5V

IN

8705 TA03c

0

1

2

3

4

5

I

= 2A

10ms/DIV

LOAD

LOAD CURRENT (A)

8705 TA03c

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

4.7V ≤ V ≤ 60V, 1.2V ≤ 60V, Regulates V , I

LT3791-1

LTC3789

LT3758

60V High Efficiency (Up to 98%) Synchronous 4-Switch

Buck-Boost DC/DC Controller

or I , TSSOP-38

IN

OUT OUT

IN

High Efficiency (Up to 98%) Synchronous 4-Switch

Buck-Boost DC/DC Controller

4V ≤ V ≤ 38V, 0.8V ≤ V

≤ 38V, SSOP-28, 4mm × 5mm QFN-28

IN

OUT

High Input Voltage, Boost, Flyback, SEPIC and Inverting

Controller

5.5V ≤ V ≤ 100V, Positive or Negative V , 3mm × 3mm DFN-10

IN

OUT

or MSOP-10E

LTC3115-1

LTM4609

40V, 2A Synchronous Buck-Boost DC/DC Converter

High Efficiency Buck-Boost DC/DC µModule Regulator

2.7V ≤ V ≤ 40V, 2.7V ≤ V

≤ 40V, 4mm × 5mm DFN-16, TSSOP-20

≤ 34V, 15mm × 15mm × 2.8mm

IN

OUT

4.5V ≤ V ≤ 36V, 0.8V ≤ V

IN

8705p

LT 0113 • PRINTED IN USA

44 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/8705

●

(408)432-1900 FAX: (408) 434-0507 www.linear.com/8705

 LINEAR TECHNOLOGY CORPORATION 2013


型号：	LT8705
厂家：	Linear
描述：	80V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller 80V的VIN和VOUT同步四开关降压 - 升压型DC / DC控制器开关控制器
文件：	总44页 (文件大小：569K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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