LT6370 [ADI]
Precision Instrumentation Amplifier with Level Shift and Output Clamping;
| 型号： | LT6370 |
| 厂家： | 
ADI |
| 描述： | Precision Instrumentation Amplifier with Level Shift and Output Clamping |
| 文件： | 总28页 (文件大小：2664K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT6372-1
Precision Instrumentation Amplifier with
Level Shift and Output Clamping
FEATURES
DESCRIPTION
The LT®6372-1 is a gain programmable, high precision
instrumentation amplifier that delivers industry leading
DC precision. This high precision enables smaller sig-
nals to be sensed and eases calibration requirements,
particularly over temperature. The LT6372-1 incorporates
features into the LT6370 which further improve accuracy
and simplify interfacing to an ADC.
n
Single Gain Set Resistor: G = 1 to >1000
Excellent DC Precision
n
n
Input Offset Voltage: 60μV Max
n
Input Offset Voltage Drift: 0.6μV/°C Max
n
Low Gain Error: 0.01% Max (G = 1)
n
Low Gain Drift: 35ppm/°C Max (G > 1)
High DC CMRR: 86dB Min (G = 1)
n
n
n
n
n
n
Integrated Output Clamps
The LT6372-1 uses a proprietary high performance bipo-
lar process which enables industry leading accuracy cou-
pled with exceptional long-term stability. The LT6372-1
is laser trimmed for very low input offset voltage (60µV)
and high CMRR (86dB, G = 1). Proprietary on-chip test
capability allows the gain drift (35ppm/°C) to be guaran-
teed with automated testing.
Integrated Output Level Shift
Input Bias Current: 800pA Max
3.1MHz –3dB Bandwidth (G = 1)
Low Noise:
n
0.1Hz to 10Hz Noise: 0.2μV
P-P
n
1kHz Voltage Noise: 7nV/√Hz
n
n
n
n
Integrated Input RFI Filter
Wide Supply Range 4.75V to 35V
The LT6372-1’s difference amplifier uses a split reference
configuration which simplifies level shifting the amplifier’s
output to the center of the ADC’s input range. Output
clamp pins are also provided to limit the voltage which can
be applied to an ADC’s input. EMI filtering is integrated on
the LT6372-1’s inputs to maintain accuracy in the pres-
ence of harsh RF interference.
Temperature Ranges: –40°C to 85°C and –40°C to 125°C
MS16E and 20-Lead 3mm × 4mm QFN Packages
APPLICATIONS
n
Bridge Amplifier
n
The LT6372-1 is available in a compact MS16E or a 20-pin
3mm x 4mm QFN. The LT6372-1 is fully specified over the
Data Acquisition
n
Thermocouple Amplifier
n
–40°C to 85°C and –40°C to 125°C temperature ranges.
Strain Gauge Amplifier
All registered trademarks and trademarks are the property of their respective owners.
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Medical Instrumentation
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Transducer Interfaces
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Differential to Single-Ended Conversion
LT6372–1 Driving LTC2367–16 with
Level Shift and Output Clamping
TYPICAL APPLICATION
ꢀ
+15V
LTC6655-5
V
ꢀ ꢁ ꢂ00
REF
V
V
OUT
IN
ꢀ
ꢀ
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ꢀꢁꢂꢁꢃ
ꢀꢁꢀꢂꢂ
ꢀꢁꢀꢂꢃ
ꢀꢁꢀ0ꢂ
0
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ꢀꢁꢂꢃꢄeꢅ
ꢀꢁꢂꢃꢄꢃve
ꢀeveꢁ ꢂꢃꢄꢅꢆeꢇ
+
ꢀꢁ ꢂRꢃꢄꢅꢆ
2.5V
VDD
10V
ꢀ
REF2
REF
350Ω
350Ω
350Ω
91Ω
R
G
CLHI
CLLO
ꢀ
LT6372-1
REF1
243Ω
LTC2367-16
GND
10nF
COG
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ꢀꢁꢂꢃꢄeꢅ
ꢀeꢁꢂꢃꢄve
+
ꢀ
V
IN
350Ω
–
–
0
–15V
GAIN OF 100 BRIDGE AMPLIFIER
ꢀꢁ
6372-1 TA01a
ꢀꢁ00 ꢀꢁꢂ ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄ ꢅꢆ0ꢄꢇ
Rev. 0
1
Document Feedback
For more information www.analog.com
LT6372-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
+
–
Total Supply Voltage (V to V ).................................36V Output Short-Circuit Duration.............Thermally Limited
Input Voltage (+IN, –IN, +R , +R , –R , –R , Output Current.......................................................80mA
G,S
G,F
G,S
G,F
–
+
REF1, REF2, CLHI, CLLO)... (V – 0.3V) to (V + 0.3V) Operating and Specified Temperature Range
Differential Input Voltage
I-Grade.................................................–40°C to 85°C
H-Grade ............................................. –40°C to 125°C
(+IN to –IN)......................................................... 36V
(REF1 to REF2) ................................................... 15V Maximum Junction Temperature .......................... 150°C
Input Current (+R , +R , –R , –R )............. 2mA Storage Temperature Range .................. –65°C to 150°C
G,S
G,F
G,S
G,F
Input Current (+IN, –IN, CLLO) ............................ 10mA Lead Temperature (Soldering, 10 sec)...................300°C
Input Current (REF1, REF2, CLHI) .......................–10mA
PIN CONFIGURATION
ꢔꢌꢋ ꢕꢐꢉꢈ
ꢄ0 ꢒꢚ ꢒꢛ ꢒꢗ
TOP VIEW
ꢑꢐꢆ
ꢖꢐꢑ
ꢑꢐꢆ
ꢑꢐꢆ
ꢟꢐꢑ
ꢑꢐꢆ
ꢒ
ꢄ
ꢞ
ꢝ
ꢃ
ꢜ
ꢒꢜ ꢑꢐꢆ
1
2
3
4
5
6
7
8
–R
–R
16 +R
15 +R
ꢀꢁꢂ
ꢀꢁꢃ
NIC
ꢀꢁꢂ
ꢀꢁꢃ
Rꢉꢠꢄ
ꢒꢃ
ꢒꢝ
14 NIC
ꢟ
ꢕ
ꢄꢒ
–IN
+IN
13 REF2
ꢗꢘ
ꢅ
ꢖ
ꢕ
12
V
ꢒꢞ ꢌꢡꢔꢋꢡꢔ
ꢒꢄ Rꢉꢠꢒ
ꢒꢒ ꢑꢐꢆ
NIC
11 OUTPUT
10 REF1
CLLO
ꢄ
V
9
CLHI
MSE PACKAGE
16-LEAD PLASTIC MSOP
ꢗ
ꢛ
ꢚ ꢒ0
θ
ꢆꢇ
ꢈ ꢉꢊꢋꢌꢍꢎ
ꢏꢐꢑꢒꢃꢏꢓ ꢑꢇꢓ ꢔꢑꢕꢖ ꢗꢘꢙ ꢚꢛꢃꢜ ꢂꢝꢒꢇꢜ ꢒR
ꢅ
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UDC PACKAGE
20-LEAD (3mm x 4mm) PLASTIC QFN
θ
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ꢀꢁ
ꢉꢊꢋꢌꢍꢉꢎ ꢋꢁꢎ ꢏꢋꢐꢑ ꢄꢒꢓ ꢐꢍ ꢆꢌꢑꢑꢉꢆꢔꢉꢎ
ꢖ
ꢔꢌ ꢕ ꢏꢋꢐꢑ ꢗꢓ ꢏꢋꢆꢘ ꢆꢌꢑꢑꢉꢆꢔꢐꢌꢑ ꢌꢋꢔꢐꢌꢑꢁꢙꢓ
ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING*
63721
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LT6372IMSE-1#PBF
LT6372HMSE-1#PBF
LT6372IUDC-1#PBF
LT6372HUDC-1#PBF
LT6372IMSE-1#TRPBF
LT6372HMSE-1#TRPBF
LT6372IUDC-1#TRPBF
LT6372HUDC-1#TRPBF
16-Lead Plastic MSOP
63721
16-Lead Plastic MSOP
–40°C to 125°C
–40°C to 85°C
LHHV
20-Lead (3mm x 4mm) Plastic QFN
20-Lead (3mm x 4mm) Plastic QFN
LHHV
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
2
For more information www.analog.com
LT6372-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2kΩ.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
G
Gain Range
G = (1 + 24.2k/R ) (Note 2)
1
1000
V/V
G
Gain Error (Notes 3, 4)
G = 1
–0.004
–0.02
–0.02
–0.05
0.01
0.015
0.12
0.42
0.12
0.42
0.12
0.5
%
%
%
%
%
%
%
%
l
l
l
l
G = 1
G = 10
G = 10
G = 100
G = 100
G = 1000
G = 1000
l
l
Gain vs Temperature (Notes 3, 4)
Gain Nonlinearity (Notes 3, 7)
G = 1 (Note 5)
G > 1(Note 6)
0.2
20
0.5
35
ppm/°C
ppm/°C
V
OUT
V
OUT
V
OUT
V
OUT
=
=
=
=
10V, G = 1
1
3
20
50
3
40
50
ppm
ppm
ppm
ppm
10V, G = 10
10V, G = 100
10V, G = 1000
V
V
V
V
=
=
=
=
10V, G = 1, R = 600Ω
4
6
70
250
ppm
ppm
ppm
ppm
OUT
OUT
OUT
OUT
L
10V, G = 10, R = 600Ω
L
10V, G = 100, R = 600Ω
L
10V, G = 1000, R = 600Ω
L
V
, Total Input Referred Offset Voltage, V = V + V /G
OST OST OSI OSO
V
Input Offset Voltage
(Note 8)
10
70
60
μV
μV
OSI
l
175
V
V
Output Offset Voltage (Note 8)
275
500
μV
μV
OSO
l
l
l
l
l
/T
Input Offset Voltage Drift (Notes 5, 8)
0.6
μV/°C
μV
OSI
Input Offset Voltage Hysteresis (Note 9) T = –40°C to 125°C
3
A
V
/T
Output Offset Voltage Drift (Notes 5, 8)
4
μV/°C
μV
OSO
Output Offset Voltage Hysteresis (Note 9) T = –40°C to 125°C
10
A
I
I
Input Bias Current
0.1
0.8
1.5
3
nA
nA
nA
B
l
l
T = –40°C to 85°C
A
A
T =–40°Cto 125°C
Input Offset Current
0.2
1.4
4
nA
nA
OS
l
Input Noise Voltage (Note 10)
0.1Hz to 10Hz, G = 1
0.1Hz to 10Hz, G = 1000
2
0.2
μV
μV
P-P
P-P
2
2
Total RTI Noise =
√
e
+ (e /G) (Note 10)
ni no
e
e
Input Noise Voltage Density
Output Noise Voltage Density
Input Noise Current
f = 1kHz
7
nV/√Hz
nV/√Hz
ni
f = 1kHz
65
no
0.1Hz to 10Hz
f = 1kHz
10
pA
P-P
i
n
Input Noise Current Density
Input Resistance
200
225
fA/√Hz
R
V
IN
= –12.6V to 13V
GΩ
IN
IN
C
Differential
Common Mode
f = 100kHz
f = 100kHz
0.9
15.9
+
pF
pF
–
V
Input Voltage Range
Guaranteed by CMRR
V + 1.8/V – 1.4
V
V
CM
–
+
l
V + 2.4
V – 2
Rev. 0
3
For more information www.analog.com
LT6372-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2kΩ.
SYMBOL PARAMETER
CMRR Common Mode Rejection Ratio
CONDITIONS
MIN
TYP
MAX
UNITS
DC to 60Hz, 1k Source Imbalance,
V
= –12.6V to 13V
CM
G = 1
86
80
100
120
140
150
dB
dB
dB
dB
dB
dB
dB
dB
l
l
l
l
G = 1
G = 10
G = 10
G = 100
G = 100
G = 1000
G = 1000
106
100
120
115
128
120
AC Common Mode Rejection Ratio
f = 20kHz, QFN20 Package
G = 1
74
98
102
105
dB
dB
dB
dB
G = 10
G = 100
G = 1000
f = 20kHz, MS16E Package
G = 1
69
92
110
110
dB
dB
dB
dB
G = 10
G = 100
G = 1000
PSRR
Power Supply Rejection Ratio
V = 2.375V to 17.5V
S
G = 1
116
110
128
120
122
118
122
118
130
140
140
140
dB
dB
dB
dB
dB
dB
dB
dB
l
l
l
G = 1
G = 10
G = 10
G = 100
G = 100
G = 1000
G = 1000
l
l
V
Supply Voltage
Supply Current
Guaranteed by PSRR
4.75
35
V
S
I
S
V = 15V
2.75
2.65
2.85
3
3.1
mA
mA
mA
S
l
l
T = –40°C to 85°C
A
T = –40°C to 125°C
A
V = 2.375V
2.7
2.85
2.95
mA
mA
mA
S
l
l
T = –40°C to 85°C
A
T = –40°C to 125°C
A
V
Output Voltage Swing
V = 15V, R = 10kΩ
–14.5 –14.9/14
–14.3
13.7
13.6
V
V
OUT
S
L
l
l
l
V = 2.375V, R = 10kΩ
–2
–1.8
–2.3/1.6
1.5
1.3
V
V
S
L
I
Output Short Circuit Current
–3dB Bandwidth
35
30
55
mA
mA
OUT
BW
G = 1
3.1
1.15
184
19
MHz
MHz
kHz
G = 10
G = 100
G = 1000
kHz
SR
Slew Rate
G = 1, V
=
10V
11
V/μs
OUT
t
Settling Time
20V Output Step to 0.0015%
S
G = 1
5.8
9.8
16
μs
μs
μs
μs
G = 10
G = 100
G = 1000
100
Rev. 0
4
For more information www.analog.com
LT6372-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2kΩ.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
30
MAX
UNITS
R
REF Input Resistance
REF Input Current
REF1 or REF2, Untested REF pin floating
kΩ
REFIN
REFIN
I
V
+IN
= V = V
= V = 0V, REF1 or REF2
REF2
–20
–30
–14
–7
3
μA
μA
–IN
REF1
l
l
–
+
V
A
REF Voltage Range
REF Gain to Output
REF Gain Error
REF1 or REF2
V
V
V
REF
V
REF1
V
REF1
= 0V to 5V, V
= 0V to 5V, V
= 0V
0.5
50
V/V
VREF
REF2
= 0V
–175
–200
175
200
ppm
ppm
REF2
l
l
l
l
l
CLLO Input Current
V
V
= 0V
= 5V
1
1
μA
μA
V
CLLO
CLHI Input Current
CLHI
–
+
CLLO Input Operating Voltage Range
CLHI Input Operating Voltage Range
Outside this range CLLO is disabled
Outside this range CLHI is disabled
V + 3
V – 2
–
+
V + 2
V – 2.5
V
CLLO Clamp Voltage (V
– V
)
–0.57
–0.74
–0.45
0.45
V
V
OUT
CLLO
l
l
CLHI Clamp Voltage (V
– V
)
0.55
0.755
V
V
OUT
CLHI
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 8: For more information on how offsets relate to the amplifiers, see
section “Input and Output Offset Voltage” in the Applications section.
Note 9: Hysteresis in output voltage is created by mechanical stress
that differs depending on whether the IC was previously at a higher or
lower temperature. Output voltage is always measured at 25°C, but
the IC is cycled to the hot or cold temperature limit before successive
measurements. Hysteresis is roughly proportional to the square of the
temperature change. For instruments that are stored at well controlled
temperatures (within 20 or 30 degrees of operational temperature),
hysteresis is usually not a significant error source. Typical hysteresis is the
worst case of 25°C to cold to 25°C or 25°C to hot to 25°C, preconditioned
by one thermal cycle.
Note 2: Gains higher than 1000 are possible but the resulting low R values
G
can make PCB and package lead resistance a significant error source.
Note 3: Gain tests are performed with –IN at mid-supply and +IN driven.
Note 4: When the gain is greater than 1 the gain error and gain drift
specifications do not include the effect of external gain set resistor R .
G
Note 5: This specification is guaranteed by design.
Note 6: This specification is guaranteed with high-speed automated testing.
Note 7: This parameter is measured in a high speed automatic tester that
does not measure the thermal effects with longer time constants. The
magnitude of these thermal effects are dependent on the package used,
PCB layout, heat sinking and air flow conditions.
Note 10: Referred to the input.
Rev. 0
5
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Distribution of Input Offset
Voltage, MS16E Package
Distribution of Input Offset
Distribution of Input Offset
Voltage Drift, MS16E Package
Voltage Drift, MS16E Package
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
ꢀ
ꢀ ꢁꢂ0ꢃꢄ ꢅꢆ ꢇꢈꢃꢄ
ꢀ ꢀ ꢁꢂ0ꢃꢄ ꢅꢆ ꢇꢈꢉꢃꢄ
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
0
0
0
ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0
ꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁ 0.0 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ
ꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁ 0.0 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ
ꢀꢁꢂꢃꢄ ꢅꢆꢆꢇꢈꢄ ꢉꢅꢊꢄꢋꢌꢈ ꢍꢎꢉꢏ
ꢀꢁꢂꢃꢄ ꢅꢆꢆꢇꢈꢄ ꢉꢅꢊꢄꢋꢌꢈ ꢍRꢀꢆꢄ ꢎꢏꢉꢐꢑꢒꢓ
ꢀꢁꢂꢃꢄ ꢅꢆꢆꢇꢈꢄ ꢉꢅꢊꢄꢋꢌꢈ ꢍRꢀꢆꢄ ꢎꢏꢉꢐꢑꢒꢓ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢅ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢃ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢁ
Distribution of Input Offset
Voltage, QFN Package
Distribution of Input Offset
Voltage Drift, QFN Package
Distribution of Input Offset
Voltage Drift, QFN Package
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
ꢀ
ꢀ ꢁꢂ0ꢃꢄ ꢅꢆ ꢇꢈꢉꢃꢄ
ꢀ
ꢀ ꢁꢂ0ꢃꢄ ꢅꢆ ꢇꢈꢃꢄ
ꢀ
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
ꢀ0 ꢁꢂꢃꢄꢅ
0
0
0
ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0
ꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁ 0.0 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ
ꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁꢀ0.ꢁ 0.0 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ
ꢀꢁꢂꢃꢄ ꢅꢆꢆꢇꢈꢄ ꢉꢅꢊꢄꢋꢌꢈ ꢍꢎꢉꢏ
ꢀꢁꢂꢃꢄ ꢅꢆꢆꢇꢈꢄ ꢉꢅꢊꢄꢋꢌꢈ ꢍRꢀꢆꢄ ꢎꢏꢉꢐꢑꢒꢓ
ꢀꢁꢂꢃꢄ ꢅꢆꢆꢇꢈꢄ ꢉꢅꢊꢄꢋꢌꢈ ꢍRꢀꢆꢄ ꢎꢏꢉꢐꢑꢒꢓ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢇ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢀ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢇ
Distribution of Output Offset
Voltage, MS16E Package
Distribution of Output Offset
Voltage Drift, MS16E Package
Distribution Output Offset Voltage
Drift, MS16E Package
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
ꢀ
ꢀ ꢁꢂ0ꢃꢄ ꢅꢆ ꢇꢈꢃꢄ
ꢀ ꢀ ꢁꢂ0ꢃꢄ ꢅꢆ ꢇꢈꢉꢃꢄ
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
0
0
0
ꢀꢁꢂ0 ꢀꢁꢂ0 ꢀꢁꢂ0 ꢀꢁ0
0
ꢀ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁꢂ ꢀꢄꢄꢅꢆꢂ ꢇꢀꢈꢂꢉꢊꢆ ꢋꢌꢇꢍ
ꢀꢁꢂꢃꢁꢂ ꢀꢄꢄꢅꢆꢂ ꢇꢀꢈꢂꢉꢊꢆ ꢋRꢌꢄꢂ ꢍꢎꢇꢏꢐꢑꢒ
ꢀꢁꢂꢃꢁꢂ ꢀꢄꢄꢅꢆꢂ ꢇꢀꢈꢂꢉꢊꢆ ꢋRꢌꢄꢂ ꢍꢎꢇꢏꢐꢑꢒ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢂ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢇ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢇ
Rev. 0
6
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Distribution of Output Offset
Voltage Drift, QFN Package
Distribution of Output Offset
Voltage Drift, QFN Package
Distribution of Output Offset
Voltage, QFN Package
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ ꢁꢂ0ꢃꢄ ꢅꢆ ꢇꢈꢉꢃꢄ
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
ꢀ
ꢀ ꢁꢂ0ꢃꢄ ꢅꢆ ꢇꢈꢃꢄ
ꢀ
ꢀ0 ꢁꢂꢃꢄꢅ
ꢀ0 ꢁꢂꢃꢄꢅ
0
0
0
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ0 ꢀꢁꢂ0 ꢀꢁ0 ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀꢁ0 ꢀꢁ0
ꢀꢁꢂꢃꢁꢂ ꢀꢄꢄꢅꢆꢂ ꢇꢀꢈꢂꢉꢊꢆ ꢋRꢌꢄꢂ ꢍꢎꢇꢏꢐꢑꢒ
ꢀꢁꢂꢃꢁꢂ ꢀꢄꢄꢅꢆꢂ ꢇꢀꢈꢂꢉꢊꢆ ꢋRꢌꢄꢂ ꢍꢎꢇꢏꢐꢑꢒ
ꢀꢁꢂꢃꢁꢂ ꢀꢄꢄꢅꢆꢂ ꢇꢀꢈꢂꢉꢊꢆ ꢋꢌꢇꢍ
ꢀꢁꢂꢃꢄꢅ ꢆꢅꢅ
ꢀꢁꢂꢃꢄꢅ ꢆꢅꢃ
ꢀꢁꢂꢃꢄꢅ ꢆꢅ0
Distribution of REF Divider Gain
Error
Distribution of Gain Error
Distribution of Gain Error
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ ꢁ ꢂ000
Rꢀꢁꢂ ꢃ 0ꢄ
ꢀ ꢁ ꢂ
ꢀ
ꢀ ꢁꢂꢃꢄ
Rꢀꢁꢂ ꢃ 0ꢄ ꢅꢆ ꢇꢄ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀꢁ0 ꢂꢃꢄꢅꢆ
ꢀ ꢀ ꢁꢂꢃꢄ
ꢀꢁ0 ꢂꢃꢄꢅꢆ
ꢀ
ꢀꢁ0 ꢂꢃꢄꢅꢆ
0
0
0
ꢀꢁ00
ꢀꢁꢂ0
0
ꢀꢁ0
ꢀ00
ꢀꢁ00 ꢀꢁ0ꢀꢁ0 ꢀꢁ0 ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ00
ꢀꢁ00ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0
0
ꢀꢁꢂꢃ ꢄRRꢅR ꢆꢇꢇꢈꢉ
ꢀꢁꢂꢃ ꢄRRꢅR ꢆꢇꢇꢈꢉ
ꢀꢁꢂꢃ ꢄRRꢅR ꢆꢇꢇꢈꢉ
ꢀꢁꢂꢃꢄꢅ ꢆꢅꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢅꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢅꢁ
REF Divider Gain Drift
REF Gain Drift
Gain Drift (G = 1)
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
Rꢀꢁꢂ ꢃ 0ꢄ
Rꢀꢁꢂ ꢃ ꢄꢅ0
ꢀ0 ꢁꢂꢃꢄꢅ
Rꢀꢁꢂ ꢃ Rꢀꢁꢄ
ꢀ ꢁꢂꢃꢄꢅ
ꢀ ꢁ ꢂ
ꢀꢁ ꢂꢃꢄꢅꢆ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
0
0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄꢅ ꢆꢅꢀ
ꢀꢁꢂꢃꢄꢅ ꢆꢅꢂ
ꢀꢁꢂꢃꢄꢅ ꢆꢅꢇ
Rev. 0
7
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Lead Free Reflow Profile Due to
Gain Drift (G = 1000)
IR Reflow
Gain Nonlinearity (G = 1)
ꢀ000
ꢀꢁ00
ꢀ000
ꢀꢁ00
ꢀ000
ꢀ00
00
0
ꢀ ꢁ ꢂ000
ꢀꢁ ꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂ0
ꢀꢁꢂ
0
R
00
0
0
0
0
0
R
0
0
ꢀꢁ00
ꢀꢁ000
ꢀꢁꢂ00
ꢀꢁ000
0
R
R
R
= 600Ω
ꢀ ꢁꢂ
ꢀ ꢁ0ꢂ
ꢀ
ꢀ
ꢀ
0
0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
0
0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢊꢄꢋꢌꢍꢄꢎ
0
ꢀꢁꢂꢃꢄꢅ ꢆꢅꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢃꢅ
Gain Nonlinearity (G = 100)
Gain Nonlinearity (G = 10)
Gain Nonlinearity (G = 1000)
ꢀ
ꢀ ꢁꢂ0
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂ0
ꢀ
ꢀ ꢁꢂ0
ꢀꢁꢂ
ꢀꢁꢂ
R
R
R
= 600Ω
R
R
R
= 600Ω
ꢀ ꢁꢂ
ꢀ ꢁ0ꢂ
R
R
R
= 600Ω
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀ ꢁꢂ
ꢀ ꢁ0ꢂ
ꢀ ꢁ0ꢂ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢊꢄꢋꢌꢍꢄꢎ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢊꢄꢋꢌꢍꢄꢎ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢊꢄꢋꢌꢍꢄꢎ
ꢀꢁꢂꢃꢄꢅ ꢆꢃꢃ
ꢀꢁꢂꢃꢄꢅ ꢆꢃꢁ
ꢀꢁꢂꢃꢄꢅ ꢆꢃꢇ
CMRR vs Frequency, RTI
QFN Package
CMRR vs Frequency, RTI
MS16E Package
Positive Power Supply Rejection
Ratio vs Frequency, RTI
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢈꢆꢉe
ꢀꢁꢂ ꢃꢄꢅꢆꢄꢇe
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇ
ꢀꢁꢂꢁꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇ
ꢀꢁꢂꢁꢃꢄꢅ
ꢀ0
ꢀ ꢁ ꢂ
ꢀ ꢁ ꢂ
ꢀ ꢁ ꢂ
ꢀ ꢁ ꢂ0
ꢀ ꢁ ꢂ00
ꢀ ꢁ ꢂ000
ꢀ ꢁ ꢂ0
ꢀ ꢁ ꢂ00
ꢀ ꢁ ꢂ000
ꢀ0
ꢀ0
ꢀ ꢁ ꢂ0
ꢀ ꢁ ꢂ00
ꢀ ꢁ ꢂ000
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀ0
ꢀ00
ꢀꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀ0ꢁ
ꢀ00ꢁ
0.ꢀ
ꢀ
ꢀ0 ꢀ00 ꢀꢁ ꢀ0ꢁ ꢀ00ꢁ ꢀꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢄꢅ ꢆꢃꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢃꢀ
ꢀꢁꢂꢃꢄꢅ ꢆꢃꢂ
Rev. 0
8
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Current Noise Density vs
Frequency
Negative Power Supply Rejection
Ratio vs Frequency
Input-Referred Voltage Noise
Density vs Frequency
ꢀ000
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀ00
ꢀꢁꢂꢃꢄꢃꢁꢅꢆꢇ ꢈꢉꢀRꢅꢆ R
ꢀꢁꢂꢁꢃꢄꢅꢆ ꢇꢈꢉRꢄꢅ R
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀ ꢁꢂꢃ
ꢀꢁRꢂꢃR
ꢀ00
ꢀꢁꢂ
ꢀ ꢁꢂꢃ
ꢀꢁRꢂꢃR
ꢀꢁꢂ
ꢀ ꢁꢂꢃ
ꢀꢁRꢂꢃR
ꢀ0
ꢀ0
ꢀ ꢁ ꢂ
ꢀꢁ ꢂꢃꢄꢃꢅ
ꢀ ꢁ ꢂ0
ꢀ ꢁ ꢂ00
ꢀ ꢁ ꢂ000
ꢀ0
ꢀ ꢁ ꢂ000
0
00 000
ꢀ0
ꢀ
0.ꢀ
ꢀ
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0ꢁ ꢀ00ꢁ
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀꢁ
0.ꢀ
ꢀ
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0ꢁ ꢀ00ꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢄꢅ ꢆꢁ0
ꢀꢁꢂꢃꢄꢅ ꢆꢃꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢅ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢃꢇ
0.1Hz to 10Hz Voltage Noise,
G = 100, RTI
0.1Hz to 10Hz Voltage Noise,
G = 1, RTI
0.1Hz to 10Hz Voltage Noise,
G = 10, RTI
ꢀ
ꢀ
ꢀ ꢁ ꢂ00
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ ꢁ ꢂ0
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ ꢁ ꢂ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢁꢉꢊ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢁꢉꢊ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢁꢉꢊ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢁ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢃ
0.1Hz to 10Hz Noise Current,
Balanced Source R
0.1Hz to 10Hz Voltage Noise,
G = 1000, RTI
0.1Hz to 10Hz Noise Current,
Unbalanced Source R
ꢀꢁꢂꢁꢃꢄꢅꢆ ꢇꢈꢉRꢄꢅ R
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢃꢁꢅꢆꢇ ꢈꢉꢀRꢅꢆ R
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁ ꢂ000
ꢀ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢁꢉꢊ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢁꢉꢊ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢁꢉꢊ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢀ
Rev. 0
9
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Input Bias Current vs Common
Mode Voltage
REF Pin Current vs Input
Common Mode Voltage
Input Bias and Offset Current vs
Temperature
ꢀ00
ꢀ00
ꢀ.0
0.ꢀ
ꢀ.0
0.ꢀ
0.ꢀ
0.ꢀ
0
ꢀ00
0.ꢀ
0.ꢀ
ꢀ00
0.ꢀ
0.ꢀ
0
0.0
0.0
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀꢁ.0
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀꢁ.0
ꢀꢁ00
ꢀꢁ00
ꢀꢁ00
ꢀꢁ00
ꢀꢁꢂ ꢃꢁꢄꢅ ꢆꢇRRꢈꢂꢉ
ꢀꢁꢂ ꢃꢁꢄꢅ ꢆꢇRRꢈꢂꢉ
ꢀꢁꢁꢂꢃꢄ ꢅꢆRRꢃꢇꢄ
ꢀꢁꢂ ꢃꢁꢄꢅ ꢆꢇRRꢈꢂꢉ
ꢀꢁꢂ ꢃꢁꢄꢅ ꢆꢇRRꢈꢂꢉ
ꢀꢁꢁꢂꢃꢄ ꢅꢆRRꢃꢇꢄ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢂꢁꢃꢄꢂꢁꢅꢆ ꢇꢃꢈꢉꢊ ꢋꢁꢌꢊꢍꢎꢆ ꢏꢋꢐ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢇꢆꢁꢈꢇꢆꢉꢊ ꢋꢆꢌꢄꢍꢎꢊ ꢏꢋꢐ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢂ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢇ
Output Voltage Swing vs Load
Resistance
Output Voltage Swing vs Load
Resistance
Supply Current vs Supply Voltage
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ
ꢀꢁ
ꢀꢁ
0
ꢀꢁ0
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0
0
ꢀ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
0.ꢀ
ꢀ
ꢀ0
ꢀ00
0.ꢀ
ꢀ
ꢀ0
ꢀ00
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
RESISTIVE LOAD (kΩ)
RESISTIVE LOAD (kΩ)
ꢀꢁꢂꢃꢄꢅ ꢆꢇ0
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢃ
Output Short Circuit Current vs
Temperature
Undistorted Output Swing vs
Frequency
Slew Rate vs Temperature
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ
ꢀ ꢁ ꢂ
0
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂ ꢀ ꢁꢂ0ꢃꢄ
ꢀ
ꢀ
R
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
.
.
ꢀ
R
0
ꢀ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀꢁ
ꢀ0ꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢁ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈ
Rev. 0
10
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Large Signal Transient Response Large Signal Transient Response Large Signal Transient Response
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢂ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ ꢁ ꢂ0
ꢀ ꢁ ꢂ00
ꢀ ꢁ ꢂ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁ00ꢂꢃ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁ00ꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ ꢁ00ꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
Large Signal Transient Response
Small Signal Transient Response
Small Signal Transient Response
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢂ
ꢀ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢇ0
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ ꢁ ꢂ000
ꢀ ꢁ ꢂ
ꢀ ꢁ ꢂ0
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁ00ꢂꢃ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁ00ꢂꢃ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁ00ꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Small Signal Transient Response
Small Signal Transient Response
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢁ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢃ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ ꢁ ꢂ000
ꢀ ꢁ ꢂ00
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁ00ꢂꢃ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁ00ꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
Rev. 0
11
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Clamp Transient Response
(Clamped Output)
Gain vs Frequency
ꢀ0
ꢀ0
ꢀ
ꢂ
ꢃꢄꢀ
ꢁ
ꢆ
ꢅ
ꢂ ꢇꢄꢈꢉ
ꢀ0
ꢀ
ꢀꢁꢂ
0ꢀ
ꢀꢁꢂꢃꢄꢁ
ꢀ0
ꢀ0
ꢀ
ꢀꢁ
0ꢀ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀ0
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ ꢁ ꢂ0
0
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢇ
0
00
000
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ ꢄ ꢅ.ꢆꢀ
ꢀꢁ0
ꢀꢁ0
ꢀꢁꢂꢃ ꢄ 0ꢀ
ꢀ
ꢀ 0ꢁ
ꢀ ꢁ.ꢂꢃ
Rꢀꢁꢂ
ꢀ
Rꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀꢁ
ꢀ0ꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈ
LT6372–1 Supply Current While
Clamping
Clamp Voltage vs Temperature
ꢀ00
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢁꢂ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ 0ꢁ
ꢀꢁꢂ
ꢀ
ꢀ00
ꢀ00
ꢀ
ꢀ
ꢀ ꢁ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ00
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢈꢉꢇ
0
ꢀ
ꢀ
ꢀ
ꢀꢁ00
ꢀꢁ00
ꢀꢁ00
ꢀꢁ00
ꢀꢁꢂꢃꢄꢅꢆ ꢁꢇꢈ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢄ ꢀ
ꢅꢆꢇꢈ
ꢄ ꢉ.ꢊꢀ
Rꢁꢂꢃ
0
ꢀ
ꢄ ꢀ
ꢄ 0ꢀ
= 10kΩ
ꢀ ꢁ ꢂ0
Rꢁꢂꢃ
ꢅꢆꢆꢇ
ꢀ
R
ꢀꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ ꢀ0.ꢁꢂꢀ0.ꢁ0ꢀ0.ꢁꢂ
0
0.ꢀꢁ 0.ꢀ0 0.ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢂ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢀ
Rev. 0
12
For more information www.analog.com
LT6372-1
PIN FUNCTIONS (MS16E/QFN20)
–R (Pin 1/Pin 19): For use with an external gain setting
REF1 (Pin 10/Pin 12): Reference for the output voltage.
REF1 can be tied to REF2 and used as a reference for the
output. REF1 can also be used with REF2 to form a voltage
divider and level shift the output.
resGis,Ftor. This connection should be routed to the gain set-
ting resistor separately from –R in order to minimize
G,S
gain errors.
–R (Pin 2/Pin 20): For use with an external gain set-
OUTPUT (Pin 11/Pin 13): Output voltage referenced to
G,S
ting resistor. This connection should be routed to the gain
the REF pins.
setting resistor separately from –R in order to minimize
V+ (Pin 12/Pin 14): Positive Power Supply. A bypass
capacitor should be used between supply pins and ground.
G,F
gain errors.
–IN (Pin 4/Pin 2): Negative Input Terminal. This input is
high impedance.
REF2 (Pin 13/Pin 15): Reference for the output voltage.
REF2 can be tied to REF1 and used as a reference for the
output. REF2 can also be used with REF1 to form a voltage
divider and level shift the output.
+IN (Pin 5/Pin 5): Positive Input Terminal. This input is
high impedance.
CLLO (Pin 7/Pin 8): Low Side Clamp Input. The voltage
applied to the CLLO pin defines the lower voltage limit
of the output. Typically, the output clamps 500mV below
the voltage applied to the CLLO pin. Do not float CCLO.
+R (Pin 15/Pin 17): For use with an external gain set-
G,S
ting resistor. This connection should be routed to the gain
setting resistor separately from +R in order to minimize
G,F
gain errors.
–
V (Pin 8/Pin 7): Negative Power Supply. A bypass capac-
+R (Pin 16/Pin 18): For use with an external gain set-
G,F
itor should be used between supply pins and ground.
ting resistor. This connection should be routed to the gain
setting resistor separately from +R in order to minimize
G,S
CLHI (Pin 9/Pin 10): High Side Clamp Input. The voltage
applied to the CLHI pin defines the upper voltage limit of
the output. Typically, the output clamps 500mV above the
voltage applied to the CLHI pin. Do not float CLHI.
gain errors.
NIC (Pins 3, 6, 14/Pins 1, 3, 4, 6, 11, 16): No Internal
Connection.
DNC (QFN Pin 9): Do Not Connect. This pin should float.
Rev. 0
13
For more information www.analog.com
LT6372-1
SIMPLIFIED BLOCK DIAGRAM
+
V
R1
12.1k
I1
D2
C1
D1
+
–
200Ω
V
–IN
EMI
Q1
FILTER
–
+
R5
10k
R6
10k
D11
D13
D3
D4
I3
OUTPUT
A1
I2
VB
–
V
–R
–R
G,F
V
G,S
D9
D14
–
+
V
V
CLHI
D13
D15
+R
+R
–
+
G,S
D18
G,F
A3
–
+
V
V
V
CLLO
REF2
V
R2
D17
I4
12.1k
R9
20k
–
–
D6
C2
D5
D8
200Ω
D19
D10
+IN
EMI
FILTER
Q2
–
+
R7
10k
R8
20k
D7
I6
REF1
I5
A2
VB
–
V
–
V
D16
+
–
PREAMP STAGE
DIFFERENCE AMPLIFIER STAGE
V
V
6372-1 BD
Rev. 0
14
For more information www.analog.com
LT6372-1
THEORY OF OPERATION
The LT6372-1 is an improved version of the classic three op voltages on REF1 and REF2. This split reference resistor
amp instrumentation amplifier topology that incorporates configuration allows the output voltage to be easily level
features to improve accuracy and simplify interfacing to shifted to the center of an ADCs input range without exter-
ADCs. Laser trimming and proprietary monolithic construc- nal components. The offset voltage of the difference ampli-
tion allow for tight matching and extremely low drift of fier is trimmed to minimize output offset voltage drift, thus
circuit parameters over the specified temperature range. assuring a high level of performance, even in low gains.
Refer to the Simplified Block Diagram to aid in understand- Resistors R5 to R9 are trimmed to maximize CMRR and
ing the following circuit description. The collector currents minimize gain error. The resulting gain equation is:
in Q1 and Q2 as well as I1 and I4 are trimmed to minimize
24.2k
G = 1+
input offset voltage drift, thus assuring a high level of per-
formance. R1 and R2 are trimmed to an absolute value of
12.1k to assure that the gain can be set accurately (0.12%
R
G
Solving for the gain set resistor gives:
24.2k
at G = 100) with only one external resistor, R . The value of
G
R determines the transconductance of the preamp stage.
G
R =
G
As RG is reduced to increase the programmed gain, the
transconductance of the input preamp stage also increases
to that of the input transistors Q1 and Q2. This causes the
open-loop gain to increase when the programmed gain is
increased, reducing the input related errors and noise. The
input voltage noise at high gains is determined only by Q1
and Q2. At lower gains the noise of the difference amplifier
and preamp gain setting resistors may increase the noise.
The gain bandwidth product is determined by C1, C2 and
the preamp transconductance, which increases with pro-
grammed gain. Therefore, the bandwidth is self-adjusting
and does not drop directly proportional to gain.
G – 1
Table 1 shows appropriate 1% resistor values for a variety of gains.
Table 1. LT6372-1 Gain and RG Lookup.
Resulting Gains for Various 1% Standard Resistor Values
Gain
1
Standard 1% Resistor Value (Ω)
–
1.996
5.007
10.06
20.06
50.69
100.6
201
24.3k
6.04k
2.67k
1.27k
487
The input transistors Q1 and Q2 offer excellent matching,
drift and noise performance, which is due to using a pro-
prietary high performance process, as well as low input
bias current due to the high beta of these input devices.
The input bias current is further reduced by trimming I3
and I6. The collector currents in Q1 and Q2 are held con-
stant due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop. The action of the amplifier loops impresses
the differential input voltage across the external gain set
243
121
497.9
996.9
48.7
24.3
Convenient Integer Gains Using Various Standard 1% Resistor Values
Integer Gain
Standard 1% Resistor Value (Ω)
1
–
3
12.1k
1.21k
1.1k
200
121
110
100
20
21
resistor R . Since the current that flows through R also
G
G
23
122
flows through R1 and R2, the ratios provide a gained-up
differential voltage,
201
R1+ R2
221
G = 1+
R
243
G
1211 (Note 2)
to the difference amplifier A3. The difference amplifier
removes the common mode voltage and provides a sin-
gle-ended output voltage referenced to the average of the
Additionally, The LT6372-1 has two integrated output
voltage clamps which can be used to limit the voltage
Rev. 0
15
For more information www.analog.com
LT6372-1
APPLICATIONS INFORMATION
applied to an ADCs input. Typically, CLHI is tied to the
ADC’s reference and CLLO is tied to the ADC’s ground
connection.
This however often fails to identify limitations associated
with internal swing limits. Referring to the Simplified
Block Diagram, the output swing of pre-amplifiers A1
and A2 as well as the common-mode input range of the
difference amplifier A3 impose limitations on the valid
operating range. Figure 1 shows the operating region
where a valid output is produced for various configura-
tions. Further valid input and output range plots can be
generated using the Diamond Plot Tool.
Valid Input and Output Range
Instrumentation amplifiers traditionally specify a valid
input common mode range and an output swing range.
ꢀꢁ
ꢀ0
ꢀꢉꢍꢌ
ꢌ ꢓꢇ
ꢒ
ꢀ
ꢁ
ꢀ
0
ꢀ ꢁ ꢂ
ꢀ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢁ
ꢂꢅꢃ
ꢄ
ꢌ
ꢁ 0ꢃ
Rꢆꢇꢈ
Rꢆꢇꢂ
ꢉꢊꢋꢌ
ꢉꢊꢊꢍ
ꢁ 0ꢃ
ꢁ ꢂꢅꢃ
ꢁ ꢎꢂꢅꢃ
ꢂꢃꢄꢅꢆꢇꢈꢉ
ꢐꢑꢃ
Rꢎꢊꢉꢏꢇ
ꢀꢁ
ꢀ
ꢁ
ꢌ
ꢔꢕ
ꢌ ꢓꢇ
ꢒ
ꢁ
ꢌ
ꢀꢁ0
ꢄꢅꢆꢇꢈꢉ ꢊ0ꢉꢋ
ꢁꢉꢍꢌ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢅꢇ
ꢀꢁ
ꢀ0
ꢀ
+15V
V /2
D
+
–
ꢀ ꢁ ꢂ00
+
ꢃ
ꢁ ꢂꢅꢃ
V
ꢄ
ꢃ
Rꢆꢇꢈ
ꢃ
Rꢆꢇꢂ
ꢃ
ꢉꢊꢋꢌ
ꢃ
ꢉꢊꢊꢍ
ꢁ 0ꢃ
ꢁ 0ꢃ
0
R
G
LT6372-1
OUT
ꢁ ꢂꢅꢃ
243Ω
REF1,2
ꢁ ꢎꢂꢅꢃ
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ
+
–
V
CM
V /2
D
–
V
6371-2 F01c
–15V
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢅꢇ
Figure 1. Input Common Mode Range vs Output Voltage
Rev. 0
16
For more information www.analog.com
LT6372-1
APPLICATIONS INFORMATION
ꢀꢁ
ꢀ0
ꢀ
+15V
V /2
D
+
ꢀ ꢁ ꢂ00
+5V
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ 0ꢁ
ꢀ 0ꢁ
ꢀ ꢁꢂ
ꢀ 0ꢁ
ꢀ
+
V
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂ
CLHI
R
G
OUT
LT6372-1
243Ω
REF1, 2
CLLO
+
0
V
CM
–
V /2
D
–
V
–
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ
6372-1 F01m
–15V
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢄ ꢅ0ꢄꢆ
ꢀ
ꢀ
ꢀ
ꢀꢌꢋ
ꢋ ꢒꢇ
ꢑ
ꢀ
ꢁ
ꢀ
ꢀ ꢁ ꢂ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢁ
ꢅꢃ
ꢀ
ꢄ
ꢀ
ꢋ
ꢁ 0ꢃ
ꢁ 0ꢃ
ꢁ ꢅꢃ
ꢁ ꢎꢅꢃ
Rꢆꢇꢈ
Rꢆꢇꢂ
ꢉꢊꢋꢌ
ꢉꢊꢊꢍ
0
ꢂꢃꢄꢅꢆꢇꢈꢉ
ꢏꢐꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
Rꢍꢊꢉꢎꢇ
ꢀ
ꢋ
ꢓꢔ
ꢁ
ꢋ ꢒꢇ
ꢑ
ꢁ
ꢋ
ꢄꢅꢆꢇꢈꢉ ꢊ0ꢉe
ꢁꢌꢋ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢅꢇ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
+5V
V /2
D
+
–
ꢀ ꢁ ꢂ00
+
V
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢁ
ꢅꢃ
ꢄ
ꢁ 0ꢃ
ꢁ 0ꢃ
ꢁ ꢅꢃ
Rꢆꢇꢈ
Rꢆꢇꢂ
ꢉꢊꢋꢌ
ꢉꢊꢊꢍ
R
G
LT6372-1
OUT
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
243Ω
REF1,2
+
V
CM
ꢁ ꢎꢅꢃ
–
V /2
D
–
V
6372-1 F01g
–5V
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢅꢇ
Figure 1 (Continued). Input Common Mode Range vs Output Voltage
Rev. 0
17
For more information www.analog.com
LT6372-1
APPLICATIONS INFORMATION
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
ꢀ ꢁ ꢂ
ꢄ
ꢃ
ꢃ
ꢃ
ꢃ
ꢁ ꢅꢃ
ꢆ
ꢁ 0ꢃ
ꢀꢍꢌ
ꢌ ꢒꢇ
ꢑ
ꢁ ꢅꢃ
ꢁ 0ꢃ
Rꢇꢈꢉ
Rꢇꢈꢂ
ꢀ
ꢀ
ꢌ
Rꢎꢊꢇ
Rꢎꢊꢉ
ꢏꢐꢃ
ꢂꢃꢄꢅꢆꢇꢈꢉ
ꢀ
ꢁ
ꢌ
ꢓꢔ
ꢌ ꢒꢇ
ꢑ
ꢁ
ꢌ
ꢁ
ꢃ
ꢃ
ꢁ ꢅꢃ
ꢁ 0ꢃ
ꢊꢋꢌꢍ
ꢊꢋꢋꢎ
ꢄꢅꢆꢇꢈꢉ ꢊ0ꢉꢋ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢅꢇ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
ꢀ ꢁ ꢂ00
ꢄ
ꢆ
ꢃ
ꢃ
ꢃ
ꢃ
ꢁ ꢅꢃ
ꢁ 0ꢃ
+5V
V /2
D
ꢁ ꢅꢃ
ꢁ 0ꢃ
Rꢇꢈꢉ
Rꢇꢈꢂ
+
–
+
V
REF2
REF1
R
G
LT6372-1
OUT
243Ω
+
–
V
CM
V /2
D
–
V
ꢃ
ꢊꢋꢋꢎ
ꢁ ꢅꢃ
ꢁ 0ꢃ
ꢊꢋꢌꢍ
6372-1 F01k
ꢃ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢅꢇ
Figure 1 (Continued). Input Common Mode Range vs Output Voltage
Rev. 0
18
For more information www.analog.com
LT6372-1
APPLICATIONS INFORMATION
Split Reference Pins
In applications where clamping is not desired, CLLO
–
+
should be tied to V and CLHI to V to disable clamping.
Output Level Shifting with the LT6372-1’s difference ampli-
fier features split reference pins, REF1 and REF2, which
allow the output to be easily and accurately level shifted
without the use of external circuitry. REF1 and REF2 are
typically tied to an ADC ground and reference respectively.
In this configuration the amplifier’s output is conveniently
level shifted to the center of the ADC input range.
Input and Output Offset Voltage
The offset voltage of the LT6372-1 has two main compo-
nents: the input offset voltage due to the input amplifiers
and the output offset due to the output amplifier. The total
offset voltage referred to the input (RTI) is found by divid-
ing the output offset by the programmed gain and adding
it to the input offset voltage. At high gains the input offset
voltage dominates, whereas at low gains the output offset
voltage dominates. The total offset voltage is:
If REF1 and REF2 are shorted to each other, they can
function as the reference for the output voltage like a tra-
ditional instrumentation amplifier.
Parasitic resistance in series with REF1 and REF2 should
be minimized to preserve CMRR and gain performance.
It is also important to note that the drift in any circuitry
used to drive REF1 or REF2 can results in an additional
output drift term. Therefore, it may be important to con-
sider the temperature accuracy of the circuitry used to
drive the REF pin.
Total input offset voltage (RTI) = V + V /G
OSI
OSO
Total output offset voltage (RTO) = V • G + V
OSI
OSO
The preceding equations can also be used to calculate
offset drift in a similar manner.
Output Offset Trimming
The LT6372-1 is laser trimmed for low offset voltage
so that no external offset trimming is required for most
applications. In the event that the offset voltage needs
to be adjusted, the circuit in Figure 2 is an example of
an optional offset adjustment circuit. The op amp buffer
provides a low impedance signal to the REF pin in order
to achieve the best CMRR and lowest gain error.
Gain Setting Resistor Connections
Each pre-amplifier gives a set of RG connection termi-
nals which should be routed separately to the gain setting
resistor. Doing this minimizes the impact which parasitic
trace and lead resistance has on gain accuracy. When
routing to the gain setting resistors, large loops should
be avoided as they can couple noise into the amplifier.
+
V
5V
Output Clamps
+
REF2
LT6372-1
REF1
+
V
OUTPUT
The CLHI and CLLO clamp pins limit the output voltage
swing of the LT6372-1. CLHI and CLLO are typically tied
to the ADC supply/reference and ADC ground respectively.
In this case the ADC input is protected from being over-
driven by the LT6372-1 which is likely running off a higher
supply voltage.
–
R1
+10mV
100Ω
–
V
–
5mV
ADJUSTMENT
RANGE
LTC2057
+
10k
100Ω
–10mV
R2
When the CLLO is tied to 0V, attempts to drive the output
below 0V will be clamped at –0.45 typically. When CLHI
is tied to 5V, attempts to drive the output above 5V will
be clamped at 5.45V typically.
–
V
LT6372-1 F02
Figure 2. Optional Trimming of Output Offset Voltage
Thermocouple Effects
CLHI and CLLO are high impedance inputs and do not
conduct significant current during clamping. Rather, inter-
nal amplifier nodes are controlled by CLHI and CLLO to
limit the output voltage.
In order to achieve accuracy on the microvolt level, ther-
mocouple effects must be considered. Any connection
of dissimilar metals forms a thermoelectric junction and
Rev. 0
19
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LT6372-1
APPLICATIONS INFORMATION
generates a small temperature-dependent voltage. Also
known as the Seebeck Effect, these thermal EMFs can be
the dominant error source in low-drift circuits.
ꢖ.0
ꢊ.ꢔ
ꢊ.ꢗ
ꢊ.ꢕ
ꢊ.ꢊ
ꢊ.0
ꢓ.ꢔ
ꢓ.ꢗ
ꢓ.ꢕ
ꢓ.ꢊ
ꢓ.0
0.ꢔ
0.ꢗ
0.ꢕ
0.ꢊ
0
Connectors, switches, relay contacts, sockets, resistors,
and solder are all candidates for significant thermal EMF
generation. Even junctions of copper wire from different
manufacturers can generate thermal EMFs of 200nV/°C,
which is comparable to the maximum input offset voltage
drift specification of the LT6372-1. Figure 3 and Figure 4
illustrate the potential magnitude of these voltages and their
sensitivity to temperature.
ꢖꢋ
ꢊꢋ
ꢖ0
ꢕ0
ꢕꢋ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
In order to minimize thermocouple-induced errors, atten-
tion must be given to circuit board layout and component
selection. It is good practice to minimize the number of
ꢗꢖꢘ0 ꢑ0ꢖ
Figure 3. Thermal EMF Generated by Two Copper Wires
From Different Manufacturers
junctions in the amplifier’s input and R signal paths and
G
avoid connectors, sockets, switches, and relays whenever
possible. If such components are required, they should be
selected for low thermal EMF characteristics. Furthermore,
the number, type, and layout of junctions should be matched
for both inputs with respect to thermal gradients on the cir-
cuit board. Doing so may involve deliberately introducing
dummy junctions to offset unavoidable junctions.
100
SLOPE ≈ 1.5µV/°C
BELOW 25°C
50
64% SN/36% Pb
60% Cd/40% SN
0
SLOPE ≈ 160nV/°C
BELOW 25°C
Air currents can also lead to thermal gradients and cause
significant noise in measurement systems. It is important
to prevent airflow across sensitive circuits. Doing so will
often reduce thermocouple noise substantially. Placing
PCB input traces close together, and on an internal PCB
layer, can help minimize temperature differentials result-
ing from air currents reacting with the input trace thermal
surface area.
–50
–100
0
10
20
30
40
50
SOLDER-COPPER JUNCTION DIFFERENTIAL TEMPERATURE
SOURCE: NEW ELECTRONICS 02-06-77
6370 F04
Figure 4. Solder-Copper Thermal EMFs
Rev. 0
20
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LT6372-1
Reducing Board-Related Leakage Effects
For the lowest leakage, amplifiers can be used to drive the
guard ring. These buffers must have very low input bias
current since that will now be a leakage.
Leakage currents can have a significant impact on system
accuracy, particularly in high temperature and high voltage
applications. Quality insulation materials should be used,
and insulating surfaces should be cleaned to remove fluxes
and other residues. For humid environments, surface coat-
ing may be necessary to provide a moisture barrier.
ꢊ
ꢊ
ꢋ
ꢇꢈꢀꢁꢂꢃꢄꢅ
ꢉ ꢋꢉ
Leakage into the RG pin conducts through the on-chip feed-
back resistor, creating an error at the output of the pre-
amplifiers. This error is independent of gain and degrades
accuracy the most at low gains. This leakage can be mini-
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢀ
Figure 6. Guard-Rings Can Be Used to Minimize
Leakage into the Input Pins
mized by encircling the R connections with a guard-ring
G
Input Bias Current Return Path
operated at a potential very close to that of the R pins.
G
The low input bias current of the LT6372-1 (800pA max) and
high input impedance (225GΩ) allow the use of high imped-
ance sources without introducing additional offset voltage
errors, even when the full common mode range is required.
However, a path must be provided for the input bias cur-
rents of both inputs when a purely differential signal is being
amplified. Without this path, the inputs will float to either rail
and exceed the input common mode range of the LT6372-1,
resulting in a saturated input amplifier. Figure 7 shows three
examples of an input bias current path. The first example
is of a purely differential signal source with a 10kΩ input
current path to ground. Since the impedance of the signal
source is low, only one resistor is needed. Two matching
resistors are needed for higher impedance signal sources as
shown in the second example. Balancing the input imped-
ance improves both AC and DC common mode rejection
and DC offset. The need for input resistors is eliminated if a
center tap is present as shown in the third example.
NIC pins adjacent to each R pin can be used to simplify
G
the implementation of this guard-ring. These NIC pins do
not provide any bias and have no internal connections. In
some cases, the guard-ring can be connected to the input
voltage which biases one diode drop below R .
G
ꢋ
ꢋ
ꢌ
ꢈꢉꢀꢁꢂꢃꢄꢅ
ꢊ ꢌꢊ
ꢀꢁꢂꢃꢄꢅ ꢆ0ꢇ
Figure 5. Guard-Rings Can Be Used to Minimize
Leakage into the RG Pins
Leakage into the input pins reacts with the source resis-
tance, creating an error directly at the input. This leakage
can be minimized by encircling the input connections with
a guard-rings operated at a potential very close to that
of the input pins. In some cases, the guard-ring can be
connected to R which biases one diode above the input.
G
ꢛ
ꢛ
ꢜ
ꢛ
ꢌꢒꢎRꢍꢐꢊꢍꢓꢋꢔ
ꢊꢕꢖRꢍꢐꢊꢍꢓꢋꢔ
ꢋꢉꢎ
R
ꢂ
R
ꢂ
R
ꢂ
ꢑꢉꢃꢄꢅꢆꢇꢀ
Rꢋꢈꢀꢔꢆ
ꢉꢊꢋRꢌꢍꢎꢍꢏꢐꢑꢋ
ꢑꢉꢃꢄꢅꢆꢇꢀ
Rꢋꢈꢀꢔꢆ
ꢑꢉꢃꢄꢅꢆꢇꢀ
Rꢋꢈꢀꢔꢆ
ꢜ
ꢜ
ꢆ00ꢁ
ꢆ00ꢁ
ꢀ0ꢁ
ꢎꢋꢓꢉꢋRꢇꢉꢗꢐ ꢐRꢍꢘꢒꢖꢋꢙ
ꢚꢒꢗꢙ ꢎꢏRRꢋꢓꢉ RꢋꢉꢏRꢓ
ꢃꢄꢅꢆꢇꢀ ꢈ0ꢅ
Figure 7. Providing an Input Common Mode Current Path
Rev. 0
21
For more information www.analog.com
LT6372-1
APPLICATIONS INFORMATION
Input Protection
The amplitude and frequency of the interference can have
an adverse effect on an instrumentation amplifier’s input
stage by causing any unwanted DC shift in the amplifier’s
input offset voltage. This well known effect is called RFI
rectification and is produced when out-of-band interfer-
ence is coupled (inductively, capacitively or via radiation)
and rectified by the instrumentation amplifier’s input tran-
sistors. These transistors act as high frequency signal
detectors, in the same way diodes were used as RF enve-
lope detectors in early radio designs. Regardless of the
type of interference or the method by which it is coupled
into the circuit, an out-of-band error signal appears in
series with the instrumentation amplifier’s inputs.
Additional input protection can be achieved by adding
external resistors in series with each input. If low value
resistors are needed, a clamp diode from the positive
supply to each input will help improve robustness. A
2N4394 drain/source to gate is a good low leakage diode
which can be used as shown in Figure 8. Robust input
resistors should be chosen, such as carbon composite
or bulk metal foil. Metal film and carbon film should not
be used because of their poor performance.
ꢀ
ꢀ
ꢊꢊ
ꢊꢊ
ꢏꢒꢑꢓꢏꢌꢔꢕ ꢈꢏR ꢖꢓꢗꢖꢁꢘꢑ
ꢁꢘꢙ ꢒRꢏꢑꢁꢊꢑꢓꢏꢌ
ꢋꢇ
ꢅꢌꢍꢃꢎꢃ
ꢋꢅ
ꢅꢌꢍꢃꢎꢃ
To help minimize this effect, the LT6372-1 has 50MHz on-
chip RFI filters to help attenuate high frequencies before
they can interact with its input transistors. These on-chip
filters are well matched due to their monolithic construc-
tion, which helps minimize any degradation in AC CMRR.
To reduce the effect of these out-of-band signals on the
input offset voltage of the LT6372-1 further, an additional
external low-pass filter can be used at the inputs. The
filter should be located very close to the input pins of
the circuit. An effective filter configuration is illustrated
in Figure 9, where three capacitors have been added to
the inputs of the LT6372-1.
ꢀ
ꢊꢊ
R
R
ꢓꢌ
ꢓꢌ
ꢛ
ꢏꢐꢑ
ꢕꢑꢂꢃꢄꢅꢆꢇ
R
ꢗ
Rꢁꢈꢇꢜꢅ
ꢚ
ꢂꢃꢄꢅꢆꢇ ꢈ0ꢉ
ꢀ
ꢁꢁ
Figure 8. Input Protection
Maintaining AC CMRR
To achieve optimum AC CMRR, it is important to balance
the capacitance on the R gain setting pins. Furthermore,
if the source resistance Gon each input is not equal, add-
ing an additional resistance to one input to improve input
source resistance matching will improve AC CMRR.
The filter limits the input signal according to the following
relationship:
1
FilterFreqDIFF
=
2πR(2CD +CC)
RFI Reduction/Internal RFI Filter
1
FilterFreqCM
=
2πRCC
In many industrial and data acquisition applications, the
LT6372-1 will be used to amplify small signals accurately
in the presence of large common mode voltages or high
levels of noise. Typically, the sources of these very small
signals (on the order of microvolts or millivolts) are sen-
sors that can be a significant distance from the signal
conditioning circuit. Although these sensors may be con-
nected to signal conditioning circuitry using shielded or
unshielded twisted-pair cabling, the cabling may act as
an antenna, conveying very high frequency interference
directly into the input stage of the LT6372-1.
where C ≥10C .
D
C
C affects the difference signal. C affects the common-
D
C
mode signal. Any mismatch in R × CC degrades the
LT6372-1 CMRR. To avoid inadvertently reducing CMRR-
bandwidth performance, make sure that C is at least one
C
magnitude smaller than C .The effect of mismatched C s
is reduced with a larger CD:C ratio.
C
D
C
Rev. 0
22
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LT6372-1
APPLICATIONS INFORMATION
1. Pick R and C to have a low pass pole at least 10x
D
+
higher than the highest signal of interest (e.g. 500Hz for
V
C
R
1.54k
C
10n
a 50Hz signal) using:
+
+
IN
1
FilterFreqDIFF
=
C
D
100n
2πR(2CD +CC)
R
G
LT6372-1
V
OUT
1
R
=
1.54k
–
–
2πR(2CD +0.1CD)
IN
C
C
1
–
10n
V
=
f
≈ 500Hz
6372-1 F09
–3dB
4.2πRCD
EXTERNAL RFI
FILTER
2. Select C = C /10.
C
D
Figure 9. Adding a Simple External RC Filter at the Inputs to
an Instrumentation Amplifier Is Effective in Further Reducing
Rectification of High Frequency Out-Of-Band Signals
If implemented this way, the common-mode pole fre-
quency is placed about 20x higher than the differential
pole frequency. Here are the differential and common-
mode low pass pole frequencies for the values shown in
Figure 9:
To avoid any possibility of common mode to differential
mode signal conversion, match the common mode low-
pass filter on each input to 1% or better. Here are the steps
to help determine appropriate values for the filter:
FilterFreq
= 500Hz
DIFF
FilterFreq = 10kHz
CM
Rev. 0
23
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LT6372-1
APPLICATIONS INFORMATION
Error Budget Analysis
intsrumentation amplifiers as shown in Figure 11 requires
external precison components which decrease accu-
racy, increase cost and occupy valuable PCB space. The
error budget in Table 2 shows the total system error of a
LT6372-1 used as a bridge amplifier.
The LT6372-1 features a split reference configuration pro-
viding a convenient and effective way to interface a bipolar
swing to an ADC input without additional precision com-
ponents. Performing the same level shift with traditional
+
5V REF
+
10V
10V
350Ω
350Ω
REF2
LT6372-1
REF1
350Ω
350Ω
350Ω
R
R
G
G
LT6370A
REF
243Ω
243Ω
5V REF
R1
350Ω
350Ω
350Ω
–
–
+
–
6372-1 F11
R2
6372-1 F10
LT6370A MONOLITHIC
INSTRUMENTATION AMPLIFIER
G = 100, R 0ꢀ1ꢁ, 10ꢂꢂp TC
PRECISION BRIDGE TRANSDUCER
LT6370A MONOLITHIC
PRECISION BRIDGE TRANSDUCER
INSTRUMENTATION AMPLIFIER
=
G = 100, R
= 0ꢀ1ꢁ, 10ꢂꢂp TC
G
G
Figure 10. Precision Bridge Amplifier Using LT6372-1
Figure 11. Precision Bridge Amplifier with External Level Shift
Table 2. Error Budget
ERROR SOURCE
ERROR, ppm OF FULL SCALE
LT6372-1
CALCULATION
°
Absolute Accuracy at T = 25 C
A
2200
3000
137.5
12.25
250
Gain Error, %
Gain Error in % • 10k + 1000
Input Offset Voltage, µV
Output Offset Voltage, µV
Input Offset Current, nA
CMRR, dB
V
/20mV
OSI
[V /100]/20mV
OSO
[(I )(350)/2]/20mV
OS
[(CMRR in ppm)(5V)/20mV
Total Accuracy Error
Total Drift Error
5599.75
Drift to 85°C
2700
1800
120
Gain Drift, ppm/°C
(Gain Drift + 10ppm/°C)(60°C)
Input Offset Voltage Drift, µV/°C
Output Offset Voltage Drift, µV/°C
[(V Drift)(60°C)]/20mV
OSI
[(V
Drift)(60°C)]/100/20mV
OSO
4620
Resolution
Gain Nonlinearity, ppm of Full Scale
Typ 0.1Hz to 10Hz Voltage Noise, µV
50
10
(0.1Hz to 10Hz Noise)/20mV
P-P
Total Resolution Error
Grand Total Error
60
10279.75
G = 100
All errors are min/max and referred to input.
Rev. 0
24
For more information www.analog.com
LT6372-1
TYPICAL APPLICATIONS
Differential Output Instrumentation Amplifier
AC Coupled Instrumentation Amplifier
+V
S
ꢀꢄ
ꢅ
+
ꢀ
ꢃ
+IN
–IN
ꢀꢁꢂ
R
LT6372-1
REF1,2
OUTPUT
G
R
ꢀꢆꢇꢈ
ꢔꢈꢉꢊꢋꢌꢍꢎ
Rꢐꢑꢎꢒꢌ
ꢙ
R1
500k
ꢎ0ꢖ
ꢎ0ꢖ
C1
0.3µF
ꢄ
ꢓꢁꢏꢅ
–
ꢃꢁꢂ
ꢃ
ꢀ
ꢎꢌꢕꢑ
–V
S
–
+
ꢃꢄ
ꢔꢈꢗꢌ0ꢘꢋ
ꢅ
1
LTC2057
f
=
–3dB
(2π)(R1)(C1)
= 1.06Hz
ꢃꢆꢇꢈ
ꢉꢊꢋꢌꢍꢎ ꢈꢏ0ꢌ
6372-1 TA03
Precision Voltage-to-Current Converter
V
S
+
+IN
R
X
LT6372-1
R
G
REF1,2
V
–
+
X
–IN
–
I
L
–V
S
LTC2057
V
R
[(+IN) – (–IN)]G
X
I
=
=
L
R
X
X
LOAD
24.2kΩ
G =
+ 1
R
G
6372-1 TA04
High Side, Bidirectional Current Sense
I
L
= 2A
R
SENSE
0.05Ω
V
BUS
V
> –12V
BUS
BUS
V
< 11V
+V
S
LOAD
+
–
R
!
$
&
%
24.2k
RG
G
LT6372-1
V
OUT =IL •RSENSE • 1+
#
499Ω
REF1,2
"
=2.5V / A
6372-1 TA05
–V
S
Rev. 0
25
For more information www.analog.com
LT6372-1
PACKAGE DESCRIPTION
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
ꢟReꢩeꢪeꢫꢬe ꢕꢈꢑ ꢊꢌꢎ ꢭ 0ꢂꢮ0ꢯꢮꢁꢤꢅꢖ Rev ꢨꢠ
0.ꢤ0 ±0.0ꢂ
ꢀ.ꢂ0 ±0.0ꢂ
ꢖ.ꢁ0 ±0.0ꢂ
ꢖ.ꢞꢂ ±0.0ꢂ
ꢁ.ꢂ0 Rꢃꢄ
ꢁ.ꢞꢂ ±0.0ꢂ
ꢒꢋꢑꢓꢋꢎꢃ ꢇꢔꢈꢕꢍꢆꢃ
0.ꢖꢂ ±0.0ꢂ
0.ꢂ0 ꢙꢏꢑ
ꢖ.ꢂ0 Rꢃꢄ
ꢀ.ꢁ0 ±0.0ꢂ
ꢅ.ꢂ0 ±0.0ꢂ
Rꢃꢑꢇꢗꢗꢃꢆꢊꢃꢊ ꢏꢇꢕꢊꢃR ꢒꢋꢊ ꢒꢍꢈꢑꢚ ꢋꢆꢊ ꢊꢍꢗꢃꢆꢏꢍꢇꢆꢏ
ꢋꢒꢒꢕꢝ ꢏꢇꢕꢊꢃR ꢗꢋꢏꢓ ꢈꢇ ꢋRꢃꢋꢏ ꢈꢚꢋꢈ ꢋRꢃ ꢆꢇꢈ ꢏꢇꢕꢊꢃRꢃꢊ
ꢒꢍꢆ ꢁ ꢆꢇꢈꢑꢚ
R ꢥ 0.ꢖ0 ꢇR 0.ꢖꢂ
× ꢅꢂ° ꢑꢚꢋꢗꢄꢃR
0.ꢤꢂ ±0.0ꢂ
ꢁ.ꢂ0 Rꢃꢄ
ꢁꢡ ꢖ0
R ꢥ 0.0ꢂ ꢈꢝꢒ
ꢀ.00 ±0.ꢁ0
0.ꢅ0 ±0.ꢁ0
ꢁ
ꢒꢍꢆ ꢁ
ꢈꢇꢒ ꢗꢋRꢓ
ꢟꢆꢇꢈꢃ ꢞꢠ
ꢖ
ꢖ.ꢞꢂ ±0.ꢁ0
ꢁ.ꢞꢂ ±0.ꢁ0
ꢅ.00 ±0.ꢁ0
ꢖ.ꢂ0 Rꢃꢄ
ꢟꢔꢊꢑꢖ0ꢠ ꢧꢄꢆ ꢁꢁ0ꢞ Rꢃꢢ ꢨ
0.ꢖ00 Rꢃꢄ
0.00 ꢦ 0.0ꢂ
0.ꢖꢂ ±0.0ꢂ
R ꢥ 0.ꢁꢁꢂ
ꢈꢝꢒ
0.ꢂ0 ꢙꢏꢑ
ꢙꢇꢈꢈꢇꢗ ꢢꢍꢃꢌꢣꢃꢘꢒꢇꢏꢃꢊ ꢒꢋꢊ
ꢆꢇꢈꢃꢉ
ꢁ. ꢊRꢋꢌꢍꢆꢎ ꢍꢏ ꢆꢇꢈ ꢋ ꢐꢃꢊꢃꢑ ꢒꢋꢑꢓꢋꢎꢃ ꢇꢔꢈꢕꢍꢆꢃ
ꢖ. ꢊRꢋꢌꢍꢆꢎ ꢆꢇꢈ ꢈꢇ ꢏꢑꢋꢕꢃ
ꢀ. ꢋꢕꢕ ꢊꢍꢗꢃꢆꢏꢍꢇꢆꢏ ꢋRꢃ ꢍꢆ ꢗꢍꢕꢕꢍꢗꢃꢈꢃRꢏ
ꢅ. ꢊꢍꢗꢃꢆꢏꢍꢇꢆꢏ ꢇꢄ ꢃꢘꢒꢇꢏꢃꢊ ꢒꢋꢊ ꢇꢆ ꢙꢇꢈꢈꢇꢗ ꢇꢄ ꢒꢋꢑꢓꢋꢎꢃ ꢊꢇ ꢆꢇꢈ ꢍꢆꢑꢕꢔꢊꢃ
ꢗꢇꢕꢊ ꢄꢕꢋꢏꢚ. ꢗꢇꢕꢊ ꢄꢕꢋꢏꢚꢛ ꢍꢄ ꢒRꢃꢏꢃꢆꢈꢛ ꢏꢚꢋꢕꢕ ꢆꢇꢈ ꢃꢘꢑꢃꢃꢊ 0.ꢁꢂꢜꢜ ꢇꢆ ꢋꢆꢝ ꢏꢍꢊꢃ
ꢂ. ꢃꢘꢒꢇꢏꢃꢊ ꢒꢋꢊ ꢏꢚꢋꢕꢕ ꢙꢃ ꢏꢇꢕꢊꢃR ꢒꢕꢋꢈꢃꢊ
ꢞ. ꢏꢚꢋꢊꢃꢊ ꢋRꢃꢋ ꢍꢏ ꢇꢆꢕꢝ ꢋ RꢃꢄꢃRꢃꢆꢑꢃ ꢄꢇR ꢒꢍꢆ ꢁ ꢕꢇꢑꢋꢈꢍꢇꢆ
ꢇꢆ ꢈꢚꢃ ꢈꢇꢒ ꢋꢆꢊ ꢙꢇꢈꢈꢇꢗ ꢇꢄ ꢒꢋꢑꢓꢋꢎꢃ
Rev. 0
26
For more information www.analog.com
LT6372-1
PACKAGE DESCRIPTION
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
1
8
0.35
REF
5.10
(.201)
MIN
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ±0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0° – 6° TYP
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0213 REV F
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
27
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT6372-1
TYPICAL APPLICATION
Programmable Gain Amplifier
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢃꢄ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀ.ꢁꢂ
Rꢀ
ꢀꢁ0ꢂ
Rꢀꢁ
Rꢀꢁ
Rꢀꢁ
ꢀ.ꢀꢁ
ꢀꢁ
ꢀꢁ.ꢂ
ꢀꢀꢁ
ꢀꢁ
ꢀꢁ
0.ꢀꢁꢂ
Rꢀ
ꢀ00ꢁ
Rꢀ
ꢀ00ꢁ
Rꢀ
ꢀ00ꢁ
Rꢀ
ꢀ00ꢁ
ꢀꢁꢂꢃꢀ
ꢀꢁ
ꢀꢁꢂ
Rꢀ
ꢀꢁ0
Rꢀ
ꢀꢁ0
ꢀRꢁꢂ
ꢀꢁ0ꢂ
Rꢀ
ꢀRꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁ ꢂꢃꢄꢅꢂꢆꢇ
ꢀꢁ.ꢂ
ꢀRꢁꢂ
Rꢀꢁꢂ
Rꢀ
Rꢀ
ꢀꢁ0
ꢀRꢁꢂ
ꢀ0ꢁ ꢂꢃꢄꢄ ꢃꢅꢆꢇꢈꢉ
ꢀꢁꢂ
Rꢀꢁꢂ
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ0ꢂ
ꢀꢁ
ꢀꢁꢂꢃ ꢄeꢅeꢆꢇ
ꢀꢁꢂꢃꢄꢅ
Rꢀꢁ
Rꢀꢁ
Rꢀꢁ
ꢀꢁ.ꢂ
ꢀ.ꢀꢁ
ꢀꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅ ꢆꢇ ꢆ0ꢇ
ꢀ00ꢁ ꢂꢃꢄ ꢅ00ꢆꢇꢆ
ꢀꢁ
ꢀꢁ0ꢂ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂꢃꢃꢄ
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
0
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Instrumentation Amplifiers
AD8429
LT6372-0.2
LT6370
Low Noise Instrumentation Amplifier
Low Drift Instrumentation Amplifier
Low Drift Instrumentation Amplifier
Zero-Drift Instrumentation Amplifier
Low Noise Instrumentation Amplifier
Low Power Instrumentation Amplifier
Instrumentation Amplifier
V = 36V, I = 6.7mA, V = 50µV, BW = 15MHz, eni = 1nV/√Hz, eno = 45nV/√Hz
S S OS
LT6372-1 with Min Gain = 0.2V/V
V = 30V, I = 2.65mA, V = 25µV, BW = 3.1MHz, eni = 7nV/√Hz, eno = 65nV/√Hz
S
S
OS
LTC1100
AD8421
AD8221
LT1167
V = 18V, I = 2.4mA, V = 10μV, BW = 19kHz, 1.9µV DC to 10Hz
S S OS P-P
V = 36V, I = 2mA, V = 25μV, BW = 10MHz, eni = 3nV/√Hz, eno = 60nV/√Hz
S
S
OS
V = 36V, I = 900μA, V = 25μV, BW = 825kHz, eni = 8nV/√Hz, eno = 75nV/√Hz
S
S
OS
V = 36V, I = 900μA, V = 40μV, BW = 1MHz, eni = 7.5nV/√Hz, eno = 67nV/√Hz
S
S
OS
AD620
Low Power Instrumentation Amplifier
RRIO Instrumentation Amplifier
V = 36V, I = 900μA, V = 50μV, BW = 1MHz, eni = 9nV/√Hz, eno = 72nV/√Hz
S S OS
LTC6800
LTC2053
LT1168
V = 5.5V, I = 800μA, V = 100μV, BW = 200kHz, 2.5µV DC to 10Hz
S S OS P-P
Zero-Drift Instrumentation Amplifier
Low Power Instrumentation Amplifier
V = 11V, I = 750μA, V = 10μV, BW = 200kHz, 2.5µV DC to 10Hz
S S OS P-P
V = 36V, I = 350μA, V = 40μV, BW = 400kHz, eni = 10nV/√Hz, eno = 165nV/√Hz
S
S
OS
Operational Amplifiers
LTC2057
40V Zero Drift Op Amp
V
OS
= 4μV, Drift = 15nV/°C, I = 200pA, I = 900μA
B S
Analog to Digital Converters
LTC2389-16
LTC2367-16
16-Bit SAR ADC
16-Bit SAR ADC
2.5Msps, 96dB SNR, 162.5mW
500Ksps, 94.7dB SNR, 6.8mW
Rev. 0
10/20
www.analog.com
ANALOG DEVICES, INC. 2020
28
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