LT6376HDF#TRPBF [Linear]
LT6376 - ±230V Common Mode Voltage G = 10 Difference Amplifier; Package: DFN; Pins: 14; Temperature Range: -40°C to 125°C;
| 型号： | LT6376HDF#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT6376 - ±230V Common Mode Voltage G = 10 Difference Amplifier; Package: DFN; Pins: 14; Temperature Range: -40°C to 125°C 放大器 光电二极管 |
| 文件： | 总30页 (文件大小：2998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT6376
230V Common Mode
Voltage G = 10 Difference Amplifier
FEATURES
DESCRIPTION
The LT®6376 is a gain of 10 difference amplifier which
combines excellent DC precision, a very high input
common mode range and a wide supply voltage range.
It includes a precision op amp and a highly-matched
thin film resistor network. It features excellent CMRR,
extremely low gain error and extremely low gain drift.
n
230V Common Mode Voltage Range
n
105nV/√Hz Input Referred Noise (Resistor
Divider = 3.1)
90dB Minimum CMRR
n
n
0.0075% (75ppm) Maximum Gain Error
n
1ppm/°C Maximum Gain Error Drift
n
2ppm Maximum Gain Nonlinearity
Comparing the LT6376 to existing difference amplifiers
with high common mode voltage range, the gain of 10
and selectable resistor divider ratios of the LT6376 offer
superior system performance by allowing the user to
achieve low input referred noise with maximum preci-
sion and speed.
The op amp at the core of the LT6376 has Over-The-Top®
protected inputs which allow for robust operation in envi-
ronments with unpredictable voltage conditions. See the
Applications Information section for more details.
n
Wide Supply Voltage Range: 3.3V to 50V
n
Rail-to-Rail Output
350µA Supply Current
n
n
Selectable Internal Resistor Divider Ratio
200µV Maximum Input Offset Voltage
n
n
300kHz –3dB Bandwidth (Resistor Divider = 3.1)
160kHz –3dB Bandwidth (Resistor Divider = 10.3)
–40°C to 125°C Specified Temperature Range
Low Power Shutdown: 20μA (DFN Package Only)
Space-Saving MSOP and DFN Packages
n
n
n
n
The LT6376 is specified over the –40°C to 125°C tem-
perature range and is available in space-saving MSOP16
and DFN14 packages.
APPLICATIONS
n
High Side or Low Side Current Sensing
n
Bidirectional Wide Common Mode Range Current Sensing
All registered trademarks and trademarks are the property of their respective owners.
n
High Voltage to Low Voltage Level Translation
n
Precision Difference Amplifier
n
Replacement for Isolation Circuits
TYPICAL APPLICATION
Precision Wide Voltage Range, Bidirectional Current Monitor
Typical Distribution of CMRR
25V
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
6ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
+
V
63ꢀ ꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ ꢄꢅꢂ ꢁꢆꢇꢈ
DF14(12)
ꢀ
ꢀꢁ
ꢀ
ꢁꢂꢃ
–REFA
±9k
–REFB
38k
–REFC
23.75k
ꢀ
ꢀ
ꢀ
ꢁꢂ3ꢃ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
760k
+
V
= –230V TO 230V
SOURCE
76k
–IN
+IN
–
+
R
OUT
REF
SENSE
R
±Ω
C
V
OUT
= ±±0ꢀV/ꢀA
±Ω
76k
LOAD
760k
±9k
+REFA
38k
23.75k
+REFC
–
ꢀꢁꢂ ꢀ3ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 3ꢀ ꢀꢁ
+REFB
SHDN
V
ꢀꢁꢂꢂ ꢃꢄꢅꢆꢅ ꢇ ꢈꢈꢉꢊ
6376 TA0±a
6376 ꢀꢁꢂꢃꢄ
–25V
6376f
1
For more information www.linear.com/LT6376
LT6376
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Output Short-Circuit Duration (Note 3) Thermally Limited
Temperature Range (Notes 4, 5)
LT6376I ...............................................–40°C to 85°C
LT6376H............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
MSOP Lead Temperature (Soldering, 10 sec)........300°C
Supply Voltages
(V to V )..............................................................60V
+IN, –IN, (Note 2)
Each Input......................................................... 240V
Differential........................................................ 480V
+REFA, –REFA, +REFB, –REFB, +REFC, –REFC,
+
–
+
–
REF, SHDN (Note 2) ................ (V + 0.3V) to (V –0.3V)
Output Current (Continuous) (Note 6)....................50mA
PIN CONFIGURATION
ꢐꢎꢕ ꢍꢄꢇꢖ
TOP VIEW
ꢃꢄꢅ
ꢀ
ꢀꢁ ꢌꢄꢅ
1
3
+IN
16 –IN
+REFA
14 –REFA
12 –REFB
ꢃꢆꢇꢈꢉ
ꢃꢆꢇꢈꢊ
ꢃꢆꢇꢈꢋ
ꢆꢇꢈ
3
ꢁ
ꢂ
6
7
ꢀꢑ ꢌꢆꢇꢈꢉ
ꢀꢀ ꢌꢆꢇꢈꢊ
ꢌ
5
6
7
8
+REFB
+REFC
REF
ꢀꢂ ꢍ
11 –REFC
+
ꢀꢒ ꢌꢆꢇꢈꢋ
ꢃ
10
9
V
–
V
OUT
ꢓ
ꢔ
ꢍ
MS PACKAGE
SHDN
ꢎꢏꢐ
VARIATION: MS16 (12)
16-LEAD PLASTIC MSOP
T
= 150°C, qJA = 130°C/W
JMAX
ꢗꢈ ꢕꢉꢋꢘꢉꢙꢇ
ꢀꢁꢚꢀꢑꢛꢜꢝꢇꢉꢗ ꢚꢁꢞꢞ × ꢁꢞꢞꢛ ꢕꢝꢉꢟꢐꢄꢋ ꢗꢈꢅ
T
= 150°C, qJA = 43°C/W, qJC = 4°C/W
JMAX
–
EXPOSED PAD (PIN 15) IS V , MUST BE SOLDERED TO PCB
http://www.linear.com/product/LT6376#orderinfo
ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LT6376IDF#PBF
LT6376HDF#PBF
LT6376IMS#PBF
LT6376HMS#PBF
LT6376IDF#TRPBF
LT6376HDF#TRPBF
LT6376IMS#TRPBF
LT6376HMS#TRPBF
6376
6376
6376
6376
14-Lead (4mm × 4mm) Plastic DFN
14-Lead (4mm × 4mm) Plastic DFN
16-Lead Plastic MSOP
–40°C to 125°C
–40°C to 85°C
16-Lead Plastic MSOP
–40°C to 125°C
*The temperature grade is identified by a label on the shipping container.
Consult ADI Marketing for parts specified with wider operating temperature ranges. Parts ending with PBF are RoHS and WEEE compliant.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
6376f
2
For more information www.linear.com/LT6376
LT6376
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at TA = 25°C,
V+ = 15V, V– = –15V, VCM = VOUT = VREF = 0V. VCMOP is the common mode voltage of the internal op amp. For Resistor Divider
Ratio = 3.1, ±REFA = ± REFC = OPEN, ±REFB = 0V. For Resistor Divider Ratio = 8.3, ±REFA = ±REFC = 0V, ±REFB = OPEN. For Resistor
Divider Ratio = 10.3, ±REFA = ±REFB = ±REFC = 0V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
10
MAX
UNITS
G
Gain
V
V
=
=
10V
10V
V/V
OUT
OUT
∆G
Gain Error,
MS16 Package
0.002
0.0075
0.0085
%
%
l
∆G
Gain Error,
V
V
V
=
=
=
10V
10V
10V
0.002
0.2
1
0.0085
0.0095
%
%
OUT
OUT
l
l
DF14 Package
∆G/∆T
GNL
Gain Drift vs Temperature
(Note 6)
1
ppm/°C
Gain Nonlinearity
2
3
ppm
ppm
OUT
–
l
+
V
Input Offset Voltage
V < V
< V –1.75V
CMOP
OS
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 8.3
Resistor Divider Ratio = 8.3
Resistor Divider Ratio = 10.3
Resistor Divider Ratio = 10.3
50
200
600
µV
µV
µV
µV
µV
µV
l
l
l
120
160
500
1600
600
2000
–
+
∆V /∆T
OS
Input Offset Voltage Drift
(Note 6)
V < V
< V –1.75V
CMOP
l
l
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 10.3
1.5
5
4
12
µV/°C
µV/°C
R
Input Impedance (Note 8)
Common Mode
IN
l
l
l
l
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 8.3
Resistor Divider Ratio = 10.3
Differential
47
36
56
43
65
50
kΩ
kΩ
kΩ
kΩ
35
42
49
128
152
176
CMRR
CMRR
Common Mode Rejection Ratio,
MS16 Package
Resistor Divider Ratio = 3.1, V
=
=
28V
28V
90
88
98
98
98
95
95
95
96
96
dB
dB
CM
l
l
l
l
l
l
l
Resistor Divider Ratio = 8.3, V
90
88
dB
dB
CM
Resistor Divider Ratio = 10.3, V
=
28V
90
88
dB
dB
CM
Common Mode Rejection Ratio,
DF14 Package
Resistor Divider Ratio = 3.1, V
=
=
28V
28V
88
86
dB
dB
CM
CM
Resistor Divider Ratio = 8.3, V
88
86
dB
dB
Resistor Divider Ratio = 10.3, V
Resistor Divider Ratio = 10.3, V
=
=
=
28V
88
86
dB
dB
CM
150V,
230V,
90
86
dB
dB
CM
V = 25V, T = –40°C to 125°C
S
A
Resistor Divider Ratio = 10.3, V
90
89
dB
dB
CM
l
l
V = 25V, T = –40°C to 85°C
S
A
V
Input Voltage Range (Note 7)
–230
230
V
CM
PSRR
Power Supply Rejection Ratio
(Input Referred)
V = 1.65V to 25V, V = V
= Mid-Supply
OUT
S
CM
l
l
l
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 8.3
105
98
96
120
110
107
dB
dB
dB
Resistor Divider Ratio = 10.3
e
Input Referred Noise Voltage
Density
f = 1kHz
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 10.3
ni
105
245
nV/√Hz
nV/√Hz
6376f
3
For more information www.linear.com/LT6376
LT6376
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at TA = 25°C,
V+ = 15V, V– = –15V, VCM = VOUT = VREF = 0V. VCMOP is the common mode voltage of the internal op amp. For Resistor Divider
Ratio = 3.1, ±REFA = ± REFC = OPEN, ±REFB = 0V. For Resistor Divider Ratio = 8.3, ±REFA = ±REFC = 0V, ±REFB = OPEN. For Resistor
Divider Ratio = 10.3, ±REFA = ±REFB = ±REFC = 0V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Referred Noise Voltage
f = 0.1Hz to 10Hz
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 10.3
4
10
µV
µV
P-P
P-P
l
l
V
V
Output Voltage Swing Low
No Load
SINK
5
50
mV
mV
OL
OH
–
(Referred to V )
I
= 5mA
280
500
l
l
Output Voltage Swing High
No Load
SOURCE
5
400
20
750
mV
mV
+
(Referred to V )
I
= 5mA
+
–
l
l
I
Short-Circuit Output Current
50Ω to V
50Ω to V
10
10
28
30
mA
mA
SC
l
SR
Slew Rate
∆V
=
5V
2.2
4.1
V/µs
OUT
BW
Small Signal –3dB Bandwidth
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 8.3
Resistor Divider Ratio = 10.3
300
190
160
kHz
kHz
kHz
t
Settling Time
Resistor Divider Ratio = 3.1
S
0.01%, ∆V
= 10V
41
26
15
µs
µs
µs
OUT
OUT
0.1%, ∆V
= 10V
0.01%, ∆V = 10V, ∆V
= 0V
= 0V
CM
DIFF
Resistor Divider Ratio = 10.3
0.01%, ∆V = 10V
26
16
5
µs
µs
µs
OUT
OUT
0.1%, ∆V
= 10V
0.01%, ∆V = 10V, ∆V
CM
DIFF
V
Supply Voltage
3
3.3
50
50
V
V
S
l
t
Turn-On Time
16
µs
V
ON
l
l
l
V
SHDN Input Logic Low
(Referred to V )
–2.5
IL
+
V
SHDN Input Logic High
(Referred to V )
–1.2
V
IH
+
I
I
SHDN Pin Current
–10
350
–15
µA
SHDN
+
+
Supply Current
Active, V
Active, V
≥ V –1.2V
400
600
25
µA
µA
µA
µA
S
SHDN
SHDN
Shutdown, V
Shutdown, V
l
l
≥ V –1.2V
+
+
≤ V –2.5V
≤ V –2.5V
20
SHDN
SHDN
70
6376f
4
For more information www.linear.com/LT6376
LT6376
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at TA = 25°C,
V+ = 5V, V– = 0V, VCM = VOUT = VREF = Mid-Supply. VCMOP is the common mode voltage of the internal op amp. For Resistor
Divider Ratio = 3.1, ±REFA = ±REFC = OPEN, ±REFB = Mid-Supply. For Resistor Divider Ratio = 8.3, ±REFA = ±REFC = Mid-Supply,
±REFB = OPEN. For Resistor Divider Ratio = 10.3, ±REFA = ±REFB = ±REFC = Mid-Supply.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
10
MAX
UNITS
G
Gain
V
OUT
V
OUT
= 1V to 4V
= 1V to 4V
V/V
∆G
Gain Error,
MS16 Package
0.002
0.01
0.012
%
%
l
∆G
Gain Error,
V
OUT
V
OUT
V
OUT
= 1V to 4V
= 1V to 4V
0.002
0.2
1
0.012
0.013
%
%
l
l
DF14 Package
∆G/∆T
Gain Drift vs Temperature
(Note 6)
1
ppm/°C
GNL
Gain Nonlinearity
= 1V to 4V
ppm
+
V
Input Offset Voltage
0 < V
< V –1.75V
OS
CMOP
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 8.3
Resistor Divider Ratio = 8.3
Resistor Divider Ratio = 10.3
Resistor Divider Ratio = 10.3
50
200
600
µV
µV
µV
µV
µV
µV
l
l
l
120
160
500
1600
600
2000
+
∆V /∆T
OS
Input Offset Voltage Drift
(Note 6)
0 < V
< V –1.75V
CMOP
l
l
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 10.3
1.5
5
4
12
µV/°C
µV/°C
R
Input Impedance (Note 8)
Common Mode
IN
l
l
l
l
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 8.3
Resistor Divider Ratio = 10.3
Differential
47
36
56
43
65
50
kΩ
kΩ
kΩ
kΩ
35
42
49
128
152
176
CMRR
CMRR
PSRR
Common Mode Rejection Ratio,
MS16 Package
Resistor Divider Ratio = 3.1
CM
90
87
97
97
97
94
94
94
dB
dB
l
l
l
l
l
l
V
= –5.25V to +4.825V
Resistor Divider Ratio = 8.3
= –18.25V to +8.725V
90
87
dB
dB
V
CM
Resistor Divider Ratio = 10.3
= –23.25V to +10.225V
90
87
dB
dB
V
CM
Common Mode Rejection Ratio,
DF14 Package
Resistor Divider Ratio = 3.1
= –5.25V to +4.825V
86
85
dB
dB
V
CM
Resistor Divider Ratio = 8.3
= –18.25V to +8.725V
86
85
dB
dB
V
CM
Resistor Divider Ratio = 10.3
= –23.25V to +10.225V
86
85
dB
dB
V
CM
Power Supply Rejection Ratio
(Input Referred)
V = 1.65V to 25V, V = V
= Mid-Supply
OUT
S
CM
l
l
l
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 8.3
Resistor Divider Ratio = 10.3
105
98
96
120
110
107
dB
dB
dB
e
ni
Input Referred Noise Voltage
Density
f = 1kHz
Resistor Divider Ratio = 3.1
105
245
nV/√Hz
nV/√Hz
Resistor Divider Ratio = 10.3
Input Referred Noise Voltage
f = 0.1Hz to 10Hz
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 10.3
4
10
µV
µV
P-P
P-P
l
l
V
V
Output Voltage Swing Low
No Load
SINK
5
50
mV
mV
OL
OH
–
(Referred to V )
I
= 5mA
280
500
l
l
Output Voltage Swing High
No Load
= 5mA
5
400
20
750
mV
mV
+
(Referred to V )
I
SOURCE
6376f
5
For more information www.linear.com/LT6376
LT6376
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at TA = 25°C,
V+ = 5V, V– = 0V, VCM = VOUT = VREF = Mid-Supply. VCMOP is the common mode voltage of the internal op amp. For Resistor
Divider Ratio = 3.1, ±REFA = ±REFC = OPEN, ±REFB = Mid-Supply. For Resistor Divider Ratio = 8.3, ±REFA = ±REFC = Mid-Supply,
±REFB = OPEN. For Resistor Divider Ratio = 10.3, ±REFA = ±REFB = ±REFC = Mid-Supply.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
l
l
I
Short-Circuit Output Current
50Ω to V
10
10
27
25
mA
mA
SC
–
50Ω to V
l
SR
Slew Rate
∆V
OUT
= 3V
1.9
3
V/µs
BW
Small Signal –3dB Bandwidth
Resistor Divider Ratio = 3.1
Resistor Divider Ratio = 8.3
Resistor Divider Ratio = 10.3
300
190
160
kHz
kHz
kHz
t
S
Settling Time
Resistor Divider Ratio = 3.1
0.01%, ∆V
= 2V
34
20
10
µs
µs
µs
OUT
OUT
0.1%, ∆V
= 2V
0.01%, ∆V = 2V, ∆V
= 0V
= 0V
CM
DIFF
Resistor Divider Ratio = 10.3
0.01%, ∆V = 2V
40
16
5
µs
µs
µs
OUT
OUT
0.1%, ∆V
= 2V
0.01%, ∆V = 2V, ∆V
CM
DIFF
V
Supply Voltage
3
3.3
50
50
V
V
S
l
t
Turn-On Time
22
µs
V
ON
l
l
l
V
SHDN Input Logic Low
(Referred to V )
–2.5
IL
+
V
SHDN Input Logic High
(Referred to V )
–1.2
V
IH
+
I
I
SHDN Pin Current
–10
330
–15
µA
SHDN
+
+
Supply Current
Active, V
Active, V
≥ V –1.2V
370
525
20
µA
µA
µA
µA
S
SHDN
SHDN
Shutdown, V
Shutdown, V
l
l
≥ V –1.2V
+
+
≤ V –2.5V
≤ V –2.5V
15
SHDN
SHDN
40
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: The LT6376I is guaranteed to meet specified performance from
–40°C to 85°C. The LT6376H is guaranteed to meet specified performance
from –40°C to 125°C.
Note 6: This parameter is not 100% tested.
Note 2: See Common Mode Voltage Range in the Applications Information
section of this data sheet for other considerations when taking +IN/–IN
pins to 240V. All other pins should not be taken more than 0.3V beyond
the supply rails.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum. This depends on the power supply, input
voltages and the output current.
Note 7: Input voltage range is guaranteed by the CMRR test at V = 25V
S
and all REF pins at ground (Resistor Divider Ratio = 10.3). For the other
voltages, this parameter is guaranteed by design and through correlation
with the 25V test. See Common Mode Voltage Range in the Applications
Information section to determine the valid input voltage range under
various operating conditions.
Note 8: Input impedance is tested by a combination of direct measurement
Note 4: The LT6376I is guaranteed functional over the operating
temperature range of –40°C to 85°C. The LT6376H is guaranteed
functional over the operating temperature range of –40°C to 125°C.
and correlation to the CMRR and gain error tests.
6376f
6
For more information www.linear.com/LT6376
LT6376
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, unless otherwise noted.
Typical Distribution of CMRR
Typical Distribution of CMRR
Typical Distribution of CMRR
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂ3ꢃ
63ꢀ ꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ ꢄꢅꢂ ꢁꢆꢇꢈ
ꢀꢁꢁ ꢂꢃꢄꢅꢆ
ꢀꢁꢁ ꢂꢃꢄꢅꢆ
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ ꢄꢅꢂ ꢁꢆꢇꢈ
ꢀꢁꢂꢃ ꢄꢅꢂ ꢁꢆꢇꢈ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀꢁꢁ DF14(12)
ꢀꢁꢁ MS16(12)
ꢀꢁꢁ DF14(12)
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁ
6ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
6ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
6ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ ꢀ3ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 3ꢀ ꢀꢁ
ꢀꢁꢂ ꢀ3ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 3ꢀ ꢀꢁ
ꢀꢁꢂ ꢀ3ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 3ꢀ ꢀꢁ
ꢀꢁꢂꢂ ꢃꢄꢅꢆꢅ ꢇ ꢈꢈꢉꢊ
ꢀꢁꢂꢂ ꢃꢄꢅꢆꢅ ꢇ ꢈꢈꢉꢊ
ꢀꢁꢂꢂ ꢃꢄꢅꢆꢅ ꢇ ꢈꢈꢉꢊ
6376 ꢀꢁꢂ
6376 ꢀꢁꢂ
6376 ꢀꢁ3
Typical Distribution of Gain Error
Typical Distribution of Gain Error
Typical Distribution of Gain Error
ꢀꢁꢁ
3ꢀꢁ
3ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
7ꢀ
ꢀꢁꢁ
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
7ꢀ
ꢀ3ꢁ7 ꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ ꢀꢂꢄꢁ ꢁꢄꢅꢆ
66ꢀ ꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ ꢄꢅꢂ ꢁꢆꢇꢈ
6ꢀꢁ ꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢂ ꢁꢆꢇꢈ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
BOTH PACKAGES
MS16(12)
DF14(12)
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ7ꢁ ꢀꢁꢂ ꢀ3ꢁ ꢀꢁꢂ ꢀꢁ
3ꢀ
ꢀꢁ
7ꢀ
ꢀ7ꢁ ꢀꢁꢂ ꢀ3ꢁ ꢀꢁꢂ ꢀꢁ
3ꢀ
ꢀꢁ
7ꢀ
ꢀ7ꢁ ꢀꢁꢂ ꢀ3ꢁ ꢀꢁꢂ ꢀꢁ
3ꢀ
ꢀꢁ
7ꢀ
ꢀꢁꢂꢃ ꢄꢅꢅꢆꢅ ꢇꢈꢈꢉꢊ
ꢀꢁꢂꢃ ꢄꢅꢅꢆꢅ ꢇꢈꢈꢉꢊ
ꢀꢁꢂꢃ ꢄꢅꢅꢆꢅ ꢇꢈꢈꢉꢊ
6376 ꢀꢁꢂ
6376 ꢀꢁꢂ
6376 ꢀꢁ6
Typical Distribution of Gain
Nonlinearity
Typical Distribution of Input
Offset Voltage
Typical Distribution of Input
Offset Voltage
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
7ꢀ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
7ꢀ
ꢀꢁꢁ
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
7ꢀ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ
ꢀꢁꢂꢃ ꢀꢂꢄꢁ ꢁꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂ ꢃ ꢄꢅ3
ꢀ
ꢀꢁꢂ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ ꢀꢂꢄꢁ ꢁꢄꢅꢆ
BOTH PACKAGES
ꢀ
BOTH PACKAGES
ꢀ3ꢁ3 ꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ ꢀꢂꢄꢁ ꢁꢄꢅꢆ
BOTH PACKAGES
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢂ ꢀꢁꢂꢃ ꢀꢁꢂꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢂ ꢀ37ꢁ ꢀꢁꢂꢃ ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ 37ꢀ ꢀꢁꢁ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁ6 ꢀꢁꢂ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁ6 ꢀꢁꢂ
ꢀ
ꢀꢁꢁꢂꢃꢄ ꢅꢀꢆꢄꢇꢈꢃ ꢉꢊꢅꢋ
ꢀꢁꢁꢂꢃꢄ ꢅꢀꢆꢄꢇꢈꢃ ꢉꢊꢅꢋ
ꢀꢁꢂꢃ ꢃꢄꢃꢅꢂꢃꢆꢁꢇꢂꢈꢉ ꢊꢋꢋꢌꢍ
6376 ꢀꢁꢂ
6376 ꢀꢁꢂ
6376 ꢀꢁ7
6376f
7
For more information www.linear.com/LT6376
LT6376
TA = 25°C, VS = ±15V, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Distribution of Input
Offset Voltage
Typical Distribution of PSRR
(Input Referred)
Typical Distribution of PSRR
(Input Referred)
ꢀꢁꢂ
3ꢀꢀ
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
3ꢀꢀ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ
ꢀꢀꢁ ꢀꢁꢂꢃ ꢀꢂꢄꢁ ꢁꢄꢅꢆ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀ
ꢀ
ꢁꢂꢃ6ꢄ ꢅꢆ ꢇ6ꢄ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ6ꢄ ꢅꢆ ꢇ6ꢄ
ꢀ
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂ ꢃ ꢄꢅ3
BOTH PACKAGES
ꢀꢁꢁ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ
ꢀꢁꢂꢃ ꢀꢂꢄꢁ ꢁꢄꢅꢆ
BOTH PACKAGES
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ
ꢀꢁꢂꢃ ꢀꢂꢄꢁ ꢁꢄꢅꢆ
BOTH PACKAGES
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
7ꢀ
ꢀꢁ
6ꢀ
6ꢀ
ꢀꢁ
3ꢀ
3ꢀ
ꢀ
ꢀ
ꢀ
ꢀ6ꢁꢁ ꢀꢁꢂꢃ ꢀ3ꢁꢁ ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ 3ꢀꢀ ꢀꢁꢂ 6ꢀꢀ
ꢀꢁ ꢀꢁ ꢀ3 ꢀꢁ ꢀꢁ
ꢀ
ꢀ
ꢀ
3
ꢀ
ꢀ
ꢀꢁꢂ ꢀꢁ ꢀ6 ꢀꢁ ꢀꢁ
ꢀ
ꢀ
ꢀ
6
ꢀ
ꢀꢁ
ꢀꢁꢁꢂꢃꢄ ꢅꢀꢆꢄꢇꢈꢃ ꢉꢊꢅꢋ
ꢀꢁꢂꢂ ꢃꢄꢅꢆꢅꢇ
ꢀꢁꢂꢂ ꢃꢄꢅꢆꢅꢇ
6376 ꢀꢁꢂ
6376 ꢀꢁꢁ
6376 ꢀꢁꢂ
Typical Distribution of PSRR
(Input Referred)
Common Mode Voltage Range vs
Power Supply Voltage
CMRR vs Frequency
3ꢀꢀ
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
6ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
3ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀ
ꢀ
ꢁꢂꢃ6ꢄ ꢅꢆ ꢇ6ꢄ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ
ꢀꢁꢂꢃ ꢀꢂꢄꢁ ꢁꢄꢅꢆ
BOTH PACKAGES
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂ ꢃ ꢄꢅ3
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁꢂ ꢃ 6ꢄ3
ꢀꢁꢂ ꢃ 7ꢄꢅ
ꢀꢁꢂ ꢃ ꢄꢅ3
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀꢁꢂꢃꢁ ꢄꢅ
ꢀꢆꢆ ꢇꢈꢉꢄꢀꢅ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀ3ꢁꢁ
6ꢀ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂ ꢃ ꢄꢅ3
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
3ꢀ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁ ꢀ6 ꢀ3
ꢀ
3
6
ꢀ
ꢀꢁ ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ ꢀꢁꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ 3ꢀ 3ꢀ ꢀꢁ ꢀꢁ
ꢀꢁꢂꢂ ꢃꢄꢅꢆꢅꢇ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄ ꢅꢆꢀꢀꢇꢈ ꢉꢁꢇꢊꢋꢌꢃ ꢍ ꢉꢎ
6376 ꢀꢁ3
6376 ꢀꢁꢂ
6376 ꢀꢁꢂ
Typical Gain Error for Low Supply
Voltages (Curves Offset for
Clarity)
Typical Gain Error for RL = 10kΩ
(Curves Offset for Clarity)
Typical Gain Error for RL = 2kΩ
(Curves Offset for Clarity)
ꢀ
ꢀ
ꢀ ꢁꢂꢃ ꢄ = 10kΩ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ ꢄ = 2kΩ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ ꢄ = 1kΩ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄꢅ ꢆ = 1kΩ
ꢀ
ꢀ
ꢀꢁꢂ ꢀꢁ6 ꢀꢁꢂ ꢀꢁ ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀ6 ꢀꢁ
ꢀꢁꢂ ꢀꢁ6 ꢀꢁꢂ ꢀꢁ ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀ6 ꢀꢁ
ꢀꢁ ꢀꢁ ꢀ3 ꢀꢁ ꢀꢁ
ꢀ
ꢀ
ꢀ
3
ꢀ
ꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
6376 ꢀꢁ6
6376 ꢀꢁ7
6376 ꢀꢁꢂ
6376f
8
For more information www.linear.com/LT6376
LT6376
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, unless otherwise noted.
Gain Nonlinearity
Gain Nonlinearity
Gain Error vs Temperature
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀꢁꢂ
ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀ ꢁ ꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ = 100kΩ
ꢀ
ꢀ = 1MΩ
ꢀ
ꢀ
ꢀꢁ ꢂꢃꢄꢅꢆ
6ꢀ
6ꢀ
6
6
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ6ꢁ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ6ꢁ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁ
ꢀꢁ
ꢀ6
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀ6
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ7ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 7ꢀ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
6376 ꢀꢁꢂ
6376 ꢀꢁꢂ
6376 ꢀꢁꢂ
Maximum Power Dissipation vs
Temperature
CMRR vs Temperature
Output Voltage vs Load Current
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
3
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀꢁ ꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢂꢅꢆ θ ꢀ ꢁ3ꢂꢃꢄꢅ
ꢀꢁ
ꢀꢁꢂ ꢃ 3ꢄꢅ
3ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀ3ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ3ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ6ꢃꢂꢄꢅ θ ꢀ ꢁ3ꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀ7ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 7ꢀ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀ7ꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
3ꢀ
ꢀ6ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀ6ꢁ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢁꢅꢅꢆꢇꢂ ꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
6376 ꢀꢁꢁ
6376 ꢀꢁ3
6376 ꢀꢁꢂ
Frequency Response vs
Capacitive Load
Input Referred Noise Density vs
Frequency
Gain vs Frequency
ꢀꢁ
3ꢀ
ꢀꢁ
3ꢀ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
3ꢀꢁ
3ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ3ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ6ꢁ
ꢀ7ꢁ
ꢀꢁꢂ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ3ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ6ꢁ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂ ꢃ ꢄꢅ3
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁꢂ ꢃ 6ꢄ3
ꢀꢁꢂ ꢃ 7ꢄꢅ
ꢀꢁꢂ ꢃ ꢄꢅ3
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
3ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀ
ꢀꢁꢀꢀꢂ
ꢀꢁꢀꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢀꢀꢂ
ꢀꢁꢀꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋ
6376 ꢀꢁꢂ
6376 ꢀꢁ6
6376 ꢀꢁ7
6376f
9
For more information www.linear.com/LT6376
LT6376
TA = 25°C, VS = ±15V, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
0.1Hz to 10Hz Noise
(Input Referred)
Positive PSRR vs Frequency
Negative PSRR vs Frequency
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀ3ꢁ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
7ꢀ
6ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢀꢁ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀꢁꢂ ꢃ ꢄꢅ3
ꢀꢁꢂ ꢃ ꢄꢅ3
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
7ꢀ
6ꢀ
ꢀꢁ
ꢀꢁ
3ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
6
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ6
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
3ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢁꢊꢋ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋ
6376 ꢀꢁꢂ
6376 ꢀꢁꢂ
6376 ꢀ3ꢁ
Slew Rate vs Temperature
Large-Signal Step Response
Small-Signal Step Response
7
6
ꢀ
ꢀ
3
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀ ꢁꢂꢂꢂꢃꢄ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂꢁꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢂꢂꢃꢄ
= 2kΩ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀ
ꢀ
ꢀ = 2kΩ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
= 10kΩ
ꢀ ꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢁꢊꢋ
ꢀ7ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 7ꢀ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀ7ꢁ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢁꢊꢋ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
6376 ꢀ33
6376 ꢀ3ꢁ
6376 ꢀ3ꢁ
Small-Signal Step Response
vs Capacitive Load
Large-Signal Step Response
Small-Signal Step Response
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀ ꢀ ꢁꢂꢂꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀ6ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢂꢂꢃꢄ
= 2kΩ
ꢀ
= 2kΩ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
= 2kΩ
ꢀꢁꢁꢁꢂꢃ
6ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ6ꢁ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢁꢊꢋ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ 3ꢀ 3ꢀ ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢁꢊꢋ
ꢀꢁꢂꢃ ꢄꢅꢆꢇ
6376 ꢀ3ꢁ
6376 ꢀ36
6376 ꢀ3ꢁ
6376f
10
For more information www.linear.com/LT6376
LT6376
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, unless otherwise noted.
Small-Signal Step Response
vs Capacitive Load
Settling Time
Settling Time
ꢀꢁꢂ
3ꢀꢁ
3ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ6
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ ꢃ ꢄꢅꢆ3
ꢀ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢁꢂꢁ ꢃꢂꢄꢅꢆꢇꢀ
ꢀꢁꢂꢃ
ꢀ6ꢁꢂꢃ
ꢀꢁꢁꢁꢂꢃ
ꢀ
= 2kΩ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ3ꢁꢂ
ꢀ3ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀ6
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ6
6ꢀ
ꢀꢁ
6
ꢀꢁ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ6ꢁ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ
ꢀ
ꢀꢁꢁꢂꢁ ꢃꢂꢄꢅꢆꢇꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ 3ꢀ 3ꢀ ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢊꢁꢋꢌ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢊꢁꢋꢌ
ꢀꢁꢂꢃ ꢄꢅꢆꢇ
6376 ꢀ3ꢁ
6376 ꢀ37
6376 ꢀ3ꢁ
Input Common Mode Step
Response
Input Offset Voltage vs
Temperature
Quiescent Current vs Temperature
ꢀꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
3ꢀꢁ
3ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢁ
3ꢀꢀ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁ ꢂꢃꢄꢅꢆ
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁ ꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢁ
ꢀ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢇꢆꢁ ꢇꢆꢈꢉ
ꢀꢁꢂꢂ
ꢀꢁꢂꢂ
ꢀ3ꢁꢁ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢁꢊꢋ
ꢀ7ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 7ꢀ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀ7ꢁ
ꢀ6ꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
6376 ꢀꢁꢂ
6376 ꢀꢁꢂ
6376 ꢀꢁꢂ
Quiescent Current vs Supply
Voltage
Thermal Shutdown Hysteresis
6ꢀꢀ
ꢀꢁꢁ
ꢀꢁꢁ
3ꢀꢀ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀ
6ꢀꢀ
ꢀꢁꢁ
ꢀꢁꢁ
3ꢀꢀ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄꢅ
ꢀ
ꢀ
ꢀ ꢁꢂꢂꢃꢄ
ꢀ
ꢀꢁꢂꢁꢃꢄꢅꢂꢆꢇ ꢈꢉꢄꢄꢀ ꢆꢊ ꢋꢌꢍꢎꢇ
ꢀꢁꢂꢃꢄꢅꢄꢁꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀ6ꢁ
ꢀ6ꢁ
ꢀ7ꢁ
ꢀ
ꢀꢁ
ꢀꢁ
3ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
6376 ꢀꢁ3
6376 ꢀꢁꢁ
6376f
11
For more information www.linear.com/LT6376
LT6376
TA = 25°C, VS = ±±5V, ꢀunl ee ꢁot l ꢂwiel uꢁol d.
Miuimꢀm Sꢀppny Vꢁnoagl
TYPICAL PERFORMANCE CHARACTERISTICS
Qꢀil ecl uo Cꢀꢂꢂl uo ve SHDN
Vꢁnoagl
St ꢀodꢁwu Qꢀil ecl uo Cꢀꢂꢂl uo ve
Sꢀppny Vꢁnoagl
ꢀꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
3ꢀꢁ
3ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
3ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀ
ꢁ ꢂꢀ
SHDN
ꢀꢁꢂ ꢃ 3ꢄꢅ
ꢀꢁꢁ
ꢀ
ꢂ ꢃꢄꢀ
ꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃꢄꢅ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃꢄꢅ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
3
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
3ꢀ
ꢀꢁ
ꢀꢁ
SHDN ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁꢀꢂꢃ ꢄꢅꢆꢆꢃꢇ ꢈꢁꢃꢀꢂꢉꢊ ꢋꢈꢌ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
6376 ꢀꢁ6
6376 ꢀꢁ7
6376 ꢀꢁꢂ
6376f
12
For more information www.linear.com/LT6376
LT6376
PIN FUNCTIONS (DFN/MSOP)
V (Piu 9/Piu ±0): Positive Supply Pin.
+
–REFA (Piu ±2/Piu ±4): Reference Pin A. Sets the input
common mode range and the output noise and offset.
–
V (Expꢁel d Pad Piu ±5/Piu 8): Negative Supply Pin.
–REFB (Piu ±±/Piu ±2): Reference Pin B. Sets the input
OUT (Piu 8/Piu 9): Output Pin.
common mode range and the output noise and offset.
+IN (Piu ±/Piu ±): Noninverting Input Pin. Accepts input
voltages from 230V to –230V.
–REFC (Piu ±0/Piu ±±): Reference Pin C. Sets the input
common mode range and the output noise and offset.
+REFA (Piu 3/Piu 3): Reference Pin A. Sets the input com-
mon mode range and the output noise and offset.
REF (Piu 6/Piu 7): Reference Input. Sets the output level
when the difference between the inputs is zero.
+REFB (Piu 4/Piu 5): Reference Pin B. Sets the input
common mode range and the output noise and offset.
SHDN (Piu 7) DFN Ouny: Shutdown Pin. Amplifier is active
+
when this pin is tied to V or left floating. Pulling the pin
+
+REFC (Piu 5/Piu 6): Reference Pin C. Sets the input
common mode range and the output noise and offset.
>2.5V below V causes the amplifier to enter a low power
state.
–IN (Piu ±4/Piu ±6): Inverting Input Pin. Accepts input
voltages from 230V to –230V.
6376f
13
For more information www.linear.com/LT6376
LT6376
BLOCK DIAGRAM
ꢁ
ꢀꢆꢇꢈꢉ
ꢍꢎꢏ
ꢀꢆꢇꢈꢌ
ꢀꢆꢇꢈꢕ
ꢒ3ꢓ7ꢔꢏ
ꢂ
3ꢐꢏ
76ꢑꢏ
76ꢏ
76ꢏ
ꢀꢊꢋ
ꢁꢊꢋ
ꢀ
ꢁ
ꢃꢄꢅ
ꢆꢇꢈ
76ꢑꢏ
ꢁ
ꢂ
ꢍꢎꢏ
3ꢐꢏ
ꢁꢆꢇꢈꢌ
ꢒ3ꢓ7ꢔꢏ
ꢁꢆꢇꢈꢕ
ꢍꢑꢗꢉ
ꢀ
ꢂ
ꢁꢆꢇꢈꢉ
SHDN
6376 ꢌꢖ
APPLICATIONS INFORMATION
TRANSFER FUNCTION
performance of the part. It is recommended to use the
lowest resistor divider ratio that achieves the required
input common mode voltage range of the application in
order to maximize the system SNR, precision and speed.
The LT6376 is a gain of 10 difference amplifier with the
transfer function:
V
OUT
= 10 • (V – V ) + V
+IN –IN REF
Table 1 shows the noise, offset/drift, and –3dB bandwidth
of the LT6376 in gain of 10 configurations.
The voltage on the REF pin sets the output voltage when
the differential input voltage (V = V – V ) is zero.
This reference is used to shift the output voltage to the COMMON MODE VOLTAGE RANGE
desired input level of the next stage of the signal chain.
DIFF
+IN
–IN
The wide common mode voltage range of the LT6376 is
enabled by both a resistor divider at the input of the op
amp and by an internal op amp that can withstand high
input voltages.
BENEFITS OF SELECTABLE RESISTOR DIVIDER RATIOS
The LT6376 offers smaller package size, better gain
accuracy and better noise performance than existing
high common mode voltage range difference amplifiers.
Additionally, the LT6376 allows users to maximize sys-
tem performance by selecting the resistor divider ratio
(DIV) appropriate to their input common mode voltage
range. A higher resistor divider ratio (DIV) enables a
higher common mode voltage range at the input pins,
but it also increases output noise and output offset/drift
and decreases the –3dB bandwidth. Therefore, a trade-
off exists between input range and DC, AC, and drift
The internal resistor network of the LT6376 divides down
the input common mode voltage. The resulting voltage
at the op amp inputs determines the op amp’s operating
region. In the configuration shown in Figure 1, a resistor
divider is created at both op amp inputs by the 76k input
resistor and the resistance from each input to ground,
which is ~36.19k. The resistance to ground is formed
by the 38k (REFB resistors) in parallel with the 760k
(feedback/REF resistor). The result is a divide by 3.1 of
the input voltage. As shown in Tables 1 to 5, different
connections to reference pins (i.e. pins +REFA, –REFA,
6376f
14
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
Tabnl ±. LT6376 Pl ꢂfꢁꢂmaucl ao Diffl ꢂl uo Rl eieoꢁꢂ Dividl ꢂ Raoiꢁe
RESISTOR DIVIDER OPTIONS
RESISTOR
INPUT NOISE
AT ±kHz
MAXIMUM INPUT
OFFSET DRIFT
(µV/°C)
–3dB
BANDWIDTH
(kHz)
+REFA AND +REFB AND +REFC AND
DIVIDER DIFFERENTIAL
MAXIMUM INPUT
OFFSET (µV)
–REFA
–REFB
–REFC
23.75k
OPEN
GND
REF RATIO (DIV)
GAIN
(uV/√Hz)
19k
38k
760k
REF
REF
REF
REF
REF
REF
REF
OPEN
OPEN
GND
OPEN
GND
GND
GND
GND
3.1
4.3
5.1
6.3
7.1
8.3
10.3
10
10
10
10
10
10
10
105
130
145
170
185
210
245
200
250
300
380
420
500
600
4
300
275
245
225
200
190
160
OPEN
OPEN
GND
5.5
6.5
7.5
8.5
10
OPEN
GND
GND
OPEN
GND
OPEN
GND
GND
12
+REFB, –REFB, +REFC, –REFC) result in different resis-
tor divider ratios (DIV) and different attenuation of the
LT6376’s input common mode voltage.
the voltage ranges in this table ensures that the internal
op amp is operating in its normal (and best) region. The
figure entitled Common Mode Voltage Range vs Power
Supply Voltage, in the Typical Performance Characteristics
section of this data sheet, illustrates the information in
Table 2 graphically.
The internal op amp of LT6376 has two operating regions:
a) If the common mode voltage at the inputs of the inter-
–
+
nal op amp (V
) is between V and V –1.75V, the op
CMOP
amp operates in its normal region; b) If VCMOP is between
V+ –1.75V and V– +76V, the op amp continues to operate,
but in its Over-The-Top region with degraded performance
(see Over-The-Top operation section of this data sheet for
more detail).
Table 3 lists the valid input common mode voltage range
for an LT6376 that results in the internal op amp operating
in its Over-The-Top region.
The reference pins can be connected to ground (as in
Tables 2 and 3) or to any reference voltage. In order to
achieve the specified gain accuracy and CMRR perfor-
mance of the LT6376, this reference must have a very
low impedance over the entire bandwidth of interest. As
needed, ensure there are quality high frequency ceramic
or film capacitors and low frequency electrolytic capaci-
tors, from the reference to ground.
Table 2 lists the valid input common mode voltage range
for an LT6376 with different configurations of the refer-
ence pins when used with dual power supplies. Using
ꢁ
ꢂ
ꢃ
ꢁ
ꢀꢉꢊꢋꢌ
ꢎꢏꢐ
ꢀꢉꢊꢋꢍ
3ꢑꢐ
ꢀꢉꢊꢋꢖ
ꢓ3ꢔ7ꢕꢐ
ꢂ
The valid input common mode range changes depending
on the voltages chosen for reference pins. Table 4 lists the
valid input common mode voltage range for an LT6376
when the part is used with a single power supply, and REF
and the other reference pins are connected to mid-supply.
If, as shown in Table 5, the REF pin remains connected to
mid-supply, while the other reference pins are connected
to ground, the result is a higher positive input range at
the expense of a more restricted negative input range.
76ꢒꢐ
76ꢐ
ꢀꢄꢅ
ꢁꢄꢅ
ꢂ
ꢂ
ꢀ
ꢁ
ꢀꢄꢅ
ꢁꢄꢅ
ꢆꢇꢈ
ꢉꢊꢋ
ꢂ
ꢆꢇꢈ
76ꢐ
76ꢒꢐ
ꢎꢏꢐ
ꢁꢉꢊꢋꢌ
3ꢑꢐ
ꢓ3ꢔ7ꢕꢐ
ꢁꢉꢊꢋꢖ
ꢀ
ꢁꢉꢊꢋꢍ
SHDN
ꢂ
6376 ꢋꢒꢎ
ꢁ
ꢀ
ꢂ
ꢃ
ꢂ
ꢃ
Figꢀꢂl ±. Baeic Cꢁuul coiꢁue fꢁꢂ Dꢀan-Sꢀppny Opl ꢂaoiꢁu
(Rl eieoꢁꢂ Dividl ꢂ Raoiꢁ = 3.±)
6376f
15
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
Tabnl 2. Cꢁmmꢁu Mꢁdl Vꢁnoagl Opl ꢂaoiug Raugl wiot Dꢀan
Pꢁwl ꢂ Sꢀppnil e (Nꢁꢂman Rl giꢁu)
Tabnl 5. Cꢁmmꢁu Mꢁdl Vꢁnoagl Opl ꢂaoiug Raugl wiot a Siugnl
Pꢁwl ꢂ Sꢀppny, Rl fl ꢂl ucl e oꢁ GND (Nꢁꢂman Rl giꢁu)
INPUT RANGE (REF = GND)
INPUT RANGE (REF = V /2)
S
+REFA +REFB +REFC
AND AND AND
+REFA +REFB +REFC
AND AND AND
V = ±2.5V
S
V = ±±5V
S
V = ±25V
S
V = 5V
S
V = 30V
S
V = 50V
S
–REFA –REFB –REFC DIV HIGH LOW HIGH LOW HIGH LOW
OPEN GND OPEN 3.1 2.325 –7.75 41.075 –46.5 72.075 –77.5
OPEN OPEN GND 4.3 3.225 –10.75 56.975 –64.5 99.975 –107.5
GND OPEN OPEN 5.1 3.825 –12.75 67.575 –76.5 118.575 –127.5
OPEN GND GND 6.3 4.725 –15.75 83.475 –94.5 146.475 –157.5
GND GND OPEN 7.1 5.325 –17.75 94.075 –106.5 165.075 –177.5
GND OPEN GND 8.3 6.225 –20.75 109.975 –124.5 192.975 –207.5
GND GND GND 10.3 7.725 –25.75 136.475 –154.5 230 –230
–REFA –REFB –REFC DIV HIGH LOW HIGH LOW HIGH LOW
OPEN GND OPEN 3.1 9.825 –0.25 86.075 –1.5 147.075 –2.5
OPEN OPEN GND 4.3 13.725 –0.25 119.975 –1.5 204.975 –2.5
GND OPEN OPEN 5.1 16.325 –0.25 142.575 –1.5 230
OPEN GND GND 6.3 20.225 –0.25 176.475 –1.5 230
GND GND OPEN 7.1 22.825 –0.25 199.075 –1.5 230
GND OPEN GND 8.3 26.725 –0.25 230 –1.5 230
GND GND GND 10.3 33.225 –0.25 230 –1.5 230
–2.5
–2.5
–2.5
–2.5
–2.5
Tabnl 3. Cꢁmmꢁu Mꢁdl Vꢁnoagl Opl ꢂaoiug Raugl wiot Dꢀan
Pꢁwl ꢂ Sꢀppnil e (Ovl ꢂ-Tt l -Tꢁp Rl giꢁu)
INPUT RANGE (REF = GND)
The LT6376 will not operate correctly if the common
mode voltage at its input pins goes below the range speci-
fied in above tables, but the part will not be damaged as
long as the lowest common mode voltage at the inputs
+REFA +REFB +REFC
AND AND AND
V = ±2.5V
S
V = ±±5V
S
V = ±25V
S
–REFA –REFB –REFC DIV HIGH LOW HIGH LOW HIGH LOW
OPEN GND OPEN 3.1 227.85 –7.75 189.1 –46.5 158.1 –77.5
OPEN OPEN GND 4.3 230 –10.75 230 –64.5 219.3 –107.5
GND OPEN OPEN 5.1 230 –12.75 230 –76.5 230 –127.5
OPEN GND GND 6.3 230 –15.75 230 –94.5 230 –157.5
GND GND OPEN 7.1 230 –17.75 230 –106.5 230 –177.5
GND OPEN GND 8.3 230 –20.75 230 –124.5 230 –207.5
GND GND GND 10.3 230 –25.75 230 –154.5 230 –230
of the internal op amp (V
) is always greater than
CMOP
–
V –25V. Also, the voltage at LT6376 input pins should
never be higher than 230V or lower than –230V under
any circumstances.
SHUTDOWN
The LT6376 in the DFN14 package has a shutdown pin
(SHDN). Under normal operation this pin should be tied
+
Tabnl 4. Cꢁmmꢁu Mꢁdl Vꢁnoagl Opl ꢂaoiug Raugl wiot a Siugnl
Pꢁwl ꢂ Sꢀppny, Rl fl ꢂl ucl e oꢁ Mid-Sꢀppny (Nꢁꢂman Rl giꢁu)
to V or allowed to float. Driving this pin to at least 2.5V
+
below V will cause the part to enter a low power state.
INPUT RANGE (REF = V /2)
S
The supply current is reduced to less than 25µA and the
op amp output becomes high impedance.
+REFA +REFB +REFC
AND AND AND
V = 5V
V = 30V
V = 50V
S
S
S
–REFA –REFB –REFC DIV HIGH LOW HIGH LOW HIGH LOW
OPEN V /2 OPEN 3.1 4.825 –5.25 56.075 –31.5 97.075 –52.5
S
SUPPLY VOLTAGE
OPEN OPEN V /2 4.3 5.725 –8.25 71.975 –49.5 124.975 –82.5
S
The positive supply pin of the LT6376 should be bypassed
with a small capacitor (typically 0.1µF) as close to the
supply pin as possible. When driving heavy loads an addi-
tional 4.7µF electrolytic capacitor should be added. When
V /2 OPEN OPEN 5.1 6.325 –10.25 82.575 –61.5 143.575 –102.5
S
OPEN V /2 V /2 6.3 7.225 –13.25 98.475 –79.5 171.475 –132.5
S
S
V /2 V /2 OPEN 7.1 7.825 –15.25 109.075 –91.5 190.075 –152.5
S
S
V /2 OPEN V /2 8.3 8.725 –18.25 124.975 –109.5 217.975 –182.5
S
S
–
using split supplies, the same is true for the V supply pin.
V /2 V /2 V /2 10.3 10.225 –23.25 151.475 –139.5 230 –230
S
S
S
6376f
16
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
ACCURATE CURRENT MEASUREMENTS
Increasing RSENSE and RC slightly to RSENSE' removes
the gain error.
The LT6376 can be used in high side, low side and bi-
directional wide common mode range current sensing.
Figure 2 shows the LT6376 sensing current by measur-
R
SENSE
' = R
• 76k/(76k – R ).
SENSE
SENSE
ing the voltage across R
. The added sense resistors
SENSE
NOISE AND FILTERING
create a CMRR error and a gain error. For R
greater
SENSE
The noise performance of the LT6376 can be optimized
both by appropriate choice of its internal attenuation set-
ting and by the addition of a filter to the amplifier output
(Figure 3). For applications that do not require the full
bandwidth of the LT6376, the addition of an output filter
will lower system noise. Table 6 shows the output noise
for different internal resistor divider ratios and output filter
bandwidths.
than 0.5Ω the source resistance mismatch degrades the
CMRR. Adding a resistor equal in value to RSENSE in series
with the +IN terminal (R ) eliminates this mismatch.
C
Using an RSENSE greater than 4.7Ω will cause the gain
error to exceed the 0.0075% specification of the LT6376.
This is due to the loading effects of the LT6376.
V
OUT
= 10 • I
• R
• 76k/(76k + R
)
LOAD
SENSE
SENSE
ꢁ
ꢂ
ꢄ ꢅꢆꢂ
ꢃ
ꢁ
ꢀꢇꢈꢒꢎ
ꢅꢔꢕ
ꢀꢇꢈꢒꢓ
3ꢖꢕ
ꢀꢇꢈꢒꢐ
ꢗ3ꢘ7ꢆꢕ
ꢂ
76ꢑꢕ
ꢁ
ꢂ
ꢄ ꢅꢅꢑꢂ
ꢃꢊꢋꢇꢐꢈ
76ꢕ
76ꢕ
–IN
+IN
ꢀ
ꢁ
ꢊꢋꢌ
ꢇꢈꢒ
ꢂ
ꢂ
≅ 10 • R
• I
ꢇ
ꢃꢈꢉꢃꢈ
ꢊꢋꢌ
ꢃꢈꢉꢃꢈ ꢍꢊꢎꢏ
ꢇ
ꢐ
I
ꢍꢊꢎꢏ
ꢇꢈꢒ
76ꢑꢕ
ꢅꢔꢕ
3ꢖꢕ
ꢗ3ꢘ7ꢆꢕ
ꢁꢇꢈꢒꢐ
ꢀ
ꢁꢇꢈꢒꢎ
ꢁꢇꢈꢒꢓ
SHDN
ꢂ
ꢁ
ꢀ
ꢃ
ꢂ
ꢂ
ꢄ ꢀꢅꢆꢂ
ꢄ ꢅꢆꢂ
ꢃ
ꢍꢊꢎꢏ
ꢁ
ꢂ
ꢃ
ꢁ
ꢀꢇꢈꢒꢎ
ꢅꢔꢕ
ꢀꢇꢈꢒꢓ
3ꢖꢕ
ꢀꢇꢈꢒꢐ
ꢗ3ꢘ7ꢆꢕ
ꢂ
76ꢑꢕ
I
ꢍꢊꢎꢏ
76ꢕ
–IN
+IN
ꢀ
ꢁ
ꢊꢋꢌ
ꢇꢈꢒ
ꢇ
ꢂ
ꢂ
≅ 10 • ꢇ
• I
ꢃꢈꢉꢃꢈ
ꢊꢋꢌ
ꢃꢈꢉꢃꢈ ꢍꢊꢎꢏ
ꢇ
76ꢕ
ꢐ
ꢀ
ꢇꢈꢒ
ꢂ
ꢄ ꢀꢅꢅꢑꢂ
ꢃꢊꢋꢇꢐꢈ
76ꢑꢕ
ꢅꢔꢕ
ꢁꢇꢈꢒꢎ
3ꢖꢕ
ꢗ3ꢘ7ꢆꢕ
ꢁꢇꢈꢒꢐ
ꢀ
ꢁꢇꢈꢒꢓ
SHDN
ꢂ
6376 ꢒꢑꢗ
ꢁ
ꢀ
ꢄ ꢀꢅꢆꢂ
ꢂ
ꢂ
ꢃ
ꢃ
Figꢀꢂl 2. Widl Vꢁnoagl Raugl Cꢀꢂꢂl uo Sl ueiug
6376f
17
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
ꢁ
ꢂ
ꢃ
ꢁ
ꢀꢉꢊꢋꢌ
ꢎꢏꢐ
ꢀꢉꢊꢋꢍ
3ꢑꢐ
ꢀꢉꢊꢋꢖ
ꢓ3ꢔ7ꢕꢐ
ꢂ
76ꢒꢐ
ꢖꢓ
ꢉꢓ
ꢀ
ꢁ
76ꢐ
ꢀꢄꢅ
ꢁꢄꢅ
ꢗꢈ6ꢒꢎꢕ
ꢂ
ꢂ
ꢂ
ꢆꢇꢈ
ꢀ
ꢁ
ꢀꢄꢅ
ꢁꢄꢅ
ꢉꢎ
ꢆꢇꢈ
ꢉꢊꢋ
76ꢐ
ꢖꢎ
ꢂ
ꢉꢊꢋ
76ꢒꢐ
ꢎꢏꢐ
ꢁꢉꢊꢋꢌ
3ꢑꢐ
ꢓ3ꢔ7ꢕꢐ
ꢁꢉꢊꢋꢖ
ꢀ
ꢁꢉꢊꢋꢍ
SHDN
ꢂ
6376 ꢋꢒ3
ꢁ
ꢀ
ꢂ
ꢃ
ꢂ
ꢃ
Figꢀꢂl 3. Oꢀopꢀo Finol ꢂiug wiot 2-Pꢁnl Bꢀool ꢂwꢁꢂot Finol ꢂ
Tabnl 6. Oꢀopꢀo Nꢁiel (VP-P) fꢁꢂ 2-Pꢁnl Bꢀool ꢂwꢁꢂot Finol ꢂ fꢁꢂ
Diffl ꢂl uo Iuol ꢂuan Rl eieoꢁꢂ Dividl ꢂ Raoiꢁe
Tabnl 7. Cꢁmpꢁul uo Vanꢀl e fꢁꢂ Diffl ꢂl uo 2-Pꢁnl Bꢀool ꢂwꢁꢂot
Finol ꢂ Baudwidot e
Cꢁꢂul ꢂ
Cꢁꢂul ꢂ Fꢂl qꢀl ucy
100kHz
R±
R2
C±
C2
Fꢂl qꢀl ucy
No Filter
100kHz
10kHz
3.±
4.3
5.±
6.3
7.±
8.3
±0.3
11kΩ 11.3kΩ 100pF 200pF
548µV 606µV 638µV 678µV 707µV 747µV 809µV
328µV 394µV 434µV 488µV 523µV 572µV 649µV
107µV 131µV 146µV 168µV 183µV 204µV 239µV
10kHz
11kΩ 11.3kΩ
1nF
2nF
20nF
0.2µF
1kHz
11kΩ 11.3kΩ 10nF
11kΩ 11.3kΩ 0.1µF
100Hz
1kHz
33µV
12µV
41µV
15µV
46µV
17µV
53µV
19µV
57µV 64µV
21µV 24µV
75µV
28µV
100Hz
15V
+
–REFA
19k
–REFB
38k
–REFC
23.75k
V
760k
+
V
= 80V
SOURCE
76k
76k
–IN
–
+
R
OUT
REF
SENSE
V
OUT
1Ω
R , 1Ω
C
+IN
1A
760k
19k
+REFA
38k
23.75k
+REFC
–
LOAD
+REFB
SHDN
V
6376 F04
–15V
Figꢀꢂl 4. Cꢀꢂꢂl uo Ml aeꢀꢂl ml uo Appnicaoiꢁu
6376f
18
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
ERROR BUDGET ANALYSIS
+
of the positive power supply voltage V ), but its perfor-
mance is degraded. The op amp’s input bias currents
change from under 2nA to 14µA. The op amp’s input
offset current rises to 50nA which adds 3.8mV to the
input offset voltage.
Figure 4 shows the LT6376 in a current measurement
application. The error budget for this application is shown
in Table 8. The resistor divider ratio is set to 6.3 to divide
the 80V input common mode voltage down to 12.7V at
the op amp inputs. The 1A current and 1Ω sense resis-
tor produce an output full-scale (FS) voltage of 10V (in
the LT6376) and 1V (in all the other listed parts). Table 8
shows the error sources in parts per million (ppm) of the
output full-scale voltage across the temperature range of
25°C to 85°C.
In addition, when operating in the Over-The-Top region,
the differential input impedance decreases from 1MΩ in
normal operation to approximately 3.7kΩ in Over-The-Top
operation. This resistance appears across the summing
nodes of the internal op amp and boosts noise and offset
while decreasing speed. Noise and offset will increase by
between 66% and 83% depending on the resistor divider
ratio setting. The bandwidth will be reduced by between
40% to 45%. For more detail on Over-The-Top operation,
consult the LT6015 data sheet.
Different sources of error contribute to the maximum
accuracy that can be achieved in an application. Gain error,
offset voltage and common mode rejection error combine
to set the initial error. Additionally, the gain error and off-
set voltage drift across the temperature range. The excel-
lent gain accuracy, low offset voltage, high CMRR, low
offset voltage drift and low gain error drift of the LT6376
all combine to enable extremely accurate measurements.
OUTPUT
The output of the LT6376 can typically swing to within
5mV of either rail with no load and is capable of sourcing
and sinking approximately 25mA. The LT6376 is inter
-
nally compensated to drive at least 1nF of capacitance
under any output loading conditions. A 0.22µF capacitor
in series with a 150Ω resistor between the output and
ground will compensate the amplifier to drive capaci-
tive loads greater than 1nF. Additionally, the LT6376 has
more gain and phase margin as the resistor divider ratio
is increased.
Ovl ꢂ-Tt l -Tꢁp OPERATION
When the input common mode voltage of the internal op
amp (V
) in the LT6376 is biased near or above the
CMOP
+
V supply, the op amp is operating in the Over-The-Top
region. The op amp continues to operate with an input
–
common mode voltage of up to 76V above V (regardless
Tabnl 8. Eꢂꢂꢁꢂ Bꢀdgl o Auanyeie
ERROR, ppm ꢁf OUTPUT FS
LT6376
(DIV = 6.3)
LT6375
(DIV = 7)
ERROR SOURCE
AD629B
COMPETITOR
LT6376 LT6375
AD629B
COMPETITOR
Differential Gain (V/V)
Output FS Voltage (V)
10
10
1
1
1
1
1
1
Accꢀꢂacy, T = 25°C
A
Initial Gain Error
0.0075% FS
3800µV
0.006% FS
450µV
0.03% FS
500µV
0.02% FS
1100µV
75
60
300
500
200
Output Offset Voltage
380
450
1100
10 • (80V/90dB)
= 25300µV
80V/89dB =
2839µV
80V/86dB =
4009µV
80V/90dB =
2530µV
Common Mode
2530
2985
2839
3349
4009
4809
2530
3830
Tꢁoan Accꢀꢂacy Eꢂꢂꢁꢂ
Tl mpl ꢂaoꢀꢂl Dꢂifo
Gain
1ppm/°C ×60°C 1ppm/°C ×60°C 10ppm/°C ×60°C 10ppm/°C ×60°C
60
450
510
3495
60
720
780
4129
600
600
600
900
Output Offset Voltage 75µV/°C ×60°C 12µV/°C ×60°C 10µV/°C ×60°C
15µV/°C ×60°C
Tꢁoan Dꢂifo Eꢂꢂꢁꢂ
Tꢁoan Eꢂꢂꢁꢂ
1200
6009
1500
5330
6376f
19
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
DISTORTION
For a given supply voltage, the worst-case output power
dissipation POD(MAX) occurs with the output voltage at half
The LT6376 features excellent distortion performance
when the internal op amp is operating within the supply
rails. Operating the LT6376 with input common mode
voltages that go from normal to Over-The-Top operation
will significantly degrade the LT6376’s linearity as the op
amp must transition between two different input stages.
of either supply voltage. P
is given by:
OD(MAX)
2
P
= (V /2) /R
OD(MAX)
S
LOAD
The power dissipated in the internal resistors (PRESD
)
depends on the input voltage, the resistor divider ratio
(DIV), the output voltage and the voltage on REF and the
other reference pins. The following equations and Figure 5
POWER DISSIPATION CONSIDERATIONS
show different components of P
corresponding to
RESD
different groups of LT6376’s internal resistors (assuming
that LT6376 is used with a dual supply configuration with
REF and all reference pins at ground).
Because of the ability of the LT6376 to operate on power
supplies up to 25V, to withstand very high input voltages
and to drive heavy loads, there is a need to ensure the die
junction temperature does not exceed 150°C. The LT6376
is housed in DF14 (qJA = 43°C/W, qJC = 4°C/W) and MS16
2
P
P
P
P
P
= (V ) /(76k + 76k/(DIV – 1))
RESDA
RESDB
RESDC
RESDD
+IN
2
= (V – V /DIV) /(76k)
–IN
+IN
2
(
qJA = 130°C/W) packages.
= (V /DIV) /(76k/(DIV – 1.1))
+IN
In general, the die junction temperature (T ) can be esti-
J
2
= (V /DIV – V ) /(760k)
+IN
OUT
mated from the ambient temperature (TA), and the device
= P
+ P
+ P
+ P
power dissipation (P ):
RESD
RESDA
RESDB
RESDC RESDD
D
P
RESD
simplifies to:
T = T + P • qJA
J
A
D
PRESD=2(V+IN2((DIV–1)/DIV–VOUT/(10•V+IN))+0.055
Power is dissipated by the amplifier’s quiescent cur-
rent, by the output current driving a resistive load and by
the input current driving the LT6376’s internal resistor
network.
2
• V
)/76k
OUT
In general, PRESD increases with higher input voltage,
higher resistor divider ratio (DIV), and lower output, REF
and reference pin voltages.
+
–
P = ((V – V ) • I ) + P + P
D
S
S
S
OD
RESD
ꢁ
ꢂ
ꢅ ꢆꢏꢂ
ꢐ
ꢁ
ꢀꢒꢓꢔꢕ ꢀꢒꢓꢔꢖ ꢀꢒꢓꢔꢛ
ꢂ
ꢙ
ꢒꢓꢐꢚꢛ
ꢙ
ꢒꢓꢐꢚꢚ
76ꢇꢘ
ꢌꢗꢘ
3ꢍꢘ
ꢆ3ꢎ7ꢏꢘ
ꢙ
ꢒꢓꢐꢚꢖ
76ꢘ
ꢀꢃꢄ
ꢁꢃꢄ
ꢂ
ꢀꢃꢄ
ꢅ ꢆ3ꢇꢂ ꢀ ꢂ ꢋꢌꢇ
ꢈꢉꢊ
ꢅ ꢆꢆꢍꢎ7ꢏꢂ
ꢀ
ꢁ
ꢈꢉꢊ
ꢒꢓꢔ
ꢂ
ꢈꢉꢊ
ꢅ ꢌꢆꢎꢏꢂ
ꢙ
ꢒꢓꢐꢚꢕ
76ꢘ
ꢂ
ꢅ ꢆ3ꢇꢂ
ꢁꢃꢄ
76ꢇꢘ
ꢌꢗꢘ
3ꢍꢘ
ꢆ3ꢎ7ꢏꢘ
ꢀ
ꢁꢒꢓꢔꢕ ꢁꢒꢓꢔꢖ ꢁꢒꢓꢔꢛ
SHDN
ꢂ
6376 ꢔꢇꢏ
ꢑ
ꢂ
ꢐ
ꢅ ꢀꢆꢏꢂ
Figure 5. Power Dissipation Example
6376f
20
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
Example: An LT6376 in a DFN package mounted on a PC
board has a thermal resistance of 43°C/W. Operating on
25V supplies and driving a 2.5kΩ load to 12.5V with
REF offset signal. These configurations allow the LT6376
to be used as a versatile precision gain block with essen-
tially no external components besides the supply decou-
pling. In most cases, only a single positive supply will be
required. In Table 9, connections are identified as NC (no
connect), INPUT (refers to both inputs driven, +signal to
+pins,–signal to –pins), CROSS (refers to inputs cross-
coupled, +signal to –pins, –signal to +pins), OUT (refers
to the output fed back to –pins), or REF (refers to con-
necting the REF pin to +pins). The same configurations
provide inverting gains by grounding any pins intended
for the +signal source. The differential input resistance is
also tabulated as well as the amplification factor of the
internal gain section involved (noise-gain, which helps to
estimate the error-budget of the configuration).
V
= 230V and DIV = 10.3, the total power dissipation
+IN
is given by:
2
2
P = (50 • 0.6mA) + 12.5 /2.5k + 230 /84.17k
D
2
+ (228.75 – 230/10.3) /76k
2
+ (230/10.3) /8.26k + (230/10.3
2
– 12.5) /760k = 1.342W
Assuming a thermal resistance of 43°C/W, the die tem-
perature will experience a 57.7°C rise above ambient.
This implies that the maximum ambient temperature the
LT6376 should operate under the above conditions is:
T =150°C – 57.7°C = 92.3°C
A
Single-ended noninverting gains are also available as
shown in Table 10, including many that operate as buf-
fers (loaded only by the op amp input bias). A rich option
set exists by using the REF pin as an additional variable.
In Table 10, connections are identified as NC (no con-
nect), INPUT (driven by the input), OUT (fed back from the
output), or GROUND (grounded). Table 10 also includes
tabulations of the internal resistor divider (DIV), noise
gain (re-amplification), and the input loading presented
by the circuit.
Keep in mind that the DFN package has an exposed pad
which can be used to lower the qJA of the package. The
more PCB metal connected to the exposed pad, the lower
the thermal resistance.
The MSOP package has no exposed pad and a higher
thermal resistance (qJA = 130°C/W). It should not be used
in applications which have a high ambient temperature,
require driving a heavy load, or require an extreme input
voltage.
USE AS PRECISION AC GAIN BLOCK
THERMAL SHUTDOWN
In AC-coupled applications operating from a single power
supply, it is useful to set the output voltage near mid-
supply to maximize dynamic range. The LT6376 readily
supports this with no additional biasing components by
For safety, the LT6376 will enter shutdown mode when
the die temperature rises to approximately 163°C. This
thermal shutdown has approximately 9°C of hysteresis
requiring the die temperature to cool 9°C before enabling
the amplifier again.
+
–
connecting specific pins to the V and V potentials and
AC-coupling the signal paths. Table 11 shows the available
inverting gains and also tabulates the load resistances
presented at the input. In Table 11, connections are identi-
fied as NC (no connect), AC IN (AC-coupled to the input)
USE AT OTHER PRECISION DC GAINS
The array of resistors within the LT6376 provides numer-
ous configurable connections that provide precision gains
other than the G = 10 differential gain options described
previously. Note that only the +IN and –IN pins can oper-
ate outside of the supply window. Since most of these
alternate configurations involve driving the REFx pins, as
well as the +IN and –IN pins, the input signals must be less
than the supply voltages. Fully differential gains are avail-
able as shown in Table 9, and may be output-shifted with a
+
–
OUT (fed back from the output), tied to V , tied to V ,
or AC GND (AC- grounded). All pins that require an AC
ground can share a single bypass capacitor. Likewise, all
pins driven from the source signal may share a coupling
capacitor as well. The output should also connect to the
load circuitry using a coupling capacitor to block the mid-
supply DC voltage.
6376f
21
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
The LT6376 may also be used for single-supply nonin-
verting AC gains by employing a combination of input
attenuation and re-amplification. With numerous choices
of attenuation and re-amplification, several hundred over-
all gain combinations are possible, ranging from 0.1 to
73. The combinations are more plentiful than the DC con-
figurations because there is no constraint on matching
internal source resistances to minimize offset.
The high attenuations that only use +IN for the signal
path can accept waveform peaks that significantly exceed
the supply range. Table 12 also includes tabulations of
the resulting AC load resistance presented to the signal
source. Here again, all pins that require an AC-ground
connection may share a single bypass capacitor, and all
AC signal connections may share a coupling capacitor.
The single-supply AC-coupled noninverting circuit is
completed by configuring the post-attenuator amplifica-
tion factor. Table 13 shows the available re-amplification
factors. Once again, all pins that require an AC-ground
connection may share a single bypass capacitor, and the
output should use a coupling capacitor to its load desti-
nation as well.
The input attenuator section dedicates some pins to
establishing a bias point and with the remaining pins,
provides several choices of input signal division factors as
shown in Table 12. The bias point varies between 20% and
49% of the supply voltage depending on the configura-
tion. Swapping V+ and V– will bias the circuit closer to V+.
Table 9. Configurations for Precision Differential Gains
LT6376 DIFFERENTIAL AND INVERTING PRECISION DC GAINS
GAIN
2
±IN
CROSS
NC
±REFA
NC
±REFB
CROSS
NC
±REFC
INPUT
CROSS
NC
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
DIFF R (k)
NOISE GAIN
IN
24.52
21.11
152
63
73
11
53
83
21
43
31
33
41
43
51
53
61
63
71
73
83
93
103
8
INPUT
NC
10
12
18
20
22
30
32
40
42
50
52
60
62
70
72
82
92
102
INPUT
NC
NC
NC
CROSS
NC
INPUT
CROSS
NC
29.23
18.54
76
INPUT
NC
INPUT
NC
INPUT
NC
CROSS
INPUT
NC
NC
INPUT
NC
36.19
50.67
47.50
38
NC
INPUT
NC
NC
INPUT
NC
NC
INPUT
NC
NC
INPUT
INPUT
NC
NC
INPUT
NC
36.19
30.40
29.23
25.33
24.52
21.71
21.11
18.54
16.52
14.90
INPUT
NC
NC
INPUT
INPUT
INPUT
INPUT
NC
INPUT
NC
NC
INPUT
NC
INPUT
INPUT
NC
INPUT
NC
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
NC
NC
INPUT
INPUT
INPUT
6376f
22
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
Table 10. Configurations for Precision Noninverting Gains
LT6376 NONINVERTING PRECISION DC GAINS
NOISE
GAIN
GAIN FEATURE
+IN
GROUND
INPUT
INPUT
INPUT
INPUT
NC
+REFA
NC
+REFB
NC
+REFC
NC
REF
–IN
–REFA
NC
–REFB
NC
–REFC
NC
DIV
11
R (k)
IN
1
INPUT
GROUND
11
11
11
31
31
33
41
41
43
51
51
53
61
61
63
71
73
83
83
93
93
103
103
836
836
10
NC
NC
NC
GROUND GROUND
INPUT GROUND
GROUND GROUND
NC
NC
NC
1.10
1
11
30
31
32
40
41
42
50
51
52
60
61
62
70
72
82
83
92
93
102
103
BUFFER
BUFFER
NC
NC
NC
NC
NC
NC
Hi-Z
NC
INPUT
INPUT
NC
NC
NC
GROUND
GROUND
NC
NC
1.03 785.33
Hi-Z
1.03 783.75
NC
NC
INPUT
GROUND
GROUND
INPUT
GROUND
NC
NC
NC
1
NC
INPUT
NC
NC
GROUND
NC
NC
INPUT
INPUT
NC
NC
NC
GROUND
GROUND
NC
NC
1.03
1
779
BUFFER
BUFFER
BUFFER
NC
NC
NC
NC
NC
NC
Hi-Z
INPUT
INPUT
INPUT
NC
NC
INPUT
NC
GROUND GROUND
NC
GROUND
NC
1.02 778.10
1.02 775.20
INPUT
INPUT
NC
NC
GROUND GROUND GROUND
NC
NC
NC
INPUT
GROUND
GROUND
INPUT
GROUND GROUND
NC
NC
1
Hi-Z
INPUT
INPUT
INPUT
INPUT
INPUT
NC
INPUT
NC
NC
NC
NC
NC
GROUND GROUND
1.02 774.62
1.02 772.67
NC
INPUT
INPUT
NC
GROUND GROUND
GROUND GROUND
NC
NC
NC
NC
1
Hi-Z
INPUT
INPUT
NC
INPUT
NC
GROUND GROUND
NC
GROUND GROUND
1.02 772.26
1.01 770.86
1.01 770.56
1.01 769.27
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GROUND GROUND GROUND GROUND
NC
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GROUND
NC
GROUND
NC
NC
NC
GROUND
GROUND
GROUND
INPUT
INPUT
NC
NC
GROUND GROUND GROUND
BUFFER
BUFFER
BUFFER
NC
INPUT
GROUND
INPUT
GROUND GROUND
1
Hi-Z
1.01 768.26
Hi-Z
1.01 767.45
Hi-Z
INPUT
INPUT
INPUT
INPUT
NC
NC
GROUND GROUND GROUND
GROUND GROUND GROUND
NC
1
INPUT
INPUT
GROUND GROUND GROUND GROUND GROUND
INPUT GROUND GROUND GROUND GROUND
1
6376f
23
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
Table 11. Configurations for Single-Supply AC-Coupled Inverting Gains
LT6376 SINGLE-SUPPLY INVERTING AC GAINS
GAIN
–10
–20
–30
–32
–40
–42
–50
–52
–60
–62
–70
–72
–82
–92
–102
–IN
AC IN
NC
–REFA
NC
–REFB
NC
–REFC
NC
+IN
+REFA
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
+REFB
+REFC
REF
AC R (k)
IN
–
–
+
–
V
V
V
V
76
38
25
24
19
18
15
15
13
12
11
11
9
–
–
+
–
NC
AC IN
AC IN
NC
NC
V
V
V
V
–
–
+
–
AC IN
NC
NC
NC
V
V
V
V
–
–
+
–
NC
AC IN
NC
V
V
V
V
–
–
+
–
NC
AC IN
NC
NC
V
V
V
V
–
–
+
–
AC IN
AC IN
NC
NC
AC IN
NC
V
V
V
V
–
–
+
–
AC IN
NC
NC
V
V
V
V
–
–
+
–
AC IN
AC IN
AC IN
AC IN
NC
AC IN
NC
V
V
V
V
–
–
+
–
NC
AC IN
NC
V
V
V
V
–
–
+
–
AC IN
AC IN
NC
AC IN
NC
V
V
V
V
–
–
+
–
AC IN
AC IN
AC IN
AC IN
AC IN
V
V
V
V
–
–
+
–
AC IN
AC IN
AC IN
AC IN
V
V
V
V
–
–
+
–
AC IN
NC
NC
V
V
V
V
–
–
+
–
AC IN
AC IN
V
V
V
V
8
–
–
+
–
AC IN
V
V
V
V
7
Table 12. Configurations for Single-Supply AC-Coupled Input Attenuations
LT6376 SINGLE-SUPPLY AC ATTENUATOR CONFIGURATIONS
DIV
1.41
1.42
1.43
1.69
1.70
1.72
1.73
1.75
1.78
1.91
1.94
1.94
1.96
1.97
1.98
2.02
DC BIAS
0.33
0.33
0.35
0.24
0.24
0.26
0.33
0.33
0.35
0.33
0.33
0.20
0.20
0.35
0.22
0.38
+IN
+REFA
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
NC
+REFB
+REFC
REF
AC IN
NC
AC R (k)
IN
+
–
–
–
V
V
V
V
AC IN
AC IN
AC IN
36
36
35
31
31
30
44
44
44
48
49
30
30
48
30
30
+
V
+
+
V
V
+
–
V
AC IN
AC IN
AC IN
V
AC IN
NC
+
–
V
V
+
–
+
V
V
V
+
–
V
V
NC
AC IN
NC
+
–
V
V
NC
+
–
+
V
V
NC
V
+
–
V
V
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
NC
+
–
V
NC
V
+
–
V
V
AC IN
AC IN
AC IN
NC
+
–
V
V
+
–
+
V
NC
V
V
+
–
+
V
V
AC IN
V
+
–
AC IN
AC IN
V
V
AC IN
6376f
24
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
Table 12. Configurations for Single-Supply AC-Coupled Input Attenuations (continued)
LT6376 SINGLE-SUPPLY AC ATTENUATOR CONFIGURATIONS
DIV
2.04
2.06
2.27
2.30
2.33
2.51
2.55
2.58
3.12
3.19
3.22
3.32
3.40
3.43
3.38
3.50
3.55
4.90
5.10
5.15
5.73
6.20
6.30
9.36
10.20
10.30
31
DC BIAS
0.38
0.40
0.38
0.38
0.40
0.48
0.48
0.49
0.43
0.43
0.44
0.44
0.44
0.45
0.20
0.20
0.22
0.49
0.49
0.48
0.38
0.38
0.40
0.44
0.44
0.45
0.33
0.24
0.20
0.38
0.33
0.48
0.43
0.44
0.49
0.43
0.49
+IN
AC IN
AC IN
NC
+REFA
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
+REFB
+REFC
REF
AC R (k)
IN
+
–
V
V
NC
30
30
+
–
+
V
V
V
+
–
V
V
AC IN
33
+
–
NC
V
V
NC
34
+
–
+
NC
V
V
V
33
+
+
–
V
V
V
AC IN
NC
31
+
+
–
V
V
V
31
+
+
–
+
V
V
V
V
31
+
–
+
V
V
V
AC IN
AC IN
AC IN
AC IN
NC
34
+
–
+
V
V
V
35
+
–
+
+
V
V
V
V
34
–
+
AC IN
AC IN
AC IN
V
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
V
AC IN
NC
35
–
+
V
V
36
–
+
+
V
V
V
36
+
–
V
V
NC
NC
NC
AC IN
NC
51
+
–
V
V
53
+
–
+
V
V
V
53
–
+
–
V
V
V
AC IN
NC
45
–
+
–
V
V
V
47
–
+
–
–
V
V
V
V
47
+
–
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
NC
NC
NC
V
V
AC IN
NC
84
+
–
V
V
91
+
–
+
V
V
V
90
–
+
V
AC GND
AC GND
AC GND
V
AC IN
77
–
V
V+
V+
NC
NC
84
–
+
V
V
84
+
–
V
NC
NC
V
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
AC IN
785
778
775
775
773
772
771
771
769
768
767
+
–
43
V
NC
NC
V
+
–
51
V
V
NC
+
–
53
NC
NC
V
V
–
+
61
NC
V
V
NC
+
+
–
63
V
NC
V
V
+
–
+
71
V
V
V
NC
–
+
73
NC
V
NC
NC
V
–
+
–
83
V
V
V
+
–
–
93
NC
V
V
V
+
+
–
–
103
V
V
V
V
6376f
25
For more information www.linear.com/LT6376
LT6376
APPLICATIONS INFORMATION
Table 13. Configurations for Single-Supply AC-Coupled Re-Amplications
LT6376 NONINVERTING AC RE-AMPLIFICATIONS
GAIN
11
21
31
33
41
43
51
53
61
63
71
73
83
93
103
–IN
AC GND
NC
–REFA
NC
–REFB
NC
–REFC
NC
NC
AC GND
AC GND
NC
NC
AC GND
NC
NC
NC
NC
AC GND
NC
NC
AC GND
NC
NC
AC GND
AC GND
NC
NC
AC GND
NC
AC GND
NC
NC
AC GND
AC GND
AC GND
AC GND
NC
AC GND
NC
NC
AC GND
NC
AC GND
AC GND
NC
AC GND
NC
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
AC GND
NC
NC
AC GND
AC GND
AC GND
6376f
26
For more information www.linear.com/LT6376
LT6376
TYPICAL APPLICATIONS
40.2dB Audio Gain Stage
ꢂ
ꢃ
ꢄ 3ꢅ3ꢂ ꢆꢇ ꢈꢉꢂ
ꢁ
ꢀꢋꢌꢍꢎ
ꢔꢕꢖ
ꢀꢋꢌꢍꢓ
3ꢗꢖ
ꢀꢋꢌꢍꢘ
ꢑ3ꢅ7ꢈꢖ
ꢂ
76ꢉꢖ
ꢑꢅꢑꢒꢍ
ꢀꢏꢐ
76ꢖ
ꢂ
ꢑꢅꢑꢒꢍ
ꢀ
ꢁ
ꢏꢐ
ꢇꢊꢆ
ꢋꢌꢍ
ꢂ
ꢇꢊꢆ
76ꢖ
ꢁꢏꢐ
ꢂ
ꢇꢊꢆ
ꢄ ꢀꢔꢉꢑ
ꢂ
ꢏꢐ
76ꢉꢖ
ꢔꢕꢖ
ꢁꢋꢌꢍꢎ
3ꢗꢖ
ꢑ3ꢅ7ꢈꢖ
ꢁꢋꢌꢍꢘ
ꢀ
ꢁꢋꢌꢍꢓ
SHDN
ꢂ
ꢑꢅꢑꢒꢍ
6376 ꢆꢎꢉꢑ
6376f
27
For more information www.linear.com/LT6376
LT6376
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT6376#packaging for the most recent package drawings.
DF Package
14(12)-Lead Plastic DFN (4mm × 4mm)
ꢀꢁꢂfꢂꢃꢂꢄꢅꢂ ꢆꢇꢈ ꢉꢊꢋ ꢌ ꢍꢎꢏꢍꢐꢏꢑꢒ63 ꢁꢂꢓ ꢔꢕ
3.00 REF
ꢀ.00
BSC
0.70 0.05
4.50 0.05
ꢀ.70 0.05
3.ꢀ0 0.05
3.38 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
4.00 0.ꢀ0
(4 SIDES)
ꢀ.00
BSC
8
ꢀ4
0.40 0.ꢀ0
3.38 0.ꢀ0
ꢀ.70 0.ꢀ0
PIN ꢀ NOTCH
0.35 × 45°
CHAMFER
PIN ꢀ
TOP MARK
(NOTE 6)
(DFꢀ4)(ꢀ2) DFN ꢀꢀꢀ3 REV 0
7
R = 0.ꢀꢀ5
TYP
ꢀ
0.25 0.05
0.50 BSC
0.200 REF
0.75 0.05
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
ꢀ. PACKAGE OUTLINE DOES NOT CONFORM TO JEDEC MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6376f
28
For more information www.linear.com/LT6376
LT6376
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT6376#packaging for the most recent package drawings.
MS Package
16 (12)-Lead Plastic MSOP with 4 Pins Removed
(Reference LTC DWG # 05-08-1847 Rev B)
1.0
0.889 ±0.127
(.035 ±.005)
(.0394)
BSC
5.10
3.20 – 3.45
(.201)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.126 – .136)
MIN
0.280 ±0.076
(.011 ±.003)
REF
16 14 121110
9
0.50
(.0197)
BSC
0.305 ±0.038
(.0120 ±.0015)
TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1
3 5 6 7 8
GAUGE PLANE
1.0
(.0394)
BSC
0.53 ±0.152
(.021 ±.006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS12) 0213 REV B
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6376f
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
29
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
For more information www.linear.com/LT6376
LT6376
TYPICAL APPLICATION
Bidirectional Full Range Current Monitor
ꢂ
ꢍ
ꢆ ꢏꢂ (OR 2V GREATER THAN ꢂ
ꢎ
ꢃꢄꢅ
ꢁ
–REFA
ꢀꢊꢋꢌꢔ
3ꢗꢖ
ꢀꢊꢋꢌꢘ
ꢒ3ꢑ7ꢏꢖ
ꢂ
ꢐꢕꢖ
76ꢇꢖ
ꢂ
ꢆ ꢇꢂ ꢈꢄ 3ꢂ
ꢃꢄꢅ
ꢊ
ꢍꢋꢅꢍꢋ
76ꢖ
ꢀꢓꢅ
ꢁꢓꢅ
ꢀ
ꢄꢉꢈ
ꢊ
ꢂ
ꢄꢉꢈ
ꢆ ꢂ
+ 102 • (ꢂ
ꢎ
ꢍꢋꢅꢍꢋ
ꢍꢋꢅꢍꢋ
ꢊꢋꢌ
76ꢖ
ꢁ
ꢊꢋꢌ
LOAD
ꢂ
ꢆ ꢐꢑꢒꢏꢂ
ꢊꢋꢌ
76ꢇꢖ
ꢐꢕꢖ
+REFA
3ꢗꢖ
ꢒ3ꢑ7ꢏꢖ
ꢁꢊꢋꢌꢘ
ꢀ
ꢁꢊꢋꢌꢔ
SHDN
ꢂ
6376 TA03
NOTE: OPERATES OVER FULL RANGE OF LOAD VOLTAGE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT6375
270V Input Range Difference Amplifier
250V Input Range Difference Amplifier
3.3V to 50V Operation, CMRR > 90dB, Input Voltage = 270V, G = 1
2.7V to 36V Operation, CMRR > 70dB, Input Voltage = 250V, G = 1 AND 10
3.3V to 50V Operation, CMRR > 90dB, Input Voltage = 160V, G = 1, 3 and 9
LT1990
LT1997-3
Precision, Wide Voltage Range Gain Selectable
Amplifier
LT1999-10/
LT1999-20/
LT1999-50
High Voltage, Bidirectional Current Sense Amplifier Input Voltage = –5V to 80V, 750µV V , CMRR 80dB at 100kHz, Gain: 10V/V,
OS
20V/V, 50V/V
LT1991
LT1996
LTC6090
LT6108
Precision, 100µA Gain Selectable Amplifier
Precision, 100µA Gain Selectable Amplifier
140V Operational Amplifier
2.7V to 36V Operation, 50μV Offset, CMRR > 75B, Input Voltage = 60V
Micropower, Pin Selectable Up to Gain = 118
50pA I , 1.6mV V , 9.5V to 140V V , 4.5mA I , RR Output
B
OS
S
S
High Side Current Sense Amplifier with Reference
and Comparator with Shutdown
2.7V to 60V, 125µV, Resistor Set Gain, 1.25% Threshold Error
LT1787/
LT1787HV
Precision, Bidirectional High Side Current Sense
Amplifier
2.7V to 60V Operation, 75μV Offset, 60μA Current Draw
LTC6101/
High Voltage High Side Current Sense Amplifier
Zero Drift High Side Current Sense Amplifier
Bidirectional, High Side Current Sense
4V to 60V/5V to 100V Operation, External Resistor Set Gain, SOT23
LTC6101HV
LTC6102/
LTC6102HV
4V to 60V/5V to 100V Operation, 10μV Offset, 1μs Step Response,
MSOP8/DFN Packages
LTC6104
4V to 60V, Gain Configurable, 8-Pin MSOP Package
LT6015/LT6016/ Single, Dual, and Quad, Over-The-Top Precision Op 3.2MHz, 0.8V/µs, 50µV V , 3V to 50V V , 0.335mA I , RRIO
OS
S
S
LT6017
Amp
AD629
High Common-Mode Voltage Difference Amplifier
5V to 36V Operation, CMRR > 86dB, Input Voltage = 270V, G = 1
6376f
LT 1217 • PRINTED IN USA
www.linear.com/LT6376
30
ANALOG DEVICES, INC. 2017
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